TLS4120D0EPV33XUMA1

OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Features • • • • • • • • • • • • • • • • • • • • • • 2 A step down regulator Input voltage from 3.7 V to 35 V 3.3 V output voltage ±1.5% feedback voltage accuracy in PWM mode Ultra low current consumption 31 µA Integrated high side and low side power MOSFETs Peak current mode PWM regulation Light load PFM mode with improved efficiency Switching frequency range: 320 kHz to 560 kHz or 1.6 MHz to 2.8 MHz 100% duty cycle operation Synchronization input Spread spectrum frequency modulation for improved EMI performance Soft-start function Integrated compensation network Output discharge function in disabled state Ultra low current consumption in disabled state (typically 1 µA) Undervoltage monitoring Overvoltage monitoring Overcurrent protection and overload protection Input undervoltage shutdown Wide temperature range Tj = -40°C to 150°C Green Product (RoHS compliant) Potential applications • • • • Body ADAS Infotainment, telematics Navigation Product validation Qualified for automotive applications. Product validation according to AEC-Q100. Datasheet Please read the Important Notice and Warnings at the end of this document www.infineon.com/OPTIREG-switcher Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Description Description The OPTIREG™ switcher TLS4120D0EPV33 is a 2.8 MHz synchronous step down regulator especially designed for automotive applications. The device has a current capability of 2 A, fixed 3.3 V output voltage and a feedback voltage accuracy of ±1.5% in PWM mode. The integrated power stages, soft-start feature and integrated compensation network reduce the required amount of external components and thus system costs and board space. The wide input voltage range and a 100% duty cycle operation mode make the device suitable for battery cranking scenarios in automotive applications. The wide switching frequency range allows the selection of appropriate coils and capacitors. The switching frequency can be synchronized to an external clock signal. Spread spectrum frequency modulation can be activated to improve the EMI performance in PWM operation. The device offers low current consumption in PFM mode at light loads to optimize efficiency. The TLS4120D0EPV33 can detect undervoltage and overvoltage conditions of the output voltage and indicates this with the reset output signal. Overcurrent and overload protections avoid excessive current to protect the device during short circuit conditions at the buck converter output. The integrated thermal shutdown feature protects the device from overheating. The enhanced PG-TSDSO-14 exposed pad package offers advantageous thermal performance in the application. Type Package Marking TLS4120D0EPV33 PG-TSDSO-14 4120D0V3 Datasheet 2 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Table of contents Table of contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 2.1 2.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.2 3.3 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 4.1 4.1.1 4.1.1.1 4.1.1.2 4.1.1.3 4.1.1.4 4.1.2 4.1.2.1 4.1.2.2 4.1.3 4.1.3.1 4.1.3.2 4.1.3.3 4.2 4.3 Buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional description buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Regulation loop and operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PWM (Pulse Width Modulation) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PFM (Pulse Frequency Modulation) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Continuous conduction mode and discontinuous conduction mode . . . . . . . . . . . . . . . . . . . . .12 High duty cycle operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-up and power-down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Startup procedure with soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Active output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overcurrent protection and overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Input undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Electrical characteristics buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical performance characteristics buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 5.1 5.1.1 5.1.2 5.2 5.3 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Functional description oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Electrical characteristics oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical performance characteristics oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Datasheet 3 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Table of contents 6.1 6.2 6.3 Functional description current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Electrical characteristics current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical performance characteristics current consumption and enable . . . . . . . . . . . . . . . . . . . . . . . 28 7 7.1 7.2 7.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Functional description reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Electrical characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical performance characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 8.1 8.2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Datasheet 4 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Block diagram 1 Block diagram VS VS EN Enable Overtemperature shutdown UVLO Internal supply Bandgap reference FREQ Control loop + driver SYNC SW Oscillator PGND SSON Spread spectrum FB Soft-start ramp generator RT Reset RO AGND Figure 1 Datasheet Block diagram 5 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Pin configuration 2 Pin configuration 2.1 Pin assignment FREQ SYNC RO AGND EN VS VS 1 2 3 4 5 6 7 TSDSO-14 14 13 12 11 10 9 8 Figure 2 Pin configuration 2.2 Pin definitions and functions FB RT SSON SW SW PGND PGND Pin Symbol Function 1 FREQ Frequency selection input: Connect this pin to GND via resistor for frequency selection. Leave this pin open to set the default high switching frequency. Connect this pin to GND to set the default low switching frequency. 2 SYNC Synchronization input: Connect this pin to external clock to synchronize the switching frequency. If this pin is not used, then connect it to GND. 3 RO Reset output: Open drain reset output. Provides the reset output signal. If the reset feature is used, then connect this pin via external resistor to VCC or to an external pull-up voltage. If the reset feature is not used, then leave this pin open. 4 AGND Analog ground: Connect this pin to GND using a low inductive, broad PCB trace. 5 EN Enable input: This pin has an integrated pull-down resistor. "High" enables the device. "Low" disables the device. 6, 7 VS Supply voltage input: Connect this pin to supply voltage. Short pins 6 and 7 at the PCB. 8, 9 PGND Power ground: Connect this pin directly to GND using a low inductive, broad PCB trace. Short pins 8 and 9 at the PCB. 10, 11 SW Datasheet Regulator switch node: 6 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Pin configuration Pin Symbol Function Connect this pin to the buck converter power inductor. Short pins 10 and 11 at the PCB. 12 SSON Spread spectrum enable input: This pin has an integrated pull-down resistor. "High" enables spread spectrum. "Low" disables spread spectrum. 13 RT Reset configuration input: Connect this pin via a resistor to GND to adjust the reset delay time and the reset undervoltage threshold. Connect this pin to GND, if the reset function is not needed or to configure the default reset delay time and default undervoltage reset threshold. 14 FB Feedback input: Feedback input to the regulator. Connect this pin directly to the output capacitor of the buck converter. – Exposed Connect the exposed pad to a heatsink area and to GND with low inductive and broad PCB pad trace. Datasheet 7 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator General product characteristics 3 General product characteristics 3.1 Absolute maximum ratings Table 1 Absolute maximum ratings1) Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or condition Number Voltages Enable input VEN -20 – 35 V – P_3.1.1 Enable input VEN,dyn -20 – 42 V 2) Transients P_3.1.2 Synchronization input VSYNC -0.3 – 6 V – P_3.1.3 Spread spectrum enable input VSSON -0.3 – 6 V – P_3.1.4 Frequency selection VFREQ -0.3 – 6 V – P_3.1.5 Reset output VRO -0.3 – 6 V – P_3.1.6 Reset configuration VRT -0.3 – 6 V – P_3.1.7 Feedback input VFB -0.3 – 7 V – P_3.1.8 Buck switch output VSW -0.3 – VVS + 0.3 V Minimum -2.0 V in transient condition (single event < 15 ns) P_3.1.9 Supply voltage input VVS -0.3 – 35 V – P_3.1.10 Supply voltage input VVS,dyn -0.3 – 42 V 2) Transients P_3.1.11 Power GND VPGND -0.3 – 0.3 V – P_3.1.12 Analog GND VAGND -0.3 – 0.3 V – P_3.1.13 Junction temperature Tj -40 – 150 °C – P_3.1.14 Storage temperature Tstg -55 – 150 °C – P_3.1.15 VESD,HBM -2 – 2 kV 3) HBM P_3.1.16 V 4) CDM P_3.1.17 present on this pin present on this pin Temperatures ESD susceptibility ESD susceptibility to GND ESD susceptibility to GND 1 2 3 4 VESD,CDM -500 – 500 Not subject to production test, specified by design. Transients between 35 V and 42 V can be tolerated for a total lifetime duration shorter than 48 s. ESD susceptibility, Human Body Model (HBM) according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF). ESD susceptibility, Charged Device Model (CDM) according to JEDEC JESD22-C101. Datasheet 8 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator General product characteristics Table 1 Absolute maximum ratings1) (continued) Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. ESD susceptibility corner pins 1, 7, 8, 14 to GND VESD,CDM,C -750 Typ. – Max. 750 Unit Note or condition 4) CDM V Number P_3.1.18 Notes: 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions are not designed for continuous repetitive operation. 3.2 Functional range Table 2 Functional range Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Number 5) Minimum value P_3.2.1 Max. Supply voltage decreasing VVS,dec 3.7 – 35 V Supply voltage increasing VVS,inc 6.0 – 35 V Minimum value represents startup condition P_3.2.2 Enable input VEN 0 – 35 V – P_3.2.3 Output voltage VCC – 3.3 – V – P_3.2.4 SYNC input voltage VSYNC 0 – 3.5 V – P_3.2.7 Reset output voltage VRO,hi 0 – 3.5 V 6) P_3.2.10 Output current ICC 0 – 2 A – P_3.2.14 Junction temperature Tj -40 – 150 °C – P_3.2.15 1 4 5 6 represents low battery voltage condition (cranking) Not subject to production test, specified by design. ESD susceptibility, Charged Device Model (CDM) according to JEDEC JESD22-C101. With 3.7 V < VVS < 6 V, a reduced performance of parameter settings applies to feedback voltage accuracy, synchronization and the reset function. Allowed external pull-up voltage applied via pull-up resistance to pin RO. Datasheet 9 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator General product characteristics Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the electrical characteristics table. 3.3 Thermal resistance Table 3 Thermal resistance7) Parameter Symbol Values Min. Typ. Unit Note or condition Number Max. Junction to case RthJC – 8.6 – K/W – P_3.3.1 Junction to ambient RthJA,1 – 34 – K/W 8) 2s2p P_3.3.2 Junction to ambient RthJA,2 – 45 – K/W 9) 1s0p + 600 mm² P_3.3.3 Junction to ambient RthJA,3 – 54 – K/W 9) 1s0p + 300 mm² P_3.3.4 K/W 9) 1s0p footprint P_3.3.5 Junction to ambient Note: 7 8 9 RthJA,4 – 116 – This thermal data was generated in accordance with JEDEC JESD51 standards. For more information visit www.jedec.org. Not subject to production test, specified by design. Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with two inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable, a thermal via array next to the package contacted the first inner copper layer. Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; the product (IC and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 × 70 µm Cu). Datasheet 10 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator 4 Buck regulator 4.1 Functional description buck regulator The TLS4120D0EPV33 is a synchronous current mode step down (buck) regulator with selectable switching frequency fOSC. The device regulates the output voltage in pulse width modulation (PWM) or in pulse frequency modulation (PFM) mode and automatically moves between both modes on load change or input voltage change. At low input voltage conditions, for example during battery cranking, the device can operate at a duty cycle of 100%. 4.1.1 Regulation loop and operation modes Figure 3 shows the regulation loop. An internal resistor divider is connected between pin FB and pin AGND to reduce the magnitude of the output voltage signal, which is connected to pin FB. The error amplifier processes the difference between scaled output feedback voltage and internal reference voltage to provide a reference current to the PWM comparator. The PWM comparator compares that reference current to a scaled version of the inductor current to determine the PWM duty cycle that is required for stable output voltage regulation. In PFM mode the error amplifier output signal also serves to modulate the switching frequency. The control logic supervises the handover between operation modes and triggers the drivers of high side PMOS power stage and the low side NMOS power stage accordingly. For the modes of PWM, PFM and 100% duty cycle operation see PWM (Pulse Width Modulation) mode, PFM (Pulse Frequency Modulation) mode, Continuous conduction mode and discontinuous conduction mode and High duty cycle operation respectively. FB VS Current sense Internal comp. Error amp. GND Softstart Control logic PWM comp. SW LOUT VCC Voltage reference COUT Slope compensation Oscillator Clock Clock manager PGND GND SYNC AGND Figure 3 Functional block diagram buck regulator 4.1.1.1 PWM (Pulse Width Modulation) mode At high load the TLS4120D0EPV33 operates with the configured switching frequency fOSC in PWM mode. In PWM mode the device modulates the duty cycle to achieve a regulated output voltage. The nominal switching frequency can be set using one of the following methods, see Oscillator: • by an external resistor connected at pin FREQ • from a synchronization signal applied at the SYNC pin Datasheet 11 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator The pulse width modulation is based on peak current mode detection to achieve a fast reaction time and an optimized feedback accuracy. The PWM comparator processes the current signal detected at the high side power stage as well as the current signals of the slope compensation and the error amplifier to adjust the switching duty cycle to regulate the output voltage accordingly. With a duty cycle above 50% the slope compensation ensures system stability. This is achieved by avoidance of subharmonic oscillations of the output inductor current. Due to a current sense signal inaccuracy at the beginning of each high side switch conduction phase, a short blanking time is required to mask the output of the current sense before processing it. The blanking time defines the minimum allowed on-time ton,min of the high side PMOS power stage and therefore the point of transition from PWM to PFM operation. 4.1.1.2 PFM (Pulse Frequency Modulation) mode The device can operate at constant on-time ton,min of the high side PMOS power stage to achieve a stable output voltage at light load or high input voltage conditions. In PFM mode the device operates at a constant on-time and modulates the switching frequency to regulate the output voltage. The switching frequency is lower than in PWM mode. For further information about the PFM boundary condition and the frequency modulation depending on load and on input voltage, see Typical performance characteristics buck regulator. In PFM mode with light load the device offers optimized efficiency with reduced current consumption. 4.1.1.3 Continuous conduction mode and discontinuous conduction mode Continuous conduction mode (CCM) The device operates at a continuously rising or falling triangular positive inductor current. The on-time and the switching duty cycle mainly depend on the ratio of output voltage to input voltage. Boundary condition for CCM → DCM transition With a decrease of the load current during continuous conduction mode, the minimum valley inductor current can obtain approximately zero, which is the boundary condition for the discontinuous conduction mode. Further reduction of the load current leads to discontinuous conduction mode. Discontinuous conduction mode (DCM) The device turns off the low side power stage to avoid a negative inductor current. Further reduction of the load current reduces the on-time and leads to transition from PWM into PFM when obtaining the minimum on-time. High load PWM-CCM IL t CCM-DCM boundary IL t IL Medium-low load PWM-DCM t IL Low load PFM-DCM t Figure 4 Datasheet Typical example inductor current waveforms for CCM and DCM 12 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator 4.1.1.4 High duty cycle operation In 100% duty cycle mode the high side PMOS power stage constantly conducts current. If the input voltage is close to the nominal output voltage or lower, then the device enters this operation mode, see Figure 5. If the input voltage is decreased (for example during a battery cranking scenario) and the device moves from regulation to the 100% duty cycle mode, then the output voltage tracks the input voltage as accurate as possible down to an input voltage VVS of 3.7 V. During steady state operation, the difference of the output voltage and the tracked input voltage as well as the entry point into 100% duty cycle mainly depend on the voltage drop at the resistance Ron,hs of the high side PMOS power stage, which in turn depends on the load current ICC. Parasitic elements of external application circuitry and components, such as the output inductor series resistance, increase the voltage drop. At high duty cycles close to 100%, the loop might not propagate very short off-times and compensates this by skipping switching cycles to ensure a smooth transition to 100% duty cycle with a stable output voltage. VVS Voltage VCC VCC = VCC,nom t Dutycycle 100% Regulation Tracking Regulation t Figure 5 Datasheet Typical 100% duty cycle mode tracking behavior 13 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator 4.1.2 Power-up and power-down control The following features of the device control power up and power down, see Table 4 for electrical characteristics: • Startup with soft-start • Active output discharge 4.1.2.1 Startup procedure with soft-start The soft-start function of the TLS4120D0EPV33 controls the ramp-up of the output voltage with defined timing tstart during startup, see Figure 6. If VVS > VVS,on, then a "high" signal VEN,hi at pin EN triggers the startup procedure. During startup the internal supply establishes a stable state and the device initializes the switching frequency and the reset function according to the configuration. The regulator then increases the output voltage Vcc by ramping up the internal voltage reference connected to the error amplifier. VVS VVS > VVS,on 0V t VEN VEN,hi 0V t VCC Initialization Soft-start VCC,nom 95% of VCC,nom 5% of VCC,nom 0V tinit tstart t Figure 6 Typical startup procedure 4.1.2.2 Active output discharge The active output discharge function of the TLS4120D0EPV33 controls the ramp-down of the output voltage during power down, see Figure 7. If the device detects a "low" signal VEN,lo at the EN pin, then it switches on the integrated discharge transistor connected to the SW pin in order to discharge the output capacitor COUT via the output inductor LOUT. The typical on-resistance Rdc of the discharge transistor is 55 Ω. VS SW Internal supply EN Discharge control LOUT VCC Discharge current COUT Discharge transistor GND GND Figure 7 Datasheet Active output discharge block diagram 14 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator 4.1.3 Protection features The device offers features that are designed to protect it from fault events such as overcurrent, overload, input undervoltage and overtemperature, see Table 4. 4.1.3.1 Overcurrent protection and overload protection If the sensed current through the high side PMOS power stage exceeds the buck peak overcurrent limit IBUOC after the blanking time of the current sense, then the device switches off the high side power stage for the remaining time of the current cycle. Active current limitation can decrease the output voltage level. If the sensed freewheeling current through the low side NMOS power stage exceeds the overload limit IBUOL, then the device prevents the high side PMOS power stage from switching on in the subsequent clock cycles to avoid overheating. The overload threshold level is set to a higher value than the overcurrent threshold level. If an overload condition and an undervoltage condition occur for longer than 3 ms typically, then the device detects a short circuit at the output voltage node and shuts down. After a waiting time of typically 1 s, the device restarts with a soft-start. 4.1.3.2 Input undervoltage shutdown The device incorporates an undervoltage shutdown function. If the input voltage VVS drops below the input undervoltage shutdown threshold VVS,off, then the device shuts down. 4.1.3.3 Overtemperature protection The integrated overtemperature protection turns off the device in case of a too high junction temperature. The typical junction thermal shutdown temperature is 175°C. After the device has cooled down by the amount of the typical junction temperature hysteresis 10 K and a subsequent waiting time of typically 1 s, the device restarts with a soft-start to resume normal operation. The thermal shutdown is an integrated protection function to prevent the immediate destruction of the device during fault conditions. However, a junction temperature above 150°C is outside of the maximum ratings and reduces the lifetime of the device. Datasheet 15 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator 4.2 Electrical characteristics buck regulator Table 4 Electrical characteristics buck regulator VVS = 6 V to 35 V; Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Unit Note or condition Number Typ. Max. – +1.5 % 6 V ≤ VVS ≤ 35 V; PWM mode P_4.2.1 Feedback voltage accuracy Feedback voltage accuracy VFB,PWM -1.5 Feedback voltage accuracy VFB,PFM,1 -2 – +3.5 % 6 V ≤ VVS ≤ 35 V; PFM mode P_4.2.2 Feedback voltage VFB VFB – 3.3 – V – P_4.2.4 High side MOSFET onresistance Ron,hs – 120 240 mΩ ICC = 100 mA P_4.2.7 Low side MOSFET onresistance Ron,ls – 70 150 mΩ ICC = 100 mA P_4.2.9 Maximum duty cycle Dmax – – 100 % 10) P_4.2.11 Minimum on-time, high frequency ton,min,hf – 78 – ns 11) I = 1.5 A; valid for high frequency operation range P_4.2.12 Minimum on-time, low frequency ton,min,lf – 308 – ns 11) I P_4.2.13 MOSFETs Regulation loop CC CC = 1.5 A; valid for low frequency operation range Startup and active discharge12) Soft-start time tstart 0.8 1 1.2 ms VCC rising from 5% to 95% of P_4.2.14 nominal VCC level Startup initialization time tinit – – 2.6 ms time from rising edge of VEN (0 V to VEN,hi ) until soft-start P_4.2.15 Input voltage startup threshold VVS,on 2.6 – 6.0 V VVS increasing; VEN ≥ 2 V P_4.2.16 Output discharge resistance Rdc – 55 – Ω VEN = 0 V; VVS = 13.5 V; VSW = 100 mV P_4.2.17 IBUOC 2.8 3.4 4.0 A – P_4.2.18 Current limitation Buck peak overcurrent limit 10 11 12 See Functional range and High duty cycle operation. Specified by design, not subject to production test. See Power-up and power-down control Datasheet 16 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator Table 4 Electrical characteristics buck regulator (continued) VVS = 6 V to 35 V; Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. 3.4 Unit Note or condition Number Typ. Max. 3.9 4.4 A – P_4.2.20 Overload current limit IBUOL Overload overcurrent gap IBUOL,gap 0.05 0.5 – A Overload current limit is typically 0.5 A above buck peak overcurrent limit P_4.2.22 Input undervoltage shutdown threshold VVS,off 3.3 – 3.55 V VVS decreasing P_4.2.23 Input undervoltage shutdown hysteresis VVS,hys 180 280 420 mV – P_4.2.24 Undervoltage shutdown Datasheet 17 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator 4.3 Typical performance characteristics buck regulator FREQ: 2.2 MHz; VVS = 13.5 V; Tj = 25°C (if not otherwise specified). The shown performance characteristics was measured on a 4 layer FR4 printed circuit board with external components as recommended in Application information. Efficiency FREQ: 440 kHz; Tj = 25°C Efficiency FREQ: 440 kHz; Tj = 25°C Efficiency FREQ: 2.2 MHz; Tj = 25°C Efficiency FREQ: 2.2 MHz; Tj = 25°C Datasheet 18 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator Line regulation ICC = 1 A Load regulation VVS = 13.5 V Output voltage precision ICC = 200 mA Line regulation (low load) ICC = 100 µA Datasheet 19 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator High side MOSFET on-resistance ICC = 100 mA Low side MOSFET on-resistance ICC = 100 mA Output discharge resistance VEN = 0 V; VSW = 100 mV Input undervoltage shutdown threshold VVS decreasing Datasheet 20 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator PFM frequency modulation (CCM) FREQ: 440 kHz; ICC = 1.5 A PFM frequency modulation (CCM) FREQ: 2.2 MHz; ICC = 1.5 A PFM frequency modulation (DCM) FREQ: 440 kHz; Tj = 25°C PFM frequency modulation (DCM) FREQ: 2.2 MHz; Tj = 25°C Datasheet 21 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Buck regulator PFM boundary Tj = 25°C Load step response ICC: 0.6 A to 2 A to 0.6 A V CC [100 mV/div] I CC [2 A/div] 3.3 V 0.6 A -0.5 0 0.5 1 1.5 t [ms] Buck peak overcurrent limit VVS = 13.5 V Datasheet Overload current limit VVS = 13.5 V 22 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Oscillator 5 Oscillator 5.1 Functional description oscillator The integrated clock provides a constant frequency to the regulation loop. In PWM mode the device switches on and off the high side and low side power stages at the oscillator frequency fOSC. The oscillator frequency can be set by connecting a resistor RFREQ between the FREQ pin and ground, see Table 5, Table 6 and Table 7. The device sets the selected switching frequency during startup. Table 5 FREQ configuration for typical oscillator frequencies in the low frequency range RFREQ [kΩ]13) fOSC [kHz] 2.2 320 3.3 360 4.7 400 ≤ 1.0 (or connect FREQ pin directly to GND) 44014) 6.8 480 10 520 15 560 Table 6 FREQ configuration for typical oscillator frequencies in the high frequency range RFREQ [kΩ]15) fOSC [MHz] 22 1.6 33 1.8 47 2.0 ≥ 200 (or leave FREQ pin open) 2.216) 68 2.4 100 2.6 150 2.8 5.1.1 Synchronization input In PWM mode the device can synchronize the switching frequency to an external oscillator connected to the SYNC pin. The internal clock manager triggers at the falling edge of the external signal. The phase shift towards the switching frequency can be adjusted with the duty cycle of the external oscillator. 50% duty cycle of the external oscillator corresponds to a phase shift of approximately zero. A suitable setting of RFREQ is required so that the internal operation frequency is equal to the corresponding external synchronization frequency or above it. This is a prerequisite for the automatic transitions between PWM mode and PFM mode. As soon as the startup is completed and the device accepts the external signal at the SYNC pin, the synchronization turns active. 13 14 15 16 Resistor tolerance ≤ 5%. Default oscillator low frequency. Resistor tolerance ≤ 5%. Default oscillator high frequency. Datasheet 23 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Oscillator 5.1.2 Spread spectrum In PWM mode, when used without an external clock at the SYNC pin, the TLS4120D0EPV33 can apply spread spectrum to optimize EMI performance. The device modulates the switching frequency up and down by a triangle waveform with a typical frequency of 8.3 kHz within a range of typically ±7.5% of the selected oscillator frequency. The logical signal on the SSON pin switches spread spectrum on or off. 5.2 Electrical characteristics oscillator Table 7 Electrical characteristics oscillator VVS = 6 V to 35 V; Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Number Max. Frequency setting Default oscillator low frequency fosc,1 396 440 484 kHz RFREQ ≤ 1.0 kΩ or connect FREQ pin directly to GND P_5.2.1 Default oscillator high frequency fosc,2 1.98 2.2 2.42 MHz RFREQ ≥ 200 kΩ or leave FREQ pin open P_5.2.2 Oscillator frequency fosc,3 288 320 352 kHz RFREQ = 2.2 kΩ P_5.2.3 Oscillator frequency fosc,4 324 360 396 kHz RFREQ = 3.3 kΩ P_5.2.4 Oscillator frequency fosc,5 360 400 440 kHz RFREQ = 4.7 kΩ P_5.2.5 Oscillator frequency fosc,6 432 480 528 kHz RFREQ = 6.8 kΩ P_5.2.6 Oscillator frequency fosc,7 468 520 572 kHz RFREQ = 10 kΩ P_5.2.7 Oscillator frequency fosc,8 504 560 616 kHz RFREQ = 15 kΩ P_5.2.8 Oscillator frequency fosc,9 1.44 1.6 1.76 MHz RFREQ = 22 kΩ P_5.2.9 Oscillator frequency fosc,10 1.62 1.8 1.98 MHz RFREQ = 33 kΩ P_5.2.10 Oscillator frequency fosc,11 1.8 2.0 2.2 MHz RFREQ = 47 kΩ P_5.2.11 Oscillator frequency fosc,12 2.16 2.4 2.64 MHz RFREQ = 68 kΩ P_5.2.12 Oscillator frequency fosc,13 2.34 2.6 2.86 MHz RFREQ = 100 kΩ P_5.2.13 Oscillator frequency fosc,14 2.52 2.8 3.08 MHz RFREQ = 150 kΩ P_5.2.14 Synchronization low frequency capture range fsync,lf 320 – 560 kHz 17) valid for P_5.2.15 Synchronization high frequency capture range fsync,hf 1.6 – 2.8 MHz 17) valid for P_5.2.16 SYNC "high" signal VSYNC,hi 2 – – V 17) V P_5.2.19 Synchronization input 17 oscillator low frequency range oscillator high frequency range CC = 3.3 V Synchronization of PWM to the falling edge. Datasheet 24 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Oscillator Table 7 Electrical characteristics oscillator (continued) VVS = 6 V to 35 V; Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Number Max. SYNC "low" signal VSYNC,lo – – 0.8 V 17) P_5.2.21 SYNC signal hysteresis VSYNC,hys 45 255 600 mV 17) P_5.2.22 SYNC "high" input current ISYNC,hi – 0.1 1 µA VSYNC = 3.3 V P_5.2.24 SYNC "low" input current ISYNC,lo – 0.1 1 µA VSYNC = 0 V P_5.2.26 SYNC signal duty cycle DSYNC 10 – 90 % – P_5.2.28 Spread spectrum "high" signal VSSON,hi 2.0 – – V Enables spread spectrum P_5.2.29 Spread spectrum "low" signal VSSON,lo – – 0.8 V Disables spread spectrum P_5.2.30 Spread spectrum enable hysteresis VSSON,hys 100 250 1000 mV – P_5.2.31 Spread spectrum enable "high" input current ISSON,hi 0.7 1 1.25 µA VSSON = 5.0 V P_5.2.32 Spread spectrum modulation frequency fSS,mod 7.5 8.3 9.3 kHz Spread spectrum enabled P_5.2.33 Spread spectrum modulation range fSS,range – ±7.5 – % Spread spectrum enabled P_5.2.34 Spread spectrum 17 Synchronization of PWM to the falling edge. Datasheet 25 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Oscillator 5.3 Typical performance characteristics oscillator Oscillator (low frequency) VVS = 13.5 V; FREQ: 440 kHz Datasheet Oscillator (high frequency) VVS = 13.5 V; FREQ: 2.2 MHz 26 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Current consumption and enable 6 Current consumption and enable 6.1 Functional description current consumption and enable A "high" signal VEN,hi at the EN pin switches on the regulator. In on-state the device can operate at very low current consumption IVS,on to improve the efficiency with low load in PFM mode. A "low" signal VEN,lo at the EN pin switches the regulator off. In turned off-state, the current consumption IVS,off of the device is 1 µA typically. If the EN pin is left open, then an internal pull-down resistor REN,int ensures that the device remains switched off. 6.2 Electrical characteristics current consumption and enable Table 8 Electrical characteristics current consumption and enable VVS = 6 V to 35 V; Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Number Max. Current consumption Current consumption in off- IVS,off state – 1 2 µA VEN = 0 V; VVS = 13.5 V; Tj < 85°C P_6.2.1 Current consumption in on- IVS,on state – 31 65 µA VEN = 5.0 V; VVS = 13.5 V; Tj < 85°C; not switching18) P_6.2.2 Enable Enable "high" signal VEN,hi 2.0 – – V – P_6.2.3 Enable "low" signal VEN,lo – – 0.8 V – P_6.2.4 Enable hysteresis VEN,hys 100 400 1000 mV – P_6.2.5 Enable "high" input current IEN,hi,1 – 0.6 1 µA VEN = 5.0 V P_6.2.6 Enable "high" input current IEN,hi,2 – 2.5 3.5 µA VEN = 13.5 V P_6.2.7 Enable, internal resistor to GND 5.6 8 10.4 MΩ VEN = 2.0 V P_6.2.8 18 REN,int The current consumption is tested while the output voltage is forced to a slightly higher value than the nominal output voltage to prevent switching activities of the regulator. Datasheet 27 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Current consumption and enable 6.3 Typical performance characteristics current consumption and enable Current consumption in off-state VVS = 13.5 V; VEN = 0 V Current consumption in on-state VVS = 13.5 V; VEN = 5 V; no switching Enable "high" input current VVS = 13.5 V Datasheet 28 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Reset 7 Reset 7.1 Functional description reset The reset function supervises the regulator output voltage VCC by monitoring the feedback voltage VFB. The device indicates the reset status at the RO pin. RO "high" indicates, that the output voltage is within the desired reset thresholds. RO "low" indicates that the output voltage is outside the desired reset thresholds. As long as the device operates within the specified range, the reset function is active, see Table 10 and Functional range. Reset output RO The reset output pin RO is an open drain structure and needs to be pulled up to VCC or to a voltage rail via an external pull-up resistor RRO, which must be chosen according to the maximum pull-up current IRO,lo. During battery cranking conditions of the input voltage VVS, the reset feature is active down to an input voltage VVS of 2.8 V. Power-on reset delay time Power-on reset delay time tRD,PWR-on is the time period from completion of the soft-start until the device releases the reset by switching the reset output RO from "low" to "high", see Figure 8. An external resistor RRT connected to the RT pin determines the value of power-on reset delay time tRD,PWR-on, see Table 9. Reset undervoltage, overvoltage and delay time In contrast to the power-on reset delay time tRD,PWR-on, the reset delay time tRD refers to an output undervoltage or output overvoltage event during operation, see Figure 8. If VFB drops below the undervoltage reset threshold VRT,UV,th, then the device sets the reset signal at the RO to "low". When the output voltage recovers and VFB exceeds the undervoltage reset threshold plus the hysteresis (VRT,UV,th + VRT,UV,hys), then the device sets the RO pin to "high" after the reset delay time tRD. In accordance with the undervoltage reset delay time, the overvoltage reset delay time tRD considers an output overvoltage event. If case VFB exceeds the overvoltage reset threshold VRT,OV,th, then the device sets the RO pin to "low". When the output voltage recovers and VFB drops below the overvoltage reset threshold minus the hysteresis (VRT,OV,th - VRT,OV,hys), then the device sets the RO pin to "high" after the reset delay time tRD. An external resistor RRT connected to the RT pin determines the value of the reset delay time tRD along with the reset undervoltage threshold VRT,UV,th, see Table 9. The device sets the selected reset delay time and reset threshold during initialization phase. The value of the overvoltage reset threshold VRT,OV,th is fixed. Reset reaction time If the output voltage of the regulator drops below the output undervoltage reset threshold VRT,UV,th or rises above the output overvoltage reset threshold VRT,OV,th, then this triggers the internal output voltage monitoring circuit. If that condition lasts longer than the blanking time tr,blank (see Table 10), then the device sets the reset signal at the RO pin to "low". If the output overvoltage or undervoltage condition lasts shorter than tr,blank, then the device keeps the reset signal "high". This prevents a microcontroller reset due to very short distortions of the output voltage, see Figure 8. Datasheet 29 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Reset Table 9 RT configuration for typical values of power-on, undervoltage, overvoltage reset delay time and undervoltage reset threshold RRT [kΩ]19) tRD,PWR-on [ms] tRD [ms] VRT,UV,th [% of VFB]20) ≤ 1.0 (or connect to GND) 0.06 0.03 -8 2.2 0.06 0.03 -14 3.3 0.06 0.03 -25 4.7 0.06 0.03 -40 6.8 1.9 1.3 -8 10 1.9 1.3 -14 15 1.9 1.3 -25 22 1.9 1.3 -40 33 7.7 5.1 -14 47 7.7 5.1 -25 68 7.7 5.1 -40 100 15.4 10.2 -8 150 15.4 10.2 -14 ≥ 200 (or leave open) 7.7 5.1 -8 VEN VEN,hi VEN,lo VCC Softstart Undervoltage Short undervoltage Undervoltage t Overvoltage t < tr,blank VRT,OV,th VRT,UV,th 1.5 V t VRO tRD,PWR-on tr,blank tRD tr,blank tRD tr,blank tRD VRO,lo t Figure 8 19 20 21 Reset timing diagram21) Resistor tolerance ≤ 5%. In relation to the typical feedback voltage level 3.3 V. The diagram neglects the reset undervoltage hysteresis and reset overvoltage hysteresis to improve the overview. VRO is connected to the output voltage VCC via an external pull-up resistor. The input voltage VVS is set to a level higher than VVS,on. Datasheet 30 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Reset 7.2 Electrical characteristics reset Table 10 Electrical characteristics reset VVS = 6 V to 35 V; Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Number Max. Reset output RO Reset output "low" voltage VRO,lo – – 0.4 V VCC ≥ 1.5 V; VEN ≥ 2 V; IRO ≤ 1.5 mA P_7.2.1 Reset output "low" pull-up current IRO,lo – – 1.5 mA VEN ≥ 2 V; VRO = 0.4 V P_7.2.2 Reset output "high" leakage current IRO,hi – – 1 µA VRO = 3.3 V P_7.2.3 Output overvoltage reset threshold Output overvoltage reset threshold increasing VRT,OV,th 5 7 9 % percentage of VFB P_7.2.4 Output overvoltage reset hysteresis VRT,OV,hys – 1 2 % percentage of VFB P_7.2.5 Output undervoltage reset threshold22) Output undervoltage reset threshold decreasing -8% VRT,UV,th,1 -10 -8 -6 % percentage of VFB P_7.2.6 Output undervoltage reset threshold decreasing -14% VRT,UV,th,2 -16 -14 -12 % percentage of VFB P_7.2.7 Output undervoltage reset threshold decreasing -25% VRT,UV,th,3 -27 -25 -23 % percentage of VFB P_7.2.8 Output undervoltage reset threshold decreasing -40% VRT,UV,th,4 -42 -40 -38 % percentage of VFB P_7.2.9 Output undervoltage reset hysteresis VRT,UV,hys – 1 2 % percentage of VFB P_7.2.10 Reset delay timing22) Power-on reset delay time 60 µs tRD,PWR-on,1 15 60 90 µs – P_7.2.11 Power-on reset delay time 1.9 ms tRD,PWR-on,2 1.7 1.9 2.2 ms – P_7.2.12 Power-on reset delay time 7.7 ms tRD,PWR-on,3 6.9 7.7 8.6 ms – P_7.2.13 Power-on reset delay time 15.4 ms tRD,PWR-on,4 13.9 15.4 17.1 ms – P_7.2.14 22 For RT configuration see Table 9 Datasheet 31 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Reset Table 10 Electrical characteristics reset (continued) VVS = 6 V to 35 V; Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Number Max. Reset delay time 30 µs tRD,1 15 30 95 µs – P_7.2.15 Reset delay time 1.3 ms tRD,2 1.1 1.3 1.5 ms – P_7.2.16 Reset delay time 5.1 ms tRD,3 4.6 5.1 5.7 ms – P_7.2.17 Reset delay time 10.2 ms tRD,4 9.3 10.2 11.4 ms – P_7.2.18 Reset blanking time tr,blank 2 5 10 µs – P_7.2.19 Datasheet 32 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Reset 7.3 Typical performance characteristics reset Output undervoltage reset threshold VVS = 13.5 V Datasheet Output overvoltage reset threshold VVS = 13.5 V 33 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Application information 8 Application information Note: The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. DIN *) LIN **) VBAT CIN3 **) CIN2 CIN1 VS Enable signal (e.g. from IGN) VS EN RFREQ *) Enable UVLO Over temperature shutdown Bandgap reference Internal supply FREQ Control loop + driver Synchronisation signal (e.g. from µC) SYNC SW SSON ON/OFF control for spread spectrum VCC Oscillator PGND High signal (e.g. VCC) LOUT Spread spectrum COUT FB Soft-start ramp generator RRO RT Reset RRT *) RO Reset signal (e.g. indicate output voltage status to µC) AGND *) optional **) optional for improved EMI performance Figure 9 Note: Datasheet Application diagram This figure is a simplified example of an application circuit. The function must be verified in the application. 34 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Application information Table 11 Recommended values for components in the application diagram Name Value23) Switching frequency Component type CIN1 100 nF – Ceramic X7R capacitor; 50 V CIN2 10 µF – Ceramic X7R capacitor; 50 V LOUT 22 µH 320 kHz to 560 kHz Shielded power inductor; ISAT > IBUOC DCR < 70 mΩ COUT 88 µF24) 320 kHz to 560 kHz 22 µF (x4) ceramic X7R capacitor; 16 V LOUT 2.2 µH 1.6 MHz to 2.8 MHz Shielded power inductor; ISAT > IBUOC DCR < 70 mΩ COUT 44 µF24) 1.6 MHz to 2.8 MHz 22 µF (x2) ceramic X7R capacitor; 16 V 23 24 Typical condition For maintenance of loop stability it is recommended to use capacitors with a limited voltage derating at the typical output voltage level. A capacitor in parallel can be added to match the recommended typical capacitance value as close as possible. Datasheet 35 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Application information 8.1 Layout recommendations Introduction A switch mode power supply is a potential source of electromagnetic disturbance, which may affect the application environment as well as the device itself. This can lead to sporadic malfunction including regulator instability or irreversible damage depending on the amount of generated disturbance. Main types of electromagnetic disturbance: • Radiated emission • Conducted emission Radiated emission Radiated emission is caused by circulating currents and voltage oscillations. Alternating currents appear in so called current windows, which are defined by the area of the circulating current within the corresponding filter stage at the input or the output of the regulator. Voltage oscillations are mainly caused by resonant circuits induced by parasitic inductance and capacitance of the PCB layout. The following PCB layout design recommendations help to minimize radiated emission: • Place external components close to the device to reduce parasitic elements of the PCB layout and to keep the area of circulating currents small. At the same time some distance should be kept between the components to avoid coupling. • Reduce the switching area at pin SW to minimize the inductance and especially the parasitic capacitance. The parasitic capacitance can be further reduced by removing inner GND layers below the switching area. Routing of other signal traces below the switching area should be avoided generally. • Use GND layers to shield areas with alternating currents or voltage oscillations. Conducted emission Conducted emission consists of voltage oscillations, which occur permanently or by occasion at the regulator input or output connection. Their frequency range can exceed 100 MHz and they are superimposed to the input voltage VVS and to the output voltage VCC. This might disturb other components of the application. Countermeasures against conducted disturbances are the same as against radiated emission. The following recommendations can further reduce the conducted emission: • Reduce high frequency conducted emission by placing well connected small ceramic filter capacitors (1 nF to 220 nF) with low ESR and low ESL in parallel to the input capacitors as close as possible to the input pin VS and in parallel to the output capacitor COUT close to the output inductor LOUT. • Reduce noise injected into the battery supply line by using a π-filter, for example consisting of CIN1, CIN2, CIN3 and LIN. This requires additional capacitors and an inductor. The filter must be designed according to the requirements of the application. 8.2 Additional information Please contact Infineon: • for information regarding the pin behavioral assessment • for application notes with more detailed information about this device • for any further information visit https://www.infineon.com/ Datasheet 36 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Package information 2) 0.25±0.05 0.25 0.1 2x 0.67±0.25 0.08 C Coplanarity 6±0.2 A-B C 14x 0.2 D 14x Bottom View A Index Marking 14 8 8 14 1 7 7 1 B 0°...8° C Seating Plane 1) 3.9±0.1 0.65 4±0.1 2.65±0.1 0.1 2x 1.15 Max. 1) 4.9±0.1 (0.2) 0.05±0.05 Standoff Package information (0.95) 9 0.15 0.15 D A-B 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width. All dimensions are in units mm The drawing is in compliance with ISO 128-30, Projection Method 1 [ ] Figure 10 PG-TSDSO-14 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a Green Product. Green Products are RoHS compliant (Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Information on alternative packages Please visit www.infineon.com/packages. Datasheet 37 Rev. 1.02 2021-02-05 OPTIREG™ switcher TLS4120D0EPV33 2.8 MHz synchronous step down regulator Revision history Revision history Version Date Changes Rev. 1.02 2021-02-05 Editorial changes Rev. 1.01 2020-10-15 Editorial changes Rev. 1.0 Datasheet 2020-03-20 Initial datasheet 38 Rev. 1.02 2021-02-05 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-02-05 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-Z8F61113666 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 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