Low Dropout Linear Voltage Regulator
TLS820F1ELV50
TLS820F1ELV50
Linear Voltage Regulator
Data Sheet
Rev. 1.0, 2016-04-28
Automotive Power
TLS820F1ELV50
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment TLS820F1ELV50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions TLS820F1ELV50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
4.1
4.2
4.3
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Block Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Characteristics Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Characteristics Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Characteristics Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Characteristics Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Characteristics Standard Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
13
16
17
18
19
20
24
25
30
6
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.5
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection of External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
31
32
33
33
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data Sheet
2
Rev. 1.0, 2016-04-28
Low Dropout Linear Voltage Regulator
1
TLS820F1ELV50
Overview
Features
•
Wide Input Voltage Range from 3.0 V to 40 V
•
Fixed Output Voltage 5 V
•
Output Voltage Precision ≤ ±2 %
•
Output Current Capability up to 200 mA
•
Ultra Low Current Consumption typ. 40 µA
•
Very Low Dropout Voltage typ. 70 mV @100 mA
•
Stable with Ceramic Output Capacitor of 1 µF
•
Delayed Reset at Power-On with 2 Programmable Delay Times 8.5 ms
/ 16.5 ms
•
Adjustable Reset Threshold down to 2.50 V
•
Watchdog with flexible timings: 16 ms / 32 ms / 48 ms / 96 ms
•
Enable, Undervoltage Reset, Overtemperature Shutdown
•
Output Current Limitation
•
Wide Temperature Range
•
Green Product (RoHS compliant)
•
AEC Qualified
Data Sheet
Figure 1
3
PG-SSOP-14
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Overview
Functional Description
The TLS820F1ELV50 is a high performance very low dropout linear voltage regulator for 5 V supply in a PGSSOP-14 package.
With an input voltage range of 3 V to 40 V and very low quiescent of only 40 µA, these regulators are perfectly
suitable for automotive or any other supply systems connected to the battery permanently. The TLS820F1ELV50
provides an output voltage accuracy of 2 % and a maximum output current up to 200 mA.
The new loop concept combines fast regulation and very good stability while requiring only one small ceramic
capacitor of 1 µF at the output. At currents below 100 mA the device will have a very low typical dropout voltage
of only 70 mV. The operating range starts already at input voltages of only 3 V (extended operating range). This
makes the TLS820F1ELV50 also suitable to supply automotive systems that need to operate during cranking
condition.
The device can be switched on and off by the Enable feature as described in Chapter 5.5.
The output voltage is supervised by the Reset feature, including Undervoltage Reset, delayed Reset at Power-On
and an adjustable lower Reset Threshold, more details can be found in Chapter 5.7.
In addition, a Watchdog circuit with flexible timings is integrated to monitor the microcontroller‘s operation.
Internal protection features like output current limitation and overtemperature shutdown are implemented to
protect the device against immediate damage due to failures like output short circuit to GND, over-current and
over-temperatures.
Choosing External Components
An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for
the stability of the regulating circuit. TLS820F1ELV50 is designed to be also stable with low ESR ceramic
capacitors.
Type
Package
Marking
TLS820F1ELV50
PG-SSOP-14
820F1V50
Data Sheet
4
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Diagram
2
Block Diagram
I
Q
Current
Limitation
Reset
EN
RADJ
Enable
WI
RO
Bandgap
Reference
Temperature
Shutdown
DT1
DT2
Watchdog
WO
GND
Figure 2
Data Sheet
Block Diagram TLS820F1ELV50
5
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment TLS820F1ELV50
I
n.c.
EN
n.c.
GND
n.c.
WI
1
2
3
4
5
6
7
SSOP-14
14
13
12
11
10
9
8
Q
n.c.
WO
RO
DT2
DT1
RADJ
Figure 3
Pin Configuration
3.2
Pin Definitions and Functions TLS820F1ELV50
Pin
Symbol
Function
1
I
Input
It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close
to the IC terminals, in order to compensate line influences. See also Chapter 6.2.1
2, 4, 6
n.c.
not connected
Leave open or connect to GND
3
EN
Enable (integrated pull-down resistor)
Enable the IC with high level input signal;
Disable the IC with low level input signal;
5
GND
Ground
7
WI
Watchdog Input (integrated pull-down resistor)
Serve Watchdog with trigger input signal (usable for microcontroller monitoring)
8
RADJ
Reset Threshold Adjustment
Connect to GND to use standard value;
Connect an external voltage divider to adjust reset threshold
9
DT1
Delay Timing 1 (integrated pull-down resistor)
Connect to GND or Q to select Reset timing acc. to Table 7
Connect to GND or Q to select Watchdog timing acc. to Table 10
10
DT2
Delay Timing 2 (integrated pull-down resistor)
Connect to GND or Q to select Watchdog timing acc. to Table 10
11
RO
Reset Output (integrated pull-up resistor to Q)
Open collector output;
Leave open if the reset function is not needed
12
WO
Watchdog Output (integrated pull-up resistor to Q)
Open collector output;
Leave open if the watchdog function is not needed
Data Sheet
6
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Pin Configuration
Pin
Symbol
Function
13
n.c.
not connected
Leave open or connect to GND
14
Q
Output Voltage
Connect output capacitor CQ to GND close to the IC’s terminals, respecting the
values specified for its capacitance and ESR in “Functional Range” on Page 9
Pad
–
Exposed Pad
Connect to heatsink area;
Connect to GND
Data Sheet
7
Rev. 1.0, 2016-04-28
TLS820F1ELV50
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note /
Number
Test Condition
-0.3
–
45
V
–
P_4.1.1
-0.3
–
7
V
–
P_4.1.3
Input I, Enable EN
Voltage
VI, VEN
Output Q, Reset Output RO, Watchdog Output WO
Voltage
VQ, VRO,
VWO
Watchdog Input WI, Delay Timing DT1 and DT2, Reset Threshold Adjustment RADJ
Voltage
VWI,VDT1,
-0.3
VDT2, VRADJ
–
7
V
–
P_4.1.5
Tj
Tstg
-40
–
150
°C
–
P_4.1.7
-55
–
150
°C
–
P_4.1.8
-2
–
2
kV
2)
HBM
P_4.1.9
V
3)
CDM
P_4.1.10
V
3)
CDM
P_4.1.11
Temperatures
Junction Temperature
Storage Temperature
ESD Absorption
VESD
ESD Susceptibility to GND
VESD
ESD Susceptibility Pin 1, 7, 8, 14 (corner VESD1,7,8,14
ESD Susceptibility to GND
-500
-750
–
–
500
750
pins) to GND
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Note:
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
8
Rev. 1.0, 2016-04-28
TLS820F1ELV50
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Input Voltage Range
VI
VI,ext
VEN
CQ
Values
Min.
Extended Input Voltage Range
Enable Voltage Range
Output Capacitor’s
Requirements for Stability
ESR
Junction Temperature
1)
2)
3)
4)
Typ.
VQ,nom + Vdr –
Unit
Note /
Test Condition
Number
V
1)
–
P_4.2.1
–
P_4.2.3
Max.
40
3.0
–
40
V
2)
0
–
40
V
–
1
ESR(CQ) –
Tj
-40
P_4.2.5
–
–
µF
3)4)
–
100
Ω
3)
–
150
°C
–
–
–
P_4.2.6
P_4.2.7
P_4.2.9
Output current is limited internaly and depends on the input voltage, see Electrical Characteristics for more details.
When VI is between VI,ext,min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V.
Not subject to production test, specified by design.
The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
Data Sheet
9
Rev. 1.0, 2016-04-28
TLS820F1ELV50
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3
Thermal Resistance
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
P_4.3.1
Min.
Typ.
Max.
–
9
–
K/W
1)
–
43
–
K/W
1)2)
Junction to Ambient
RthJC
RthJA
RthJA
–
128
–
Junction to Ambient
RthJA
–
58
Junction to Ambient
RthJA
–
50
Package Version PG-SSOP-14
Junction to Case
Junction to Ambient
–
2s2p board
P_4.3.2
K/W
1)3)
1s0p board,
footprint only
P_4.3.3
–
K/W
1)3)
1s0p board,
300 mm2 heatsink
area on PCB
P_4.3.4
–
K/W
1)3)
P_4.3.5
1s0p board,
600 mm2 heatsink
area on PCB
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
10
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5
Block Description and Electrical Characteristics
5.1
Voltage Regulation
The output voltage VQ is divided by a resistor network. This fractional voltage is compared to an internal voltage
reference and the pass transistor is driven accordingly.
The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the
internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent series
resistor (ESR) requirements given in “Functional Range” on Page 9 have to be maintained. For details, also see
the typical performance graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on
Page 14. As the output capacitor also has to buffer load steps, it should be sized according to the application’s
needs.
An input capacitor CI is recommended to compensate line influences. In order to block influences like pulses and
HF distortion at input side, an additional reverse polarity protection diode and a combination of several capacitors
for filtering should be used. Connect the capacitors close to the component’s terminals.
In order to prevent overshoots during start-up, a smooth ramp up function is implemented. This ensures almost
no output voltage overshoots during start-up, mostly independent from load and output capacitance.
Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited
and the output voltage decreases.
The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g.
output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed. However, junction
temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.
Supply
II
I
Q
Current
Limitation
Reset
EN
CI
RO
RADJ
Enable
VI
Bandgap
Reference
Temperature
Shutdown
WI
Regulated
Output Voltage
IQ
C
VQ
ESR
DT1
LOAD
CQ
DT2
Watchdog
WO
GND
Figure 4
Voltage Regulation
V
VQ,nom
VI,ext,min
VI
Vdr
VQ
t
Figure 5
Data Sheet
Output Voltage vs. Input Voltage
11
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
Table 4
Electrical Characteristics Voltage Regulator 5 V version
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Unit
Note / Test Condition
Number
Min.
Typ.
Max.
Output Voltage Precision
VQ
4.9
5.0
5.1
V
0.05 mA < IQ < 200 mA
5.44 V < VI < 28 V
P_5.1.1
Output Voltage Precision
VQ
4.9
5.0
5.1
V
0.05 mA < IQ < 100 mA
5.27 V < VI < 40 V
P_5.1.2
Output Voltage Start-up
slew rate
dVQ/dt
3.0
7.5
18
V/ms VI > 18 V/ms
CQ = 1 µF
0.5 V < VQ < 4.5 V
Output Current Limitation
IQ,max
201
∆VQ,load -15
350
550
mA
0 V < VQ < 4.8 V
P_5.1.8
-1.5
5
mV
P_5.1.10
Line Regulation
steady-state
∆VQ,line
-20
0
20
mV
P_5.1.12
Dropout Voltage
Vdr = VI - VQ
Vdr
–
140
340
mV
IQ = 0.05 mA to 200 mA
VI = 6 V
VI = 8 V to 32 V
IQ = 1 mA
1)
IQ = 200 mA
Dropout Voltage
Vdr = VI - VQ
Vdr
–
70
170
mV
1)
IQ = 100 mA
P_5.1.15
Power Supply Ripple Rejection
PSRR
–
59
–
dB
2)
fripple = 100 Hz
P_5.1.18
Load Regulation
steady-state
Values
Overtemperature Shutdown
Threshold
Tj,sd
151
–
200
°C
Overtemperature Shutdown
Threshold Hysteresis
Tj,sdh
–
15
–
K
Vripple = 0.5 Vpp
2)
Tj increasing
2)
P_5.1.7
P_5.1.14
P_5.1.19
Tj decreasing
P_5.1.20
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V
2) Not subject to production test, specified by design
Data Sheet
12
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.2
Typical Performance Characteristics Voltage Regulator
Typical Performance Characteristics
Output Voltage VQ versus
Junction Temperature Tj
Dropout Voltage Vdr versus
Junction Temperature Tj
300
IQ = 100 mA
IQ = 100mA
IQ = 200 mA
5.15
250
VQ = 5 V
5.1
200
Vdr [mV]
VQ [V]
5.05
5
150
4.95
100
4.9
50
4.85
4.8
0
50
Tj [°C]
100
0
150
Load Regulation ∆VQ,load versus
Output Current Change IQ
0
50
Tj [°C]
100
150
Line Regulation ∆VQ,line versus
Input Voltage VI
0
8
−0.5
6
−1
4
2
−2
ΔVQ,line [mV]
ΔVQ,load [mV]
−1.5
−2.5
−3
0
−2
−3.5
VI = 6 V
−4
IQ = 1 mA
Tj = −40 °C
−4
Tj = −40 °C
Tj = 25 °C
−4.5
−6
Tj = 25 °C
Tj = 150 °C
−5
0
Data Sheet
50
100
IQ [mA]
150
Tj = 150 °C
−8
200
13
10
15
20
VI [V]
25
30
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
Output Voltage VQ versus
Input Voltage VI
Power Supply Ripple Rejection PSRR versus
ripple frequency f
80
6
Tj = −40 °C
Tj = 25 oC
Tj = 25 °C
70
Tj = 150 °C
5
IQ = 100 mA
60
4
PSRR [dB]
VQ [V]
50
3
40
30
2
20
1
IQ = 10 mA
CQ = 1 μF
Vripple = 0.5 Vpp
10
0
0
1
2
3
VI [V]
4
5
0
−2
10
6
−1
10
0
1
10
10
2
10
3
10
f [kHz]
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
Maximum Output Current IQ versus
Input Voltage VI
3
10
800
Tj = −40 °C
Tj = 25 °C
700
Unstable Region
Tj = 150 °C
2
10
600
500
Stable Region
IQ,max [mA]
ESR(CQ) [Ω]
1
10
VQ = 0 V
0
10
400
300
200
−1
10
CQ = 1 μF
100
o
−2
10
0.05
Data Sheet
Tj = 25 C
1
10
IQ [mA]
100
0
500
14
0
10
20
VI [V]
30
40
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
Dropout Voltage Vdr versus
Output Current IQ
300
Tj = 25 oC
250
Vdr [mV]
200
150
100
50
0
0
Data Sheet
50
100
IQ [mA]
150
200
15
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.3
Current Consumption
Table 5
Electrical Characteristics Current Consumption
Tj = -40 °C to +150 °C, VI = 13.5 V (unless otherwise specified)
Typical values are given at Tj = 25 °C
Conditions of other pins: DT1 = DT2 = WI = GND
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note / Test Condition
Number
Current Consumption
Iq = II
Iq,off
–
1.3
5
µA
VEN = 0 V; Tj < 105 °C
P_5.3.1
Current Consumption
Iq,off
–
–
8
µA
VEN = 0.4 V; Tj < 125 °C
P_5.3.3
Iq
–
40
52
µA
IQ = 0.05 mA
Tj = 25 °C
P_5.3.4
Iq = II
Current Consumption
Iq = II - IQ
Watchdog enabled
Current Consumption
Iq = II - IQ
Iq
–
62
77
µA
IQ = 0.05 mA
Tj < 125 °C
P_5.3.7
Watchdog enabled
Current Consumption
Iq = II - IQ
Iq
–
62
80
µA
1)
IQ = 200 mA
Tj < 125 °C
P_5.3.9
Watchdog enabled
1) Not subject to production test, specified by design
Data Sheet
16
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.4
Typical Performance Characteristics Current Consumption
Typical Performance Characteristics
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Input Voltage VI
100
200
Tj = −40 °C
90
180
80
160
70
140
60
120
Iq [uA]
Iq [uA]
Tj = 25 °C
50
80
30
60
20
40
10
20
0
Data Sheet
50
100
IQ [mA]
150
0
200
17
Tj = 150 °C
VEN = 5 V
IQ = 50 uA
100
40
0
Tj = 25 °C
5
10
15
20
25
VI [V]
30
35
40
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.5
Enable
The TLS820F1ELV50 can be switched on and off by the Enable feature: Connect a HIGH level as specified below
(e.g. the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to
shut it down. The enable has a built in hysteresis to avoid toggling between ON/OFF state, if signals with slow
slopes are applied to the EN input.
Table 6
Electrical Characteristics Enable
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
VEN,H
Low Level Input Voltage
VEN,L
Enable Threshold Hysteresis
VEN,Hy
High Level Input Current
IEN,H
High Level Input Current
IEN,H
Enable internal pull-down resistor REN
High Level Input Voltage
Data Sheet
Values
Unit
Note / Test Condition
Number
P_5.5.1
Min.
Typ.
Max.
2
–
–
V
–
–
0.8
V
VQ settled
VQ ≤ 0.1 V
100
–
–
mV
–
P_5.5.3
–
–
3.5
µA
P_5.5.4
–
–
22
µA
VEN = 3.3 V
VEN ≤ 18 V
0.95
1.5
2.6
MΩ
–
P_5.5.7
18
P_5.5.2
P_5.5.6
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.6
Typical Performance Characteristics Enable
Typical Performance Characteristics
Input Current IIN versus
Input Voltage VIN (condition: VEN = 0 V)
Enabled Input Current IEN versus
Enabled Input Voltage VEN
50
30
Tj = −40 °C
Tj = 25 °C
25
Tj = −40 °C
45
Tj = 150 °C
Tj = 25 °C
Tj = 150 °C
40
VEN = 0V
35
20
IEN [uA]
IIN [uA]
30
15
25
20
10
15
10
5
5
0
0
10
20
VIN [V]
30
0
40
0
10
20
VEN [V]
30
40
Output Voltage VQ versus
time (EN switched ON)
6
5
VQ, VEN [V]
4
3
2
IQ = 100 mA
Tj = −40 °C
Tj = 25 °C
1
Tj = 150 °C
VEN
0
0
Data Sheet
500
1000
t [us]
1500
2000
19
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.7
Reset
The TLS820F1ELV50’s output voltage is supervised by the Reset feature, including Undervoltage Reset, delayed
Reset at Power-On and an adjustable Reset Threshold.
The Undervoltage Reset function sets the pin RO to LOW, in case VQ is falling for any reason below the Reset
Threshold VRT,low.
When the regulator is powered on, the pin RO is held at LOW for the duration of the Power-On Reset Delay Time
trd.
I
Q
VDD
CQ
RRO,int
Control
RO
S
Reference
OR
R
optional
Supply
Reset
IRO
Q
RADJ ,1
OR
MicroController
RADJ
IRADJ
GND
opti onal
Timer
DT1
RADJ ,2
Figure 6
GND
Block Diagram Reset Circuit
Reset Delay Time
The pin DT1 is used to set the desired Reset Delay Time trd. Connect this pin either to GND or Q to select the
timing according to Table 7.
Table 7
Reset DelayTime Selection
DT1 connected to
trd
GND
16.5 ms
Q
8.5 ms
Power-On Reset Delay Time
The power-on reset delay time is defined by the parameter trd and allows a microcontroller and oscillator to start
up. This delay time is the time period from exceeding the upper reset switching threshold VRT,high until the reset is
released by switching the reset output “RO” from “LOW” to “HIGH”.
Undervoltage Reset Delay Time
Unlike the power-on reset delay time, the undervoltage reset delay time is defined by the parameter trd and
considers an output undervoltage event where the output voltage VQ trigger the VRT,low threshold.
Reset Blanking Time
The reset blanking time trr,blank avoids that short undervoltage spikes trigger an unwanted reset “low” signal.
Data Sheet
20
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
Reset Reaction Time
In case the output voltage of the regulator drops below the output undervoltage lower reset threshold VRT,low, the
reset output “RO” is set to low, after the delay of the internal reset reaction time trr,int. The reset blanking time trr,blank
is part of the reset reaction time trr,int.
Reset Output “RO”
The reset output “RO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic “RO”
signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the maximum “RO” sink
current is limited, the minimum value of the optional external resistor “RRO,ext” is given in Table “Reset Output
RO” on Page 23.
Reset Output “RO” Low for VQ ≥ 1 V
In case of an undervoltage reset condition reset output “RO” is held “low” for VQ ≥ 1 V, even if the input “I” is not
supplied and the voltage VI drops below 1 V. This is achieved by supplying the reset circuit from the output
capacitor.
Reset Adjust Function
The undervoltage reset switching threshold can be adjusted according to the application’s needs by connecting
an external voltage divider (RADJ1, RADJ2) at pin “RADJ”. For selecting the default threshold connect pin “RADJ” to
GND. The reset adjustment range for the TLS820F1ELV50 is given in Reset Threshold Adjustment Range.
When dimensioning the voltage divider, take into consideration that there will be an additional current constantly
flowing through the resistors.
With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows
(neglecting the Reset Adjust Pin Current IRADJ):
VRT,lo,new = VRADJ,th × (RADJ,1 + RADJ,2) / RADJ,2
(1)
with
•
•
•
VRT,lo,new: Desired undervoltage reset switching threshold.
RADJ,1, RADJ,2: Resistors of the external voltage divider, see Figure 6.
VRADJ,th: Reset adjust switching threshold given in Reset Adjustment Switching Threshold.
Data Sheet
21
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
VI
t
VQ
t < trr,blank
VRH
VRT,hi gh
VRT,low
1V
t
trd
trr,int
trd
trr,int
trd
trr,int
VRO
trd
VRO,low
1V
t
Thermal
Shutdown
Figure 7
Data Sheet
Input
Voltage Dip
Undervoltage
Spike at
output
Over load
Typical Timing Diagram Reset
22
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
Table 8
Electrical Characteristics Reset
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ. Max.
Number
Output Undervoltage Reset 5V Version only
Output Undervoltage Reset Upper
Switching Threshold
VRT,high
4.6
4.7
4.8
V
VQ increasing
P_5.7.1
Output Undervoltage Reset Lower
Switching Threshold - Default
VRT,low
4.5
4.6
4.7
V
VQ decreasing
P_5.7.2
Output Undervoltage Reset
Switching Hysteresis
VRT,hy
60
100
–
mV
RADJ connected to GND P_5.7.3
Output Undervoltage Reset
Headroom VQ - VRT
VRH
200
400
–
mV
RADJ = GND
P_5.7.4
VRADJ,th
1.15
1.20
1.25
V
–
P_5.7.9
2.5
–
4.4
V
for VQ,nom = 5 V
P_5.7.10
P_5.7.12
RADJ = GND
Reset Threshold Adjustment
Reset Adjustment Switching
Threshold
Reset Threshold Adjustment Range VRT,range
Reset Output RO
Reset Output Low Voltage
VRO,low
–
0.2
0.4
V
1 V ≤ VQ ≤ VRT;
RRO ≥ 5.1 kΩ
Reset Output
Internal Pull-Up Resistor
RRO,int
13
20
36
kΩ
internally connected to Q P_5.7.13
Reset Output External
Pull-up Resistor to VQ
RRO,ext
5.1
–
–
kΩ
1 V ≤ VQ ≤ VRT ;
VRO ≤ 0.4 V
P_5.7.14
trd,slow
trd,fast
13.2
16.5
19.8
ms
DT1 connected to GND
P_5.7.20
6.8
8.5
10.2
ms
DT1 connected to Q
P_5.7.21
P_5.7.46
Reset Delay Timing
Reset Delay Time
Reset Delay Time
Reset blanking time
trr,blank
–
7
–
µs
1)
Internal Reset Reaction Time
trr,int
–
10
33
µs
for VQ,nom = 5 V
P_5.7.36
Delay Input DT1
High Signal Valid
VDT1,H
2.0
–
–
V
–
P_5.7.24
Delay Input DT1
Low Signal Valid
VDT1,L
–
–
0.80
V
–
P_5.7.25
Delay Input DT1
Signal Slew Rate
dVDT1/dt
1
–
–
V/µs VDT1,L < VDT1 < VDT1,H
High Level Input Current
IDT1,H
RDT1
–
–
3.5
µA
VDT1 = 3.3 V
P_5.7.27
0.9
1.5
2.6
MΩ
–
P_5.7.28
for VQ,nom = 5 V
Reset Delay Input DT1
Delay Input DT1
internal pull-down resistor
P_5.7.34
1) Not subject to production test, specified by design.
Data Sheet
23
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.8
Typical Performance Characteristics Reset
Typical Performance Characteristics
Undervoltage Reset Threshold VRT versus
Junction Temperature Tj
Power On Reset Delay Time trd versus
Junction Temperature Tj
25
5
fast
slow
IQ = 1 mA
4.9
4.8
20
4.7
trd [ms]
VRT [V]
4.6
4.5
15
4.4
4.3
IQ = 1 mA
VQ = 5 V
RADJ set to GND
4.2
10
VRT, high
4.1
VRT, low
4
0
50
Tj [°C]
100
5
150
0
50
Tj [°C]
100
150
Internal Reset Reaction Time trr,int versus
Junction Temperature Tj
20
18
16
14
trr,int [μs]
12
10
8
6
4
2
0
−40
Data Sheet
0
50
Tj [°C]
100
150
24
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
5.9
Standard Watchdog
The TLS820F1ELV50 features a load dependent watchdog function with a prgrammable watchdog timing. The
watchdog function monitors a microcontroller, including time base failures. In case of a missing falling edge within
a certain pulse repetition time, the watchdog output “WO” is set to “low”.
The watchdog uses an internal oscillator as timebase. The effective trigger window is derived from the watchdog
timebase and can be adjusted by using the pins DT1 and DT2.
The watchdog output “WO” is separated from the reset output “RO”. Hence, the watchdog output might be used
as an interrupt signal for the microcontroller independent from the reset signal. It is possible to interconnect pin
“WO” and pin “RO” in order to establish a wire-or function with a dominant low signal.
I
Q
VDD
CQ
RWO,int
WO
Control
optional
Supply
Reset
I WO
Reference
MicroController
WD core
WI
Control
IWI
GND
Figure 8
DT1
DT2
GND
Block Diagram Watchdog Circuit
Watchdog Timing
By changing the condition on the “DT” pins, the new timing is valid from the beginning of next period. From this
time on, the frequency of the WI signal must be adapted (see also “Typical Watchdog Timing Diagram,
Watchdog and Reset Modes” on Page 26).
Figure 9 shows the state diagram of the watchdog (WD) and the mode selection. After power-on, the reset output
signal at the “RO” pin (microcontroller reset) is kept LOW for the reset delay time trd. With the LOW to HIGH
transition of the signal at “WO” the device starts the watchdog ignore time tWI.i. Next, the WD starts the watchdog
trigger time (time frame within a trigger at WI must occur).
From now on, the timing of the signal on WI from the microcontroller must fit to the WD-trigger time tWI,tr, based on
the setting of the “DT” pins. A Re-Trigger of the WD-trigger time is done with a HIGH-to-LOW transient at the WIpin within the active tWI,tr.
Watchdog Output “WO”
The watchdog output “WO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic
“WO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the maximum “WO”
sink current is limited, the minimum value of the optional external resistor “RWO,ext” is given in Table “Watchdog
Output WO” on Page 28. A HIGH to LOW transition of the watchdog trigger signal on pin WI is taken as a trigger.
A watchdog signal is generated (“WO” goes LOW), if there is no trigger pulse during the Watchdog trigger time.
Data Sheet
25
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
VI
t
VQ
VRT,high
VRT,low
t
DT1
Capture DT1
Capture DT1
Capture DT1
Capture DT1
Capture DT1
Capture DT1
Capture DT1
Capture DT2
DT2
Capture DT2
Setup trd (slow)
Capture DT2
trd
16.5ms typ.
Ignore Time
tWI,i
(WD-trigger time tWI,tr)
48ms *)
VWO
NO WD Trigger
t
WD Trigger
WD Trigger
16ms *)
48ms *)
WD Trigger
96ms *)
WD Trigger
Don’t care WI
during t WO,low and
ignore time
Don’t care WI
during t rd and ignore time
trd
32ms *)
Capture DT2
t
WD Trigger
VWI
96ms *)
32ms
t
Capture DT2
Capture DT2
Capture DT2
Trigger
Capture DT1
t
tWO,low
Normal operation
Normal operation
t
VRO
Power
Fail
trd
trr,int
t
*) watchdog trigger time interrupted by correct WI signal serving the watchdog
Figure 9
Typical Watchdog Timing Diagram, Watchdog and Reset Modes
Watchdog Input “WI”
The watchdog is triggered by a falling edge at the watchdog input pin “WI”. The amplitude and slope of this signal
has to comply with the specification (Table “Watchdog Input WI” on Page 27). For details regarding test pulses,
see Figure 10 “Test Pulses Watchdog Input WI” on Page 26.
VWI
tWI,ph
VWI,high
tWI,pl
VWI,low
Figure 10
Data Sheet
dVWI / dt
t
Test Pulses Watchdog Input WI
26
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
Table 9
Electrical Characteristics Watchdog
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note / Test Condition
Number
ms
–
P_5.9.1
Min.
Typ. Max.
12.8
16
19.2
Watchdog Trigger Time
tWI,i
tWI,tr,1
76.8
96
115.2 ms
DT1 connected to GND;
DT2 connected to GND
P_5.9.2
Watchdog Trigger Time
tWI,tr,2
38.4
48
57.6
ms
DT1 connected to Q;
DT2 connected to GND
P_5.9.3
Watchdog Trigger Time
tWI,tr,3
25.6
32
38.4
ms
DT1 connected to GND;
DT2 connected to Q
P_5.9.4
Watchdog Trigger Time
tWI,tr,4
12.8
16
19.2
ms
DT1 connected to Q;
DT2 connected to Q
P_5.9.5
Watchdog Output Low Time
tWO,low
6.4
8
9.6
ms
–
P_5.9.6
Watchdog Input
Low Signal Valid
VWI,low
–
–
0.8
V
1)
–
P_5.9.16
Watchdog Input
High Signal Valid
VWI,high
2.0
–
–
V
1)
–
P_5.9.17
Watchdog Input
High Signal Pulse Length
tWI,ph
1
–
–
µs
1)
VWI ≥ VWI,high
P_5.9.19
Watchdog Input
Low Signal Pulse Length
tWI,pl
1
–
–
µs
1)
VWI ≤ VWI,low
P_5.9.20
Watchdog Input
Signal Slew Rate
dVWI/dt
1
–
–
V/µs
1)
VWI,low < VWI < VWI,high
P_5.9.21
–
–
3.5
µA
VWI = 3.3 V
P_5.9.22
0.9
1.5
2.6
MΩ
–
P_5.9.23
1.15
–
1.40
V
for VQ,nom = 5 V:
VI > 5.44 V;
P_5.9.31
Watchdog Timing
Watchdog Ignore Time
Watchdog Input WI
IWI,H
Watchdog Input internal pull-down RWI
High Level Input Current
resistor
Watchdog Disable Threshold
WI Signal Value
VWI,dis
signal must be applied for
> tW,filter,max to deactivate
and activate the watchdog
Watchdog Minimum Filter Time
state transition by WI
tWI,filter,min 100
–
–
µs
2)
– see Page 28
P_5.9.25
Watchdog Maximum Filter Time
state transition by WI
tWI,filter,max –
–
500
µs
2)
– see Page 28
P_5.9.26
Watchdog Delay Input DT2 (DT1 is defined in chapter Reset Delay Input DT1)
Delay Input DT2
Low Signal Valid
VDT2,L
–
–
0.8
V
–
P_5.9.27
Delay Input DT2
High Signal Valid
VDT2,H
2.0
–
–
V
–
P_5.9.28
Data Sheet
27
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
Table 9
Electrical Characteristics Watchdog (cont’d)
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Delay Input DT2
Signal Slew Rate
Values
Unit Note / Test Condition
Number
P_5.9.38
Min.
Typ. Max.
1
–
–
V/µs VDTx,L < VDTx < VDTx,H
–
–
3.5
µA
VDTx = 3.3 V
P_5.9.30
0.9
1.5
2.6
MΩ
–
P_5.9.32
150
–
–
µs
2)
VWO,low
RWO,int
–
0.2
0.4
V
RWO > 5.1 kΩ
13
20
36
kΩ
internally connected to pin P_5.9.35
Q
RWO,ext
5.1
–
–
kΩ
VWO ≤ 0.4 V;
dVDT2/dt
IDT2,H
Delay Input DT2 internal pull-down RDT2
High Level Input Current DT2
resistor
Watchdog setup and hold time
(DT1, DT2)
tsetup,hold,
DT
Within the setup and hold P_5.9.33
time phase, a DTx
transition will not be
recognized
Watchdog Output WO
Watchdog Output Low Voltage
Watchdog Output
Internal Pull-Up Resistor
Watchdog Output External
Pull-up Resistor to VQ
P_5.9.34
P_5.9.36
1) For details on applied test pulse, see Figure 10
2) Not subject to production test, specified by design.
Watchdog Trigger Time
Two pins, DT1 and DT2, are used to set the desired Watchdog Trigger Time tWI,tr. Connect these pins either to
GND or to high level (e.g. Q) to select the timing according to Table 10.
Table 10
Watchdog Trigger Time Selection
DT1 connected to
DT2 connected to
tWI,tr,typ
GND
GND
96 ms
Q
GND
48 ms
GND
Q
32 ms
Q
Q
16 ms
Watchdog deactivation by external signal (pin “WI”)
Note: Disabling the watchdog should only considered when the application is not running in the normal operating
conditions as the safe operation is not ensured any more. Example would be the flashing process of the
microcontroller.
The Watchdog can be disabled by connecting a voltage level between the range of 1.15 V to 1.40 V to WI. By
entering the Watchdog deactivation, the “WO” signal behaves like it is described in . The transition from active to
an inactive state will be performed after a dead time of tWI,filter,max, when correct level to WI pin is applied. This
protects against the unintended entering of watchdog deactivation state. After leaving the deactivation voltage
range 1.15 V to 1.40 V, the Watchdog is again active and starts with an ignore window. This scenario is also valid
for the transition from deactivation to activation state.
Data Sheet
28
Rev. 1.0, 2016-04-28
TLS820F1ELV50
Block Description and Electrical Characteristics
VWI
VWI
Scenario „D“
>tWO,low
VWI,dis.high
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