16/32-Bit
Architecture
XC2336A
16/32-Bit Single-Chip Microcontroller with
32-Bit Performance
XC2000 Family / Base Line
Data Sheet
V2.1 2011-07
Microcontrollers
Edition 2011-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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be endangered.
16/32-Bit
Architecture
XC2336A
16/32-Bit Single-Chip Microcontroller with
32-Bit Performance
XC2000 Family / Base Line
Data Sheet
V2.1 2011-07
Microcontrollers
XC2336A
XC2000 Family / Base Line
XC233xA
Revision History: V2.1, 2011-07
Previous Version(s):
V2.0, 2009-03
Page
Subjects (major changes since last revisions)
26
ID registers added
72
ADC capacitances corrected (typ. vs. max.)
76
Conditions relaxed for ΔfINT
Range for fWU adapted according to PCN 2010-013-A
Added startup time from power-on tSPO
127
Quality declarations added
Trademarks
C166™, TriCore™, and DAVE™ are trademarks of Infineon Technologies AG.
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Data Sheet
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Table of Contents
Table of Contents
1
1.1
1.2
1.3
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Basic Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
2.1
2.2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Unit (CAPCOM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . .
MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
31
33
33
34
35
36
39
41
45
47
48
50
51
52
52
53
54
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3
4.3
4.4
4.5
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolut Maximum Rating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
57
57
58
60
60
61
63
65
67
72
76
79
Data Sheet
5
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Table of Contents
4.6
4.6.1
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.3
4.6.4
4.6.5
4.6.6
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wakeup Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting and Changing the Operating Frequency . . . . . . . . . . . . . .
External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
81
82
83
86
86
87
89
92
96
5
5.1
5.2
5.3
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
102
104
105
Data Sheet
6
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Summary of Features
16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
XC233xA (XC2000 Family)
1
Summary of Features
For a quick overview and easy reference, the features of the XC233xA are summarized
here.
•
•
•
•
•
•
•
High-performance CPU with five-stage pipeline and MPU
– 12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16 × 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for code and data
– 1024 Bytes on-chip special function register area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
Interrupt system with 16 priority levels for up to 96 sources
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 12.5 ns
Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
Clock generation from internal or external clock sources,
using on-chip PLL or prescaler
Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
On-chip memory modules
– 8 Kbytes on-chip stand-by RAM (SBRAM)
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– Up to 16 Kbytes on-chip data SRAM (DSRAM)
– Up to 32 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 576 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC)
On-Chip Peripheral Modules
– Multi-functional general purpose timer unit with 5 timers
– 16-channel general purpose capture/compare unit (CAPCOM2)
– Two capture/compare units for flexible PWM signal generation (CCU6x)
Data Sheet
7
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Summary of Features
•
•
•
•
•
•
•
– Two Synchronizable A/D Converters with a total of up to 9 channels, 10-bit
resolution, conversion time below 1 μs, optional data preprocessing (data
reduction, range check), broken wire detection
– Up to 4 serial interface channels to be used as UART, LIN, high-speed
synchronous channel (SPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS
interface
– On-chip MultiCAN interface (Rev. 2.0B active) with up to 64 message objects
(Full CAN/Basic CAN) on up to 2 CAN nodes and gateway functionality
– On-chip system timer and on-chip real time clock
Single power supply from 3.0 V to 5.5 V
Programmable watchdog timer and oscillator watchdog
Up to 40 general purpose I/O lines
On-chip bootstrap loaders
Supported by a full range of development tools including C compilers, macroassembler packages, emulators, evaluation boards, HLL debuggers, simulators,
logic analyzer disassemblers, programming boards
On-chip debug support via Device Access Port (DAP) or JTAG interface
64-pin Green LQFP package, 0.5 mm (19.7 mil) pitch
Data Sheet
8
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Summary of Features
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. This ordering code identifies:
•
•
•
the function set of the corresponding product type
the temperature range:
– SAF-…: -40°C to 85°C
– SAH-…: -40°C to 110°C
the package and the type of delivery.
For ordering codes for the XC233xA please contact your sales representative or local
distributor.
This document describes several derivatives of the XC233xA group:
Basic Device Types are readily available and
Special Device Types are only available on request.
As this document refers to all of these derivatives, some descriptions may not apply to a
specific product, in particular to the special device types.
For simplicity the term XC233xA is used for all derivatives throughout this document.
1.1
Basic Device Types
Basic device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XC233xA Basic Device Types
1)
Derivative
Flash
Memory2)
Capt./Comp. ADC4) Interfaces4)
Modules
Chan.
PSRAM
DSRAM3)
None
1) xx is a placeholder for the available speed grade (in MHz).
2) Specific information about the on-chip Flash memory in Table 3.
3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM.
4) Specific information about the available channels in Table 5.
Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1).
No basic device types are available for the XC233xA.
Data Sheet
9
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Summary of Features
1.2
Special Device Types
Special device types are only available for high-volume applications on request.
Table 2
Synopsis of XC233xA Special Device Types
Derivative1)
Flash
Memory2)
XC2336A72FxxL
576 Kbytes 32 Kbytes
16 Kbytes
CC2
CCU60/1
7+2
2 CAN Nodes,
4 Serial Chan.
XC2336A56FxxL
448 Kbytes 16 Kbytes
16 Kbytes
CC2
CCU60/1
7+2
2 CAN Nodes,
4 Serial Chan.
PSRAM
DSRAM3)
Capt./Comp. ADC4) Interfaces4)
Modules
Chan.
1) xx is a placeholder for the available speed grade (in MHz).
2) Specific information about the on-chip Flash memory in Table 3.
3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM.
4) Specific information about the available channels in Table 5.
Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1).
Data Sheet
10
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Summary of Features
1.3
Definition of Feature Variants
The XC233xA types are offered with several Flash memory sizes. Table 3 describes the
location of the available memory areas for each Flash memory size.
Table 3
Flash Memory Allocation
Total Flash Size
Flash Area A1)
Flash Area B
Flash Area C
576 Kbytes
C0’0000H …
C0’EFFFH
C1’0000H …
C7’FFFFH
CC’0000H …
CC’FFFFH
448 Kbytes
C0’0000H …
C0’EFFFH
C1’0000H …
C5’FFFFH
CC’0000H …
CC’FFFFH
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
Table 4
Flash Memory Module Allocation (in Kbytes)
Total Flash Size
Flash 01)
Flash 1
Flash 2
Flash 3
576 Kbytes
256
256
---
64
448 Kbytes
256
128
---
64
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
The XC233xA types are offered with different interface options. Table 5 lists the
available channels for each option.
Table 5
Interface Channel Association
Total Number
Available Channels
7 ADC0 channels
CH0, CH2, CH4, CH8, CH10, CH13, CH15
2 ADC1 channels
CH0, CH4
2 CAN nodes
CAN0, CAN1
64 message objects
4 serial channels
U0C0, U0C1, U1C0, U1C1
Data Sheet
11
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Summary of Features
The XC233xA types are offered with several SRAM memory sizes. Figure 1 shows the
allocation rules for PSRAM and DSRAM. Note that the rules differ:
•
•
PSRAM allocation starts from the lower address
DSRAM allocation starts from the higher address
For example 8 Kbytes of PSRAM will be allocated at E0’0000h-E0’1FFFh and 8 Kbytes
of DSRAM will be at 00’C000h-00’DFFFh.
E7'FFFFh
(EF'FFFFh)
00'DFFFh
Reserved for
PSRAM
Available
DSRAM
Available
PSRAM
Reserved for
DSRAM
E0'0000h
(E8'0000h)
00'8000h
MC_XC_SRAM_ALLOCATION
Figure 1
Data Sheet
SRAM Allocation
12
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
2
General Device Information
The XC233xA series (16/32-Bit Single-Chip Microcontroller with 32-Bit Performance) is
a part of the Infineon XC2000 Family of full-feature single-chip CMOS microcontrollers.
These devices extend the functionality and performance of the C166 Family in terms of
instructions (MAC unit), peripherals, and speed. They combine high CPU performance
(up to 80 million instructions per second) with extended peripheral functionality and
enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the
application requirements. These derivatives utilize clock generation via PLL and internal
or external clock sources. On-chip memory modules include program Flash, program
RAM, and data RAM.
VAREFVAGND VDDIM VDDI1 VDDP VSS
(1)
(1)
(1)
(3)
(9)
(4)
XTAL1
XTAL2
ESR0
Port 2
11 bit
Port 10
16 bit
Port 6
2 bit
Port 15
2 bit
Port 7
1 bit
Port 5
7 bit
PORST
TRST DAP/JTAG Debug
2 / 4 bit
2 bit
via Port Pins
TESTM
MC_XY _LOGSYMB 64
Figure 2
Data Sheet
XC233xA Logic Symbol
13
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
2.1
Pin Configuration and Definition
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDDPB
ESR0
PORST
XTAL1
XTAL2
P10.15
P10.14
VDDI1
P10.13
P10.12
P10.11
P10.10
P10.9
P10.8
VDDPB
VS S
The pins of the XC233xA are described in detail in Table 6, which includes all alternate
functions. For further explanations please refer to the footnotes at the end of the table.
The following figure summarizes all pins, showing their locations on the four sides of the
package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDPB
P10.7
P10.6
P10.5
P10.4
P10.3
P2.10
VDDI1
P10.2
P10.1
P10.0
P2.9
P2.8
P2.7
VDDPB
VSS
VSS
VDDPB
P5.4
P5.8
P5.10
P5.13
P5.15
VDDI 1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
V DDPB
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDDPB
TESTM
TRST
P7.0
V DDIM
P6.0
P6.1
VDDPA
P15.0
P15.4
VAREF
VAGND
P5.0
P5.2
VDDPB
MC_XY_PIN64
Figure 3
Data Sheet
XC233xA Pin Configuration (top view)
14
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Key to Pin Definitions
•
•
Ctrl.: The output signal for a port pin is selected by bit field PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to
1x00B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
Type: Indicates the pad type and its power supply domain (A, B, M, 1).
– St: Standard pad
– Sp: Special pad e.g. XTALx
– DP: Double pad - can be used as standard or high speed pad
– In: Input only pad
– PS: Power supply pad
Table 6
Pin Definitions and Functions
Pin
Symbol
Ctrl.
Type Function
3
TESTM
I
In/B
Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to VDDPB).
An internal pull-up device will hold this pin high
when nothing is driving it.
4
TRST
I
In/B
Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XC233xA’s debug system.
In this case, pin TRST must be driven low once to
reset the debug system.
An internal pull-down device will hold this pin low
when nothing is driving it.
5
P7.0
O0 / I St/B
Bit 0 of Port 7, General Purpose Input/Output
T3OUT
O1
St/B
GPT12E Timer T3 Toggle Latch Output
T6OUT
O2
St/B
GPT12E Timer T6 Toggle Latch Output
TDO_A
OH /
IH
St/B
JTAG Test Data Output / DAP1 Input/Output
If DAP pos. 0 or 2 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
ESR2_1
I
St/B
ESR2 Trigger Input 1
Data Sheet
15
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
7
P6.0
O0 / I DA/A Bit 0 of Port 6, General Purpose Input/Output
8
Type Function
EMUX0
O1
DA/A External Analog MUX Control Output 0 (ADC0)
BRKOUT
O3
DA/A OCDS Break Signal Output
ADCx_REQG I
TyG
DA/A External Request Gate Input for ADC0/1
U1C1_DX0E
I
DA/A USIC1 Channel 1 Shift Data Input
P6.1
O0 / I DA/A Bit 1 of Port 6, General Purpose Input/Output
EMUX1
O1
DA/A External Analog MUX Control Output 1 (ADC0)
T3OUT
O2
DA/A GPT12E Timer T3 Toggle Latch Output
U1C1_DOUT O3
DA/A USIC1 Channel 1 Shift Data Output
ADCx_REQT I
RyE
DA/A External Request Trigger Input for ADC0/1
ESR1_6
I
DA/A ESR1 Trigger Input 6
P15.0
I
In/A
Bit 0 of Port 15, General Purpose Input
ADC1_CH0
I
In/A
Analog Input Channel 0 for ADC1
P15.4
I
In/A
Bit 4 of Port 15, General Purpose Input
ADC1_CH4
I
In/A
Analog Input Channel 4 for ADC1
T6INA
I
In/A
GPT12E Timer T6 Count/Gate Input
VAREF
VAGND
-
PS/A Reference Voltage for A/D Converters ADC0/1
13
-
PS/A Reference Ground for A/D Converters ADC0/1
14
P5.0
I
In/A
Bit 0 of Port 5, General Purpose Input
ADC0_CH0
I
In/A
Analog Input Channel 0 for ADC0
P5.2
I
In/A
Bit 2 of Port 5, General Purpose Input
ADC0_CH2
I
In/A
Analog Input Channel 2 for ADC0
TDI_A
I
In/A
JTAG Test Data Input
P5.4
I
In/A
Bit 4 of Port 5, General Purpose Input
10
11
12
15
19
ADC0_CH4
I
In/A
Analog Input Channel 4 for ADC0
T3EUDA
I
In/A
GPT12E Timer T3 External Up/Down Control
Input
TMS_A
I
In/A
JTAG Test Mode Selection Input
Data Sheet
16
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
20
P5.8
I
In/A
Bit 8 of Port 5, General Purpose Input
ADC0_CH8
I
In/A
Analog Input Channel 8 for ADC0
ADC1_CH8
I
In/A
Analog Input Channel 8 for ADC1
CCU6x_T12H I
RC
In/A
External Run Control Input for T12 of CCU60/1
CCU6x_T13H I
RC
In/A
External Run Control Input for T13 of CCU60/1
21
22
23
25
26
27
P5.10
I
In/A
Bit 10 of Port 5, General Purpose Input
ADC0_CH10
I
In/A
Analog Input Channel 10 for ADC0
ADC1_CH10
I
In/A
Analog Input Channel 10 for ADC1
BRKIN_A
I
In/A
OCDS Break Signal Input
CCU61_T13
HRA
I
In/A
External Run Control Input for T13 of CCU61
P5.13
I
In/A
Bit 13 of Port 5, General Purpose Input
ADC0_CH13
I
In/A
Analog Input Channel 13 for ADC0
P5.15
I
In/A
Bit 15 of Port 5, General Purpose Input
ADC0_CH15
I
In/A
Analog Input Channel 15 for ADC0
P2.0
O0 / I St/B
Bit 0 of Port 2, General Purpose Input/Output
RxDC0C
I
St/B
CAN Node 0 Receive Data Input
T5INB
I
St/B
GPT12E Timer T5 Count/Gate Input
P2.1
O0 / I St/B
Bit 1 of Port 2, General Purpose Input/Output
TxDC0
O1
St/B
CAN Node 0 Transmit Data Output
T5EUDB
I
St/B
GPT12E Timer T5 External Up/Down Control
Input
ESR1_5
I
St/B
ESR1 Trigger Input 5
P2.2
O0 / I St/B
Bit 2 of Port 2, General Purpose Input/Output
TxDC1
O1
St/B
CAN Node 1 Transmit Data Output
ESR2_5
I
St/B
ESR2 Trigger Input 5
Data Sheet
17
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
28
P2.3
O0 / I St/B
U0C0_DOUT O1
29
30
31
Type Function
St/B
Bit 3 of Port 2, General Purpose Input/Output
USIC0 Channel 0 Shift Data Output
CC2_CC16
O3 / I St/B
CAPCOM2 CC16IO Capture Inp./ Compare Out.
ESR2_0
I
St/B
ESR2 Trigger Input 0
U0C0_DX0E
I
St/B
USIC0 Channel 0 Shift Data Input
U0C1_DX0D
I
St/B
USIC0 Channel 1 Shift Data Input
RxDC0A
I
St/B
CAN Node 0 Receive Data Input
P2.4
O0 / I St/B
Bit 4 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CC2_CC17
O3 / I St/B
CAPCOM2 CC17IO Capture Inp./ Compare Out.
ESR1_0
I
St/B
ESR1 Trigger Input 0
U0C0_DX0F
I
St/B
USIC0 Channel 0 Shift Data Input
RxDC1A
I
St/B
CAN Node 1 Receive Data Input
P2.5
O0 / I St/B
Bit 5 of Port 2, General Purpose Input/Output
U0C0_SCLK
OUT
O1
St/B
USIC0 Channel 0 Shift Clock Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CC2_CC18
O3 / I St/B
CAPCOM2 CC18IO Capture Inp./ Compare Out.
U0C0_DX1D
I
St/B
USIC0 Channel 0 Shift Clock Input
ESR1_10
I
St/B
ESR1 Trigger Input 10
P2.6
O0 / I St/B
Bit 6 of Port 2, General Purpose Input/Output
U0C0_SELO
0
O1
St/B
USIC0 Channel 0 Select/Control 0 Output
U0C1_SELO
1
O2
St/B
USIC0 Channel 1 Select/Control 1 Output
CC2_CC19
O3 / I St/B
CAPCOM2 CC19IO Capture Inp./ Compare Out.
U0C0_DX2D
I
St/B
USIC0 Channel 0 Shift Control Input
RxDC0D
I
St/B
CAN Node 0 Receive Data Input
ESR2_6
I
St/B
ESR2 Trigger Input 6
Data Sheet
18
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
35
P2.7
O0 / I St/B
Bit 7 of Port 2, General Purpose Input/Output
U0C1_SELO
0
O1
St/B
USIC0 Channel 1 Select/Control 0 Output
U0C0_SELO
1
O2
St/B
USIC0 Channel 0 Select/Control 1 Output
CC2_CC20
O3 / I St/B
CAPCOM2 CC20IO Capture Inp./ Compare Out.
U0C1_DX2C
I
St/B
USIC0 Channel 1 Shift Control Input
36
37
Type Function
RxDC1C
I
St/B
CAN Node 1 Receive Data Input
ESR2_7
I
St/B
ESR2 Trigger Input 7
P2.8
O0 / I DP/B Bit 8 of Port 2, General Purpose Input/Output
U0C1_SCLK
OUT
O1
DP/B USIC0 Channel 1 Shift Clock Output
EXTCLK
O2
DP/B Programmable Clock Signal Output
CC2_CC21
O3 / I DP/B CAPCOM2 CC21IO Capture Inp./ Compare Out.
U0C1_DX1D
I
P2.9
O0 / I St/B
DP/B USIC0 Channel 1 Shift Clock Input
Bit 9 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
TxDC1
O2
St/B
CAN Node 1 Transmit Data Output
CC2_CC22
O3 / I St/B
CAPCOM2 CC22IO Capture Inp./ Compare Out.
CLKIN1
I
St/B
Clock Signal Input 1
TCK_A
IH
St/B
DAP0/JTAG Clock Input
If JTAG pos. A is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
If DAP pos. 0 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
Data Sheet
19
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
38
P10.0
O0 / I St/B
39
40
42
Type Function
Bit 0 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
CCU60_CC6
0
O2
St/B
CCU60 Channel 0 Output
CCU60_CC6
0INA
I
St/B
CCU60 Channel 0 Input
ESR1_2
I
St/B
ESR1 Trigger Input 2
U0C0_DX0A
I
St/B
USIC0 Channel 0 Shift Data Input
U0C1_DX0A
I
St/B
USIC0 Channel 1 Shift Data Input
P10.1
O0 / I St/B
Bit 1 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B
USIC0 Channel 0 Shift Data Output
CCU60_CC6
1
O2
St/B
CCU60 Channel 1 Output
CCU60_CC6
1INA
I
St/B
CCU60 Channel 1 Input
U0C0_DX1A
I
St/B
USIC0 Channel 0 Shift Clock Input
U0C0_DX0B
I
St/B
USIC0 Channel 0 Shift Data Input
P10.2
O0 / I St/B
Bit 2 of Port 10, General Purpose Input/Output
U0C0_SCLK
OUT
O1
St/B
USIC0 Channel 0 Shift Clock Output
CCU60_CC6
2
O2
St/B
CCU60 Channel 2 Output
CCU60_CC6
2INA
I
St/B
CCU60 Channel 2 Input
U0C0_DX1B
I
St/B
USIC0 Channel 0 Shift Clock Input
P2.10
O0 / I St/B
Bit 10 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
U0C0_SELO
3
O2
St/B
USIC0 Channel 0 Select/Control 3 Output
CC2_CC23
O3 / I St/B
CAPCOM2 CC23IO Capture Inp./ Compare Out.
U0C1_DX0E
I
St/B
USIC0 Channel 1 Shift Data Input
CAPINA
I
St/B
GPT12E Register CAPREL Capture Input
Data Sheet
20
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
43
P10.3
O0 / I St/B
44
45
46
Type Function
Bit 3 of Port 10, General Purpose Input/Output
CCU60_COU O2
T60
St/B
CCU60 Channel 0 Output
U0C0_DX2A
I
St/B
USIC0 Channel 0 Shift Control Input
U0C1_DX2A
I
St/B
USIC0 Channel 1 Shift Control Input
P10.4
O0 / I St/B
Bit 4 of Port 10, General Purpose Input/Output
U0C0_SELO
3
O1
St/B
USIC0 Channel 0 Select/Control 3 Output
CCU60_COU O2
T61
St/B
CCU60 Channel 1 Output
U0C0_DX2B
I
St/B
USIC0 Channel 0 Shift Control Input
U0C1_DX2B
I
St/B
USIC0 Channel 1 Shift Control Input
ESR1_9
I
St/B
ESR1 Trigger Input 9
P10.5
O0 / I St/B
Bit 5 of Port 10, General Purpose Input/Output
U0C1_SCLK
OUT
O1
St/B
USIC0 Channel 1 Shift Clock Output
CCU60_COU O2
T62
St/B
CCU60 Channel 2 Output
U0C1_DX1B
I
St/B
USIC0 Channel 1 Shift Clock Input
P10.6
O0 / I St/B
Bit 6 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B
USIC0 Channel 0 Shift Data Output
U1C0_SELO
0
O3
St/B
USIC1 Channel 0 Select/Control 0 Output
U0C0_DX0C
I
St/B
USIC0 Channel 0 Shift Data Input
U1C0_DX2D
I
St/B
USIC1 Channel 0 Shift Control Input
CCU60_CTR
APA
I
St/B
CCU60 Emergency Trap Input
Data Sheet
21
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
47
P10.7
O0 / I St/B
52
Bit 7 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
CCU60_COU O2
T63
St/B
CCU60 Channel 3 Output
U0C1_DX0B
51
Type Function
I
St/B
USIC0 Channel 1 Shift Data Input
CCU60_CCP I
OS0A
St/B
CCU60 Position Input 0
T4INB
I
St/B
GPT12E Timer T4 Count/Gate Input
P10.8
O0 / I St/B
Bit 8 of Port 10, General Purpose Input/Output
U0C0_MCLK
OUT
O1
St/B
USIC0 Channel 0 Master Clock Output
U0C1_SELO
0
O2
St/B
USIC0 Channel 1 Select/Control 0 Output
CCU60_CCP I
OS1A
St/B
CCU60 Position Input 1
U0C0_DX1C
St/B
USIC0 Channel 0 Shift Clock Input
I
BRKIN_B
I
St/B
OCDS Break Signal Input
T3EUDB
I
St/B
GPT12E Timer T3 External Up/Down Control
Input
P10.9
O0 / I St/B
Bit 9 of Port 10, General Purpose Input/Output
U0C0_SELO
4
O1
St/B
USIC0 Channel 0 Select/Control 4 Output
U0C1_MCLK
OUT
O2
St/B
USIC0 Channel 1 Master Clock Output
CCU60_CCP I
OS2A
St/B
CCU60 Position Input 2
TCK_B
IH
St/B
DAP0/JTAG Clock Input
If JTAG pos. B is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
If DAP pos. 1 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
T3INB
I
St/B
GPT12E Timer T3 Count/Gate Input
Data Sheet
22
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
53
P10.10
O0 / I St/B
Bit 10 of Port 10, General Purpose Input/Output
U0C0_SELO
0
O1
St/B
USIC0 Channel 0 Select/Control 0 Output
CCU60_COU O2
T63
St/B
CCU60 Channel 3 Output
U0C0_DX2C
I
St/B
USIC0 Channel 0 Shift Control Input
U0C1_DX1A
I
St/B
USIC0 Channel 1 Shift Clock Input
TDI_B
IH
St/B
JTAG Test Data Input
If JTAG pos. B is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
54
55
56
Type Function
P10.11
O0 / I St/B
Bit 11 of Port 10, General Purpose Input/Output
U1C0_SCLK
OUT
O1
St/B
USIC1 Channel 0 Shift Clock Output
BRKOUT
O2
St/B
OCDS Break Signal Output
U1C0_DX1D
I
St/B
USIC1 Channel 0 Shift Clock Input
TMS_B
IH
St/B
JTAG Test Mode Selection Input
If JTAG pos. B is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
P10.12
O0 / I St/B
Bit 12 of Port 10, General Purpose Input/Output
U1C0_DOUT O1
St/B
USIC1 Channel 0 Shift Data Output
TDO_B
OH /
IH
St/B
JTAG Test Data Output / DAP1 Input/Output
If DAP pos. 1 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
U1C0_DX0C
I
St/B
USIC1 Channel 0 Shift Data Input
U1C0_DX1E
I
St/B
USIC1 Channel 0 Shift Clock Input
P10.13
O0 / I St/B
Bit 13 of Port 10, General Purpose Input/Output
U1C0_DOUT O1
St/B
USIC1 Channel 0 Shift Data Output
U1C0_SELO
3
O3
St/B
USIC1 Channel 0 Select/Control 3 Output
U1C0_DX0D
I
St/B
USIC1 Channel 0 Shift Data Input
Data Sheet
23
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
58
P10.14
O0 / I St/B
Bit 14 of Port 10, General Purpose Input/Output
U1C0_SELO
1
O1
St/B
USIC1 Channel 0 Select/Control 1 Output
U0C1_DOUT O2
St/B
USIC0 Channel 1 Shift Data Output
ESR2_2
I
St/B
ESR2 Trigger Input 2
U0C1_DX0C
I
St/B
USIC0 Channel 1 Shift Data Input
P10.15
O0 / I St/B
Bit 15 of Port 10, General Purpose Input/Output
U1C0_SELO
2
O1
St/B
USIC1 Channel 0 Select/Control 2 Output
U0C1_DOUT O2
St/B
USIC0 Channel 1 Shift Data Output
U1C0_DOUT O3
St/B
USIC1 Channel 0 Shift Data Output
U0C1_DX1C
I
St/B
USIC0 Channel 1 Shift Clock Input
60
XTAL2
O
Sp/M Crystal Oscillator Amplifier Output
61
XTAL1
I
Sp/M Crystal Oscillator Amplifier Input
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Voltages on XTAL1 must comply to the core
supply voltage VDDIM.
ESR2_9
I
St/B
ESR2 Trigger Input 9
62
PORST
I
In/B
Power On Reset Input
A low level at this pin resets the XC233xA
completely. A spike filter suppresses input pulses
100 ns safely pass the filter.
The minimum duration for a safe recognition
should be 120 ns.
An internal pull-up device will hold this pin high
when nothing is driving it.
63
ESR0
O0 / I St/B
External Service Request 0
After power-up, ESR0 operates as open-drain
bidirectional reset with a weak pull-up.
U1C0_DX0E
I
St/B
USIC1 Channel 0 Shift Data Input
U1C0_DX2B
I
St/B
USIC1 Channel 0 Shift Control Input
59
Data Sheet
Type Function
24
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
6
VDDIM
-
PS/M Digital Core Supply Voltage for Domain M
Decouple with a ceramic capacitor, see Data
Sheet for details.
24,
41,
57
VDDI1
-
PS/1 Digital Core Supply Voltage for Domain 1
Decouple with a ceramic capacitor, see Data
Sheet for details.
All VDDI1 pins must be connected to each other.
9
VDDPA
-
PS/A Digital Pad Supply Voltage for Domain A
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
Note: The A/D_Converters and ports P5, P6 and
P15 are fed from supply voltage VDDPA.
2,
16,
18,
32,
34,
48,
50,
64
VDDPB
1,
17,
33,
49
VSS
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6 and P15 are fed from supply
voltage VDDPB.
Data Sheet
-
PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected
internally to VSS. To improve the EMC
behavior, it is recommended to connect the
exposed pad to the board ground.
For thermal aspects, please refer to the
Data Sheet. Board layout examples are
given in an application note.
25
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
General Device Information
2.2
Identification Registers
The identification registers describe the current version of the XC233xA and of its
modules.
Table 7
XC233xA Identification Registers
Short Name
Value
Address
SCU_IDMANUF
1820H
00’F07EH
SCU_IDCHIP
3801H
00’F07CH
SCU_IDMEM
30D0H
00’F07AH
SCU_IDPROG
1313H
00’F078H
JTAG_ID
0017’E083H
---
Data Sheet
Notes
marking EES-AA, ES-AA or AA
26
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Functional Description
3
Functional Description
The architecture of the XC233xA combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 4). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XC233xA.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC233xA.
DPRAM
OCDS
Debug Support
DSRAM
DMU
CPU
PMU
Flash
Memory
IMB
PSRAM
MAC Unit
EBC
LXBus Control
External Bus
Control
System Functions
Clock, Reset, Power
Control, StandBy RAM
WDT
MPU
Interrupt & PEC
RTC
LXB us
MCHK
ADC0 ADC1
Module Module
10 -Bit
8-Bit
GPT
CC2
Modules
CCU6 x
Modules
10 -Bit
8-Bit
5
Timers
16
Chan.
3+1
Chan.
each
Periph eral Data Bu s
Interrupt Bus
USICx
Modules
2
Chan.
each
Multi
CAN
Shared
MOs
for
Nodes
Analog and Digital General Purpose IO (GPIO) Ports
MC_BL_BLOCKDIAGRAM
Figure 4
Data Sheet
Block Diagram
27
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XC233xA is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC233xA Memory Map 1)
Address Area
Start Loc.
End Loc.
Area Size2)
Notes
IMB register space
FF’FF00H
FF’FFFFH
256 Bytes
–
Reserved (Access trap) F0’0000H
FF’FEFFH
0 mA;
not subject to
production test
not subject to
production test
not subject to
production test
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 13
Operating Conditions (cont’d)
Parameter
Symbol
Values
Unit
Note /
Test Condition
mA
not subject to
production test
Min.
Typ.
Max.
Σ|IOV|
SR
−
−
50
Digital core supply voltage VDDIM
for domain M8)
CC
−
1.5
−
Digital core supply voltage VDDI1
for domain 18)
CC
−
1.5
−
−
5.5
V
0
−
V
Absolute sum of overload
currents
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 4.5
Digital ground voltage
VSS SR
−
1) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate
buffer capacitors with the recomended values shall be connected as close as possible to each VDDIM and VDDI1
pin to keep the resistance of the board tracks below 2 Ohm. Connect all VDDI1 pins together. The minimum
capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values
slightly increase the startup time.
2) Use one Capacitor for each pin.
3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the PAD properties
section.
4) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
5) The operating frequency range may be reduced for specific device types. This is indicated in the device
designation (...FxxL). 80 MHz devices are marked ...F80L.
6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin ((IOV < 0). The absolute sum of input
overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified
limits. Proper operation under overload conditions depends on the application. Overload conditions must not
occur on pin XTAL1 (powered by VDDIM).
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pins leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.The total current through a pin is |ITOT| = |IOZ|
+ (|IOV| KOV). The additional error current may distort the input voltage on analog inputs.
8) Value is controlled by on-chip regulator
Data Sheet
59
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.1.3
Pad Timing Definition
If not otherwise noted, all timing parameters are tested and are valid for the
corresponding output pins operating in strong driver, fast edge mode.
See also “Pad Properties” on Page 89.
4.1.4
Parameter Interpretation
The parameters listed in the following include both the characteristics of the XC233xA
and its demands on the system. To aid in correctly interpreting the parameters when
evaluating them for a design, they are marked accordingly in the column “Symbol”:
CC (Controller Characteristics):
The logic of the XC233xA provides signals with the specified characteristics.
SR (System Requirement):
The external system must provide signals with the specified characteristics to the
XC233xA.
Data Sheet
60
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.2
DC Parameters
These parameters are static or average values that may be exceeded during switching
transitions (e.g. output current).
Leakage current is strongly dependent on the operating temperature and the voltage
level at the respective pin. The maximum values in the following tables apply under worst
case conditions, i.e. maximum temperature and an input level equal to the supply
voltage.
The value for the leakage current in an application can be determined by using the
respective leakage derating formula (see tables) with values from that application.
The pads of the XC233xA are designed to operate in various driver modes. The DC
parameter specifications refer to the pad current limits specified in Section 4.6.4.
Supply Voltage Restrictions
The XC233xA can operate within a wide supply voltage range from 3.0 V to 5.5 V.
However, during operation this supply voltage must remain within 10 percent of the
selected nominal supply voltage. It cannot vary across the full operating voltage range.
Because of the supply voltage restriction and because electrical behavior depends on
the supply voltage, the parameters are specified separately for the upper and the lower
voltage range.
During operation, the supply voltages may only change with a maximum speed of
dV/dt < 1 V/ms.
During power-on sequences, the supply voltages may only change with a maximum
speed of dV/dt < 5 V/μs, i.e. the target supply voltage may be reached earliest after
approx. 1 μs.
Note: To limit the speed of supply voltage changes, the employment of external buffer
capacitors at pins VDDPA/VDDPB is recommended.
Data Sheet
61
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Pullup/Pulldown Device Behavior
Most pins of the XC233xA feature pullup or pulldown devices. For some special pins
these are fixed; for the port pins they can be selected by the application.
The specified current values indicate how to load the respective pin depending on the
intended signal level. Figure 13 shows the current paths.
The shaded resistors shown in the figure may be required to compensate system pull
currents that do not match the given limit values.
VDDP
Pullup
Pulldown
VSS
MC_XC2X_PULL
Figure 13
Data Sheet
Pullup/Pulldown Current Definition
62
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.2.1
DC Parameters
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 14 is valid under the following conditions:
VDDP ≥ 4.5 V; VDDPtyp = 5 V; VDDP ≤ 5.5 V
Table 14
DC Characteristics for Upper Voltage Range
Parameter
Symbol
Values
Pin capacitance (digital
inputs/outputs). To be
doubled for double bond
pins.1)
CIO CC
Input Hysteresis2)
HYS CC 0.11 x
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
10
pF
not subject to
production test
−
−
V
RS = 0 Ohm
VDDP
Absolute input leakage
current on pins of analog
ports3)
|IOZ1|
CC
−
10
200
nA
VIN > 0 V;
VIN < VDDP
Absolute input leakage
current for all other pins.
To be doubled for double
bond pins.3)1)4)
|IOZ2|
CC
−
0.2
5
μA
−
0.2
15
μA
TJ ≤ 110 °C;
VIN < VDDP;
VIN > VSS
TJ≤ 150 °C;
VIN < VDDP;
VIN > VSS
−
−
μA
6)
−
−
30
μA
6)
0.7 x
−
VDDP
V
Pull Level Force Current5) |IPLF| SR 250
Pull Level Keep Current7)
|IPLK|
SR
Input high voltage
(all except XTAL1)
VIH SR
Input low voltage
(all except XTAL1)
VIL SR
Output High voltage8)
VOH CC VDDP
VDDP
+ 0.3
−
-0.3
0.3 x
V
VDDP
−
−
V
IOH ≥ IOHmax
−
−
V
IOH ≥ IOHnom9)
- 1.0
VDDP
- 0.4
Data Sheet
63
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 14
DC Characteristics for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Min.
Output Low Voltage8)
VOL CC
Typ.
Unit
Note /
Test Condition
IOL ≤ IOLmax
IOL ≤ IOLnom9)
Max.
−
−
1.0
V
−
−
0.4
V
1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the
normal value. For a list of affected pins refer to the pin definitions table in chapter 2.
2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
3) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
Please refer to the definition of the overload coupling factor KOV.
4) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
5) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull
device: VPIN ≤ VILmax for a pullup; VPIN ≥ VIHmin for a pulldown.
6) These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in
general purpose IO pins.
7) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level: VPIN ≥ VIHmin for a pullup; VPIN ≤ VILmax for a pulldown.
8) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
9) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Data Sheet
64
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.2.2
DC Parameters for Lower Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 15 is valid under the following conditions:
VDDP ≥ 3.0 V; VDDPtyp = 3.3 V; VDDP ≤ 4.5 V
Table 15
DC Characteristics for Lower Voltage Range
Parameter
Symbol
Values
Pin capacitance (digital
inputs/outputs). To be
doubled for double bond
pins.1)
CIO CC
Input Hysteresis2)
HYS CC 0.07 x
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
10
pF
not subject to
production test
−
−
V
RS = 0 Ohm
VDDP
Absolute input leakage
current on pins of analog
ports3)
|IOZ1|
CC
−
10
200
nA
VIN > VSS;
VIN < VDDP
Absolute input leakage
current for all other pins.
To be doubled for double
bond pins.3)1)4)
|IOZ2|
CC
−
0.2
2.5
μA
−
0.2
8
μA
TJ ≤ 110 °C;
VIN < VDDP;
VIN > VSS
TJ ≤ 150 °C;
VIN < VDDP;
VIN > VSS
−
−
−
−
10
μA
0.7 x
−
VDDP
V
Pull Level Force Current5) |IPLF| SR 150
Pull Level Keep Current7)
|IPLK|
SR
Input high voltage
(all except XTAL1)
VIH SR
Input low voltage
(all except XTAL1)
VIL SR
Output High voltage8)
VOH CC VDDP
VDDP
6)
+ 0.3
−
-0.3
6)
0.3 x
V
VDDP
−
−
V
IOH ≥ IOHmax
−
−
V
IOH ≥ IOHnom9)
- 1.0
VDDP
- 0.4
Data Sheet
65
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 15
DC Characteristics for Lower Voltage Range (cont’d)
Parameter
Symbol
Values
Min.
Output Low Voltage8)
VOL CC
Typ.
Unit
Note /
Test Condition
IOL ≤ IOLmax
IOL ≤ IOLnom10)
Max.
−
−
1.0
V
−
−
0.4
V
1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the
normal value. For a list of affected pins refer to the pin definitions table in chapter 2.
2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
3) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
Please refer to the definition of the overload coupling factor KOV.
4) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
5) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull
device: VPIN = VIH for a pulldown.
6) These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in
general purpose IO pins.
7) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level: VPIN >= VIH for a pullup; VPIN VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
10) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Data Sheet
66
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.2.3
Power Consumption
The power consumed by the XC233xA depends on several factors such as supply
voltage, operating frequency, active circuits, and operating temperature. The power
consumption specified here consists of two components:
•
•
The switching current IS depends on the device activity
The leakage current ILK depends on the device temperature
To determine the actual power consumption, always both components, switching current
IS and leakage current ILK must be added:
IDDP = IS + ILK.
Note: The power consumption values are not subject to production test. They are
verified by design/characterization.
To determine the total power consumption for dimensioning the external power
supply, also the pad driver currents must be considered.
The given power consumption parameters and their values refer to specific operating
conditions:
•
•
Active mode:
Regular operation, i.e. peripherals are active, code execution out of Flash.
Stopover mode:
Crystal oscillator and PLL stopped, Flash switched off, clock in domain DMP_1
stopped.
Note: The maximum values cover the complete specified operating range of all
manufactured devices.
The typical values refer to average devices under typical conditions, such as
nominal supply voltage, room temperature, application-oriented activity.
After a power reset, the decoupling capacitors for VDDIM and VDDI1 are charged with
the maximum possible current.
For additional information, please refer to Section 5.2, Thermal Considerations.
Note: Operating Conditions apply.
Table 16
Parameter
Switching Power Consumption
Symbol
ISACT
Power supply current
(active) with all peripherals CC
active and EVVRs on
Values
Min.
Typ.
Max.
−
10 +
0.6 x
10 +
1.0 x
fSYS1)
fSYS1)
0.7
2.0
Power supply current in
ISSO CC −
stopover mode, EVVRs on
Unit
Note /
Test Condition
mA
2)3)
mA
1) fSYS in MHz.
Data Sheet
67
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
2) The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs and the current
consumed by the pin output drivers. A small current is consumed because the drivers input stages are
switched.
In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced to 3 + 0.6 x fSYS.
3) Please consider the additional conditions described in section "Active Mode Power Supply Current".
Active Mode Power Supply Current
The actual power supply current in active mode not only depends on the system
frequency but also on the configuration of the XC233xA’s subsystem.
Besides the power consumed by the device logic the power supply pins also provide the
current that flows through the pin output drivers.
A small current is consumed because the drivers’ input stages are switched.
The IO power domains can be supplied separately. Power domain A (VDDPA) supplies the
A/D converters and Port 6. Power domain B (VDDPB) supplies the on-chip EVVRs and all
other ports.
During operation domain A draws a maximum current of 1.5 mA for each active A/D
converter module from VDDPA.
In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced
to (3 + 0.6×fSYS) mA.
Data Sheet
68
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
IS [mA]
100
ISACTmax
90
80
70
ISACTtyp
60
50
40
30
20
10
20
40
60
80
fSYS [MHz]
MC_XC2XM_IS
Figure 14
Supply Current in Active Mode as a Function of Frequency
Note: Operating Conditions apply.
Data Sheet
69
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 17
Leakage Power Consumption
Parameter
Leakage supply current
(DMP_1 powered)1)
Symbol
ILK1 CC
Values
Unit
Note /
Test Condition
0.05
mA
0.5
1.3
mA
−
2.1
6.2
mA
−
4.4
13.7
mA
TJ= 25 °C1)
TJ= 85 °C1)
TJ= 125 °C1)
TJ= 150 °C1)
Min.
Typ.
Max.
−
0.03
−
1) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP and all outputs
(including pins configured as outputs) are disconnected.
Note: A fraction of the leakage current flows through domain DMP_A (pin VDDPA). This
current can be calculated as 7 000 × e-α, with α = 5 000 / (273 + 1.3×TJ).
For TJ = 150°C, this results in a current of 160 μA.
The leakage power consumption can be calculated according to the following formulas:
ILK0 = 500 000 × e-α, with α = 3 000 / (273 + B×TJ)
Parameter B must be replaced by
•
•
1.0 for typical values
1.6 for maximum values
ILK1 = 600 000 × e-α, with α = 5 000 / (273 + B×TJ)
Parameter B must be replaced by
•
•
1.0 for typical values
1.3 for maximum values
Data Sheet
70
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
ILK [mA]
14
ILK1max
12
10
8
6
ILK1typ
4
2
-50
0
100
50
125
150
TJ [°C]
MC_XY_ILKN
Figure 15
Leakage Supply Current as a Function of Temperature
Data Sheet
71
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.3
Analog/Digital Converter Parameters
These parameters describe the conditions for optimum ADC performance.
Note: Operating Conditions apply.
Table 18
ADC Parameters
Parameter
Symbol
Switched capacitance at
an analog input
CAINSW
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
4
5
pF
not subject to
production
test1)
−
10
12
pF
not subject to
production
test1)
7
9
pF
not subject to
production
test1)
−
13
15
pF
not subject to
production
test1)
CC
CAINT
Total capacitance at an
analog input
CC
Switched capacitance at
the reference input
CC
CAREFSW −
Total capacitance at the
reference input
CAREFT
Differential Non-Linearity
Error
|EADNL|
CC
−
0.8
1.0
LSB
not subject to
production test
Gain Error
|EAGAIN| −
CC
0.4
0.8
LSB
not subject to
production test
Integral Non-Linearity
|EAINL|
CC
−
0.8
1.2
LSB
not subject to
production test
Offset Error
|EAOFF|
CC
−
0.5
0.8
LSB
not subject to
production test
Analog clock frequency
fADCI SR 0.5
−
20
MHz Upper voltage
range
0.5
−
16.5
MHz Lower voltage
range
CC
Input resistance of the
selected analog channel
RAIN CC −
−
2
kOh
m
not subject to
production
test1)
Input resistance of the
reference input
RAREF
−
−
2
kOh
m
not subject to
production
test1)
Data Sheet
CC
72
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 18
ADC Parameters (cont’d)
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Broken wire detection
delay against VAGND2)
tBWG CC −
−
50
3)
Broken wire detection
delay against VAREF2)
tBWR CC −
−
50
4)
Conversion time for 8-bit
result2)
tc8 CC
(11 + STC) x tADCI
+ 2 x tSYS
Conversion time for 10-bit tc10 CC
result2)
(13 + STC) x tADCI
+ 2 x tSYS
Total Unadjusted Error
−
1
2
LSB
Wakeup time from analog tWAF CC −
powerdown, fast mode2)
−
4
μs
Wakeup time from analog tWAS CC −
powerdown, slow mode2)
−
15
μs
−
1.5
V
Analog reference ground
|TUE|
CC
Note /
Test Condition
VAGND
VSS
SR
- 0.05
5)
Analog input voltage
range
VAIN SR VAGND
−
VAREF
V
6)
Analog reference voltage
VAREF
VAGND
−
VDDPA
V
5)
SR
+ 1.0
+ 0.05
1) These parameter values cover the complete operating range. Under relaxed operating conditions (room
temperature, nominal supply voltage) the typical values can be used for calculation.
2) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming.
3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 µs. Result below 10% (66H).
4) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10 µs. This function is influenced by leakage current, in particular at high
temperature. Result above 80% (332H).
5) TUE is tested at VAREF = VDDPA = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
6) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
Data Sheet
73
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
RSource
V AIN
R AIN, On
C AINT - C AINS
C Ext
A/D Converter
CAINS
MCS05570
Figure 16
Data Sheet
Equivalent Circuitry for Analog Inputs
74
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Sample time and conversion time of the XC233xA’s A/D converters are programmable.
The timing above can be calculated using Table 19.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Table 19
A/D Converter Computation Table
GLOBCTR.5-0
(DIVA)
A/D Converter
Analog Clock fADCI
INPCRx.7-0
(STC)
000000B
fSYS
fSYS / 2
fSYS / 3
fSYS / (DIVA+1)
fSYS / 63
fSYS / 64
00H
000001B
000010B
:
111110B
111111B
01H
02H
:
FEH
FFH
Sample Time1)
tS
tADCI × 2
tADCI × 3
tADCI × 4
tADCI × (STC+2)
tADCI × 256
tADCI × 257
1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase).
Converter Timing Example A:
Assumptions:
Analog clock
Sample time
fSYS
fADCI
tS
= 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H
= fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns
= tADCI × 2 = 100 ns
Conversion 10-bit:
tC10
= 13 × tADCI + 2 × tSYS = 13 × 50 ns + 2 × 12.5 ns = 0.675 μs
Conversion 8-bit:
tC8
= 11 × tADCI + 2 × tSYS = 11 × 50 ns + 2 × 12.5 ns = 0.575 μs
Converter Timing Example B:
Assumptions:
Analog clock
Sample time
fSYS
fADCI
tS
= 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H
= fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns
= tADCI × 5 = 375 ns
Conversion 10-bit:
tC10
= 16 × tADCI + 2 × tSYS = 16 × 75 ns + 2 × 25 ns = 1.25 μs
Conversion 8-bit:
tC8
Data Sheet
= 14 × tADCI + 2 × tSYS = 14 × 75 ns + 2 × 25 ns = 1.10 μs
75
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.4
System Parameters
The following parameters specify several aspects which are important when integrating
the XC233xA into an application system.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 20
Various System Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
ΔTJ ≤ 10 °C
Short-term deviation of
internal clock source
frequency1)
ΔfINT CC -1
−
1
%
Internal clock source
frequency
fINT CC
4.8
5.0
5.2
MHz
Wakeup clock source
frequency2)
fWU CC
400
−
700
kHz
FREQSEL= 00
210
−
390
kHz
FREQSEL= 01
140
−
260
kHz
FREQSEL= 10
110
−
200
kHz
FREQSEL= 11
2.2
2.7
ms
fWU = 500 kHz
−
12 /
μs
Startup time from poweron with code execution
from Flash
tSPO CC 1.8
Startup time from stopover tSSO CC 11 /
fWU3)
mode with code execution
from PSRAM
Core voltage (PVC)
supervision level
VPVC CC VLV
fWU3)
VLV
- 0.03
VLV
V
5)
V
Lower voltage
range5)
V
Upper voltage
range5)
+ 0.07
4)
Supply watchdog (SWD)
supervision level
VSWD
CC
VLV
- 0.106)
VLV
VLV
+ 0.15
VLV
- 0.15
VLV
VLV
+ 0.15
1) The short-term frequency deviation refers to a timeframe of a few hours and is measured relative to the current
frequency at the beginning of the respective timeframe. This parameter is useful to determine a time span for
re-triggering a LIN synchronization.
2) This parameter is tested for the fastest and the slowest selection. The medium selections are not subject to
production test - verified by design/characterization
Data Sheet
76
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
3) fWU in MHz
4) This value includes a hysteresis of approximately 50 mV for rising voltage.
5) VLV = selected SWD voltage level
6) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V.
Conditions for tSPO Timing Measurement
The time required for the transition from Power-On to Base mode is called tSPO. It is
measured under the following conditions:
Precondition: The pad supply is valid, i.e. VDDPB is above 3.0 V and remains above 3.0 V
even though the XC233xA is starting up. No debugger is attached.
Start condition: Power-on reset is removed (PORST = 1).
End condition: External pin toggle caused by first user instruction executed from FLASH
after startup.
Conditions for tSSO Timing Measurement
The time required for the transition from Stopover to Stopover Waked-Up mode is
called tSSO. It is measured under the following conditions:
Precondition: The Stopover mode has been entered using the procedure defined in the
Programmer’s Guide.
Start condition: Pin toggle on ESR pin triggering the startup sequence.
End condition: External pin toggle caused by first user instruction executed from PSRAM
after startup.
Coding of bit fields LEVxV in SWD and PVC Configuration Registers
Table 21
Coding of bit fields LEVxV in Register SWDCON0
Code
Default Voltage Level
0000B
2.9 V
0001B
3.0 V
0010B
3.1 V
0011B
3.2 V
0100B
3.3 V
0101B
3.4 V
0110B
3.6 V
0111B
4.0 V
1000B
4.2 V
Data Sheet
Notes1)
LEV1V: reset request
77
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 21
Coding of bit fields LEVxV in Register SWDCON0 (cont’d)
Code
Default Voltage Level
Notes1)
1001B
4.5 V
LEV2V: no request
1010B
4.6 V
1011B
4.7 V
1100B
4.8 V
1101B
4.9 V
1110B
5.0 V
1111B
5.5 V
1) The indicated default levels are selected automatically after a power reset.
Table 22
Coding of Bitfields LEVxV in Registers PVCyCONz
Notes1)
Code
Default Voltage Level
000B
0.95 V
001B
1.05 V
010B
1.15 V
011B
1.25 V
100B
1.35 V
LEV1V: reset request
101B
1.45 V
LEV2V: interrupt request2)
110B
1.55 V
111B
1.65 V
1) The indicated default levels are selected automatically after a power reset.
2) Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and the PVC levels, this
interrupt can be triggered inadvertently, even though the core voltage is within the normal range. It is,
therefore, recommended not to use the this warning level.
Data Sheet
78
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.5
Flash Memory Parameters
The XC233xA is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XC233xA’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 23
Flash Parameters
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
NPP SR −
−
41)
−
−
12)
Flash erase endurance for NSEC SR 10
security pages
−
−
Flash wait states3)
NWSFLAS 1
−
−
H SR
2
−
−
3
−
−
4
−
Parallel Flash module
program/erase limit
depending on Flash read
activity
NFL_RD ≤ 1,
fSYS ≤ 80 MHz
NFL_RD > 1
cycle tRET ≥ 20 years
s
fSYS ≤ 8 MHz
fSYS ≤ 13 MHz
fSYS ≤ 17 MHz
fSYS > 17 MHz
−
Erase time per
sector/page
tER CC
−
7
8.0
ms
Programming time per
page
tPR CC
−
34)
3.5
ms
Data retention time
tRET CC 20
−
−
year
s
Drain disturb limit
NDD SR 32
−
−
cycle
s
Data Sheet
79
4)
Note /
Test Condition
NEr ≤ 1 000
cycles
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 23
Flash Parameters (cont’d)
Parameter
Number of erase cycles
Symbol
NEr SR
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
15 000 cycle tRET ≥ 5 years;
s
Valid for up to
64 userselected
sectors (data
storage)
−
−
1 000
cycle tRET ≥ 20 years
s
1) All Flash module(s) can be erased/programmed while code is executed and/or data is read from only one
Flash module or from PSRAM. The Flash module that delivers code/data can, of course, not be
erased/programmed.
2) Flash module 3 can be erased/programmed while code is executed and/or data is read from any other Flash
module.
3) Value of IMB_IMBCTRL.WSFLASH.
4) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles. This increases the stated durations noticably only at extremely low system clock
frequencies.
Access to the XC233xA Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Data Sheet
80
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.6
AC Parameters
These parameters describe the dynamic behavior of the XC233xA.
4.6.1
Testing Waveforms
These values are used for characterization and production testing (except pin XTAL1).
Output delay
Output delay
Hold time
Hold time
0.8 V DDP
0.7 V DDP
Input Signal
(driven by tester)
0.3 V DDP
0.2 V DDP
Output Signal
(measured)
Output timings refer to the rising edge of CLKOUT.
Input timings are calculated from the time, when the input signal reaches
V IH or V IL, respectively.
MCD05556C
Figure 17
Input Output Waveforms
VLoad + 0.1 V
V OH - 0.1 V
Timing
Reference
Points
V Load - 0.1 V
V OL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded V OH /V OL level occurs (IOH / IOL = 20 mA).
MCA05565
Figure 18
Data Sheet
Floating Waveforms
81
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.6.2
Definition of Internal Timing
The internal operation of the XC233xA is controlled by the internal system clock fSYS.
Because the system clock signal fSYS can be generated from a number of internal and
external sources using different mechanisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate fSYS. This must be considered when calculating the timing
for the XC233xA.
Phase Locked Loop Operation (1:N)
fI N
f SYS
TCS
Direct Clock Drive (1:1)
fI N
f SYS
TCS
Prescaler Operation (N:1)
fI N
f SYS
TCS
M C_XC2X_CLOCKGEN
Figure 19
Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 19 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Data Sheet
82
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is
derived directly from the input clock signal CLKIN1:
fSYS = fIN.
The frequency of fSYS is the same as the frequency of fIN. In this case the high and low
times of fSYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY =
1B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
fSYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of fSYS equals the frequency of fOSC. In
this case the high and low times of fSYS are determined by the duty cycle of the input
clock fOSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
fSYS = fOSC / 1024.
4.6.2.1
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (fSYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the onchip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of fSYS so that it is
locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage VDDIM.
Data Sheet
83
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the given circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 20).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles
is K2 × T, where T is the number of consecutive fSYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) DTmax is defined by:
DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T × TCS the accumulated jitter DT is determined by:
DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
fSYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
Dmax = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97 × [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63 × [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
Data Sheet
84
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Acc. jitter DT
ns
±9
fSYS = 33 MHz fSYS = 66 MHz
fVCO = 66 MHz
±8
±7
f VCO = 132 MHz
±6
±5
±4
±3
±2
±1
Cycles T
0
1
20
40
60
80
100
MC_XC2X_JITTER
Figure 20
Approximated Accumulated PLL Jitter
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF.
The maximum peak-to-peak noise on the pad supply voltage (measured between
VDDPB pin 100 and VSS pin 1) is limited to a peak-to-peak voltage of VPP = 50 mV.
This can be achieved by appropriate blocking of the supply voltage as close as
possible to the supply pins and using PCB supply and ground planes.
Data Sheet
85
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
PLL frequency band selection
Different frequency bands can be selected for the VCO so that the operation of the PLL
can be adjusted to a wide range of input and output frequencies:
Table 24
System PLL Parameters
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
−
110
Note /
Test Condition
VCO output frequency
(VCO controlled)
fVCO CC 50
−
160
MHz VCOSEL = 01B
VCO output frequency
(VCO free-running)
fVCO CC 10
−
40
MHz VCOSEL = 00B
20
−
80
MHz VCOSEL = 01B
4.6.2.2
100
MHz VCOSEL = 00B
Wakeup Clock
When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is
derived from the low-frequency wakeup clock source:
fSYS = fWU.
In this mode, a basic functionality can be maintained without requiring an external clock
source and while minimizing the power consumption.
4.6.2.3
Selecting and Changing the Operating Frequency
When selecting a clock source and the clock generation method, the required
parameters must be carefully written to the respective bit fields, to avoid unintended
intermediate states.
Many applications change the frequency of the system clock (fSYS) during operation in
order to optimize system performance and power consumption. Changing the operating
frequency also changes the switching currents, which influences the power supply.
To ensure proper operation of the on-chip EVRs while they generate the core voltage,
the operating frequency shall only be changed in certain steps. This prevents overshoots
and undershoots of the supply voltage.
To avoid the indicated problems, recommended sequences are provided which ensure
the intended operation of the clock system interacting with the power system.
Please refer to the Programmer’s Guide.
Data Sheet
86
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.6.3
External Clock Input Parameters
These parameters specify the external clock generation for the XC233xA. The clock can
be generated in two ways:
•
•
By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2
By supplying an external clock signal
– This clock signal can be supplied either to pin XTAL1 (core voltage domain) or to
pin CLKIN1 (IO voltage domain)
If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH.
If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for
the operation of the on-chip oscillator.
Note: The given clock timing parameters (t1 … t4) are only valid for an external clock
input signal.
Note: Operating Conditions apply.
Table 25
External Clock Input Characteristics
Parameter
Symbol
Values
Min.
Oscillator frequency
XTAL1 input current
absolute value
XTAL11)
Note /
Test Condition
Typ.
Max.
fOSC SR 4
−
40
MHz Input = clock
signal
4
−
16
MHz Input = crystal
or ceramic
resonator
−
−
20
μA
6
−
−
ns
6
−
−
ns
−
−
8
ns
−
−
8
ns
0.3 x
−
−
V
4 to 16 MHz
−
−
V
16 to 25 MHz
−
−
V
25 to 40 MHz
−
1.7
V
2)
|IIL| CC
t1 SR
Input clock low time
t2 SR
t3 SR
Input clock rise time
Input clock fall time
t4 SR
Input voltage amplitude on VAX1 SR
Input clock high time
Unit
VDDIM
0.4 x
VDDIM
0.5 x
VDDIM
Input voltage range limits
for signal on XTAL1
Data Sheet
VIX1 SR -1.7 +
VDDIM
87
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
1) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the
operation and the resulting voltage peaks must remain within the limits defined by VIX1.
2) Overload conditions must not occur on pin XTAL1.
Note: For crystal or ceramic resonator operation, it is strongly recommended to measure
the oscillation allowance (negative resistance) in the final target system (layout) to
determine the optimum parameters for oscillator operation.
The manufacturers of crystals and ceramic resonators offer an oscillator
evaluation service. This evaluation checks the crystal/resonator specification
limits to ensure a reliable oscillator operation.
t1
VOFF
t3
0.9 V AX1
0.1 V AX1
VAX1
t2
t4
tOSC = 1/fOSC
MC_ EXTCLOCK
Figure 21
External Clock Drive XTAL1
Data Sheet
88
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.6.4
Pad Properties
The output pad drivers of the XC233xA can operate in several user-selectable modes.
Strong driver mode allows controlling external components requiring higher currents
such as power bridges or LEDs. Reducing the driving power of an output pad reduces
electromagnetic emissions (EME). In strong driver mode, selecting a slower edge
reduces EME.
The dynamic behavior, i.e. the rise time and fall time, depends on the applied external
capacitance that must be charged and discharged. Timing values are given for a
capacitance of 20 pF, unless otherwise noted.
In general, the performance of a pad driver depends on the available supply voltage
VDDP. The following table lists the pad parameters.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Data Sheet
89
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 26 is valid under the following conditions:
VDDP ≥ 4.5 V; VDDPtyp = 5 V; VDDP ≤ 5.5 V; CL ≥ 20 pF; CL ≤ 100 pF;
Table 26
Standard Pad Parameters for Upper Voltage Range
Parameter
Symbol
Min.
Typ.
Max.
Maximum output driver
current (absolute value)1)
IOmax
−
−
CC
−
Nominal output driver
current (absolute value)
IOnom
CC
Rise and Fall times (10% - tRF CC
90%)
Values
Unit
Note /
Test Condition
10
mA
Strong driver
−
4.0
mA
Medium driver
−
−
0.5
mA
Weak driver
−
−
2.5
mA
Strong driver
−
−
1.0
mA
Medium driver
−
−
0.1
mA
Weak driver
−
−
4.2 +
0.14 x
ns
Strong driver;
Sharp edge
−
−
11.6 + ns
0.22 x
Strong driver;
Medium edge
−
−
−
−
CL
CL
20.6 + ns
0.22 x
Strong driver;
Slow edge
CL
23 +
0.6 x
ns
Medium driver
ns
Weak driver
CL
−
−
212 +
1.9 x
CL
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and ΣIOH) must remain below 50 mA.
Data Sheet
90
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 27 is valid under the following conditions:
VDDP ≥ 3.0 V; VDDPtyp = 3.3 V; VDDP ≤ 4.5 V; CL ≥ 20 pF; CL ≤ 100 pF;
Table 27
Standard Pad Parameters for Lower Voltage Range
Parameter
Symbol
Min.
Typ.
Max.
Maximum output driver
current (absolute value)1)
IOmax
−
−
CC
−
Nominal output driver
current (absolute value)
IOnom
CC
Rise and Fall times (10% - tRF CC
90%)
Values
Unit
Note /
Test Condition
10
mA
Strong driver
−
2.5
mA
Medium driver
−
−
0.5
mA
Weak driver
−
−
2.5
mA
Strong driver
−
−
1.0
mA
Medium driver
−
−
0.1
mA
Weak driver
−
−
6.2 +
0.24 x
ns
Strong driver;
Sharp edge
−
−
ns
Strong driver;
Medium edge
−
−
ns
Strong driver;
Slow edge
−
−
ns
Medium driver
ns
Weak driver
CL
24 +
0.3 x
CL
34 +
0.3 x
CL
37 +
0.65 x
CL
−
−
500 +
2.5 x
CL
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and ΣIOH) must remain below 50 mA.
Data Sheet
91
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.6.5
Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply; CL = 20 pF.
Table 28
USIC SSC Master Mode Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Slave select output SELO t1 CC
active to first SCLKOUT
transmit edge
tSYS
−
−
ns
Slave select output SELO t2 CC
inactive after last
SCLKOUT receive edge
tSYS
−
−
ns
t3 CC
-6
−
9
ns
Receive data input setup t4 SR
time to SCLKOUT receive
edge
31
−
−
ns
t5 SR
-4
−
−
ns
Data output DOUT valid
time
Data input DX0 hold time
from SCLKOUT receive
edge
Note /
Test Condition
- 8 1)
- 6 1)
1) tSYS = 1 / fSYS
Table 29
USIC SSC Master Mode Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Slave select output SELO t1 CC
active to first SCLKOUT
transmit edge
tSYS
−
−
ns
Slave select output SELO t2 CC
inactive after last
SCLKOUT receive edge
tSYS
−
−
ns
-7
−
11
ns
Data output DOUT valid
time
Data Sheet
t3 CC
Note /
Test Condition
- 10 1)
- 9 1)
92
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 29
USIC SSC Master Mode Timing for Lower Voltage Range (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Receive data input setup t4 SR
time to SCLKOUT receive
edge
40
−
−
ns
t5 SR
-5
−
−
ns
Data input DX0 hold time
from SCLKOUT receive
edge
Note /
Test Condition
1) tSYS = 1 / fSYS
Table 30
USIC SSC Slave Mode Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
t10 SR
7
−
−
ns
Select input DX2 hold after t11 SR
last clock input DX1
receive edge1)
7
−
−
ns
Receive data input setup
time to shift clock receive
edge1)
t12 SR
7
−
−
ns
Data input DX0 hold time
from clock input DX1
receive edge1)
t13 SR
5
−
−
ns
Data output DOUT valid
time
t14 CC
7
−
33
ns
Select input DX2 setup to
first clock input DX1
transmit edge1)
Note /
Test Condition
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
93
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 31
USIC SSC Slave Mode Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
t10 SR
7
−
−
ns
Select input DX2 hold after t11 SR
last clock input DX1
receive edge1)
7
−
−
ns
Receive data input setup
time to shift clock receive
edge1)
t12 SR
7
−
−
ns
Data input DX0 hold time
from clock input DX1
receive edge1)
t13 SR
5
−
−
ns
Data output DOUT valid
time
t14 CC
8
−
41
ns
Select input DX2 setup to
first clock input DX1
transmit edge1)
Note /
Test Condition
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
94
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Master Mode Timing
t1
Select Output
SELOx
t2
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
First Transmit
Edge
Last Receive
Edge
Transmit
Edge
t3
t3
Data Output
DOUT
t4
Data Input
DX0
t4
t5
Data
valid
t5
Data
valid
Slave Mode Timing
t10
Select Input
DX2
Clock Input
DX1
t11
Inactive
Inactive
Active
Receive
Edge
First Transmit
Edge
t12
Data Input
DX0
t12
t13
Data
valid
t 14
Last Receive
Edge
Transmit
Edge
t 13
Data
valid
t14
Data Output
DOUT
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched
.
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
Figure 22
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration where the slave select signal
is low-active and the serial clock signal is not shifted and not inverted.
Data Sheet
95
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
4.6.6
Debug Interface Timing
The debugger can communicate with the XC233xA either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply; CL= 20 pF.
Table 32
DAP Interface Timing for Upper Voltage Range
Parameter
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
251)
−
−
ns
8
−
−
ns
8
−
−
ns
−
−
4
ns
−
−
4
ns
6
−
−
ns
pad_type= stan
dard
DAP1 hold after DAP0
rising edge
t17 SR
6
−
−
ns
pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
t19 CC
17
20
−
ns
pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Data Sheet
96
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 33
DAP Interface Timing for Lower Voltage Range
Parameter
Symbol
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
251)
−
−
ns
8
−
−
ns
8
−
−
ns
−
−
4
ns
−
−
4
ns
6
−
−
ns
pad_type= stan
dard
DAP1 hold after DAP0
rising edge
t17 SR
6
−
−
ns
pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
t19 CC
12
17
−
ns
pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t 11
0.9 VDDP
0.5 VDDP
t15
t12
t 14
0.1 VDDP
t13
MC_DAP0
Figure 23
Data Sheet
Test Clock Timing (DAP0)
97
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
DAP0
t1 6
t1 7
DAP1
MC_ DAP1_RX
Figure 24
DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 25
DAP Timing Device to Host
Note: The transmission timing is determined by the receiving debugger by evaluating the
sync-request synchronization pattern telegram.
Data Sheet
98
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply; CL= 20 pF.
Table 34
JTAG Interface Timing for Upper Voltage Range
Parameter
Symbol
Values
Min.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
Unit
Typ.
Max.
50
−
−
ns
16
−
−
ns
1)
16
−
−
ns
−
−
8
ns
−
−
8
ns
6
−
−
ns
t7 SR
6
−
−
ns
TDO valid from TCK falling t8 CC
edge (propagation delay)3)
−
25
29
ns
TDO high impedance to
valid output from TCK
falling edge4)3)
t9 CC
−
25
29
ns
TDO valid output to high
impedance from TCK
falling edge3)
t10 CC
−
25
29
ns
TDO hold after TCK falling t18 CC
edge3)
5
−
−
ns
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup to TCK
rising edge
TDI/TMS hold after TCK
rising edge
Note /
Test Condition
2)
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS.
2) Under typical conditions, the interface can operate at transfer rates up to 20 MHz.
3) The falling edge on TCK is used to generate the TDO timing.
4) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
99
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
Table 35
JTAG Interface Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
501)
−
−
ns
16
−
−
ns
16
−
−
ns
−
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
−
8
ns
−
−
8
ns
6
−
−
ns
t7 SR
6
−
−
ns
TDO valid from TCK falling t8 CC
edge (propagation delay)3)
−
32
36
ns
TDO high impedance to
valid output from TCK
falling edge4)3)
t9 CC
−
32
36
ns
TDO valid output to high
impedance from TCK
falling edge3)
t10 CC
−
32
36
ns
TDO hold after TCK falling t18 CC
edge3)
5
−
−
ns
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup to TCK
rising edge
TDI/TMS hold after TCK
rising edge
Note /
Test Condition
2)
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS.
2) Under typical conditions, the interface can operate at transfer rates up to 20 MHz.
3) The falling edge on TCK is used to generate the TDO timing.
4) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
100
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Electrical Parameters
t1
0.9 VDDP
0.5 VDDP
t5
t2
0.1 VDDP
t4
t3
MC_JTAG_TCK
Figure 26
Test Clock Timing (TCK)
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t10
TDO
MC_JTAG
Figure 27
Data Sheet
JTAG Timing
101
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Package and Reliability
5
Package and Reliability
The XC2000 Family devices use the package type PG-LQFP (Plastic Green - Low
Profile Quad Flat Package). The following specifications must be regarded to ensure
proper integration of the XC233xA in its target environment.
5.1
Packaging
These parameters specify the packaging rather than the silicon.
Table 36
Package Parameters (PG-LQFP-64-13)
Parameter
Power Dissipation
Thermal resistance
Junction-Ambient
Symbol
PDISS
RΘJA
Limit Values
Unit Notes
Min.
Max.
–
1.0
W
–
58
K/W No thermal via1)
46
K/W 4-layer, no pad2)
–
1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) or a 4-layer board without thermal vias;
exposed pad not soldered.
2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias.
Package Compatibility Considerations
The XC233xA is a member of the XC2000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Pad (if present) may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
Data Sheet
102
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Package and Reliability
0.5
H
7˚ MAX.
0.15 -0.06
+0.05
1.6 MAX.
0.1 ±0.05
1.4 ±0.05
Package Outlines
0.6 ±0.15
0.08 C 64x
C
7.5
+0.07
0.2 -0.03
0.08 M A-B D C 64x
12
10
0.2 A-B D 64x
1)
0.2 A-B D H 4x
10
B
12
A
1)
D
64
1
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
PG-LQFP-64-13-PO V07
Figure 28
PG-LQFP-64-13 (Plastic Green Thin Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet
103
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Package and Reliability
5.2
Thermal Considerations
When operating the XC233xA in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 125 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
104
V2.1, 2011-07
XC2336A
XC2000 Family / Base Line
Package and Reliability
5.3
Quality Declarations
The operation lifetime of the XC233xA depends on the applied temperature profile in the
application. For a typical example, please refer to Table 38; for other profiles, please
contact your Infineon counterpart to calculate the specific lifetime within your application.
Table 37
Quality Parameters
Parameter
Symbol
Operation lifetime
Table 38
Unit
Note /
Test Condition
20
a
See Table 38
and Table 39
−
2 000
V
EIA/JESD22A114-B
−
3
−
JEDEC
J-STD-020C
Typ.
Max.
−
−
−
MSL CC −
tOP CC
ESD susceptibility
VHBM
according to Human Body SR
Model (HBM)
Moisture sensitivity level
Values
Min.
Typical Usage Temperature Profile
Operating Time (Sum = 20 years)
Operating Temperat.
Notes
1 200 h
TJ = 150°C
TJ = 125°C
TJ = 110°C
TJ = 100°C
TJ = 0…10°C, …,
Normal operation
3 600 h
7 200 h
12 000 h
7 × 21 600 h
Table 39
Normal operation
Normal operation
Normal operation
Power reduction
60…70°C
Long Time Storage Temperature Profile
Operating Time (Sum = 20 years)
Operating Temperat.
Notes
2 000 h
Normal operation
151 200 h
TJ = 150°C
TJ = 125°C
TJ = 110°C
TJ ≤ 150°C
Data Sheet
105
16 000 h
6 000 h
Normal operation
Normal operation
No operation
V2.1, 2011-07
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