EUA2011JIR1

EUA2011 3-W Mono Filterless Class-D Audio Power Amplifier DESCRIPTION The EUA2011 is a high efficiency, 3W mono class-D audio power amplifier. A low noise, filterless PWM architecture eliminates the output filter, reducing external component count, system cost, and simplifying design. Operating in a single 5V supply, EUA2011 is capable of driving 4Ω speaker load at a continuous average output of 3W/10% THD+N or 2W/1% THD+N. The EUA2011 has high efficiency with speaker load compared to a typical class AB amplifier. With a 3.6V supply driving an 8Ω speaker , the efficiency for a 400mW power level is 88%. In cellular handsets, the earpiece, speaker phone, and melody ringer can each be driven by the EUA2011. The gain of EUA2011 is externally configurable which allows independent gain control from multiple sources by summing signals from separate sources. The EUA2011 is available in space-saving WCSP and TDFN packages. FEATURES Unique Modulation Scheme Reduces EMI Emissions Efficiency at 3.6V With an 8-Ω Speaker: − 88% at 400 mW − 80% at 100 mW Low 2.4-mA Quiescent Current and 0.5-µA Shutdown Current 2.5V to 5.5V Wide Supply Voltage Shutdown Pin Compatible with 1.8V Logic GPIO Optimized PWM Output Stage Eliminates LC Output Filter Improved PSRR (−72 dB) Eliminates Need for a Voltage Regulator Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor Improved CMRR Eliminates Two Input Coupling Capacitors Internally Generated 250-kHz Switching Frequency Integrated Pop and Click Suppression Circuitry 1.5mm × 1.5mm Wafer Chip Scale Package (WCSP) and 3mm × 3mm TDFN-8 package RoHS compliant and 100% lead(Pb)-free APPLICATIONS Typical Application Circuit Ideal for Wireless or cellular Handsets and PDAs Figure1. DS2011 Ver 1.1 Dec. 2007 1 EUA2011 Pin Configurations Package Type Pin Configurations Package Type Pin Configurations TDFN-8 WCSP-9 Pin Description PIN TDFN-8 WCSP-9 I/O DESCRIPTION SHUTDOWN PVDD +IN -IN VOVDD GND VO+ NC 1 3 4 8 6 7 5 2 C2 B2 A1 C1 A3 B1 A2/B3 C3 - I I I I O I I O Shutdown terminal (active low logic) Power Supply Positive differential input Negative differential input Negative BTL output Power supply High-current ground Positive BTL output No internal connection DS2011 Ver 1.1 Dec. 2007 2 EUA2011 Ordering Information Order Number Package Type Marking Operating Temperature range EUA2011JIR1 EUA2011HIR1 TDFN-8 WCSP-9 xxxxx A2011 xxx c0 -40 °C to 85°C -40 °C to 85°C EUA2011 □ □ □ □ Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type J: TDFN H: WCSP DS2011 Ver 1.1 Dec. 2007 3 EUA2011 Absolute Maximum Ratings ▓ Supply Voltage, VDD ------------------------------------------------------------------------------------- -0.3 V to 6V ▓ Voltage at Any Input Pin ------------------------------------------------------------------------- -0.3 V to VDD +0.3V Junction Temperature, TJMAX --------------------------------------------------------------------------------------- 150°C Storage Temperature Rang, Tstg --------------------------------------------------------------------- -65°C to 150°C ESD Susceptibility -------------------------------------------------------------------------------------------2kV 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ----------------------------------------- ▓ ▓ ▓ ▓ ▓ Thermal Resistance θJA (TDFN) --------------------------------------------------------------------------------------------------- 47°C/W θJA (WCSP) -------------------------------------------------------------------------------------------------- 77.5°C/W Recommended Operating Conditions Min Supply voltage, VDD High-level input voltage, VIH 2.5 Max 5.5 Unit V SHUTDOWN SHUTDOWN Gain ≤ 20V/V (26dB) VDD=2.5V,5.5V,CMRR ≤ -49dB 1.3 0 15 0.5 -40 VDD 0.35 VDD-0.8 85 V V kΩ V °C Low-level input voltage, VIL Input resistor, RI Common mode input voltage range, VIC Operating free-air temperature, TA Electrical Characteristics TA = 25°C (Unless otherwise noted) Symbol VOS Parameter Output offset voltage (measured differentially) Power supply rejection ratio Common mode rejection ratio Conditions VI= 0V,AV=2 V/V, VDD=2.5V to 5.5V VDD= 2.5V to 5.5V VDD= 2.5V to 5.5V, VIC= VDD/2 to 0.5V, VIC= VDD/2 to VDD -0.8 V VDD= 5.5V, VI= 5.8V VDD= 5.5V, VI= -0.3V VDD= 5.5V, no load EUA2011 Min Typ Max. 1 -72 -60 25 -55 -48 100 5 3.5 2.4 2 0.5 700 500 400 >1 200 250 300 300 4.9 Unit mV dB dB µA µA mA PSRR CMRR I IH I IL I(Q) High-level input current Low-level input current Quiescent current VDD= 3.6V, no load VDD= 2.5V, no load V (SHUTDOWN ) =0.35V, I(SD) Shutdown current Static drain-source on-state rDS(on) resistance VDD= 2.5V to 5.5V VDD= 2.5V VDD= 3.6V VDD= 5.5V V (SHUTDOWN ) =0.4V µA mΩ f(sw) Output impedance in SHUTDOWN Switching frequency Resistance from shutdown toGND kΩ kHz kΩ VDD= 2.5V to 5.5V DS2011 Ver 1.1 Dec. 2007 4 EUA2011 Electrical Characteristics TA = 25°C ,Gain= 2V/V,RL=8Ω (Unless otherwise noted) EUA2011 Symbol Parameter Conditions Min Typ Max. THD+N=10%, VDD= 3.6V f=1kHz, RL=4Ω Unit W VDD= 5V 3 1.4 0.65 2.15 1.06 0.49 1.67 0.84 0.39 1.36 0.66 0.30 0.18 0.18 0.17 -60 93 62 µVRMS 45 -55 11.5 dB ms dB dB % W W W VDD= 2.5V VDD= 5V THD+N=1%, VDD= 3.6V f=1kHz, RL=4Ω PO Output power VDD= 2.5V VDD= 5V THD+N=10%, VDD= 3.6V f=1kHz, RL=8Ω VDD= 2.5V VDD= 5V THD+N=1%, VDD= 3.6V f=1kHz, RL=8Ω VDD= 2.5V Total harmonic distortion THD+N plus noise VDD= 5V,PO=1W, RL=8Ω, f=1kHz VDD= 3.6V,PO=0.5W, RL=8Ω, f=1kHz VDD= 2.5V,PO=200mW, RL=8Ω, f=1kHz kSVR SNR Supply ripple rejection ratio Signal-to-noise ratio VDD= 3.6V, Inputs f=217 Hz, ac-grounded with V(RIPPLE)=200mVpp CI= 2µF VDD= 5V,PO=1W, RL=8Ω VDD= 3.6V, No weighting f=20Hz to 20kHz,Inputs ac-grounded with A weighting CI= 2µF VDD= 3.6V, f=217 Hz VIC=1 VPP VDD= 3.6V Vn Output voltage noise CMRR ZI Common mode rejection ratio Start-up time from shutdown DS2011 Ver 1.1 Dec. 2007 5 EUA2011 Typical Operating Characteristics EFFICIENCY vs OUTPUT POWER 100 90 80 70 90 80 70 EFFICIENCY vs OUTPUT POWER Efficiency - % Efficiency - % 60 50 40 30 20 10 0 0.0 VDD=2.5V, RL= 8 ohm + 33uH VDD=5V, RL=8 ohm+33uH VDD=3.6V, RL=8 ohm + 33uH 60 50 40 30 20 10 0 VDD=2.5V, RL= 4 ohm + 33uH VDD=5V, RL=4 ohm+33uH VDD=3.6V, RL=4 ohm + 33uH 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 PO - Output Power - W PO - Output Power - W Figure2. POWER DISSIPATION vs OUTPUT POWER 1.4 0.7 Figure3. POWER DISSIPATION vs OUTPUT POWER 1.2 0.6 PD - Power Dissipation - W PD - Power Dissipation - W 1.0 0.5 0.8 0.4 0.6 0.3 0.4 0.2 VDD=3.6V, RL=4 ohm VDD=3.6V, RL=8 ohm VDD=5V, RL=4 ohm 0.2 0.1 0.0 0.0 0.5 1.0 VDD=5V, RL=8 ohm 1.5 2.0 2.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 PO - Output Power - W PO - Output Power - W Figure4. SUPPLY CURRENT vs OUTPUT POWER 700 250 Figure5. SUPPLY CURRENT vs OUTPUT POWER RL= 8 ohm, 33uH VDD=5V RL= 4 ohm, 33uH 600 200 IDD - Supply Current - mA IDD - Supply Current -mA VDD=5V 500 VDD=3.6V 150 400 VDD=2.5V VDD=3.6V 300 100 VDD=2.5V 200 50 100 0 0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 PO - Output Power - W PO - Output Power - W Figure6. DS2011 Ver 1.1 Dec. 2007 Figure7. 6 EUA2011 SUPPLY CURRENT vs SUPPLY VOLTAGE 5.0 2.0 SHUTDOWN CURRENT vs SHUTDOWN VOLTAGE 4.5 I(SD) -Shutdown Current - uA IDD - Supply Current -mA 4.0 RL=8 ohm,(resistive) 1.5 3.5 1.0 3.0 VDD=5V VDD=3.6V 0.5 2.5 RL=8 ohm, 33uH NO Load VDD=2.5V 2.0 1.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.0 0.1 0.2 0.3 0.4 0.5 VDD - Supply Voltage -V Shutdown Voltage -V Figure8. Figure9. OUTPUT POWER vs LOAD RESISTANCE 2.5 OUTPUT POWER vs LOAD RESISTANCE 3.0 2.5 VDD=5V PO at 10% THD Gain=2 V/V F=1KHz PO - Output Power - W 2.0 PO at 1% THD Gain=2 V/V F=1KHz VDD=5V PO - Output Power - W 2.0 1.5 VDD=3.6V 1.5 VDD=2.5V 1.0 1.0 VDD=3.6V VDD=2.5V 0.5 0.5 0.0 0.0 4 8 12 16 20 24 28 32 4 8 12 16 20 24 28 32 RL - Load Resistance - ohm RL - Load Resistance - ohm Figure10. Figure11. OUTPUT POWER vs SUPPLY VOLTAGE 3.0 GAIN=2V/V F=1KHz 2.5 RL= 4 ohm, 10% THD PO - Output Power -W RL= 4 ohm, 1% THD 2.0 1.5 1.0 RL = 8 ohm, 10% THD 0.5 RL= 8 ohm, 1% THD 0.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC - Supply Voltage -V Figure12. Figure13. DS2011 Ver 1.1 Dec. 2007 7 EUA2011 Figure14. Figure15. Figure16. Figure17. TOTAL HARMONIC DISTORTION+NOISE vs COMMON MODE INPUT VOLTAGE THD+N - Total Harmonic Distortion + Noise -% 10 f= 1KHz Po=200mW 1 VDD=2.5V VDD=3.6V VDD=5V 0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VIC - Common Mode Input Voltage - V Figure18. DS2011 Ver 1.1 Dec. 2007 Figure19. 8 EUA2011 Figure20. Figure21. Figure22. Figure23. Figure24. Figure25. DS2011 Ver 1.1 Dec. 2007 9 EUA2011 SUPPLY RIPPLE REJECTION RATIO vs DC COMMON MODE VOLTAGE 0 -10 -20 -30 -40 Supply Ripple Rejection Ratio - dB VDD=2.5V -50 -60 -70 -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD=3.6V VDD=5V DC Common Mode Voltage - V Figure26. COMMON-MODE REJECTION RATIO vs COMMON-MODE INPUT VOLTAGE 0 Figure27. CMRR - Common Mode Rejection Ratio - dB -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 VDD=2.5V VDD=3.6V VDD=5V, Gain=2V/V VIC - Common Mode Input Voltage - V Figure28. Figure29. EMI Test and FCC Limits DS2011 Ver 1.1 Dec. 2007 10 EUA2011 Application Information Fully Differential Amplifier Table 1. Typical Component Values REF DES VALUE The EUA2011 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the input. The fully differential EUA2011 can still be used with a single-ended input; however, the EUA2011 should be used with differential inputs when in a noisy environment, like a wireless handset, to ensure maximum noise rejection. Advantages of Fully Differential Amplifiers Input-coupling capacitors not required: - The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For example, if a codec has a midsupply lower than the midsupply of the EUA2011, the common-mode feedback circuit will adjust, and the EUA2011 outputs will still be biased at midsupply of the EUA2011. The inputs of the EUA2011 can be biased from 0.5V to VDD – 0.8 V. If the inputs are biased outside of that range, input-coupling capacitors are required. Midsupply bypass capacitor, C(BYPASS), not required: - The fully differential amplifier does not require a bypass capacitor. This is because any shift in the midsupply affects both positive and negative channels equally and cancels at the differential output. Better RF−immunity: -GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier. Component Selection RI CS 150kΩ ( ± 0.5%) 1µF (+22%,-80%) CI (1) 3.3nF ( ± 10%) (1) CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD – 0.8 V. CI = 3.3 nF (with RI = 150 kΩ) gives a high-pass corner frequency of 321 Hz. Figure 30. Typical Application Schematic with Differential Input for a Wireless Phone Figure 31. Typical Application Schematic with Differential Input and Input Capacitors Figure 30 shows the EUA2011 typical schematic with differential inputs and Figure 31 shows the EUA2011 with differential inputs and input capacitors, and Figure 32 shows the EUA2011 with single-ended inputs. Differential inputs should be used whenever possible because the single-ended inputs are much more susceptible to noise. Figure 32. Typical Application Schematic with Single-Ended Input DS2011 Ver 1.1 Dec. 2007 11 EUA2011 Input Resistors (RI) The input resistors (RI) set the gain of the amplifier according to equation (1). 2 × 150kΩ RI  V  ---------------------------------(1)  V 1 f= c 2 πR I C I ( ) --------------------------------------------(2) Gain = Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with 1% matching can be used with a tolerance greater than 1%. Place the input resistors very close to the EUA2011 to limit noise injection on the high-impedance nodes. For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the EUA2011 to operate at its best, and keeps a high voltage at the input making the inputs less susceptible to noise. Decoupling Capacitor (CS) The EUA2011 is a high-performance class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the EUA2011 is very important for the efficiency of the class-D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 10µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Input Capacitors (CI) The EUA2011 does not require input coupling capacitors if the design uses a differential source that is biased from 0.5 V to VDD – 0.8 V (shown in Figure 31). If the input signal is not biased within the recommended common −mode input range, if needing to use the input as a high pass filter (shown in Figure 32), or if using a single-ended source (shown in Figure 33), input coupling capacitors are required. The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in equation (2). The value of the input capacitor is important to consider as it directly affects the bass (low frequency) performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the corner frequency can be set to block low frequencies in this application. Equation (3) is reconfigured to solve for the input coupling capacitance. 1 C= --------------------------------------------(3) I 2 πR I f c If the corner frequency is within the audio band, the capacitors should have a tolerance of ± 10% or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below. For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone the ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation. The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum. ( ) Single-Ended Input Depop Function In single-ended input application, there is an inherently voltage difference in input pairs when shutdown is released. In order to eliminate pop noise, the pop cancellation circuit need to charge the input capacitor CI until fully-differential inputs are balanced and output power to load gradually. The RC time constant should within the de-pop delay, if 150kΩ RI is chosen, the recommended CI should small than 10nF for a good pop immunity. Summing Input Signals Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources that need separate gain. The EUA2011 makes it easy to sum signals or use separate signal sources with different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo headphones require summing of the right and left channels to output the stereo signal to the mono speaker. DS2011 Ver 1.1 Dec. 2007 12 EUA2011 Summing Two Differential Input Signals Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input source can be set independently (see equations (4) and (5), and Figure 33). Gain1 = VO 2 × 150 kΩ = R VI1 I1 V   -----------------------(4) V Summing a Differential Input Signal and a Single-Ended Input Signal Gain 2 = VO 2 × 150 kΩ  V  =   -----------------------(5) R VI 2 V I2 Figure 34 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended input is set by CI2, shown in equation (8). To assure that each input is balanced, the single-ended input must be driven by a low-impedance source even if the input is not in use V 2 × 150 kΩ  V  ------------------------ (6) Gain1 = O =  R VI1 V I1 Gain 2 = VO 2 × 150 kΩ  V  -----------------------(7) =  R VI 2 V I2 1 If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ. If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to Gain 1 = 0.1 V/V. The resistor values would be. . . RI1=3MΩ, and=RI2=150kΩ C I2 = (2πR I2 f c 2 ) -----------------------------------------(8) If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set to gain 2 = 2 V/V, the resistor values would be… RI1=3kΩ, and=RI2=150kΩ The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less than 20 Hz... C > 1 I2 I2 (2π150 kΩ 20 Hz ) Figure 33. Application Schematic with EUA2011 Summing Two Differential Inputs C > 53 nF Figure 34. Application Schematic with EUA2011 Summing Input and Single-Ended Input Signals DS2011 Ver 1.1 Dec. 2007 13 EUA2011 Summing Two Single-Ended Input Signals PCB Layout Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner frequencies (fc1 and fc2) for each input source can be set independently (see equations (9) through (12), and Figure 35). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the IN− terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not outputting an ac signal. Gain1 = VO 2 × 150 kΩ = R VI1 I1 VO 2 × 150 kΩ Gain 2 = = R VI 2 I2 1 V   V  ----------------------(9) V   ---------------------(10) V As output power increases, interconnect resistance (PCB traces and wires) between the amplifier, load and power supply create a voltage drop. The voltage loss on the traces between the EUA2011 and the load results is lower output power and decreased efficiency. Higher trace resistance between the supply and the EUA2011 has the same effect as a poorly regulated supply, increase ripple on the supply line also reducing the peak output power. The effects of residual trace resistance increases as output current increases due to higher output power, decreased load impedance or both. To maintain the highest output voltage swing and corresponding peak output power, the PCB traces that connect the output pins to the load and the supply pins to the power supply should be as wide as possible to minimize trace resistance. The use of power and ground planes will give the best THD+N performance. While reducing trace resistance, the use of power planes also creates parasite capacitors that help to filter the power supply line. The inductive nature of the transducer load can also result in overshoot on one or both edges, clamped by the parasitic diodes to GND and VDD in each case. From an EMI stand- point, this is an aggressive waveform that can radiate or conduct to other components in the system and cause interference. It is essential to keep the power and output traces short and well shielded if possible. Use of ground planes, beads, and micro-strip layout techniques are all useful in preventing unwanted interference. As the distance from the EUA2011 and the speaker increase, the amount of EMI radiation will increase since the output wires or traces acting as antenna become more efficient with length. What is acceptable EMI is highly application specific. Ferrite chip inductors placed close to the EUA2011 may be needed to reduce EMI radiation. The value of the ferrite chip is very application specific. C I1 = C I2 = (2πR I1f c1 ) -----------------------------------------(11) (2πR I2 f c 2 ) -----------------------------------------(12) R I1 × R I 2 1 CP = C I1 + C I 2 -------------------------------------------(13) RP = (R I1 + R I2 ) ------------------------------------- (14) Figure 35. Application Schematic with EUA2011 Summing Two Single-Ended Input DS2011 Ver 1.1 Dec. 2007 14 EUA2011 Packaging Information TDFN-8 DETAIL A SYMBOLS A A1 b D D1 E E1 e L MILLIMETERS MIN. MAX. 0.70 0.80 0.00 0.05 0.20 0.40 2.90 3.10 2.30 2.90 3.10 1.50 0.65 0.25 0.45 INCHES MIN. 0.028 0.000 0.008 0.114 0.090 0.114 0.059 0.026 0.010 0.018 0.122 MAX. 0.031 0.002 0.016 0.122 DS2011 Ver 1.1 Dec. 2007 15 EUA2011 WCSP-9 SYMBOLS A A1 D D1 E E1 MILLIMETERS MIN. MAX. 0.675 0.15 0.35 1.45 1.55 0.50 1.45 1.55 0.50 INCHES MIN. 0.006 0.057 0.020 0.057 0.020 0.061 MAX. 0.027 0.014 0.061 DS2011 Ver 1.1 Dec. 2007 16