74ABT244

74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs May 1992 Revised March 2005 74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs General Description The ABT244 is an octal buffer and line driver with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. Features s Non-inverting buffers s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching, noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT244CSC 74ABT244CSJ 74ABT244CMSA 74ABT244CMSAX_NL (Note 1) 74ABT244CMTC 74ABT244CMTCX_NL (Note 1) 74ABT244CPC Package Number M20B M20D MSA20 MSA20 MTC20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Pb-Free 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS010992 www.fairchildsemi.com 74ABT244 Connection Diagram Pin Descriptions Pin Names OE1, OE2 Description Output Enable Input (Active LOW) I0–I7 O0–O7 Inputs Outputs Truth Table OE1 H L L I0–3 X H L O0–3 Z H L OE2 H L L I4–7 X H L O4–7 Z H L H H IGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance www.fairchildsemi.com 2 74ABT244 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) 65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Enable Input 50 mV/ns 20 mV/ns 40qC to 85qC 4.5V to 5.5V 0.5V to 5.5V 0.5V to VCC Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. 500 mA 10V DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 Min 2.0 0.8 Typ Max Units V V V V V Min Min Min Max Max Max 0.0 0  5.5V 0  5.5V Max Max 0.0 Max Max Max VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN IOH IOH IOL VIN VIN VIN VIN VIN IID 1.2 18 mA 3 mA 32 mA 64 mA 2.7V (Note 5) VCC 7.0V 0.5V (Note 5) 0.0V 1.9 PA PA PA PA V 1 1 All Other Pins Grounded IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 5) Note 4: For 8 bits toggling, ICCD  0.8 mA/MHz. Note 5: Guaranteed, but not tested. 10 PA PA mA VOUT VOUT VOUT VOUT VOUT 2.7V; OEn 0.5V; OEn 0.0V VCC 2.0V 2.0V 10 100 275 50 100 50 30 50 2.5 2.5 50 PA PA PA mA 5.5V; All Others GND All Outputs HIGH All Outputs LOW OE n VI VCC, VCC  2.1V VCC  2.1V VCC  2.1V PA mA mA All Others at V CC or Ground Max Enable Input VI Data Input V I Outputs OPEN OE n GND, (Note 4) One Bit Toggling, 50% Duty Cycle PA mA/ All Others at V CC or Ground No Load 0.1 MHz Max 3 www.fairchildsemi.com 74ABT244 DC Electrical Characteristics (SOIC package) Conditions Symbol Parameter Min Typ Max Units VCC CL RL VOLP VOLV VOHV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 0.5 0.8 V V V V 0.8 V 5.0 5.0 5.0 5.0 5.0 TA TA TA TA TA 50 pF, 500: 25qC (Note 6) 25qC (Note 6) 25qC (Note 8) 25qC (Note 7) 25qC (Note 7) 1.3 2.7 2.0 0.8 3.1 1.5 1.1 Note 6: Max number of outputs defined as (n). n  1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n  1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n  1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP package) TA Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.0 1.0 1.5 1.5 1.7 1.7 VCC CL 25qC 5V 50 pF Typ 2.5 2.3 3.5 3.6 3.5 3.3 Max 3.6 3.6 6.0 6.0 5.6 5.6 TA 55qC to 125qC 4.5V–5.5V 50 pF Max 5.3 5.0 6.5 7.9 7.6 7.9 CL Min 1.0 1.0 0.8 1.2 1.2 1.0 TA 40qC to 85qC 4.5V–5.5V 50 pF Max 3.6 3.6 6.0 6.0 5.6 5.6 ns ns ns Units CL VCC VCC Min 1.0 1.0 1.5 1.5 1.7 1.7 Extended AC Electrical Characteristics (SOIC package) TA40qC to 85qC VCC Symbol Parameter CL 4.5V–5.5V 50 pF TA 40qC to 85qC 4.5V–5.5V 250 pF CL TA 40qC to 85qC 4.5V–5.5V 250 pF Units CL VCC VCC 8 Outputs Switching (Note 9) Min fTOGGLE tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Max Toggle Frequency Propagation Delay Data to Outputs Output Enable Time 1.5 1.5 1.5 1.5 1.0 1.0 Typ 100 5.0 5.0 6.5 6.5 5.6 5.6 Max 1 Output Switching (Note 10) Min 1.5 1.5 2.5 2.5 (Note 12) Max 6.0 6.0 7.5 7.5 8 Outputs Switching (Note 11) Min 2.5 2.5 2.5 2.5 Max MHz 8.5 8.5 10.0 12.0 (Note 12) ns ns ns Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 12: The 3-STATE delays are dominated by the RC network (500:, 250 pF) on the output and have been excluded from the datasheet. www.fairchildsemi.com 4 74ABT244 Skew TA 40qC to 85qC 4.5V–5.5V 50 pF CL TA 40qC to 85qC 4.5V–5.5V 250 pF Units CL VCC Symbol Parameter VCC 8 Outputs Switching (Note 15) Max 8 Outputs Switching (Note 16) Max 1.8 1.8 2.5 2.5 3.0 tOSHL (Note 13) tOSLH (Note 13) tPS (Note 17) tOST (Note 13) tPV (Note 14) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH–HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 0.8 0.8 1.0 1.0 1.5 ns ns ns ns ns Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). The specification is guaranteed but not tested. Note 14: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 15: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 16: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 17: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Capacitance Symbol CIN COUT (Note 18) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0 1 MHz, per MIL-STD-883, Method 3012. Units pF pF VCC VCC 0V 5.0V Conditions TA 25qC Note 18: COUT is measured at frequency f 5 www.fairchildsemi.com 74ABT244 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load AC Waveforms FIGURE 5. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 2. Test Input Signal Levels Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements FIGURE 6. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 4. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 7 www.fairchildsemi.com 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com 74ABT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 10 74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com