74ACTQ08

74ACTQ08 Quiet Series™ Quad 2-Input AND Gate May 2007 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate Features ■ ICC reduced by 50% ■ Guaranteed simultaneous switching noise level and tm General Description The ACTQ08 contains four, 2-input AND gates and utilizes Fairchild Quiet Series™ technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance. dynamic threshold performance ■ Improved latch-up immunity ■ Outputs source/sink 24mA ■ TTL-compatible inputs Ordering Information Order Number 74ACTQ08SC 74ACTQ08SJ Package Number M14A M14D Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names An, Bn On Inputs Outputs Description FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation. ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Supply Voltage DC Input Diode Current VI = –0.5V VI = VCC + 0.5V VI IOK DC Input Voltage DC Output Diode Current VO = –0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage Parameter Rating –0.5V to +7.0V –20mA +20mA –0.5V to VCC + 0.5V –20mA +20mA –0.5V to VCC + 0.5V ±50mA ±50mA –65°C to +150°C ±300mA 140°C DC Output Source or Sink Current Storage Temperature DC Latch-Up Source or Sink Current Junction Temperature ICC or IGND DC VCC or Ground Current per Output Pin Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA ∆V / ∆t Supply Voltage Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate: Parameter Rating 4.5V to 5.5V 0V to VCC 0V to VCC –40°C to +85°C 125mV/ns VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 2 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate DC Electrical Characteristics TA = +25°C Symbol VIH VIL VOH TA = –40°C to +85°C Units V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 1.5 75 –75 µA mA mA mA µA V V V V V Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA VIN = VIL or VIH: Typ. 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 Guaranteed Limits 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 IOH = –24mA IOH = –24mA(1) 0.001 0.001 VIN = VIL or VIH: IOL = 24mA IOL = 24mA(1) VI = VCC, GND V I = VCC – 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND Figures 1 & 2(3) Figures 1 & 2(3) (4) 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 0.6 IOUT = 50µA 4.5 5.5 IIN ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 2.0 1.1 –0.6 1.9 1.2 1.5 –1.2 2.2 0.8 20.0 (4) Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND. 4. Max number of data inputs (n) switching. (n–1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1MHz. ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 3 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate AC Electrical Characteristics TA = +25°C, CL = 50pF Symbol tPLH tPHL TA = –40°C to +85°C, CL = 50pF Min. 2.5 2.5 Parameter Propagation Delay, Data to Output Propagation Delay, Data to Output VCC (V)(5) 5.0 5.0 5.0 Min. 2.5 2.5 Typ. 6.0 6.0 0.5 Max. 6.5 6.5 1.0 Max. 7.0 7.0 1.0 Units ns ns ns tOSHL, tOSLH Output to Output Skew(6) Notes: 5. Voltage range 5.0 is 5.0V ± 0.5V. 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Conditions VCC = OPEN VCC = 5.0V Typ. 4.5 70 Units pF pF ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 4 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: ■ Determine the quiet output pin that demonstrates the Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50pF, 500Ω. 2. Deskew the HFS generator so that no two channels have greater than 150ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. ■ Measure VOLP and VOLV on the quiet output during worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. ■ Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: ■ Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. ■ First increase the input LOW voltage level, VIL, until the output begins to oscillator steps out a min of 2ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. ■ Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. ■ Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Notes: 7. VOHV and VOLP are measured with respect to ground reference. 8. Input pulses have the following characteristics: f = 1MHz, tr = 3ns, tf = 3ns, skew < 150ps. Figure 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. Figure 2. Simultaneous Switching Test Circuit ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 5 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 6 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 7 74ACTQ08 Quiet Series™ Quad 2-Input AND Gate TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ 2 E CMOS™ ® EcoSPARK EnSigna™ FACT Quiet Series™ ® FACT ® FAST FASTr™ FPS™ ® FRFET GlobalOptoisolator™ GTO™ HiSeC™ ® i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ Motion-SPM™ MSX™ MSXPro™ OCX™ OCXPro™ ® OPTOLOGIC ® OPTOPLANAR PACMAN™ PDP-SPM™ POP™ ® Power220 ® Power247 PowerEdge™ PowerSaver™ Power-SPM™ ® PowerTrench Programmable Active Droop™ ® QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ ® SPM STEALTH™ SuperFET™ SuperSOT™ -3 SuperSOT™ -6 SuperSOT™ -8 SyncFET™ TCM™ ® The Power Franchise ™ TinyBoost™ TinyBuck™ ® TinyLogic TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ ® UHC UniFET™ VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I26 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production ©1990 Fairchild Semiconductor Corporation 74ACTQ08 Rev. 1.3 www.fairchildsemi.com 8