74ACTQ544

74ACQ544 • 74ACTQ544 Quiet Series Octal Registered Transceiver with 3-STATE Outputs March 1990 Revised September 2000 74ACQ544 • 74ACTQ544 Quiet Series Octal Registered Transceiver with 3-STATE Outputs General Description The ACQ/ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The 544 inverts data in both directions. The ACQ/ACTQ utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Features s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s 8-bit inverting octal latched transceiver s Separate controls for data flow in each direction s Back-to-back registers for storage s Outputs source/sink 24 mA Ordering Code: Order Number 74ACQ544SC 74ACQ544SPC 74ACTQ544SC 74ACTQ544SPC Package Number M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0 –A7 Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B0 –B7 B-to-A Data Inputs or A-to-B 3-STATE Outputs FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010685 www.fairchildsemi.com 74ACQ544 • 74ACTQ544 Logic Symbols Functional Description The ACQ/ACTQ544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0 –A7 or take data from B0 –B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs. IEEE/IEC Data I/O Control Table Inputs CEAB H X L X L LEAB X H L X X OEAB X X X H L Latch Status Latched Latched Transparent — — Output Buffers High Z — — High Z Driving H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74ACQ544 • 74ACTQ544 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-up Source or Sink Current Junction Temperature (TJ) PDIP 140°C −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150 °C ±300 mA Recommended Operating Conditions Supply Voltage VCC ACQ ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t ACQ Devices VIN from 30% to 70% of VCC VCC @3.0V, 4.5V, 5.5V Minimum Input Edge Rate ∆V/∆t ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics for ACQ Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOLD IOHD IOZT Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum I/O Leakage Current VOLP Quiet Output Maximum Dynamic VOL 5.5 ±0.6 ±6.0 µA 5.5 5.5 5.5 8.0 75 −75 80.0 mA mA µA VOLD = 1.65V Max VOHD = 3.85V Min VIN= VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.0 1.1 1.5 V Figures 1, 2 (Note 5)(Note 6) 5.5 0.002 0.001 0.001 TA = + 25°C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ± 0.1 TA = − 40°C to + 85°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 ± 1.0 µA V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND V IOUT = 50 µA V IOH = − 12 mA IOH = − 24 mA IOH = − 24 mA (Note 2) V IOUT = − 50 µA V VOUT = 0.1V or VCC − 0.1V V Units Conditions VOUT = 0.1V or VCC − 0.1V ICC (Note 4) Maximum Quiescent Supply Current 3 www.fairchildsemi.com 74ACQ544 • 74ACTQ544 DC Electrical Characteristics for ACQ Symbol VOLV VIHD VILD Parameter Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 Typ −0.6 3.1 1.9 (Continued) TA = − 40°C to + 85°C Guaranteed Limits −1.2 3.5 1.5 V V V Figures 1, 2 (Note 5)(Note 6) (Note 5)(Note 7) (Note 5)(Note 7) TA = + 25°C Units Conditions Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 5: DIP package. Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND. Note 7: Max number of Data Inputs (n) switching. (n-1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD). f = 1 MHz. DC Electrical Characteristics for ACTQ Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZT ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum I/O Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 9) Maximum Quiescent or GND Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 1.1 −0.6 1.9 1.2 8.0 1.5 −1.2 2.2 0.8 0.6 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ± 0.1 ±0.6 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ± 1.0 ±6.0 1.5 75 −75 80.0 µA µA mA mA mA µA V V V V V Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = − 50 µA VIN = VIL or VIH V IOH = − 24 mA IOH = − 24 mA (Note 8) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 8) VI = VCC, GND VI, (OE) = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Figure 1, Figure 2 (Note 10)(Note 11) Figure 1, Figure 2 (Note 10)(Note 11) (Note 10)(Note 12) (Note 10)(Note 12) Note 8: All outputs loaded; thresholds on input associated with output under test. Note 9: Maximum test duration 2.0 ms, one output loaded at a time. Note 10: DIP package. Note 11: Max number of outputs defined as (n-1). Data Inputs are driven 0V to 3V, one output @ GND. Note 12: Max number of Data Inputs (n) switching (n-1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 4 74ACQ544 • 74ACTQ544 AC Electrical Characteristics for ACQ VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA, LEAB to An, Bn Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Output to Output Skew (Note 14) 3.3 5.0 1.0 0.5 1.5 1.0 1.5 1.0 ns 3.3 5.0 1.0 1.0 7.5 5.0 10.5 7.0 1.0 1.0 11.0 7.5 ns 3.3 5.0 3.3 5.0 1.5 1.5 1.5 1.5 8.5 6.0 10.0 7.0 12.0 8.0 14.0 9.5 1.5 1.5 1.5 1.5 12.5 8.5 15.0 10.0 ns ns (V) (Note 13) 3.3 5.0 Min 1.5 1.5 TA = +25°C CL = 50 pF Typ 8.0 5.0 Max 11.0 7.5 TA = − 40°C to + 85°C CL = 50 pF Min 1.5 1.5 Max 12.0 8.0 ns Units Note 13: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements for ACQ VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An or Bn to LEBA or LEAB Latch Enable, B to A Pulse Width, LOW Note 15: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.0V ± 0.3V TA = +25°C CL = 50 pF Typ 3.0 1.5 4.0 TA = − 40°C to + 85°C CL = 50 pF Guaranteed Minimum 3.0 1.5 4.0 ns ns ns Units (V) (Note 15) 3.3 5.0 3.3 5.0 3.3 5.0 5 www.fairchildsemi.com 74ACQ544 • 74ACTQ544 AC Electrical Characteristics for ACTQ VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Parameter Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA, LEAB to An, Bn Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn Output to Output Skew (Note 17) 5.0 0.5 1.0 1.0 ns 5.0 1.0 5.5 7.5 1.0 8.0 ns 5.0 1.5 8.0 10.0 1.5 10.5 ns 5.0 1.5 6.5 8.5 1.5 9.0 ns 5.0 1.5 5.5 7.5 1.5 8.5 ns (V) (Note 16) Min TA = + 25°C CL = 50 pF Typ Max TA = − 40°C to + 85°C CL = 50 pF Min Max Units Note 16: Voltage Range 5.0 is 5.0V ± 0.5V Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements for ACTQ VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An or Bn to LEBA or LEAB Latch Enable, B to A Pulse Width, LOW Note 18: Voltage Range 5.0 is 5.0V ± 0.5V TA = + 25°C CL = 50 pF Typ TA = − 40°C to + 85°C CL = 50 pF Guaranteed Minimum Units (V) (Note 18) 5.0 5.0 5.0 3.0 1.5 4.0 3.0 1.5 4.0 ns ns ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 80.0 Units pF pF VCC = 5.0V VCC = 5.0V Conditions www.fairchildsemi.com 6 74ACQ544 • 74ACTQ544 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability on the measurements. Note A. VOHV and VOLP are measured with respect to ground reference. Note B. input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms FIGURE 2. Simultaneous Switching Test Circuit 7 www.fairchildsemi.com 74ACQ544 • 74ACTQ544 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 8 74ACQ544 • 74ACTQ544 Quiet Series Octal Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com