74ALS161

DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter April 1984 Revised February 2000 DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter General Description These synchronous presettable counters feature an internal carry look ahead for application in high speed counting designs. The DM74ALS162B is a four-bit decade counter, while the DM74ALS161B and DM74ALS163B are four-bit binary counters. The DM74ALS161B clears asynchronously, while the DM74ALS162B and DM74ALS163B clear synchronously. The carry output is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform. These counters are fully programmable, that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the load input are perfectly acceptable regardless of the logic levels on the clock or enable inputs. The DM74ALS161B clear function is asynchronous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. These two counters are provided with a clear on power-up feature. The DM74ALS162B and DM74ALS163B clear function is synchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs. LOW-to-HIGH transitions at the clear input of the DM74ALS162B and DM74ALS163B are also permissible regardless of the levels of logic on the clock, enable or load inputs. The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two count enable inputs (P and T) and a ripple carry output. Both count enable inputs must be HIGH to count. The T input is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse with a duration approximately equal to the high level portion of QA output. This high level overflow ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable P or T inputs of the DM74ALS161B through DM74ALS163B may occur regardless of the logic level on the clock. The DM74ALS161B through DM74ALS163B feature a fully independent clock circuit. changes made to control inputs (enable P or T, or load) that will modify the operating mode will have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable set-up and hold times. Features s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart s Improved AC performance over Schottky and low power Schottky counterparts s Synchronously programmable s Internal look ahead for fast counting s Carry output for n-bit cascading s Synchronous counting s Load control line s ESD inputs Ordering Code: Order Number DM74ALS161BM DM74ALS161BN DM74ALS162BM DM74ALS162BN DM74ALS163BM DM74ALS163BN Package Number M16A N16E M16A N16E M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS006206 www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Connection Diagram Mode Select Table Clear L H H H H Load Enable T Enable P X L H H H X X H L X X X H X L Action on the Rising Clock Edge ( Reset (Clear) Load (Pn → Qn) Count (Increment) No Change (Hold) No Change (Hold) )  H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagrams DM74ALS161B www.fairchildsemi.com 2 DM74ALS161B • DM74ALS162B • DM74ALS163B Logic Diagrams (Continued) DM74ALS162B DM74ALS163B 3 www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Timing Diagrams DM74ALS162B www.fairchildsemi.com 4 DM74ALS161B • DM74ALS162B • DM74ALS163B Timing Diagrams (continued) DM74ALS161B, DM74ALS163B 5 www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical θJA N Package M Package 78.1°C/W 106.8°C/W 7V 7V 0°C to +70°C −65°C to +150°C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK tSETUP Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Setup Time Data; A, B, C, D En P, En T DM74ALS162B DM74ALS163B Load Clear (Only for DM74ALS162B and DM74ALS163B) Setup 1 (Only for 161B) tHOLD Hold Time Clear Inactive Data; A, B, C, D En P, En T Load Clear (Only for DM74ALS162B and DM74ALS163B Hold 0 (Only for 161B) tW Width of Clock or Clear Pulse Width of Load Pulse TA Operating Free Air Temperature Note 2: The symbol (↑) indicates that the rising edge of the clock is used as a reference. Parameter Min 4.5 2 Nom 5 Max 5.5 0.8 −0.4 8 Units V V V mA mA MHz ns ns ns ns ns ns 0 15↑ (Note 2) DM74ALS161B 15↑ (Note 2) 15↑ (Note 2) 15↑ (Note 2) LOW HIGH 15↑ (Note 2) 12↑ (Note 2) 10 0↑ (Note 2) 0↑ (Note 2) 0↑ (Note 2) 0↑ (Note 2) 0 12.5 15 15 0 4 −3 −3 −4 −7 −4 40 ns ns ns ns ns ns ns ns ns 70 °C Clear CLK HIGH or LOW DM74ALS161B CLR LOW www.fairchildsemi.com 6 DM74ALS161B • DM74ALS162B • DM74ALS163B Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Symbol VIK VOH VOL II IIH IIL IO ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current at Max Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current VCC = 5.5V, VIH = 7V VCC = 5.5V, VIH = 2.7V VCC = 5.5V, VIL = 0.4V VCC = 5.5V, VO = 2.25V VCC = 5.5V −30 12 IOH = −0.4 mA VCC = 4.5V to 5.5V VCC = 4.5V IOL = 4 mA IOL = 8 mA Conditions VCC = 4.5V, II = −18 mA VCC − 2 0.25 0.35 0.4 0.5 0.1 20 −0.2 −112 21 Min Typ Max −1.5 Units V V V V mA µA mA mA mA Switching Characteristics DM74ALS161B over recommended operating free air temperature range. Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output Clear Clear En T Clock Clock En T Conditions VCC = 4.5V to 5.5V RL = 500Ω CL = 50 pF Clock Clock Ripple Carry Ripple Carry Any Q Any Q Ripple Carry Ripple Carry Any Q Ripple Carry From To Min 40 5 5 4 6 3 3 8 11 20 20 15 20 13 13 24 23 Max Units MHz ns ns ns ns ns ns ns ns Switching Characteristics DM74ALS162B, DM74ALS163B over recommended operating free air temperature range. Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output En T Clock Clock En T Conditions VCC = 4.5V to 5.5V RL = 500Ω CL = 50 pF TA = Min to Max Clock Clock Ripple Carry Ripple Carry Any Q Any Q Ripple Carry Ripple Carry From To Min 40 5 5 4 6 3 3 20 20 15 20 13 13 Max Units MHz ns ns ns ns ns ns 7 www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 8 DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com