74F779

74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs April 1988 Revised March 2000 74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs General Description The 74F779 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applications. All control functions (hold, count up, count down, synchronous load) are controlled by two mode pins (S0, S1). The device also features carry lookahead for easy cascading. All state changes are initiated by the rising edge of the clock. Features s Multiplexed 3-STATE I/O ports s Built-in lookahead carry capability s Count frequency 100 MHz typ s Supply current 80 mA typ s Available in SOIC (300 mil only) Ordering Code: Order Number 74F779SC 74F779PC Package Number M16B N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram © 2000 Fairchild Semiconductor Corporation DS009593 www.fairchildsemi.com 74F779 Unit Loading/Fan Out Pin Names I/O0–I/O7 S0, S1 OE CET CP TC Data Inputs Data Outputs Select Inputs Output Enable Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Terminal Count Output (Active LOW) Description U.L. HIGH/LOW 0.25/0.33 75/15 (12.5) 0.25/0.33 0.25/0.33 0.25/0.33 0.25/0.33 25/12.5 Input IIH/IIL Output IOH/IOL 5 µA/−0.2 mA −3 mA/24 mA (20 mA) 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA −1 mA/20 mA Function Table S1 X X L (Not LL) H L L H S0 X X L CET X X X H L L OE H L H X X X CP X Function I/O0 to I/O7 in High Z Flip-Flop Outputs Appear on I/O Lines Parallel Load All Flip-Flops Hold (TC Held HIGH) Count Up Count Down H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition (Not LL) means S0 and S 1 should never both be LOW level at the same time.     X  www.fairchildsemi.com 2 74F779 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F779 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current ((Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V −0.5V to VCC −0.5V to +5.5V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT ICEX VID IOD IZZ IIL IIH + IOZH IIL + IOZL IOS ICCH ICCL ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Bus Drainage Test Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Power Supply Current Power Supply Current Power Supply Current −60 4.75 3.75 500 −0.2 70 −200 −150 90 105 110 10% VCC 5% VCC 10% VCC 5% VCC 2.4 2.7 0.5 0.5 5.0 7.0 0.5 50 Min 2.0 0.8 −1.2 Typ Max Units V V V V V µA µA mA µA V µA µA mA µA µA mA mA mA mA Min Min Min Max Max Max Max 0.0 0.0 0.0 Max Max Max Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −3 mA IOL = 20 mA IOL = 20 mA VIN = 2.7V (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (I/On) VOUT = VCC IID = 1.9 µA All other pins grounded VIOD = 150 mV All other pins grounded VOUT = 5.25V VIN = 0.5V (Non I/O Pins) VOUT = 2.7V (I/On) VOUT = 0.5V (I/On) VOUT = 0V VO = HIGH VO = LOW VO = HIGH Z www.fairchildsemi.com 4 74F779 AC Electrical Characteristics TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to I/On Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay SN to TC Output Enable Time OE to I/On Output Disable Time OE to I/On 100 3.0 5.0 5.0 5.0 2.5 4.5 3.5 3.5 3.0 5.0 1.0 1.0 VCC = +5.0V CL = 50 pF Typ 105 5.0 7.5 7.5 9.3 3.8 6.1 6.5 7.5 5.0 8.0 4.0 3.7 8.0 11.0 9.0 10.5 5.5 8.0 12.0 12.0 7.0 10.0 6.5 6.5 Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 90 3.0 5.0 5.0 5.0 2.5 4.5 3.5 3.5 3.0 5.0 1.0 1.0 8.5 11.0 10.0 11.5 6.0 8.5 13.0 13.0 8.0 10.5 7.0 7.0 ns ns Max Units ns ns ns ns AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time I/On to CP Hold Time I/On to CP Setup Time Sn to CP Hold Time Sn to CP Setup Time CET to CP Hold Time CET to CP Clock Pulse Width HIGH or LOW 5.0 5.0 0.0 0.0 9.5 9.5 0.0 0.0 7.0 7.0 0.0 0.0 4.0 4.0 Max TA = 0°C to +70°C VCC = +5.0V Min 5.0 5.0 0.0 0.0 10.0 10.0 0.0 0.0 7.0 7.0 0.0 0.0 4.0 4.0 Max ns ns ns ns ns Units ns ns 5 www.fairchildsemi.com 74F779 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B www.fairchildsemi.com 6 74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com