74LCX16652

74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs February 1994 Revised April 2001 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs General Description The LCX16652 contains sixteen non-inverting bidirectional bus transceivers with 3-STATE outputs providing multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function (see Functional Description). The LCX16652 is designed for low-voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16652 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V–3.6V VCC specifications provided s 5.7 ns tPD max (VCC = 3.3V), 20 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s ±24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX16652MEA 74LCX16652MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names A0–A15 B0–B15 CPABn, CPBAn SABn, SBAn Description Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs Clock Pulse Inputs Select Inputs OEABn, OEBAn Output Enable Inputs © 2001 Fairchild Semiconductor Corporation DS012005 www.fairchildsemi.com 74LCX16652 Connection Diagram Truth Table (Note 2) Inputs OEAB OEBA1 CPAB1 CPBA1 SAB1 L L X H L L L L H H H H H H H X L L L H H L H or L SBA1 X X X X X X L H X X H Output Output Input Output Input Input Not Specified Output Output Not Specified Output Input Input Input Inputs/Outputs A0 thru A7 Input B0 thru B7 Input Operating Mode Isolation Store A and B Data Store A, Hold B Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition H or L X     X X H or L H or L     X X X X X X X X X X X L H H H or L H or L H or L H or L  Note 2: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins. www.fairchildsemi.com 2 74LCX16652 Functional Description In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the 74LCX16652. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus A to Bus B OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 L L X X X L OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 H H X X L X Transfer Storage Data to A or B Storage OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 H L H or L H or L H H OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 X L L H X H X     X X X X X X X 3 www.fairchildsemi.com 74LCX16652 Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 74LCX16652 Absolute Maximum Ratings(Note 3) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC V mA mA mA mA mA −0.5 to +7.0 −0.5 to +7.0 −0.5 to +7.0 −0.5 to VCC + 0.5 −50 −50 +50 ±50 ±100 ±100 −65 to +150 °C Recommended Operating Conditions (Note 5) Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V − 3.6V VCC = 2.7V − 3.0V VCC = 2.3V − 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 Units V V V ±24 ±12 ±8 −40 0 85 10 mA °C ns/V ∆t/∆V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: U nused (inputs or I/O's) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −8 mA IOH = −12 mA IOH = −18 mA IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF Input Leakage Current 3-STATE I/O Leakage Power-Off Leakage Current 0 ≤ VI ≤ 5.5V 0 ≤ VO ≤ 5.5V VI = V IH or VIL VI or VO = 5.5V Conditions VCC (V) 2.3 − 2.7 2.7 − 3.6 2.3 − 2.7 2.7 − 3.6 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 − 3.6 0 VCC − 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 ±5.0 ±5.0 10 µA µA µA V V TA = −40°C to +85°C Min 1.7 2.0 0.7 0.8 Max Units V V 5 www.fairchildsemi.com 74LCX16652 DC Electrical Characteristics Symbol ICC ∆ICC Parameter Quiescent Supply Current Increase in ICC per Input (Continued) VCC (V) 2.3 − 3.6 2.3 − 3.6 2.3 − 3.6 TA = −40°C to +85°C Min Max 20 ±20 500 µA µA Conditions VI = VCC or GND 3.6V ≤ VI, VO ≤ 5.5V (Note 6) VIH = VCC −0.6V Units Note 6: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V CL = 50 pF Min fMAX tPHL tPLH tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time Hold Time Pulse Width Output to Output Skew (Note 7) Output Disable Time Maximum Clock Frequency Propagation Delay Bus to Bus Propagation Delay Clock to Bus Propagation Delay Select to Bus Output Enable Time 170 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 1.0 1.0 5.7 5.7 6.2 6.2 6.5 6.5 7.0 7.0 6.5 6.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 6.2 6.2 7.0 7.0 7.0 7.0 8.0 8.0 7.0 7.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 6.8 6.8 7.4 7.4 7.8 7.8 9.1 9.1 7.8 7.8 Max VCC = 2.7V CL = 50 pF Min Max VCC = 2.5V ± 0.2V CL = 30 pF Min Max MHz ns ns ns ns ns ns ns ns ns Units Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL =0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL =0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25°C Typical 0.8 0.6 −0.8 −0.6 Units V V Capacitance Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF www.fairchildsemi.com 6 74LCX16652 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V trise and tfall 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V 7 www.fairchildsemi.com 74LCX16652 Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 74LCX16652 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 9 www.fairchildsemi.com 74LCX16652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com