74LS174

DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear August 1992 Revised April 2000 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (175) versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. Features s DM74LS174 contains six flip-flops with single-rail outputs s DM74LS175 contains four flip-flops with double-rail outputs s Buffered clock and direct clear inputs s Individual data input to each flip-flop s Applications include: Buffer/storage registers Shift registers Pattern generators s Typical clock frequency 40 MHz s Typical power dissipation per flip-flop 14 mW Ordering Code: Order Number DM74LS174M DM74LS174SJ DM74LS174N DM74LS175M DM74LS175SJ DM74LS175N Package Number M16A M16D N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74LS174 DM74LS175 © 2000 Fairchild Semiconductor Corporation DS006404 www.fairchildsemi.com DM74LS174 • DM74LS175 Function Table (Each Flip-Flop) Inputs Clear L H H H Clock X ↑ ↑ L D X H L X Q L H L Q0 Outputs Q† H L H Q0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care ↑ = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established. † = D M74LS175 only Logic Diagrams DM74LS174 DM74LS175 www.fairchildsemi.com 2 DM74LS174 • DM74LS175 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0°C to +70°C −65°C to +150°C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DM74LS174 Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK fCLK tW tSU tH tREL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 4) Data Setup Time (Note 4) Data Hold Time (Note 4) Clear Release Time (Note 4) Free Air Operating Temperature Clock Clear 0 0 20 20 20 0 25 0 70 Parameter Min 4.75 2 0.8 −0.4 8 30 25 Nom 5 Max 5.25 Units V V V mA mA MHz MHz ns ns ns ns °C Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 4: TA = 25°C and VCC = 5V. DM74LS174 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL Conditions VCC = Min, II = −18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min Input Current @ Max Input Voltage VCC = Max, VI = 7V HIGH Level Input Current LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current VCC = Max, VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 6) VCC = Max (Note 7) Clock Clear Data −20 16 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 −0.4 −0.4 −0.36 −100 26 mA mA mA mA µA Min Typ (Note 5) Max −1.5 Units V V V Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: N ot more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: W ith all outputs OPEN and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock. 3 www.fairchildsemi.com DM74LS174 • DM74LS175 DM74LS174 Switching Characteristics at VCC = 5V and TA = 25°C From (Input) Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output Clock to Output Clock to Output Clear to Output To (Output) CL = 15 pF Min 30 30 30 35 Max RL = 2 kΩ CL = 50 pF Min 25 32 36 42 Max MHz ns ns ns Units www.fairchildsemi.com 4 DM74LS174 • DM74LS175 DM74LS175 Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK fCLK tW tSU tH tREL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 8) Clock Frequency (Note 9) Pulse Width (Note 10) Data Setup Time (Note 10) Data Hold Time (Note 10) Clear Release Time (Note 10) Free Air Operating Temperature Clock Clear 0 0 20 20 20 0 25 0 70 Parameter Min 4.75 2 0.8 −0.4 8 30 25 Nom 5 Max 5.25 Units V V V mA mA MHz MHz ns ns ns ns °C Note 8: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 9: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 10: TA = 25°C and VCC = 5V. DM74LS175 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL Conditions VCC = Min, II = −18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min Input Current @ Max Input Voltage VCC = Max, VI = 7V HIGH Level Input Current LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current VCC = Max, VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 12) VCC = Max (Note 13) Clock Clear Data −20 11 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 −0.4 −0.4 −0.36 −100 18 mA mA mA mA µA Min Typ (Note 11) Max −1.5 Units V V V Note 11: All typicals are at VCC = 5V, TA = 25°C. Note 12: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 13: With all outputs OPEN and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock input. DM74LS175 Switching Characteristics at VCC = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load) From (Input) Symbol fMAX tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Clock to Q or Q To (Output) CL = 15 pF Min 30 30 Max RL = 2 kΩ CL = 50 pF Min 25 32 Max MHz ns Units Clock to Q or Q 30 36 ns Clear to Q Clear to Q 25 35 29 42 ns ns 5 www.fairchildsemi.com DM74LS174 • DM74LS175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com