74LVQ174SC

74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset February 1992 Revised June 2001 74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset General Description The LVQ174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops. Features s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Guaranteed incident wave switching into 75Ω Ordering Code: Order Number 74LVQ174SC 74LVQ174SJ Package Number M16A M16D Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D5 CP MR Q0–Q5 Description Data Inputs Clock Pulse Input Master Reset Input Outputs © 2001 Fairchild Semiconductor Corporation DS011353 www.fairchildsemi.com 74LVQ174 Functional Description The LVQ174 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LVQ174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs MR L H H H CP D X H L X Output Q L H L Q   X L H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74LVQ174 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±200 mA −65°C to +150°C ±100 mA Recommended Operating Conditions (Note 2) Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 3.0V 125 mV/ns 2.0V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Minimum Dynamic (Note 4) Output Current Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.6 3.6 3.6 3.6 3.3 3.3 3.3 3.3 0.7 −0.6 1.8 1.6 4.0 0.8 −0.8 2.0 0.8 0.002 TA = +25°C Typ 1.5 1.5 2.99 2.0 0.8 2.9 2.58 0.1 0.36 ±0.1 TA = −40°C to +85°C Guaranteed Limits 2.0 0.8 2.9 2.48 0.1 0.44 ±1.0 36 −25 40.0 V V V V V V µA mA mA µA V V V V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND (Note 6)(Note 7) (Note 6)(Note 7) (Note 6)(Note 8) (Note 6)(Note 8) Units Conditions Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: M aximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed. Note 6: Worst case package. Note 7: M ax number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com 74LVQ174 AC Electrical Characteristics TA = +25°C Symbol Parameter VCC (V) fMAX tPLH tPHL tPHL tOSHL, tOSLH Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn Output to Output Skew (Note 9) 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 Min 60 90 2.0 2.0 2.0 2.0 2.5 2.5 CL = 50 pF Typ 90 100 10.8 9.0 10.2 8.5 10.8 9.0 1.0 1.0 16.2 11.5 15.5 11.0 16.2 11.5 1.5 1.5 Max 50 70 1.5 1.5 1.5 1.5 2.0 2.0 18.0 12.5 17.0 12.0 18.0 12.5 1.5 1.5 TA = −40°C to +85°C CL = 50 pF Min Max MHz ns ns ns ns Units Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements TA = +25°C Symbol Parameter VCC (V) tS tH Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP tW tW tREC MR Pulse Width, LOW CP Pulse Width Recovery Time MR to CP 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 2.7 3.3 ± 0.3 Typ 3.0 2.5 1.2 1.0 1.2 1.0 1.2 1.0 0 0 CL = 50 pF 8.0 6.5 4.0 3.0 7.0 5.5 7.0 5.5 3.5 2.5 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 10.0 7.0 4.5 3.0 10.0 7.0 10.0 7.0 3.5 2.5 ns ns Units ns ns ns Capacitance Symbol CIN CPD (Note 10) Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 23 Units pF pF VCC = Open VCC = 3.3V Conditions Note 10: CPD is measured at 10 MHz. www.fairchildsemi.com 4 74LVQ174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com 74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com