74LVTH16240

74LVT16240 • 74LVTH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs March 1999 Revised June 2005 74LVT16240 • 74LVTH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs General Description The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVTH16240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16240 and LVTH16240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16240), also available without bushold feature (74LVT16240) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 16240 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number 74LVT16240MEA 74LVT16240MTD 74LVTH16240MEA 74LVTH16240MTD Package Number MS48A MTD48 MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation DS012025 www.fairchildsemi.com 74LVT16240 • 74LVTH16240 Connection Diagram Pin Descriptions Pin Names OEn I0–I15 O0–O15 Description Output Enable Inputs (Active LOW) Inputs 3-STATE Outputs Truth Table Inputs OE1 L L H Inputs OE2 L L H X Inputs OE3 L L H Inputs OE4 L L H H H IGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Outputs I0–I3 L H X O0–O3 H L Z Outputs I4–I7 L H O4–O7 H L Z Outputs I8–I11 L H X O8–O11 H L Z Outputs I12–I15 L H X O12–O15 H L Z Functional Description The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble (4-bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74LVT16240 • 74LVTH16240 Absolute Maximum Ratings(Note 1) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 2) VI  GND VO  GND VO ! VCC Output at HIGH State VO ! VCC Output at LOW State mA mA mA mA mA V 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to VCC  0.5 50 50 64 128 r64 r128 65 to 150 qC Recommended Operating Conditions Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA 32 64 40 0 85 10 qC ns/V 't/'V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol Parameter VCC (V) 2.7 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 4) II(OD) (Note 4) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3.6 3.6 3.6 0 0–1.5V 3.6 3.6 3.0 Bushold Input Minimum Drive 3.0 75 VCC  0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 V V 2.0 0.8 TA 40qC to 85qC Min Typ (Note 10) VIK VIH VIL VOH Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Max Units Conditions 1.2 V V V II 18 mA VO d 0.1V or VO t VCC  0.1V IOH IOH IOH IOL IOL IOL IOL IOL VI VI 100 PA 8 mA 32 mA 100 PA 24 mA 16 mA 32 mA 64 mA 0.8V 2.0V 75 500 PA PA 10 (Note 5) (Note 6) VI 5.5V 0V or VCC 0V VCC 0.5V to 3.0V GND or VCC 0.5V 3.0V VI VI VI 500 r1 5 1 PA r100 r100 5 5 PA PA PA PA 0V d VI or VO d 5.5V VO VI VO VO 3 www.fairchildsemi.com 74LVT16240 • 74LVTH16240 DC Electrical Characteristics Symbol IOZH ICCH ICCL ICCZ ICCZH Parameter 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current (Continued) TA 40qC to 85qC Min Typ (Note 10) 3.6 3.6 3.6 3.6 3.6 10 0.19 5 0.19 0.19 Max Units Conditions VCC  VO d 5.5V VI VI VI GND or VCC, GND or VCC, GND or VCC, Outputs HIGH mA mA mA Outputs LOW Outputs Disabled VI GND or VCC, VCC d VO d 5.5V, Outputs Disabled One Input at VCC  0.6V Other Inputs at VCC or GND VCC (V) PA mA 'ICC Increase in Power Supply Current (Note 7) 3.3V, TA 25qC. 3.6 0.2 mA Note 3: All typical values are at VCC Note 4: Applies to bushold versions only (LVTH16240). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 (Note 8) TA Min 2 5 qC Typ 0.8 Max Units V V Conditions CL 50 pF, RL (Note 9) (Note 9) 500: 0.8 Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output at LOW. AC Electrical Characteristics TA Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 11) 3.3V, TA 25qC. 40qC to 85qC, CL 3.3V r 0.3V Typ (Note 10) 50 pF, RL 500: VCC 2.7V Max 4.2 4.0 4.9 6.1 5.2 4.4 1.0 Units VCC Max 3.5 3.5 4.0 4.8 4.7 4.2 1.0 Min 1.0 1.0 1.0 1.2 1.7 1.7 Propagation Delay Data to Output Output Enable Time Output Disable Time 1.0 1.0 1.0 1.2 1.7 1.7 ns ns ns ns Note 10: All typical values are at VCC Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 12) Symbol CIN COUT Parameter Input Capacitance Output Capacitance VCC VCC 0V, VI 3.0V, VO Conditions 0V or VCC 0V or VCC Typical 4 8 Units pF pF Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74LVT16240 • 74LVTH16240 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 5 www.fairchildsemi.com 74LVT16240 • 74LVTH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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