74LVTH574SJX

74LVT574 • 74LVTH574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs March 1999 Revised March 2005 74LVT574 • 74LVTH574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description The LVT574 and LVTH574 are high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The LVTH574 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT574 and LVTH574 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH574), also available without bushold feature (74LVT574) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 574 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number 74LVT574WM 74LVT574SJ 74LVT574MSA 74LVT574MTC 74LVT574MTCX_NL (Note 1) 74LVTH574WM 74LVTH574SJ 74LVTH574MSA 74LVTH574MTC 74LVTH574MTCX_NL (Note 1) Package Number M20B M20D MSA20 MTC20 MTC20 M20B M20D MSA20 MTC20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS012451 www.fairchildsemi.com 74LVT574 • 74LVTH574 Logic Symbols Pin Descriptions Pin Names D0–D7 CP OE O0–O7 Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Description IEEE/IEC Truth Table Inputs Dn H L X X CP Outputs OE L L L H On H L Oo Z   L X Connection Diagram H H IGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition Oo Previous Oo before HIGH to LOW of CP  Functional Description The LVT574 and LVTH574 consist of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74LVT574 • 74LVTH574 Absolute Maximum Ratings(Note 2) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI  GND VO  GND VO ! VCC VO ! VCC Output at HIGH State Output at LOW State V mA mA mA mA mA 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 64 128 r64 r128 65 to 150 qC Recommended Operating Conditions Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA 32 64 40 0 85 10 qC ns/V 't/'V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol Parameter VCC (V) 2.7 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3.6 3.6 3.6 0 0–1.5V 3.6 3.6 3.0 Bushold Input Minimum Drive 3.0 75 VCC  0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 V V 2.0 0.8 TA Min 40qC to 85qC Typ (Note 4) Max Units Conditions VIK VIH VIL VOH Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage 1.2 V V V II 18 mA VO d 0.1V or VO t VCC  0.1V IOH IOH IOH IOL IOL IOL IOL IOL VI VI 100 PA 8 mA 32 mA 100 PA 24 mA 16 mA 32 mA 64 mA 0.8V 2.0V 75 500 PA PA 10 (Note 6) (Note 7) VI 5.5V 0V or VCC 0V VCC 0.5V to 3.0V GND or VCC 0.5V 3.0V VI VI VI 500 r1 5 1 PA r100 r100 5 5 PA PA PA PA 0V d VI or VO d 5.5V VO VI VO VO 3 www.fairchildsemi.com 74LVT574 • 74LVTH574 DC Electrical Characteristics Symbol IOZH ICCH ICCL ICCZ ICCZ Parameter 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 8) Note 4: All typical values are at VCC 3.3V, TA 25qC. Note 5: Applies to bushold versions only (74LVTH574). (Continued) TA Min VCC (V) 3.6 3.6 3.6 3.6 3.6 3.6 40qC to 85qC Typ (Note 4) 10 0.19 5 0.19 0.19 0.2 Max Units Conditions VCC  VO d 5.5V Outputs High Outputs Low Outputs Disabled VCC d VO d 5.5V, Outputs Disabled One Input at VCC  0.6V Other Inputs at V CC or GND PA mA mA mA mA mA 'ICC Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 (Note 9) TA Min 25qC Typ 0.8 Max Units V V Conditions CL 50 pF, RL (Note 10) (Note 10) 500: 0.8 Note 9: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA 40qC to 85qC CL 50 pF, RL 500: Symbol Parameter Min fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Note 11: All typical values are at VCC 3.3V, TA 25qC. VCC 3.3V r 0.3V Typ (Note 11) Max VCC Min 150 4.6 4.5 5.2 4.8 4.4 4.8 1.8 1.8 1.5 1.5 2.0 2.0 2.4 0.0 3.3 1.0 1.0 2.7V Max Units Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width Output to Output Skew (Note 12) 150 1.8 1.8 1.5 1.5 2.0 2.0 2.0 0.3 3.3 MHz 5.3 5.3 6.1 5.9 4.4 5.1 ns ns ns ns ns ns 1.0 1.0 ns Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Capacitance (Note 13) Symbol CIN COUT Parameter Input Capacitance Output Capacitance VCC VCC Open, VI 3.0V, VO Conditions 0V or VCC 0V or VCC Typical 4 6 Units pF pF Note 13: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74LVT574 • 74LVTH574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVT574 • 74LVTH574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVT574 • 74LVTH574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com 74LVT574 • 74LVTH574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com