74VCX16835

74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs October 1998 Revised August 2001 74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs General Description The VCX16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Ouputs (O n) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The 74VCX16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s Compatible with PC100 DIMM module specifications s 1.65V–3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (CLK to O n) 4.2ns max for 3.0V to 3.6V VCC 5.2ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Static Drive (IOH/IOL) ±24mA @ 3.0V ±18mA @ 2.3V ±6mA @ 1.65V s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC (OE to GND) through a pulldown resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number 74VCX16835GX (Note 2) 74VCX16835MTD (Note 3) Package Number BGA54A (Preliminary) MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: BGA package available in Tape and Reel only. Note 3: D evices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS500173 www.fairchildsemi.com 74VCX16835 Connection Diagrams Pin Assignment for TSSOP Pin Descriptions Pin Names OE LE CLK I1 - I18 O1 - O18 NC Description Output Enable Input (Active LOW) Latch Enable Input Clock Input Data Inputs 3-STATE Outputs No Connect FBGA Pin Assignments 1 A B C D E F G H J O2 O4 O6 O8 O10 O12 O14 O16 O17 2 O1 O3 O5 O7 O9 O11 O13 O15 O18 3 NC NC VCC GND GND GND VCC OE LE 4 GND NC VCC GND GND GND VCC CLK GND 5 I1 I3 I5 I7 I9 I11 I13 I15 I18 6 I2 I4 I6 I8 I10 I12 I14 I16 I17 Truth Table Inputs OE H Pin Assignment for FBGA L L L L L L LE X H H L L L L CLK X X X In X L H L H X X Outputs On Z L H L H O0 (Note 4) O0 (Note 5) ↑ ↑ H L H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 4: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 5: Output level before the indicated steady-state input conditions were established. (Top Thru View) www.fairchildsemi.com 2 74VCX16835 Logic Diagram 3 www.fairchildsemi.com 74VCX16835 Absolute Maximum Ratings(Note 6) Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 7) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0 V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V −0.5 to VCC + 0.5V −50 mA −50 mA +50 mA ±50 mA ±100 mA −65°C to +150 °C Recommended Operating Conditions (Note 8) Power Supply Operating Data Retention Only Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V Free Air Operating Temperature (TA) Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 6: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 7: IO Absolute Maximum Rating must be observed. Note 8: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. 1.65V to 3.6V 1.2V to 3.6V −0.3V to 3.6V 0V to VCC 0V to 3.6V ±24 mA ±18 mA ±6 mA −40°C to +85°C DC Electrical Characteristics (2.7V < VCC ≤ 3.6V) Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −12 mA IOH = −18 mA IOH = −24 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 12 mA IOL = 18 mA IOL = 24 mA II IOZ IOFF ICC ∆ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0V ≤ VI ≤ 3.6V 0V ≤ VO ≤ 3.6V VI = VIH or VIL 0V ≤ (VI, VO) ≤ 3.6V VI = VCC or GND VCC ≤ (VI, VO) ≤ 3.6V (Note 9) VIH = VCC − 0.6V Note 9: Outputs disabled or 3-STATE only. Conditions VCC (V) 2.7–3.6 2.7–3.6 2.7–3.6 2.7 3.0 3.0 2.7–3.6 2.7 3.0 3.0 2.7–3.6 2.7–3.6 0 2.7–3.6 2.7–3.6 Min 2.0 Max Units V 0.8 VCC − 0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 ±5.0 ±10 10 20 ±20 750 V V V µA µA µA µA µA www.fairchildsemi.com 4 74VCX16835 DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V) Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −6 mA IOH = −12 mA IOH = −18 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 12mA IOL = 18 mA II IOZ IOFF ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current 0V ≤ VI ≤ 3.6V 0V ≤ VO ≤ 3.6V VI = V IH or VIL 0V ≤ (VI, VO) ≤ 3.6V VI = V CC or GND VCC ≤ (VI, VO) ≤ 3.6V (Note 10) Note 10: Outputs disabled or 3-STATE only. Conditions VCC (V) 2.3 - 2.7 2.3 - 2.7 2.3 -2.7 2.3 2.3 2.3 2.3 - 2.7 2.3 2.3 2.3 - 2.7 2.3 - 2.7 0 2.3 - 2.7 2.3 - 2.7 Min 1.6 Max Units V 0.7 VCC − 0.2 2.0 1.8 1.7 0.2 0.4 0.6 ±5.0 ±10 10 20 ±20 V V V µA µA µA µA DC Electrical Characteristics (1.65V ≤ VCC < 2.3V) Symbol VIH VIL VOH VOL II IOZ IOFF ICC Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current IOH = −100 µA IOH = −6 mA IOL = 100 µA IOL = 6mA 0V ≤ VI ≤ 3.6V 0V ≤ VO ≤ 3.6V VI = V IH or VIL 0V ≤ (VI, VO) ≤ 3.6V VI = V CC or GND VCC ≤ (VI, VO) ≤ 3.6V (Note 11) Note 11: Outputs disabled or 3-STATE only. Conditions VCC (V) 1.65 - 2.3 1.65 - 2.3 1.65 - 2.3 1.65 1.65 - 2.3 1.65 1.65 - 2.3 1.65 - 2.3 0 1.65 - 2.3 Min 0.65 × VCC Max Units V 0.35 × V CC VCC − 0.2 1.25 0.2 0.3 ±5.0 ±10 10 20 ±20 V V V µA µA µA µA 5 www.fairchildsemi.com 74VCX16835 AC Electrical Characteristics (Note 12) TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V Min fMAX tPHL, tPLH tPHL, tPLH tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH tW tOSHL tOSLH Maximum Clock Frequency Propagation Delay Bus to Bus Propagation Delay Clock to Bus Propagation Delay LE to Bus Output Enable Time Output Disable Time Setup Time Hold Time Pulse Width Output to Output Skew (Note 13) 250 0.6 1.4 0.6 0.6 0.6 1.5 0.7 1.5 0.5 3.3 4.2 3.8 3.8 3.9 Max VCC = 2.5 ± 0.2V Min 200 0.8 1.5 0.8 0.8 0.8 1.5 0.7 1.5 0.5 4.2 5.2 4.9 4.9 4.5 Max VCC = 1.8 ± 0.15V Min 100 1.5 2.0 1.5 1.5 1.5 2.5 1.0 4.0 0.75 8.4 9.2 9.8 9.8 7.6 Max MHz ns ns ns ns ns ns ns ns ns Units Note 12: For CL=50pF, add approximately 300ps to the AC maximum specification. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). AC Electrical Characteristics Over Load (Note 14) TA = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.15V Symbol Parameter Min tPHL, tPLH tPHL, tPLH tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tPHL, tPLH tS tH Propagation Delay Bus to Bus Propagation Delay Clock to Bus Propagation Delay LE to Bus Output Enable Time Output Disable Time SSO Prop Delay Clock to Bus (Note 15) Setup Time Hold Time 0.7 1.5 0.7 0.7 0.7 1.5 1.5 0.7 CL = 0 pF Max 2.1 3.0 2.6 2.6 2.7 3.3 1.5 0.7 Min 1.0 1.7 1.0 1.0 1.0 CL = 50 pF Max 3.6 4.5 4.1 4.1 4.2 ns ns ns ns ns ns ns ns Units Note 14: This parameter is guaranteed by characterization but not tested. Note 15: SSO = Simultaneous Switching Output. Any output combination of LOW-to-HIGH and/or HIGH-to-LOW transition. Dynamic Switching Characteristics Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA=+25°C Typical 0.35 0.7 0.9 −0.35 −0.7 −0.9 1.3 1.7 2.0 V V V Units www.fairchildsemi.com 6 74VCX16835 Capacitance Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Conditions VI = 0V or VCC, VCC = 1.8V, 2.5V, or 3.3V, VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V TA = +25°C Typical 3.5 5.5 13 Units pF pF pF IOUT - VOUT Characteristics IOH versus VOH FIGURE 1. Characteristics for Output - Pull Up Driver IOL versus VOL FIGURE 2. Characteristics for Output - Pull Down Driver 7 www.fairchildsemi.com 74VCX16835 AC Loading and Waveforms FIGURE 3. AC Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V to ± 0.15V GND FIGURE 4. Waveform for Inverting and Non-inverting Functions tr = tf ≤ 2.0ns, 10% to 90% FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% Symbol Vmi Vmo Vx Vy VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V 1.8 ± 0.15V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V www.fairchildsemi.com 8 74VCX16835 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com 74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com