AN-6083

www.fairchildsemi.com AN-6083 Highly Integrated, Dual-PWM Combination Controller Introduction This application note shows the step-by-step process to design a high-performance power supply which includes a flyback converter for standby power and a single forward converter for main power. Design considerations and mathematical equations are presented, as well as guidelines for a printed-circuit-board (PCB) layout. The complete power-supply circuits shown in Figure 1 demonstrate the FAN6791’s ability to manage high-output power while complying with international requirements regarding AC line quality. The FAN6791 is designed for the power supplies to achieve high efficiency. The highly integrated FAN6791 dual-PWM combination controller provides several features to enhance the performance of converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. With the internal highvoltage startup circuitry, the power loss due to bleeding resistors is also eliminated. The built-in synchronized slope compensation of FAN6791 achieves stable peak-currentmode control. The proprietary internal line compensation ensures constant output-power limit. Figure 1. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 Typical Application www.fairchildsemi.com AN-6083 APPLICATION NOTE Startup Circuitry When the power is turned on, the internal current source (typically 2.5mA) charges the hold-up capacitor C6 through a startup resistor RHV. During the startup sequence, the VAC from the bulk capacitor provides a startup current of about 2.5mA and charges the capacitor C6. RHV can be directly connected by VAC to the HV pin. As the VDD pin reaches the start threshold voltage VTH-ON, the FAN6791 activates and signals the MOSFET. The high-voltage source current is switched off, and the supply current is drawn from the auxiliary winding of the main transformer. VAC VTH-ON IDD 6mA 80µA 10µA VDD 7.5V 10V 16V Figure 3. UVLO Specification If the secondary output short circuits or the feedback loop is open, the FB pin voltage rises rapidly toward the open-loop voltage, VFB-OLP. Once the FB voltage remains above VFBOLP for tOLP, the FAN6791 stops emitting output pulses. To further limit the input power under a short-circuit or openloop condition, a special two-step UVLO mechanism prolongs the discharge time of the VDD capacitor. Figure 4 shows the traditional UVLO method with the special twostep UVLO method. In the two-step UVLO mechanism, an internal sinking current, ITH-OLP, pulls the VDD voltage toward the VTH-OLP. This sinking current is disabled after the VDD drops below VTH-OLP; after which, the VDD voltage is charged towards VTH-ON. With the addition of the two-step UVLO mechanism, the average input power during shortcircuit or open-loop condition is greatly reduced and overheating doesn’t occur. 16V V DD 10V General UVLO Gate RHV HV FAN6791 GND VDD IHV tD_ON C6 Figure 2. Startup Circuit for Power Transfer The minimum power-on delay time is determined as: t D _ ON = ( C6 × VTH −ON ) 2.5mA (1) where VTH-ON is the turn-on threshold voltage and tD_ON is the power-on delay time of the power supply. Due to the low startup current, a large RHV, such as 100kΩ, can be used. With a hold-up capacitor of 22µF, the poweron delay tD_ON is less than 300ms for 90VAC input. When the supply current is drawn from the transformer, it draws a leakage current of about 10µA from pin HV. The power dissipation of the RHV is: 16V V DD 10V 7.5V PHV = I HV −CS 2 × RHV (2) Gate Two Step UVLO where IHV-CS is the supply current drawn from the HV pin. Figure 4. UVLO Effect Under-Voltage Lockout (UVLO) FAN6791 has a voltage detector on the VDD pin to ensure that the chip has enough power to drive the MOSFET. Figure 3 shows a hysteresis of the turn-on and turn-off threshold levels and an open-loop-release voltage. The turn-on and turn-off thresholds of the FAN6791 are internally fixed at 16V and 10V, respectively. During startup, the VDD capacitor must be charged to 16V to enable the IC. The capacitor continues to supply the VDD until the energy can be delivered from the auxiliary winding of the main transformer. The VDD must not drop below 10V during the startup sequence. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 2 Oscillator and Green Mode Resistor RI programs the frequency of the internal oscillator. A 24kΩ resistor RI generates 50µA reference current II and determines the PWM frequency as 65KHz: I I (mA) = 1.2 RI (kΩ ) 1560 RI (kΩ) (3) f OSC (kHz) = (4) The range of the PWM oscillation frequency is designed as 33KHz ~ 130KHz. FAN6791 integrates frequency hopping www.fairchildsemi.com AN-6083 APPLICATION NOTE function internally. The frequency variation ranges from around 61KHz to 69KHz for a center frequency 65KHz. The frequency hopping function helps reduce EMI emission of a power supply with minimum line filters. Remote On/Off Figure 8 shows the remote on / off function. When the supervisor FPO pin pulls down and enables the system by connecting an opto-coupler, VREF applies to the ON/OFF pin to enable forward PWM stage. RI RI FAN6791 GND Figure 5. Setting the PWM Frequency Figure 8. Remote On/Off For power saving, flyback PWM stage has a green mode function. Frequency linearly decreases when VFBFYB is within VG and VN. Once VFBFYB is lower than VG, switching frequency disables, and it enters burst mode. Interleave Switching The FAN6791 uses interleaved switching to synchronize the stand-by PWM / forward PWM stages. This reduces switching noise and spreads the EMI emissions. Figure 9 shows off-time tOFF is inserted in between the turn-off of the stand-by gate drives and the turn-on of the forward PWM. Figure 6. Oscillation Frequency in Green Mode Line Voltage Detection (VRMS) Xxx Figure 7 shows a resistive divider with low-pass filtering for line-voltage detection on VRMS pin. The VRMS voltage is used for brownout protection: when VRMS drops below 0.8V, OPWM turns off. Figure 9. Interleaved Switching FBFYB and FBPWM The FAN6791 is designed for peak-current-mode control. A current-to-voltage conversion is done externally with a current-sense resistor RS. Under normal operations, the peak inductor is controlled by an FBFYB level as: I PEAK = VFBFYB − 1.3 3.2 × RS (5) when VFBFYB is less than 1.3V, the FAN6791 terminates the output pulses. Figure 10 is a typical feedback circuit consisting mainly of a shunt regulator and an opto-coupler. R1 and R2 form a voltage divider for the output voltage regulation. R3 and C1 are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB = 47Ω, CFB = 1nF) placed on the FB pin to the GND can further increase the stability. Figure 7. Line-Voltage Detection on VRMS Pin © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 www.fairchildsemi.com 3 AN-6083 APPLICATION NOTE FB RFB CFB RB VOUT effective, highly efficient, compact flyback power supply operating in CCM without additional external components. The positive ramp added is: R3 C1 R1 VSLOPE = ΔVSLOPE × D where ΔVSLOPE = 0.37V and D = duty cycle. (7) R2 Figure 10. Feedback Circuit The maximum sourcing current of the FB pin is 1.04mA. The phototransistor must be capable of sinking this current to pull FB level down at no load. The value of the biasing resistor RB is determined as: VOUT − VD − VZ × K ≥ 2 mA RB Figure 11. Synchronized Slope Compensation (6) where: VD is the drop voltage of photodiode, approximately 1.2V; VZ is the minimum operating voltage, 2.4V of the shunt regulator; and K is the current transfer rate (CTR) of the opto-coupler. For output voltage VOUT = 5V, with CTR = 100%, the maximum value of RB is 560Ω. Constant Power Control To limit the output power of the converter constantly, a powerlimit function is included. Sensing the converter input voltage through the VRMS pin, the power limit function generates a relative peak-current-limit threshold voltage for constant power control, as shown in Figure 12. Built-In Slope Compensation A flyback converter can be operated in either discontinuous current mode (DCM) or continuous current mode (CCM). There are many advantages to operating the converter in CCM. With the same output power, a converter in CCM exhibits a smaller peak inductor current than in DCM; therefore, a small-sized transformer and a low-rated MOSFET can be applied. On the secondary side of the transformer, the RMS output current of DCM can be twice that of the CCM. Larger wire gauge and output capacitors with larger ripple-current ratings are required. DCM operation also results in higher output-voltage spikes. A large LC filter has to be added. A flyback converter in CCM achieves better performance with a lower component cost. Despite the above advantages of CCM operation, there is one concern—stability. In CCM operation, the output power is proportional to the average inductor current, while the peak current remains controlled. This causes sub-harmonic oscillation when the PWM duty cycle exceeds 50%. Adding slope compensation (reducing the current-loop gain) is an effective way to prevent oscillation. The FAN6791 introduces a synchronized positive-going ramp (VSLOPE) in every switching cycle to stabilize the current loop. Therefore, the FAN6791 can be used to design a cost © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 Figure 12. Constant Power Compensation Leading Edge Blanking (LEB) A voltage signal proportional to the MOSFET current develops on the current-sense resistor RS. Each time the MOSFET is turned on, a spike is induced by the diode reverse recovery and by the output capacitances of the MOSFET and diode, inevitably appearing on the sensed signal. Inside the FAN6791, a leading-edge blanking time of about 270ns is introduced to avoid premature termination of MOSFET by the spike. Only a small-value RC filter (e.g. 100Ω + 470pF) is required between the SENSE pin and RS. Still, a non-inductive resistor for the RS is recommended. www.fairchildsemi.com 4 AN-6083 APPLICATION NOTE Open-Loop Protection FAN6791’s OCP & SCP are based on the detection of feedback signal on FBPWM pin. As shown in Figure 15, when over current or short circuit occurs, FBPWM is pulled to a high voltage through the feedback loop. After a 95ms debounce time, FAN6791 is turned off. The 600ms time-out signal prevents FAN6791 from being latched off when the input voltage is fast on/off. RS FAN6791 GATE Blanking Circuit SENSE Flyback PWM Figure 13. Turn-On Spike Sense Pin Short-Circuit Protection FAN6791 provides safety protection for power supply production. When a sense resistor is shorted by soldering in production, the pulse-by-pulse current limiting loses efficacy to provide an over-power protection of the unit. The unit may malfunction when the loading is larger than original maximum load. To protect against a short circuit across the current-sense resistor, the controller immediately shuts down if a continuously low voltage (around 0.15V) for 180µs on the SENSE pin is detected. Forward PWM Output Driver / Soft Driving The output stage is a fast totem-pole gate driver capable of directly driving an external MOSFET. An internal Zener diode clamps the driver voltage under 18V to protect the MOSFET against over-voltage. By integrating circuits to control the slew rate of switch-on rising time, the external resistor RG may not be necessary to reduce switching noise, improving EMI performance. VDD Figure 15. Timing for OCP & SCP Forward Transformer The topology used in this application note is dual switch forward, so the maximum duty cycle must be limited to less than 50%. To address transient load, efficiency, and hold-up time considerations, 30% duty cycle is chosen for determining the turn ratio of the transformer. The secondary voltage of 12V, 5V should be: VSEC (12V ) = VSEC (5V ) O N/OFF D river 1 8V GATE RG V12 + VFD12 D V = 5 + VFD 5 D (8) (9) Where, VFD12 and VFD5 are the forward voltage of rectifier diodes of 12V and 5V outputs. D is the duty cycle of the switching signal for steady-state operation. Assume VFD12 and VFD5 are 0.5V and D is 30% duty cycle, VSEC (12V) is 40.5V and VSEC (5V) is 17.17V. FAN6791 Figure 14. Gate Drive © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 www.fairchildsemi.com 5 AN-6083 APPLICATION NOTE The turn ratio is given as: Lab Note = = VOUT VSEC (12V ) VOUT VSEC (5V ) (10) N PRI (VOUT ) N SEC (12V ) N PRI (VOUT ) N SEC (5V ) (11) Before modifying or soldering/de-soldering the power supply, discharge the primary capacitors through the external bleeding resistor. Otherwise, the PWM IC may be destroyed by external high voltage during the process. This device is sensitive to electrostatic discharge (ESD). To improve the production yield, the production line should be ESD protected as required by ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1 standards. If VOUT is 400V, the turn ratio is 69:7:3. The primary winding turns is calculated by Faraday’s Law: VOUT ⋅ = N PRI (VOUT ) × ΔBMAX × Ae (12) Δt N PRI (VOUT ) × ΔBMAX × Ae D/ f 400V × 0.3 / 65kHz = × 108 2500G × 1.07cm 2 = 69 N PRI (VOUT ) (13) Choose ERL35 and the turn ratio is 69:7:3. If the topology is a single-switch forward, the maximum duty cycle can be designed around 40%~45% for the steady-state operation. The turns of the transformer can be calculated using the above equations. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 www.fairchildsemi.com 6 AN-6083 APPLICATION NOTE Printed Circuit Board Layout High-frequency switching current/voltage makes PCB layout a very important design issue. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge/ESD tests. GND3→2→1→4: Potentially better for ESD testing where a ground is not available for the power supply. The ESD-discharge charges go from secondary through the transformer stray capacitance to the GND2 first. Then charges go from GND2 to GND1 and back to the mains. Control circuits should not be placed on the discharge path. Point discharge for common choke can decrease high-frequency impedance and help increase ESD immunity. Should a Y-cap between primary and secondary be required, the Y-cap should be connected to the positive terminal of the C2. If this Y-cap is connected to the primary GND, it should be connected to the negative terminal of the C2 (GND1) directly. Point discharge of the Y-cap also helps with ESD. However, according to safety requirements, the creepage between the two pointed ends should be at least 5mm. Isolating the interference between the dual-PWM stages is also important. The GND 5 provides the single-forwardsignal ground. It should be connected directly to the decoupling capacitor C6 and/or to the GND pin of the FAN6791. The ground in the output capacitor C2 is the major ground reference for power switching, providing a good ground reference and reducing the switching noise of both the dual-PWM stages. Guidelines To improve EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor C2 first, then to the switching circuits (see Figure 16). The high-frequency current loop is in C2 – Transformer – MOSFET – RS – GND – C2. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 4→1) short, direct, and wide. Highvoltage traces related to the drain of the MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, connect this heatsink to ground. As indicated by 3, the control-circuit ground should be connected first, then to other circuitry. As indicated by 2, the area enclosed by the transformer auxiliary winding, D1 and C6 should also be kept small. Place C6 close to the FAN6791 for good decoupling. Two options with different pros and cons for ground connections are recommended: © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 www.fairchildsemi.com 7 AN-6083 APPLICATION NOTE Figure 16. Layout Considerations © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 www.fairchildsemi.com 8 AN-6083 APPLICATION NOTE Reference FAN6791 — Highly Integrated, Dual-PWM Combination Controller AN-6741 — Flyback Power Supply Control with the SG6741 AN-6932 — Applying SG6932 to Control a PFC and Forward/PWM Power Supply DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.2 • 3/11/09 www.fairchildsemi.com 9