AN-682

AN-682 Terminating F100K ECL Inputs AN-682 Fairchild Semiconductor Application Note July 1992 Revised November 2001 Terminating F100K ECL Inputs Introduction Many F100K designs require that certain inputs be presented with a HIGH or LOW level. Because of the construction of the F100K input circuitry, a LOW can be realized by simply leaving the input OPEN. However, a HIGH must be terminated in a special way. Simply tying the input to VCC/VCCA is unacceptable. cuit. The designer should be aware that although Figure 2A, Figure 2B, and Figure 2C supply ECL compatible signals levels, they differ in power consumption and susceptibility to changes in temperature and VEE. For designs where there are multiple unused inputs and extra logic gates available, fanout from the unused gates is possible. As an example, one gate of the 100302 is capable of driving ten quiescent inputs at voltage and current levels typical of F100K as shown in Figure 3. Figure 4 shows in detail the F100K pull-up scheme and the input circuitry. Although the circuits of Figure 2 are good examples, a detailed circuit analysis must include the 50 kΩ input resistor. In Figure 4A, the resistor (RD) which sets the diode biasing current is in parallel with the 50 kΩ input resistor. Similarly, the circuit of Figure 4B shows that R2 is in parallel with the input resistor. The point to emphasize is never tie an F100K input to VCC/ VCCA in order to realize a HIGH preset. Instead, the following is recommended: • For a LOW level — leave input open or tie to VEE. • For a HIGH level — tie input to a diode drop or 0.9V below VCC/VCCA. Remember also that the 50 kΩ input resistor must be considered in the circuit parameter calculations. Design Considerations The ranges of VIH and VIL across VEE (−4.2V to −5.7V for F100K ECL 300 Series) are −870 mV to −1165 mV and −1475 mV to −1830 mV respectively. By staying within these ranges, proper input conditions are assured. Figure 1 shows the voltage versus current for the F100K input transistor. If the input is tied to VCC/VCCA the input transistor saturates (Point D) which can damage internal circuitry. The best VIH to realize a HIGH is a voltage drop of 0.9V below VCC/VCCA. As can be seen from the graph, this locates the quiescent point on the flat part of the curve (Point C) midway within the acceptable range of VIH. Figure 2 shows three ways in which a HIGH can be realized on the input. These circuits allow the user to maintain constant input signals at optimum levels of VEE and temperature. Each circuit can handle multiple fanouts, the number will depend upon the maximum current capability of the cir- A = 50 KΩ Pull-Down Current B = Transition (Switching) Region C = Base Current plus 50 k Ω D = Input Transistor Saturation FIGURE 1. Input Characteristics © 2001 Fairchild Semiconductor Corporation AN010644 www.fairchildsemi.com AN-682 Design Considerations (Continued) B A C Note: Nominal values are shown. FIGURE 2. Equivalent Circuits for HIGH Termination FIGURE 3. Utilizing Unused Gates to Terminate Multiple HIGHs and LOWs www.fairchildsemi.com 2 AN-682 Terminating F100K ECL Inputs Design Design Considerations (Continued) A FIGURE 4. Pull-Up Circuit Examples B Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 3 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com