AN-780

AN-780 Operating ECL from a Single Positive Supply AN-780 Fairchild Semiconductor Application Note May 1991 Revised February 2004 Operating ECL from a Single Positive Supply Introduction ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the only one. Operating ECL from a positive VCC supply is a practical alternative that is gaining in popularity. Positive referenced ECL, or PECL as it is referred to, has been implemented in various mixed signal ASIC for use in the Video Graphics and Communications fields and is used in clock distribution as well. New single supply translator chips are becoming available to facilitate the interface of PECL logic levels to TTL and back again. Logic designers who strive for maximum speed in a system, now can easily replace sections of TTL logic with ECL and operate in PECL fashion from the common TTL VCC supply. Standard Negative Supply ECL Operation and Why Figure 1 shows F100K logic elements operating in standard negative supply ECL configuration. The most positive potential is the primary voltage reference for ECL operation. Standard ECL input and output levels are therefore negative potentials referenced to the stable passive Ground (0V). The inherent F100K voltage compensation permits stable input and output levels over a broad range of VEE’s; i.e., −4.2 to −5.7 VDC for 300 Series F100K. Thus ECL logic operating from a −4.2V VEE is compatible to logic operating from a −5.7V supply assuming both are referenced to a common 0V Ground. Since ECL logic outputs only source currents that originate from the potential applied to its VCC/VCCA pins, the use of a 0V low impedance and low inductance ground potential is the optimum choice for operation. The use of a continuous copper ground plane as the primary ECL reference is the ideal source for the high frequency transient currents demanded by the logic during switching. Note that despite the ideal nature of a ground plane as the primary ECL reference, when mixing TTL (or other noisy circuitry) into ECL systems, the recommendation is to reference the TTL to a separate ground plane. This is to keep the high transient TTL switching energy out of the primary ECL reference and preserve ECL noise margins. When F100K ECL output signal interconnection lengths are direct and short enough, transmission line effects may be ignored and then only a RE output biasing resistor is required for logic operation. Please refer to section seven of the “F100K ECL Logic Databook and Design Guide” for a more detailed explanation of transmission line effects and ECL termination techniques. The RE resistor provides F100K 300 Series Voltage Levels Specified for Standard Negative VEE Supply Operation Level VOH VIH VBB VIL VOL Min Typ Max Units VDC VDC VDC VDC VDC bias to keep the ECL emitter follower output transistor on for both high and low logic states. The RE resistor is normally connected between the ECL output and the most negative potential (VEE) thus permitting “single” supply operation. The VEE potential will ideally be distributed to the ECL logic from a power plane or bus which has low DC series resistance and low AC impedance. The low AC impedance is essential to supply the transient energy needed during switching. Although the inherent nature of ECL by design is to maintain essentially constant IEE current even during switching, the charging and discharging of internal and external capacitances and the switching currents in the RE resistors place transient demands on VEE. The degree to which the user can maintain complementary balance of ECL output loading will greatly influence the nature of the transient IEE demands. −1.025 −0.955 −1.165 −1.320 −1.83 −1.83 −1.705 −0.87 −0.87 −1.475 −1.62 Conditions: VCC/VCCA = 0.0 VDC Ground VEE = −4.2 to −5.7 VDC RT = 50Ω; VTT = −2.0 VDC All Levels W.R.T. Ground FIGURE 1. ECL Standard Operation from a Negative VEE Supply © 2004 Fairchild Semiconductor Corporation AN010919 www.fairchildsemi.com AN-780 Standard Negative Supply ECL Operation and Why The usual recommendation for the VEE plane is to bypass every ECL device at its VEE pin with a good RF quality ceramic capacitor. The point at which the RE resistors return to the VEE plane should also be bypassed particularly if it is a single return from a multiple resistor R-PAK. Values from 0.01 µF to 0.10 µF of the “High K Class II Dielectric” ceramic Z5U grade capacitor are recommended for commercial applications. The lower series inductance inherent in the leadless chip style capacitor is preferred over leaded types for highest frequency performance. The “Mid K Class II Dielectric” ceramic X7R grade capacitor offers acceptable bypass operating characteristics over the broader temperature range of −55°C to +125°C. Bulk bypassing of the VEE plane with a 1 µF to 10 µF is recommended at the point where the VEE supply connects to the plane. Aluminum or Tantalum Electrolytic capacitors are usually used for bulk bypassing. Miniaturized surface mount Electrolytic capacitors are available for use in high density component applications. In typical ECL system designs, some inter-connection lengths will exceed the critical values and force the consideration of transmission line effects. The most common high performance and power efficient termination scheme requires the use of a negative 2.0V VTT termination supply. A single RT resistor in conjunction with the VTT supply will terminate each output's transmission line in its characteristic impedance and will also provide optimum bias to the ECL output transistor. The VTT potential will ideally be distributed to the RT terminators from a power plane which has low DC series resistance and low AC impedance. The low AC impedance is essential to supply the transient energy in the termination resistors during switching. Bypassing VTT wherever RT resistors return to the VTT plane is essential to maintaining the low AC impedance of the plane. Capacitor recommendations for bypassing VTT are the same as for VEE above. The regulation of the VTT supply is not critical. A variation of ±5% from nominal causes typically only ±12 mV variation in output levels for 50Ω terminations or ±7 mV variation for 100Ω terminations. Note that in standard ECL configuration, the VTT supply need only sink current into its negative terminal (single ended VTT operation with positive terminal grounded). VTT here will typically be a simple series regulated supply. If the need for single negative supply operation is paramount, a less power efficient Thevenin termination scheme can be used between the VCC/VCCA and VEE planes and selective use of series damping in conjunction with RE resistors may also be implemented. The PECL Transformation Transforming ECL from negative supply to positive supply operations is conceptually quite easy. Just offset all standard ECL operating potentials by a positive amount equal to an absolute value within the normal VEE operating range. For F100K 300 Series the normal VEE range is −4.5 to −5.7 VDC. A 5V offset fits nicely within the range and happens to match the nominal potential for TTL systems. Thus VEE becomes the 0V ground with VCC/VCCA offset to +5V and VTT (if required) offset to +3 VDC. Figure 2 illustrates the transformation (from Figure 1). (Continued) F100K 300 Series Voltage Levels Specified for Positive VCC Supply [PECL] Operation Level VOH VIH VBB VIL VOL VCC − 1.83 VCC − 1.83 VCC − 1.705 Min VCC − 1.165 VCC − 1.320 VCC − 1.475 VCC − 1.62 Typ Max VCC − 0.87 VCC − 0.87 Units VDC VDC VDC VDC VDC VCC − 1.025 VCC − 0.955 Conditions: VCC/VCCA = 4.2 to 5.7 VDC VEE = 0.0V to Ground RT = 50Ω ; VTT = VCC − 2.0 VDC All Levels W.R.T. Ground FIGURE 2. ECL Operation from a Positive VCC Supply [PECL] Considerations for PECL Operation All the considerations previously discussed for standard operation still apply; i.e., solid isolated and well bypassed reference planes, etc. Some additional considerations apply for PECL operation. PECL input and output levels are referenced to the active positive VCC rail that is variable and subject to line and load regulation. PECL level compatibility between sub-systems or systems can be difficult if precise VCC distribution and accuracy are not maintained throughout. Differential PECL signal transmission and reception between systems may be necessary to ease the VCC accuracy burden. This active positive VCC potential is the primary reference for PECL levels and the source of PECL switching currents. The distribution of VCC to PECL logic is just as important as is the ground distribution to the standard ECL configuration. VCC should be delivered from a continuous copper plane with liberal use of high frequency decoupling capacitors at each PECL device's VCC /VCCA pins. If TTL or other noisy circuitry is to share the VCC, a separate powerplane should be provided. TTL switching transients should be isolated from the PECL VCC plane to preserve PECL noise immunity. Again, differential PECL operation may be warranted for situations where noise control is limited and good common mode noise rejection is required. The various requirements for output termination and bias previously discussed for standard ECL applies directly to PECL operation. Note that the nominal +3V VTT supply in PECL mode is required to sink current into its positive ter2 www.fairchildsemi.com AN-780 Power Supply Sequencing Considerations minal (single ended VTT operation with negative terminal grounded) from the emitter follower outputs through the RT resistors. A current sinking VTT supply will be necessary if operated single ended to ground. The VTT supply should track the VCC supply keeping a nominal 2V offset to assure optimum biasing of the outputs. The VEE for PECL operation is 0V or ground potential and should be distributed from a continuous copper plane in consideration of handling the transients switching currents from the RE bias resistors. Although the PECL VEE plane will be somewhat tolerant of TTL noise, the recommendation is to isolate TTL transient switching energy in a separate TTL ground plane. Powerplanes The dedication and organization of powerplanes is essential to successful ECL system design. Figure 3 illustrates an optimum powerplane implementation for Standard ECL operation on a printed circuit mother board in conjunction with TTL circuitry. Figure 4 shows an optimum powerplane configuration for PECL operation. Note that the dedication and positioning of separate ECL and TTL powerplanes is intended to preserve ECL noise immunity when operating in a mixed signal environment. Copper Plane 1 Signal 2 TTL 0V Ground 3 TTL +5V VCC 4 Auxiliary GND/Power/Thermal 5 ECL − 2V VTT 6 ECL − 4.5V VEE 7 ECL 0V Ground 8 Signal FIGURE 3. Powerplane Layup for Standard ECL Operation Copper Plane 1 Signal 2 TTL 0V Ground 3 TTL +5V VCC 4 Auxiliary GND/Power/Thermal 5 ECL + 3V VTT 6 ECL 0V VEE/Ground 7 ECL + 5V VCC 8 Signal FIGURE 4. Powerplane Layup for Positive Referenced ECL The optimum multiple powerplane approach may not be feasible for some designs. Logic and powerplane partitioning (islands) can be used to control noise when ECL and TTL must share the same powerplane. Figure 5 illustrates the basic concept where areas of a system board are organized by logic type and share the same horizontal powerplane. Low pass filters are usually used to help isolate high frequency signals in sections of the shared plane. Power Supply Sequencing Considerations In logic systems where multiple independent power supplies are used, or where two independently powered systems are connected logically, some consideration must be given to supply sequencing. This is particularly true for 3 (Continued) ECL/PECL logic due to placement of ESD (Electrostatic Discharge) protection diodes on the inputs and outputs. Figure 6 shows the typical ESD diode placement in a F100K 300 Series device. Figure 7 and Figure 8 illustrate independently powered ECL driver and receiver operating with an independent ground referenced VTT termination supply. FIGURE 5. Powerplane and Logic Partitioning FIGURE 6. F100K 300 Series ESD Diode Circuit Placement When the devices (Figure 7) are operated in Standard ECL fashion, VEE1 may be off while VEE2 and VTT remain on without causing a forward bias potential on any of the ESD diodes. Note that both the true and complement outputs of the ECL1 driver will source logic one current simultaneously to the VTT supply when VEE1 is off while VTT remains on. Emitter follower transistors of ECL1 are biased on to a logic high level by the VTT/RT even in absence of VEE1. The potential for VTT current overload exists under these circumstances. When VEE2 is powered off and VTT remains on, the low rail input ESD diode of ECL2 (connected to VEE2) will forward bias and conduct heavily as VTT tries to re-power the VEE2 rail. The diode conduction will be limited by the RT resistor and the impedance of the off VEE2 supply in parallel with the ECL2 logic impedance. Although the ESD diode current density rating will typically support this current overstress, the recommendation is to avoid this by insuring that VEE2 and VTT are ramped together and that VEE2 is never more positive than VTT by 0.5V. When the devices (Figure 8) are operated in PECL fashion, there is a very clear forward bias hazard to ESD diodes when supplies are sequenced. If VCC2 is dropped before VCC1, the positive referenced emitter followers of ECL1 will attempt to re-power up ECL2 through its high rail input ESD diode (connected to VCC). The ECL emitter follower outputs are low impedance voltage sources (6Ω typical) www.fairchildsemi.com AN-780 Single Supply Translators—The New Wave Approach and can source an incredible amount of current (greater than 200 mA each output). Thus VCC2 must never be more negative than VCC1 by 1.0V to avoid current overstress. When VCC1 is powered off and VTT and VEE2 remain on, the output ESD diode of ECL1 (connected to VCC1) will forward bias and conduct heavily as VTT tries to re-power the VCC1 rail. The diode conduction will be current limited by the RT resistor and the impedance of the off VCC1 supply in parallel with the ECL1 impedance. Although the ESD diode current density rating will typically support this current overstress, the recommendation is to avoid this by insuring that VTT is never more positive than VCC1 by 0.5V. If VCC1 and VCC2 are dropped while VTT remains on, then VTT tries to re-power both VCC rails through the output ESD diode of ECL1 and the high rail input ESD diode of ECL2. The forward bias current is limited by the RT resistor and the VCC1/VCC2 supply impedance in parallel with the collective logic impedance. This diode overstress is undesirable and should be avoided by insuring that VTT is never more positive than VCC1 or VCC2 by more than 0.5V. If VTT is dropped before VCC1, then increased load current can flow through the RT resistor from the emitter follower output of ECL1. Therefore VTT ramping should be timed with VCC1 and VCC2. From the previous discussion, the most critical concern is that no PECL receiver should be powered down if driven directly by a powered up PECL driver without some form of current limiting. The inputs to the receiver must be current limited with external resistors of 100Ω or greater to be able to survive the overstress caused if VCC1 is ever permitted to be more positive than VCC2 by more than 1.0V. Although the use of current limiting resistors will alter the effective input edge rates and device propagation delays slightly, careful selection and placement of resistors will minimize device performance degradation. Use of surface mounted chip resistors located close to the input is recommended. (Continued) tive VCC supply. This approach naturally allows each logic family to operate in their conventional and Data Book specified manner. System designers typically are most comfortable with the dual supply approach. This conventional method permits the use of the most familiar design practice for ECL and should easily yield reliable mixed signal system operation. The growing list of F100K 300 Series Dual Supply Translators, as shown in Figure 9, is testimony to the continued popularity and versatility of this approach. Features Data Bits ECL-to-TTL TTL-to-ECL Flow-Thru Latched Registered ECL Differential Input ECL Differential Output ECL Output Drive (Ω) ECL Cutoff (Hi Z) TTL Output Drive (mA) (IOL/IOH) TTL 3-STATE ECL Control Pins TTL Control Pins TPD E to T (ns Max) TPD T to E (ns Max) IEE (mA Max) IEE (mA Max) (Cutoff) ICC (mA Max) 38 65 Note 1: VBB provided for Single-ended Operation 100324 100325 100329 100395 6 X X X X X (Note 1) X 50 50 X 20/−2 24/−3 X X X 4.8 3.0 7.7 3.9 6.4 64/−15 X X X 6 X 8 X X 9 X −70 −37 −199 −199 74 −67 65 FIGURE 9. Table of F100K 300 Series Dual Supply Translators Single Supply Translators— The New Wave Approach Single Supply Translators that allow PECL-to-TTL or TTLto-PECL interfaces are a recent addition to the F100K 300 Series ECL family. Development of these devices is motivated by the need for a convenient technique by which higher performance ECL logic can be integrated into existing TTL systems containing a single positive supply. These devices should also provide a vehicle for new lower cost designs of mixed signal single supply systems. Figure 10 describes three such devices being offered in the F100K 300 Series family. The popularity of PECL operation is expected to grow significantly as designers become more familiar with the technique. As interest and usage of Single Supply Translators increase, the family of this type of device can be expected to expand. A simple illustration of the ease with which the Single Supply Translator can accomplish the interface from TTL to PECL and back to TTL is shown in Figure 11. Note that the translator devices have on chip VCC partitions that facilitate the use of dual powerplanes for the preservation of ECL 4 FIGURE 7. ESD Diodes in Standard ECL Operation FIGURE 8. ESD Diodes in PECL Operation Dual Supply Translators— The Conventional Approach Dual supply ECL-to-TTL and TTL-to-ECL IC translators have been in general use for several years. These devices perform the logic level translations between ECL operating from a negative VEE supply and TTL operating from a posiwww.fairchildsemi.com AN-780 Operating ECL from a Single Positive Supply Single Supply Translators—The New Wave Approach noise immunity. Differential operation on the PECL side of the translator is recommended to be used to maximize Features Data Bits ECL-to-TTL TTL-to-ECL CMOS-to-ECL ECL Differential Input ECL Differential Output ECL Output Drive (Ω) ECL Cutoff (Hi Z) TTL Output Drive (mA) (IOL/IOH) TTL 3-STATE TTL Control Pins CMOS Control Pins TPD E to T (ns Max) TPD T to E (ns Max) TPD C to E (ns Max) IEE (mA Max) (Cutoff) ICC (mA Max) Note 2: VBB provided for Single-ended Operation (Continued) noise immunity. A VBB reference voltage output is provided on the 100390 device to facilitate single ended operation. 100390 6 X X X (Note 2) X 50 24/−3 X X 6.4 1.7 X 100391 6 48 60 FIGURE 10. Table of F100K 300 Series Single Supply Translators FIGURE 11. Use of Single Supply Translators Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com