AN-9050

www.fairchildsemi.com AN-9050 FDMF6704 Power Loss Calculation YoungSub Jeong MCCC Application Engineering Introduction The FDMF6704 DrMOS MCM (Multi Chip Module) product has HS and LS FETs and a gate driver all contained within a single module. The design has been optimized for Synchronous Buck applications. The switching and conduction loss of each HS FET, LS FET and gate driver are critical for system and application design. Generally it is hard to get measurement of each internal loss because of its MCM structure. Instead of measuring each power loss elements, expression of module power loss have been used to show MCM product power related performance. Module power loss is defined to be all power losses dissipated by DrMOS module itself. It includes all HS FET, LS FET and gate driver power losses. Using this approach, a system designer can easily estimate total power loss of the system, and do easy and convenient predictions of design related application performance. This application note explains basic theory of module power loss, and how to use the module power loss calculation tool. It is easy and convenient to use the power loss calculator when the system designer does a particular application design. FDMF6704 are optimized for a 5 V power rail in computing applications. Both pins are normally connected to each other in an application. The VSWH pin is the switch node of Synchronous Buck converter. It is connected to the internal HS FET source and LS FET drain. As a point of view of a module product, VIN, VCIN and VDRV are inputs and VSWH is output. The module power loss and efficiency are defined by formulas as below. Module Power Loss = Module input power – Module output power = (Pin + Pcin&Pdrv) – Psw [W] Module Efficiency = Module output power / Module input power = Psw / (Pin + Pcin&Pdrv) * 100 [%] Power Loss of DrMOS Figure 1 shows a typical Synchronous Buck application circuit using an FDMF6704 DrMOS product. The application schematic is based on a Fairchild Semiconductor FDMF6704 evaluation board which is used for datasheet characterization testing. The circuit includes all components in a Sync Buck converter except for the PWM controller. The PWM control function is accomplished by external voltage compensation loop using a pulse generator and a PC automation program. All passive components and layout, such as input caps, output caps, output inductor and boot cap, are optimized for DrMOS products. Power loss sense point pins of FDMF6704 are VIN, VCIN, VDRV and VSWH. VIN is an input pin for main DC/DC power converting. It is connected to the internal HS FET drain. The current into VIN is related to HS FET switching and conduction losses. Its voltage level is typically 12 V in computing application. The VCIN pin is connected to the VCC of internal gate drive logic. The VDRV pin is used for HS and LS FET gate driving voltage. VCIN & VDRV of © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/14/09 Figure 1. Typical Application Circuit of FDMF6704 The primary power loss elements in a Sync Buck converter are the switching devices and the output inductor. Silicon conduction and switching loss represent the largest element of the power loss in a typical Sync Buck converter. Normally inductor power loss is added to silicon loss to determine the system total performance. Key points of good inductor design include saturation current (adequate to handle peak transients), low DCR, core type, low noise and thermal characteristics. With a properly chosen inductor, module power loss is essentially independent of inductor power loss. Since we want to focus on silicon loss tradeoffs, we will use module power loss as our figure of merit to compare MCM designs. www.fairchildsemi.com APP NOTE NUMBER APPLICATION NOTE Power Loss Measurement Figure 2 shows the power loss diagram of a Fairchild DrMOS evaluation board. The input powers are PIN, PCIN and PDRV. Output power of the module is PSW. POUT is total board output power after power loss of the inductor. POUT is connected to Load. PLmodule Pcin& Pdrv Effi@SW DrMOS FDMF 6704 PLinductor Effi@Out Load Pin Psw Output Inductor Table 1 and Table 2 show an example of power loss definition, measurement and calculation. A Fairchild FDMF6704 evaluation board was used for the testing. Note that module power loss without inductor power loss makes SW node efficiency higher than output node efficiency. Inductor power loss is 0.64 W and it makes output efficiency 1.3 % lower than SW node efficiency. If the inductor value is not optimized, the whole system performance as well as DrMOS will be affected and decreased. All input/output voltage and current are measured with precise DMM and current shunt resistors for accurate data capture. Pout Power Loss Graph in Datasheet The evaluation board total efficiency, SW node efficiency and module power loss are measured and calculated to represent DrMOS product performance in the datasheet. The FDMF6704 datasheet has several graphs which indicate module power loss, output current, normalized module power loss and each design parameter variations. Figure 3 shows an example of a graph in the datasheet for module power loss vs. output current. Figure 2. Ploss Diagram of FDMF6704 Eval Board When designing a Sync Buck application, critical design parameters are input/output voltage, output current, switching frequency and inductor value. Typically input and output voltages are decided by the system application. Switching frequency and output inductor are then optimized to get the best trade-off among dynamic performance, EMI, thermal, BOM, cost, etc. Using module power loss as a figure of merit, it is easy to judge which DrMOS design point is better or not since the module power loss does not include the inductor power loss. In other words, even using different inductors, module power loss can specify the real and accurate power loss of module itself and it is only slightly affected by inductor power loss, if the inductor value is correct and the application design is optimized. PIN PCIN&PDRV PSW POUT PLmodule PLinductor Efficiency@SW Efficiency@Out VIN x IIN [W] VCIN x ICIN [W] (including PDRV) VSW x IOUT [W] VOUT x IOUT [W] PIN + PCIN&PDRV – PSW [W] PSW – POUT [W] PSW/(PIN+PCIN&PDRV)*100 [%] POUT/(PIN+PCIN&PDRV)*100 [%] Figure 3 represents a performance of FDMF6704 with particular parameter values, such as VIN=12 V, VOUT=1.3 V, LOUT=440 nH, Fsw=350 kHz and output current from 0 to 35 A. This graph shows a performance under specific condition. In order to use the datasheet graphs easily in various system designs, normalized power loss graphs for each key parameter are included in the datasheet. In the Figure 4, power loss of the module is plotted with a normalized value according to the output voltage change. The reference value of module power loss for normalization is chosen as 1.3 Vout because this voltage is typical in a computing application, such as multi-phase VRD for Vcore. When the output voltage is 2 V, normalized module power loss will be around 1.13 times higher compared to 1.3 Vout. Figure 3. Module Power Loss vs. Iout Table 1. Power, Power Loss and Efficiency Total Pin [W] 46.49 PLmod [W] 6.771 Psw [W] 39.72 PLind [W] 0.64 Pout [W] 39.08 Effi @SW [%] 85.44 Effi @Out [%] 84.06 Table 2. Power Loss Example at 30A Load © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/14/09 www.fairchildsemi.com 2 APP NOTE NUMBER APPLICATION NOTE Calculation Example of Power Loss All power loss graphs in the FDMF6704 datasheet are generated from measured evaluation board test data. System designer can calculate module power loss with normalized power loss graphs, and estimate performance of the module and application. Examples below show how to calculate module power loss with normalized power loss graphs in datasheet. Example 1 1. Define design parameters Figure 4. Normalized Module Ploss vs. Vout Vin=12 V Vcin & Vdrv=5 V Vout=1.5 V FDMF6704 Evaluation Board The FDMF6704 evaluation board is used for FDMF6704 electrical characterization test. The board specifications and structure are shown in Table 3. Dimension No. of layers Layer sequence Total thickness TOP and BOT GND and PWR 15 x 15 cm 4 layers TOP-GND-PWR-BOT 1.6 mm 1.5 oz (1 oz base + 0.5 oz plating) 1 oz Iout=30 A Fsw=600 kHz Inductor=440 nH 2. Calculate each steps - Find reference design parameter values and module power loss with Figure 3 6.8 W with 12 Vin, 5 Vcin, 1.3 Vout, 30 A, 350 kHz and 440 nH - Find normalized value of module power loss with Figure 4 when Vout is 1.5 V 1.04 - Multiply 6.8 W by 1.04 7.072 W Table 3. Evaluation Board Spec. and Structure - Find normalized value of module power loss with Figure 5 when Fsw is 600 kHz 1.12 - Multiply 7.072 W by 1.12. 7.921 W Table 4 shows reference test condition of evaluation board. VIN VCIN & VDRV VOUT PWM HI/LO FSW IOUT Soaking time LOUT Snubber Air flow Heat sink Ambient Temp. 12 V 5V 1.3 V 5 V/0 V 350 kHz 0~35 A, 5 A step 5 minutes 440 nH/0.32 mOhms/35 A Not used Not used Not used 25 C - The calculated module power loss is 7.921 W. Figure 5. Normalized Module Ploss vs. Fsw Table 4. Evaluation Board Reference Test Condition In this example 1, two design parameters, such as Vout and Fsw, are changed from reference values. The calculated module power loss shows under 0.5 % error compared to the real lab test data. Table 5 shows the module power loss www.fairchildsemi.com 3 © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/14/09 APP NOTE NUMBER APPLICATION NOTE error between calculated result with datasheet graphs and real lab data from test. Calculated Module Ploss 7.921 W Real Module Ploss 7.96 W Ploss Error (1-7.921/7.96)*100 =0.495 % Table 5. Power Loss Error of Example 1 Example 2 1. Define design parameters Vin=10 V Vcin & Vdrv=5.5 V Vout=2 V Iout=25 A Fsw=600 kHz Inductor=320 nH 2. Calculate each steps - Find reference design parameter values and module power loss with Figure 3 4.6 W with 12 Vin, 5 Vcin, 1.3 Vout, 25 A, 350 kHz and 440 nH - Ploss at 10 Vin. Note Figure 6: 4.6 W * 1.016 = 4.674 W - Ploss at 10 Vin and 5.5 Vcin. Note Figure 7 4.674 W * 0.957 = 4.473 W - Ploss at 10 Vin, 5.5 Vcin and 2 Vout. Note Figure 4: 4.473 W * 1.13 = 5.054 W - Ploss at 10 Vin, 5.5 Vcin, 2 Vout and 600 kHz. Note Figure 5: 5.054 W * 1.12 = 5.661 W - Ploss at 10 Vin, 5.5 Vcin, 2 Vout, 600 kHz and 320 nH. Note Figure 8: 5.661 W * 1.007 = 5.7 W - The calculated module power loss is 5.7 W. The error between calculated and real data is around 3.8 %. See Table 6 below for error calculation. Calculated Module Ploss 5.7 W Real Module Ploss 5.489 W Ploss Error (1-5.7/5.489)*100 =-3.844 % Figure 8. Normalized Module Ploss vs. Lout Figure 7. Normalized Module Ploss vs. Vcin&Vdrv Figure 6. Normalized Module Ploss vs. Vin Table 6. Power Loss Error of Example 2 © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/14/09 www.fairchildsemi.com 4 APP NOTE NUMBER APPLICATION NOTE FDMF6704 Ploss Calculation Tool In order to get quick and accurate performance estimation, the automatic power loss calculation tool was developed using concepts mentioned in the previous paragraph. The calculator excel file can be used for estimating FDMF6704 performance regarding power loss and efficiency. Figure 9 shows the table for parameter input. The yellow cells are user input parameters and the blue cells are calculated parameters by internal logic of excel file. Once the user inputs parameter value into the yellow cells, the sheet automatically calculates power loss, efficiency and module temperature, and also generates performance related charts. Note that each user input parameter has a minimum input step. For example, the “VIN” parameter has input range from 5 V to 16 V with 0.5 V step. The “Recommended OUTL” parameter shows a calculated inductor value according to other parameter input. The user can enter this “Recommended OUTL” value into the yellow “OUTL Value” cell. The “Δ IL Ratio Value” depends on application design related to output voltage ripple. The user inputs this value from 20 % to 30 % of Iout for normal Sync Buck application. Figure 11 shows a chart which depicts the calculated efficiency and power loss at module. The user is able to use this chart on another document by copying and pasting. Calculated SW Node Efficiency and Ploss 100 14 95 12 90 Effi@SW [%] 85 80 75 70 65 60 0 5 10 15 20 Iout [A] 25 30 35 40 EFFI@SW [%] PD_MOD [W] 0 8 6 4 2 PD_module [W] PD_module [W] 10 Figure 11. Calculated Efficiency and Power Loss Chart Figure 12 is another example of a chart for module temperature. This chart can be also copied or pasted for end user documentation. Calculated Module Case Top Temp. and Ploss 140 120 14 12 10 8 6 4 MOD_TEMP [C] PD_MOD [W] 2 0 0 5 10 15 20 Iout [A] 25 30 35 40 Figure 9. Input Parameters of Ploss Calculation Tool Module Temp. [ C 100 80 60 40 20 0 Figure 10 is a table which is generated by input parameter values. All design parameters, input/output powers, efficiencies and module case top temperature are generated automatically. The red values mean a warning for overspecification of FDMF6704 maximum current and module temperature. For example, current of 35 A would make 10.93 W module power loss and 145 C module case top temperature. The user should consider specification of FDMF6704 and application when using this design tool. Figure 12. Calculated Module Temp. and Ploss Chart Figure 10. Calculated Power Loss and Efficiency The data used for this tool is based on a real lab test data, and the models of each parameter are extracted with multi element polynomial equations. So its accuracy is good enough to check brief power loss related to performance of FDMF6704. Typical power loss calculation error of this tool at max load is under 5 % compared to real data. Note that some application at various customers would show different performance, if their application circuit, components, board layout and structure are significantly different from Fairchild evaluation board environment. The internal parameters, equations and calculating logic are Fairchild confidential since they are directly related to the HS FET, LS FET and gate driver electrical characteristics. The locked version of FDMF6704 power loss calculator www.fairchildsemi.com 5 © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/14/09 APP NOTE NUMBER APPLICATION NOTE tool will be provided to customers so that its internal parameters should not be opened to outside. If the user would like to use an unlocked version, please contact to Fairchild staff. Summary Fairchild DrMOS FDMF6704 is a multi-chip module product for Sync Buck applications. To specify its performance, the concept of module power loss measurement and calculation is developed. Normalized power loss graphs are added in the datasheet to let the system designer use them for designing various applications. The graphs are based on the real lab test data and have a good accuracy. To support easy and convenient application design, the FDMF6704 automatic power loss calculation tool has been developed. The tool accuracy is a good to match to real data so that the designer is able to use this tool to know how much FDMF6704 application consumes power loss and how the performance it shows, before system design and test. Related Documents FDMF6704 Datasheet: FDMF6704A Datasheet: FDMF6704V Datasheet: FDMF6704/A Power Loss Calculator REV0: FDMF6704V Power Loss Calculator REV0: © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/14/09 www.fairchildsemi.com 6 APP NOTE NUMBER APPLICATION NOTE DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2007 Fairchild Semiconductor Corporation Rev. 1.0.0 • 7/14/09 www.fairchildsemi.com 7