AN4146

www.fairchildsemi.com Application Note AN4146 Design Guidelines for Quasi-Resonant Converters Using FSCQ-series Fairchild Power Switch (FPSTM) Abstract In general, a Quasi-Resonant Converter (QRC) shows lower EMI and higher power conversion efficiency compared to the conventional hard switched converter with a fixed switching frequency. Therefore, it is well suited for color TV applications that are noise sensitive. This application note presents practical design considerations of Quasi-Resonant Converters for color TV applications employing FSCQseries FPSTM (Fairchild Power Switch). It includes designing the transformer, output filter and sync network, selecting the components and closing the feedback loop. The step-by-step design procedure described in this application note will help engineers design Quasi-Resonant Converter easily. To make the design process more efficient, a software design tool, FPS design assistant which contains all the equations described in this application note, is also provided. The design procedure is verified through an experimental prototype converter. DR(n) NS(n) CO(n) Np DR1 NS1 CO1 LP(n) VO(n) CP(n) LP1 VO1 (B+) CP1 AC IN FSCQ-series Sync Drain Cr GND NS2 DR2 LP2 PWM VO2 (Sound) VFB CB Vcc Rcc Ca1 Vco Da Na CO2 CP2 Linear regulator Rd R3 R1 Dz MCU Dzc Ca2 DSY Rbias Rstr CSY RSY1 H11A817A RSY2 KA431 RF CF R2 R1 Q Picture ON Figure 1. Basic Quasi-Resonant Converter (QRC) Using FPS (Color TV Application) 1. Introduction The FSCQ-series FPSTM (Fairchild Power Switch) is an integrated Pulse Width Modulation (PWM) controller and Sense FET specifically designed for Quasi-resonant off-line Switch Mode Power Supplies (SMPS) with minimal external components. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight, while simultaneously increasing efficiency, productivity, and system reliability. Figure 1 shows the basic schematic of an FPS based QuasiResonant Converter for the color TV application, which also serves as the reference circuit for the design process described in this application note. An experimental converter from the design example has been built and tested to show the validity of the design procedure. Rev. 1.0.1 ©2005 Fairchild Semiconductor Corporation AN4146 APPLICATION NOTE 2. Step-by-step Design Procedure 1. Define the system specifications (Vlinemin, Vlinemax, fL , Po , Eff ) 2. Determine DC link capacitor (CDC) and DC link voltage range 3. Determine the reflected output voltage (VRO) 4. Determine the transformer primary side inductance (Lm) 5. Choose proper FPS considering input power and Idspeak 6. Determine the proper core and the minimum primary turns (Npmin) 7. Determine the number of turns for each output and Vcc auxiliary circuit In this section, a design procedure is presented using the schematic of Figure 1 as a reference. Figure 2 illustrates the design flow chart. The detailed design procedures are as follows: [STEP-1] Define the system specifications - Line voltage range (Vlinemin and Vlinemax). - Line frequency (fL). - Maximum output power (Po). - Estimated efficiency (Eff) : The power conversion efficiency must be estimated to calculate the maximum input power. If no reference data is available, set Eff = 0.7~0.75 for low voltage output applications and Eff = 0.8~0.85 for high voltage output applications. In the case of Color TV applications, the typical efficiency is 80~83%. With the estimated efficiency, the maximum input power is given by Po P in = -----E ff (1) 8. Determine the startup resistor For multiple output SMPS, the load occupying factor for each output is defined as Po ( n K L ( n ) = ------------) Po (2) 9. Determine the wire diameter for each winding Is the winding window area (Aw) enough ? N Y Is it possible to change the core ? N Y where Po(n) is the maximum output power for the n-th output. For single output SMPS, KL(1)=1. It is assumed that Vo1 is the reference output that is regulated by the feedback control in normal operation. [STEP-2] Determine DC link capacitor (CDC) and the DC link voltage range. 10. Choose the secondary side rectifier diodes Typically, the DC link capacitor is selected as 2-3uF per watt of input power for universal input range (85-265Vrms) and 1uF per watt of input power for European input range (195V265Vrms). With the DC link capacitor selected, the minimum DC link voltage is obtained as 11. Determine the output capacitors V DC 12. Design the synchronization network min = 2 ⋅ ( V line min 2 P in ⋅ ( 1 – D ch ) ) – ----------------------------------C DC ⋅ f L (3) 13. Design the voltage drop circuit for burst operation where CDC is the DC link capacitor and Dch is the duty cycle ratio for CDC to be charged as defined in Figure 3, which is typically about 0.2. Pin, Vlinemin and fL are specified in STEP-1. The maximum DC link voltage is given as 14. Design the feedback control circuit Design finished V DC max = 2V line max (4) Figure 2. Flow Chart of Design Procedure where Vlinemax is specified in STEP-1. ©2005 Fairchild Semiconductor Corporation 2 APPLICATION NOTE AN4146 [STEP-4] Determine the transformer primary side inductance (Lm) DC link voltage Minimum DC link voltage T1 Dch = T1 / T2 = 0.2 T2 Figure 3. DC Link Voltage Waveform Figure 5 shows the typical waveforms of MOSFET drain current, secondary diode current and the MOSFET drain voltage of a Quasi-Resonant Converter. During TOFF, the current flows through the secondary side rectifier diode and the MOSFET drain voltage is clamped at (VDC+VRO). When the secondary side current reduces to zero, the drain voltage begins to drop because of the resonance between the effective output capacitor of the MOSFET and the primary side inductance (Lm). To minimize the switching loss, the FSCQ-series is designed to turn on the MOSFET when the drain voltage reaches its minimum voltage (VDC -VRO). Ids [STEP-3] Determine the reflected output voltage (VRO) Figure 4 shows the typical waveforms of the drain voltage of Quasi-resonant flyback converter. When the MOSFET is turned off, the DC link voltage (VDC) together with the output voltage reflected to the primary (VRO) is imposed on the MOSFET and the maximum nominal voltage across the MOSFET (Vdsnom) is V ds nom ID = V DC max + V RO (5) where VDCmax is as specified in equation (4). By increasing VRO, the capacitive switching loss and conduction loss of the MOSFET are reduced. However, this increases the voltage stress on the MOSFET as shown in Figure 4. Therefore, VRO should be determined by a trade-off between the voltage margin of the MOSFET and the efficiency. It is typical to set VRO as 120~180V so that Vdsnorm is 490~550V (75~85% of MOSFET rated voltage). V ds V DC +V RO V RO V RO V DC V DC -V RO T ON + VDC VRO FPS Drain T OFF TS TF + Lm VO - Figure 5. Typical Waveforms of Quasi-Resonant Converter + Cr + Vds - To determine the primary side inductance (Lm), the following variables should be determined beforehand. • The minimum switching frequency (fsmin) : The minimum switching frequency occurs at the minimum input voltage and full load condition, which should be higher than the minimum switching frequency of FPS (20kHz). By increasing fsmin, the transformer size can be reduced. However, this results in increased switching losses. Therefore determine fsmin by a trade-off between switching losses and transformer size. Typically, fsmin is set to be around 25kHz. • The falling time of the MOSFET drain voltage (TF) : As shown in Figure 5, the MOSFET drain voltage fall time is half of the resonant period of the MOSFET’s effective output capacitance and primary side inductance. By increasing TF, EMI can be reduced. Meanwhile, this forces an increase of the resonant capacitor (Cr) resulting in increased switching losses. The typical value for TF is 2-2.5us. 3 GND VRO VRO Vdsnom VDC max 0V VRO Vdsnom VRO Figure 4. The Typical Waveform of MOSFET Drain Voltage for Quasi Resonant Converter ©2005 Fairchild Semiconductor Corporation AN4146 APPLICATION NOTE After determining fsmin and TF, the maximum duty cycle is calculated as V RO min D max = ------------------------------------- ⋅ ( 1 – f s × TF ) min V RO + V DC (6) [STEP-6] Determine the proper core and the minimum primary turns. where VDCmin is specified in equation (3) and VRO is determined in STEP-3. Then, the primary side inductance is obtained as Lm ( V DC ⋅ D max ) = --------------------------------------------min 2 ⋅ fs ⋅ P in min 2 (7) Table 2 shows the commonly used cores for C-TV application for different output powers. When designing the transformer, consider the maximum flux density swing in normal operation (∆B) as well as the maximum flux density in transient (Bmax). The the maximum flux density swing in normal operation is related to the hysteresis loss in the core while the maximum flux density in transient is related to the core saturation. With the chosen core, the minimum number of turns for the transformer primary side to avoid the over temperature in the core is given by min where Pin, VDCmin and Dmax are specified in equations (1), (3), and (6), respectively and fsmin is the minimum switching frequency. Once Lm is determined, the maximum peak current and RMS current of the MOSFET in normal operation are obtained as I ds peak NP L m I ds 6 = ------------------------- × 10 ∆ BA e peak (10) V DC D max = ----------------------------------min Lm fs = D max peak ------------- ⋅ I ds 3 min (8) I ds rms (9) where Lm is specified in equation (7), Idspeak is the peak drain current specified in equation (8), Ae is the crosssectional area of the transformer core in mm2 as shown in Figure 6 and ∆B is the maximum flux density swing in tesla. If there is no reference data, use ∆B =0.25~0.30 T. Since the MOSFET drain current exceeds Idspeak and reaches ILIM in a transient or fault condition, the transformer should be designed not to be saturated when the MOSFET drain current reaches ILIM . Therefore, the maximum flux density (Bmax) when drain current reaches ILIM should be also considered as min where VDCmin, Dmax and Lm are specified in equations (3), (6) and (7), respectively and fsmin is the minimum switching frequency. [STEP-5] Choose the proper FPS considering input power and peak drain current. NP With the resulting maximum peak drain current of the MOSFET (Idspeak) from equation (8), choose the proper FPS whose the pulse-by-pulse current limit level (ILIM) is higher than Idspeak. Since FPS has ± 12% tolerance of ILIM, there should be some margin for ILIM when choosing the proper FPS device. Table 1 shows the lineups of FSCQ-series with rated output power and pulse-by-pulse current limit. Maximum Output Power PRODUCT FSCQ0565RT FSCQ0765RT FSCQ0965RT FSCQ1265RT FSCQ1465RT FSCQ1565RT FSCQ1565RP 230VAC 85-265Vac ±15% 70 W 100 W 130 W 170 W 190 W 210 W 250 W 60 W 85 W 110 W 140 W 160 W 170 W 210 W L m I LIM 6 = -------------------- × 10 B max A e (11) ILIM (A) Min 3.08 4.4 5.28 6.16 7.04 7.04 10.12 where Lm is specified in equation (7), ILM is the pulse-bypulse current limit, Ae is the cross-sectional area of the core in mm2 as shown in Figure 6 and Bmax is the maximum flux density in tesla. Figure 7 shows the typical characteristics of ferrite core from TDK (PC40). Since the core is saturated at low flux density as the temperature goes high, consider the high temperature characteristics. If there is no reference data, use Bmax =0.35~0.4 T. The primary turns should be determined as less than Npmin values obtained from equation (10) and (11). Typ 3.5 5 6 7 8 8 11.5 Max 3.92 5.6 7.84 7.84 8.96 8.96 12.88 Aw (mm2) Table 1. FPS Lineups with Rated Output Power Ae (mm2) Figure 6. Window Area and Cross Sectional Area 4 ©2005 Fairchild Semiconductor Corporation APPLICATION NOTE AN4146 M agnetization Curves (typical) M aterial :PC40 25 ℃ N p = n ⋅ N s1 > N p min (13) 500 60 ℃ 100 ℃ where n is obtained in equation (12) and Np and Ns1 are the number of turns for the primary side and the reference output, respectively. The number of turns for the other output (n-th output) is determined as Vo ( n ) + VF ( n ) N s ( n ) = --------------------------------- ⋅ N s1 V o1 + V F1 ( 14 ) 400 Flux density B (mT) 300 200 where Vo(n) is the output voltage and VF(n) is the diode (DR(n)) forward voltage drop of the n-th output, respectively. 100 NS(n) + VF(n) DR(n) + VO(n) Np NS2 + VF2 DR2 VO2 + + VF1 DR1 + VO1 - 0 0 800 M agnetic field H (A/m) 1600 Figure 7. Typical B-H Characteristics of Ferrite Core (TDK/PC40) Linear Regulator Output Power 70-100W 100-150W 150-200W Core EER35 EER40 EER42 EER49 Vcc + 18V Rcc VRO + - VFa + N a Va D a + NS1 Table 2. Commonly Used Cores for C-TV Applications [STEP-7] Determine the number of turns for each output and Vcc auxiliary circuit Figure 8. Simplified Diagram of the Transformer Figure 8 shows the simplified diagram of the transformer. It is assumed that Vo1 is the reference output that is regulated by the feedback control in normal operation. It is also assumed that linear regulator is connected to Vo2 to supply a stable voltage for MCU. First, calculate the turns ratio (n) between the primary winding and reference output (Vo1) winding as a reference as in V R0 n = ------------------------V o1 + V F1 (12) where VRO is determined in STEP-3 and Vo1 is the reference output voltage and VF1 is the forward voltage drop of diode (DR1). Then, determine the appropriate integer for Ns1 so that the resulting Np is larger than Npmin as - Vcc winding design : As shown in Figure 9, FSCQ-series drops all the outputs including the Vcc auxiliary voltage (Va) in standby mode to minimize the power consumption. Because the Vcc auxiliary voltage (Va) changes a over wide range, a regulation circuit using zener diode is typically used to provide a stable supply voltage (Vcc) for FPS in normal operation, as shown in Figure 8. It is typical to design the regulation circuit so that the Vcc voltage is regulated as 18V in normal operation and is above Vcc stop voltage (9V) by 2~3V in standby operation as shown in Figure 9. After FSCQ-series enters into standby mode, the current consumed by FPS drops below 500uA and the voltage drop across Rcc is negligible. ©2005 Fairchild Semiconductor Corporation 5 AN4146 APPLICATION NOTE - Vcc drop resistor (Rcc) : The current consumed by FPS in normal operation is given by Vo2 Vo2normal I cc = I op + I drv ( 18 ) Vo2stby where Iop and Idrv are the currents required for IC operation and MOSFET gate drive, respectively. Iop is given in the data sheet and Idrv is obtained as I drv = V cc ⋅ C iss ⋅ f s Va Vcc ( 19 ) Vanormal 18V Vastby 9V where Ciss is the input capacitance of the MOSFET and fs is the switching frequency. When considering Idrv, it is typical to assume that Vcc is Vz (18V) and fs is 90kHz. The condition for the Vcc drop resistor (Rcc) is given by V co – Vz R cc < ------------------------------------I cc Standby mode normal 2-3 V ( 20 ) Normal mode The heat dissipation of Rcc in normal operation is given by ( v co – Vz ) P a = -------------------------------------------R cc normal 2 Figure 9. Output Voltage Drop in Standby Mode ( 21 ) where Vz is the zener breakdown voltage (typically 18V). In standby mode, Vo2 is regulated by the feedback control and the voltage drop ratio of the Vo2 winding is defined in V 02 + V F2 K drop = -----------------------------------------normal V 02 + V F2 stby (15) When a large voltage drop of more than 20V is required, application circuit shown in Figure 11 is preferred to minimize the power dissipation in the voltage drop circuit. Da 3-5 Ω where VF2 is the diode forward voltage drop of the DR2, and Vo2normaland Vo2stby are the output voltages of Vo2 in normal mode and standby mode, respectively, as shown in Figure 9. Assuming that the Vcc auxiliary voltage (Va) is reduced with the ratio of Kdrop, Va in normal mode is obtained as stby Vcc FSCQ-series Ca1 10kΩ Ca2 Vz (18V) Va normal Va + V Fa = -------------------------------- – V F2 K drop ( 16 ) where Vastby is the minimum voltage of Va in standby mode, which should be larger than Vcc stop voltage of FPS (typically 9V). Notice that the operating current is reduced in standby mode and therefore the voltage drop across Rcc is negligible. It is typical to have a voltage margin of 2-3V when determining Vastby. After determining Vanormal, the number of turns for the Vcc auxiliary winding (Na) is obtained as Va + V Fa N a = -------------------------------------- ⋅ N s1 V o1 + V F1 normal Figure. 10 Vcc Auxiliary Circuit for a Large Voltage Drop [STEP-8] Determine the startup resistor ( 17 ) where VFa is the forward voltage drop of Da as defined in Figure 8. 6 Figure 10 shows the typical circuit of Vcc winding for FSCQ-series. Initially, FPS consumes only startup current (max 50uA) before it begins switching. Therefore, the current supplied through the startup resistor (Rstr) can charge the capacitors Ca1 and Ca2 while supplying startup current to FPS. When Vcc reaches start voltage of 15V (VSTART), FPS begins switching and the current consumed by FPS increases. Then, the current required by FPS is supplied from the transformer’s auxiliary winding. ©2005 Fairchild Semiconductor Corporation APPLICATION NOTE AN4146 [STEP-9] Determine the wire diameter for each winding based on the RMS current of each output. C DC The RMS current of the n-th secondary winding is obtained as V RO ⋅ K L ( n ) 1 – D max ---------------------- ⋅ ------------------------------------( Vo ( n ) + VF ( n ) ) D max AC line Rstr I sec ( n ) I sup rms = I ds rms ( 25 ) Vcc R CC Vco Da FSCQ-series Vz (18V) C a1 C a2 Figure. 11 Startup and Vcc Auxiliary Circuit - Startup resistor (Rstr) : The average of the minimum current supplied through the startup resistor is given by avg min ⎛ 2⋅V ⎞ V line start 1 ⎜ ------------------------------------- – ---------------- ⎟ ⋅ ----------= ⎜ π 2 ⎟R str ⎝ ⎠ where Dmax and Idsrms are specified in equations (6) and (9), Vo(n) is the output voltage of the n-th output, VF(n) is the diode (DR(n)) forward voltage drop, VRO is specified in STEP-3 and KL(n) is the load occupying factor for n-th output defined in equation (2). The current density is typically 5A/mm2 when the wire is long (>1m). When the wire is short with a small number of turns, a current density of 6-10 A/mm2 is also acceptable. Avoid using wire with a diameter larger than 1 mm to avoid severe eddy current losses as well as to make winding easier. For high current output, it is recommended using parallel windings with multiple strands of thinner wire to minimize skin effect. Check if the winding window area of the core, Aw (refer to Figure 6) is enough to accommodate the wires. The required winding window area (Awr) is given by Aw r = Ac ⁄ KF (26) I sup ( 22 ) where Vlinemin is the minimum input voltage, Vstart is the start voltage (15V) of FPS and Rstr is the startup resistor. The startup resistor should be chosen so that Isupavg is larger than the maximum startup current (50uA). If not, Vcc can not be charged up to the start voltage and FPS will fail to start up. The maximum startup time is determined as T str max V start = C e ⋅ -------------------------------------------------avg max ( I sup – I start ) ( 23 ) where Ac is the actual conductor area and KF is the fill factor. Typically the fill factor is 0.2~0.25 for single output applications and 0.15~0.2 for multiple outputs applications. If the required window (Awr) is larger than the actual window area (Aw), go back to the STEP-6 and change the core to a bigger one. Sometimes it is impossible to change the core due to cost or size constraints. In that case, reduce VRO in STEP-3 or increase fsmin, which reduces the primary side inductance (Lm) and the minimum number of turns for the primary (Npmin) shown in equation (7) and (10). Where Ce is the effective Vcc capacitor (Ca1+Ca2) and Istartmax is the maximum startup current (50uA) of FPS. Once the startup resistor (Rstr) is determined, the maximum approximate power dissipation in Rstr is obtained as max⎞ 2 2 max⎞ ⎛⎛V +V ⋅V 2 2⋅V ⎜ ⎝ line ⎟ ⎠ start 1 start line P = ----------- ⋅ ⎜ --------------------------------------------------------------- – ---------------------------------------------------------------- ⎟ str R str ⎜ π 2 ⎟ ⎝ ⎠ [STEP-10] Choose the proper rectifier diodes in the secondary side based on the voltage and current ratings. The maximum reverse voltage and the rms current of the rectifier diode (DR(n)) of the n-th output are obtained as V DC ⋅ ( Vo (n ) + VF ( n ) ) V D ( n ) = V o ( n ) + --------------------------------------------------------------V RO ID ( n ) rms max ( 24 ) ( 27 ) ( 28 ) where Vlinemax is the maximum input voltage, which is specified in STEP-1. The startup resistor should have a proper dissipation rating based on the value of Pstr. = I ds rms V RO K L ( n ) 1 – D max ---------------------- ⋅ ------------------------------------( Vo ( n ) + VF ( n ) ) D max where KL(n), VDCmax, Dmax and Idsrms are specified in equations (2), (4), (6) and (9), respectively, VRO is specified in STEP-3, Vo(n) is the output voltage of the n-th output and VF(n) is the diode (DR(n)) forward voltage drop. The typical ©2005 Fairchild Semiconductor Corporation 7 AN4146 APPLICATION NOTE voltage and current margins for the rectifier diode are as follows V RRM > 1.3 ⋅ V D ( n ) I F > 1.5 ⋅ I D ( n ) rms [STEP-11] Determine the output capacitors considering the voltage and current ripple. (29) (30) The ripple current of the n-th output capacitor (Co(n)) is obtained as rms where VRRM is the maximum reverse voltage and IF is the average forward current of the diode. A quick selection guide for the Fairchild Semiconductor rectifier diodes is given in Table 3. In this table, trr is the maximum reverse recovery time. I cap ( n ) = ( ID ( n ) rms 2 ) – Io ( n) 2 (31) where Io(n) is the load current of the n-th output and ID(n)rms is specified in equation (28). The ripple current should be smaller than the maximum ripple current specification of the capacitor. The voltage ripple on the n-th output is given by I D I peak Ultra Fast Recovery Diode Products EGP10B UF4002 EGP20B EGP30B FES16BT EGP10C EGP20C EGP30C FES16CT EGP10D UF4003 EGP20D EGP30D FES16DT EGP10F EGP20F EGP30F EGP10G UF4004 EGP20G EGP30G UF4005 EGP10J EGP20J EGP30J UF4006 UF4007 VRRM 100 V 100 V 100 V 100 V 100 V 150 V 150 V 150 V 150 V 200 V 200 V 200 V 200 V 200 V 300 V 300 V 300 V 400 V 400 V 400 V 400 V 600 V 600 V 600 V 600 V 800 V 1000 V IF 1A 1A 2A 3A 16 A 1A 2A 3A 16 A 1A 1A 2A 3A 16 A 1A 2A 3A 1A 1A 2A 3A 1A 1A 2A 3A 1A 1A trr 50 ns 50 ns 50 ns 50 ns 35 ns 50 ns 50 ns 50 ns 35 ns 50 ns 50 ns 50 ns 50 ns 35 ns 50 ns 50 ns 50 ns 50 ns 50 ns 50 ns 50 ns 75 ns 75 ns 75ns 75 ns 75 ns 75 ns Package DO-41 DO-41 DO-15 DO-210AD TO-220AC DO-41 DO-15 DO-210AD TO-220AC DO-41 DO-41 DO-15 DO-210AD TO-220AC DO-41 DO-15 DO-210AD DO-41 DO-41 DO-15 DO-210AD DO-41 DO-41 DO-15 DO-210AD TO-41 TO-41 o ( n ) max ds RO C ( n ) L ( n ∆ V o ( n ) = -------------------------- + ----------------------------------------------------------) (32) - Co ( n ) fs min VR K ( Vo ( n ) + VF ( n ) ) where Co(n) is the capacitance, Rc(n) is the effective series resistance (ESR) of the n-th output capacitor, KL(n), Dmax and Idspeak are specified in equations (2), (6) and (8) respectively, VRO is specified in STEP-3, Io(n) and Vo(n) are the load current and output voltage of the n-th output, respectively and VF(n) is the diode (DR(n)) forward voltage drop. Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. In those cases, use additional LC filter stages (post filter) to reduce the ripple on the output. [STEP-12] Design the synchronization network. The FSCQ-series employs a quasi-resonant switching technique to minimize the switching noise and loss. In this technique, a capacitor (Cr) is added between the MOSFET drain and source as shown in Figure 12. The basic waveforms of a Quasi-Resonant Converter are shown in Figure 13. The external capacitor lowers the rising slope of drain voltage, which reduces the EMI caused by the MOSFET turn-off. To minimize the MOSFET switching loss, the MOSFET should be turned on when the drain voltage reaches its minimum value as shown in Figure 13. The optimum MOSFET turn-on time is indirectly detected by monitoring the Vcc winding voltage as shown in Figure 12 and 13. The output of the sync detect comparator (CO) becomes high when the sync voltage (Vsync) exceeds 4.6V and low when the Vsync reduces below 2.6V. The MOSFET is turned on at the falling edge of the sync detect comparator output (CO). Table 3. Fairchild Diode Quick Selection Table ©2005 Fairchild Semiconductor Corporation 8 APPLICATION NOTE AN4146 Np FSCQ-series Sync comparator + CO Drain N s1 V o1 Vds Lm Cr Ids GND VRO VRO 4.6/2.6V Sync Vcc R cc 18V C a1 Vco Da C a2 + V ds - VDC Na Vsync TF Vovp (12V) Vsyncpk D SY 4.6V V sync R SY1 CO TQ 2.6V C SY R SY2 MOSFET Gate Figure. 12 Synchronization Circuit ON ON The peak value of the sync signal is determined by the voltage divider network RSY1 and RSY2 as V sync pk Figure. 13 Synchronization Waveforms R SY2 normal = --------------------------------- ⋅ V a R SY1 + R SY2 ( 33 ) [STEP-13] Design voltage drop circuit for the burst operation. where Vanormal is the Vcc auxiliary voltage in normal mode. Choose the voltage divider RSY1 and RSY2 so that the peak value of sync voltage (Vsyncpk) is lower than the OVP threshold voltage (12V) to avoid triggering OVP in normal operation. It is typical to set Vsyncpk to be 8~10V. To synchronize the Vsync with the MOSFET drain voltage, the sync capacitor (CSY) should be chosen so that TF is same as TQ as shown in Figure 13. TF and TQ are given as T F = π ⋅ L m ⋅ C eo R SY2 ⎛ Va ⎞ = R SY2 ⋅ C SY ⋅ ln ⎜ ------------------- ⋅ --------------------------------- ⎟ 2.6 R SY1 + R SY2⎠ ⎝ normal VO2 VO1 (B+) RD Rbias R1 CF C R Linear Regulator M icom Dz (VZB ) R3 (34) RF D1 Q1 Picture ON TQ (35) KA431 A R2 where Lm is the primary side inductance of the transformer, Ns and Na are the number of turns for the output winding and Vcc winding, respectively, Vanormal is the Vcc auxiliary voltage in normal mode and Ceo is the effective MOSFET output capacitance (Coss+Cr). Figure 14. Typical Feedback Circuit to Drop Output Voltage in Standby Mode To minimize the power consumption in the standby mode, FSCQ-series employs burst operation. Once FPS enters into burst mode, all output voltages and effective switching frequencies are reduced. Figure 14 shows the typical output voltage drop circuit for C-TV applications. Under normal ©2005 Fairchild Semiconductor Corporation 9 AN4146 APPLICATION NOTE operation, the picture on signal is applied and the transistor Q1 is turned on, which de-couples R3, Dz and D1 from the feedback network. Thus, only Vo1 is regulated by the feedback circuit in normal operation and is determined as R1 + R2 V o1 = 2.5 ⋅ ⎛ --------------------⎞ ⎝ R2 ⎠ (36) in Figure 16, the feedback loop can be easily implemented with a one-pole and one-zero compensation circuit. The current control factor of FPS, K is defined as I pk I LIM K = --------- = ----------------V FB V FBsat (38) Figure 15 shows the standby mode operation waveforms. In standby mode, the picture on signal is disabled and the transistor Q1 is turned off, which couples R3, Dz and D1 to the reference pin of KA431. If R3 is much smaller than R1, Vo2 is dominant in the feedback loop. Before Vo2 drops to Vo2stby, the voltage on the reference pin of KA431 is higher than 2.5V, which increases the current through the opto LED. This pulls down the feedback voltage (VFB) of FPS and forces to stop switching. Once FPS stops switching, Vo2 decrease, and when Vo2 reaches Vo2stby, the current through the opto LED decreases allowing the feedback voltage to rise. When the feedback voltage reaches 0.4V, FPS resumes switching with a predetermined peak drain current. Assuming that the forward voltage drop of D1 is 0.5V, the approximate output voltage for Vo2 in standby mode is given by stby where Ipk is the peak drain current and VFB is the feedback voltage for a given operating condition, ILIM is the current limit of the FPS and VFBsat is the internal feedback saturation voltage, which is typically 2.5V. In order to express the small signal AC transfer functions, the small signal variations of feedback voltage (vFB) and ˆ ˆ controlled output voltage (vo1) are introduced as vFB and vo1. vo1 FPS vFB iD CTR :1 vbias RD ibias Rbias RB CB V 02 = V ZB + 0.5 + 2.5 (37) CF RF R1 where VZB is the zener breakdown voltage of Dz. KA431 R2 Vo2 Vo2stby Ipk MOSFET current Figure 16. Control Block Diagram VFB 0.4V For quasi-resonant flyback converter, the control-to-output transfer function using current mode control is given by ˆ v o1 G vc = -------ˆ v FB Ids K ⋅ R L V DC ( N p ⁄ N s1 ) ( 1 + s ⁄ w z ) ( 1 – s ⁄ w rz ) = ---------------------------------------------------- ⋅ ---------------------------------------------------------1 + s ⁄ wp 2 ( 2V RO + v DC ) ( 39 ) Normal mode Standby mode Figure 15. Burst Operation Waveforms where VDC is the DC input voltage, RL is the effective total load resistance of the controlled output, which is defined as Vo12/Po , Np and Ns1 are specified in STEP-7, VRO is specified in STEP-3, Vo1 is the reference output voltage, Po is specified in STEP-1 and K is specified in equation (38). The pole and zeros of equation (39) are defined as RL ( 1 – D ) 1 (1 + D) w z = ------------------- , w rz = ---------------------------------------- and w p = -----------------2 R c1 C o1 R L C o1 DL m ( N s1 ⁄ N p ) 2 [STEP-14] Design the feedback control circuit. Since FSCQ-series employs current mode control as shown where Lm is specified in equation (7), D is the duty cycle of ©2005 Fairchild Semiconductor Corporation 10 APPLICATION NOTE AN4146 the FPS, Co1 is the output capacitor of Vo1 and RC1 is the ESR of Co1. When the converter has more than one output, the low frequency control-to-output transfer function is proportional to the parallel combination of all load resistance, adjusted by the square of the turns ratio. Therefore, the effective load resistance is used in equation (39) instead of the actual load resistance of Vo1. Notice that there is a right half plane (RHP) zero (wrz) in the control-to-output transfer function of equation (39). Because the RHP zero reduces the phase by 90 degrees, the crossover frequency should be placed below the RHP zero. Figure 17 shows the variation of a quasi-resonant flyback converter control-to-output transfer function for different input voltages. This figure shows the system poles and zeros together with the DC gain change for different input voltages. The gain is highest at the high input voltage condition and the RHP zero is lowest at the low input voltage condition. Figure 18 shows the variation of a quasi-resonant flyback converter control-to-output transfer function for different loads. This figure shows that the gain between fp and fz does not change for different loads and the RHP zero is lowest at the full load condition. The feedback compensation network transfer function of Figure 16 is obtained as ˆ w i 1 + s ⁄ w zc v FB -------- = - ---- ⋅ ------------------------ˆs 1 + s ⁄ w pc v o1 R B ⋅ CTR 1 1 where w i = ------------------------ , w zc = -------------- , w pc = -------------R1 RD CF RF CF RB CB 4 dB 0 fp 20 d B L ht loa ig d fp 0dB H vy load ea -2 dB 0 fz -4 dB 0 1H z 10H z 1 Hz 00 1z kH frz frz 1 Hz 0k 10 Hz 0k Figure 18. QR Flyback Converter Contro to Output Transfer Function Variation for Different Loads When the input voltage and the load current vary over a wide range, determining the worst case for the feedback loop design is difficult. The gain together with zeros and poles varies according to the operating conditions. One simple and practical solution to this problem is designing the feedback loop for low input voltage and full load condition with enough phase and gain margin. The RHP zero is lowest at low input voltage and full load condition. The gain increases only about 6dB as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. The procedure to design the feedback loop is as follows (a) Set the crossover frequency (fc) below 1/3 of RHP zero to minimize the effect of the RHP zero. Set the crossover frequency below half of the minimum switching frequency (fsmin). (b) Determine the DC gain of the compensator (wi/wzc) to cancel the control-to-output gain at fc. (c) Place a compensator zero (fzc) around fc/3. (d) Place a compensator pole (fpc) around 3fc. ( 40 ) and RB is the internal feedback bias resistor of FPS, which is typically 2.8kΩ, CTR is the current transfer ratio of opto coupler and R1, RD, RF, CF and CB are shown in Figure 16. 4 dB 0 fp 20 d B Loop gain T 40 dB fp 0dB H input voltage igh 20 dB L input volta ow ge -2 dB 0 fz fzc fp fpc fc frz fz Compensator frz fz frz 0 dB Control to output -20 dB -4 dB 0 1H z 10H z 1 Hz 00 1z kH 1 Hz 0k 10 Hz 0k Figure 17. QR Flyback Converter Control to Output Transfer Function Variation for Different Input Voltages -40 dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz Figure 19. Compensator Design ©2005 Fairchild Semiconductor Corporation 11 AN4146 APPLICATION NOTE When determining the feedback circuit component, there are some restrictions as described below: (a) Design the voltage divider network of R1 and R2 to provide 2.5V to the reference pin of the KA431. The relationship between R1 and R2 is given as 2.5 ⋅ R 1 R 2 = ----------------------V o1 – 2.5 (41) where Vo1 is the reference output voltage. (b) The capacitor connected to feedback pin (CB) is related to the shutdown delay time in an overload condition by T delay = ( V SD – 2.5 ) ⋅ C B ⁄ I delay (42) where VSD is the shutdown feedback voltage and Idelay is the shutdown delay current. Typical values for VSD and Idelay are 7.5V and 5uA, respectively. In general, a 20 ~ 50 ms delay is typical for most applications. Because CB also determines the high frequency pole (wpc) of the compensator transfer function as shown in equation (40), too large a CB can limit the control bandwidth by placing wpc at too low a frequency. Typical value for CB is 10-50nF. (c) The resistors Rbias and RD used together with the optocoupler H11A817A and the shunt regulator KA431 should be designed to provide proper operating current for the KA431 and to guarantee the full swing of the feedback voltage for the FPS device chosen. In general, the minimum cathode voltage and current for the KA431 are 2.5V and 1mA, respectively. Therefore, Rbias and RD should be designed to satisfy the following conditions. V bias – V OP – 2.5 -------------------------------------------- > I FB RD V OP ------------- > 1mA R bias ( 43 ) (44) where Vbias is the KA431 bias voltage as shown in Figure 16 and VOP is opto-diode forward voltage drop, which is typically 1V. IFB is the feedback current of FPS, which is typically 1mA. 12 ©2005 Fairchild Semiconductor Corporation APPLICATION NOTE AN4146 3. Design Example Using FPS Design Assistant Application Color TV Device FSCQ0765RT Input Voltage 85-265Vac (60Hz) Output Power 83W Output Voltage (Rated Current) 125V (0.4A) 24V (0.5A) 18V (0.5A) 12V (1.0A) Ripple Spec ±5% ±5% ±5% ±5% FPS Design Assistant for AN4146 Ver 1.00 by H.S. Choi Blue cells are the input parameters Red cells are the output parameters 1. Define the system specifications Minimum Line voltage (V linemin) Maximum Line voltage (V line Line frequency (fL) max 85 V.rms 265 V.rms 60 Hz V o(n) Io(n) 0.40 0.50 0.50 1.00 P o(n) 50 12 9 12 0 K L(n) 60 14 11 14 0 ) 1st output (Vo1) ; regulated by feedback 2nd output (Vo2) 3rd output (Vo3) 4th output (Vo4) 5th output (Vo5) Maximum output power (P o) = Estimated efficiency (E ff) Maximum input power (P in) = 125 24 18 12 V V V V V A A A A A W W W W W % % % % % 83.0 W 82 % 101.2 W - It is assumed that the efficiency is 83% at the minimum input voltage and full load condition. 2. Determine DC link capacitor and DC link voltage range 220 uF DC link capacitor (CDC) Minimum DC link voltage (VDC min )= )= 91 V 375 V Maximum DC link voltage (VDC max - Since the maximum input power is 101.2W, the DC link capacitor is set to be 220uF by 2uF/Watt. 3. Determine the reflected output (V RO) Output voltage reflected to primary (V RO) Maximum nominal Drain voltage (V ds nom 126 V 501 V )= - VRO is set to be 126V so that Vdsnom should be about 77% of BVdss ©2005 Fairchild Semiconductor Corporation 13 AN4146 APPLICATION NOTE 4. Determine transformer primary side inductance (Lm) 2.3 us Drain voltage falling time (T F) Minimum Switching frequency of FPS (f s_min) 24 kHz Maximum duty cycle (D max) = Primary side inductance (L m) = Maximum peak drain current (Ids RMS drain current (Ids rms peak 0.55 514 uH )= 4.05 A 1.73 A )= 5. Choose the proper FPS considering the input power and current limit 5.00 A Typical current limit of FPS (ILIM) Minimum ILIM considering tolerance 4.40 A ->O.K. > 4.05 A - Considering the tolerance of 12%, FSCQ0765RT is chosen, whose pulse-by-pulse current limit is 5A (typical). 6. Determine the proper core and the minimum primary turns 0.30 T Maximum flux density swing in normal mode ( ∆ Maximum flux density in transient (Bsat) Cross sectional area of core (A e) Minimum primary turns (N p min --> --> 2 Np> 63.69 T Np> 62.07 T 0.38 T 109 mm 63.7 T 2 )= - EER3540 core is chosen, whose cross sectional area is 109mm . 7. Determine the number of turns for each output and Vcc drop circuit Vo2 in standby mode (Vo2stby) 8.0 V Vo2= 24 V in normal mode Vcc auxiliary voltage drop ratio (Kdrop) = Minimum Va in standby mode Va in normal mode (Vanormal) = VF(n) Winding for Va (37.7V) Winding for Vo1 (125V) Winding for Vo2 (24V) Winding for Vo3 (18V) Winding for Vo4 (12V) Winding for Vo5 (V) Number of turns for primary winding (Np)= Ungapped AL value (AL) Gap length (G) ; center pole gap = stby (Va ) 0.37 13.0 V 37.7 V # of turns 1.2 V 19.7 => 20 T 1.2 V 64 => 64 T 13 T 1.2 V 12.8 => 10 T 1.2 V 9.7 => 1.2 V 6.7 => 7T 0T V 0.0 => 64 T > 63.7 T --->enough turns 3130 nH/T2 1.04337 mm 14 ©2005 Fairchild Semiconductor Corporation APPLICATION NOTE AN4146 Maximum operating current of FPS (Iop) MOSFET input capacitance (Ciss) Breakdown voltage of Vcc zener diode Current consummed by FPS (Icc) = Vcc drop resistor (Rcc) Power dissipation of Rcc = 6 mA 1840 18 9.0 1.5 0.3 pF V mA kΩ W at < 90 kHz 2 kΩ - In standby mode, Vo2 is reduced from 24V to 8V. In order to prevent Vcc under voltage lockout in standby mode, Va in standby mode is designed as 13V. Then, Va would be 37.7V in normal mode. -Assuming that the maximum switching frequency is 90kHz, the maximum current consumed by FPS is 9mA. Vcc resistor is determined as 1.5kΩ. 8. Determine the startup resistor Maximum Startup current of FPS (Istart) Startup resistor Effective Vcc capacitor (Ce) Maximum dissipation in startup resistor = Maximum startup time (Tstrmax) = 50 240 20 0.13 3.83 uA kΩ uF W s < at at 616 kΩ 265 Vac 85 Vac 9. Determine the wire diameter for each winding Diameter 0.6 0.3 0.5 0.4 0.4 0.5 Parallel mm × mm × mm × mm × mm × mm × mm × ID(n)rms 1.7 0.1 0.9 1.1 1.1 2.2 ##### (A/mm2) 6.1 1.4 4.8 4.5 4.5 5.5 #### Primary winding Winding for Vcc (37.7V) Winding for Vo1 (125V / 0.4A) Winding for Vo2 (24V / 0.5A) Winding for Vo3 (18V / 0.5A) Winding for Vo4 (12V / 1A) Winding for Vo5 (V / A) Copper area (Ac) = Fill factor (KF) Required window area (Awr) 1 1 1 2 2 2 A A A A A A A 40.56 mm2 0.2 202.78 mm2 - For each winding, the diameter of wire is determined so that the current density should be about 5A/mm2 - For EER3540 core, the winding window area is 223mm2. Assuming a fill factor of 0.2, this core is enough to accommodate the wires. ©2005 Fairchild Semiconductor Corporation 15 AN4146 APPLICATION NOTE 10. Choose the rectifier diode in the secondary side VD(n) Rectifier Rectifier Rectifier Rectifier Rectifier Rectifier diode diode diode diode diode diode for for for for for for Vcc Vo1 Vo2 Vo3 Vo1 Vo5 (125V / 0.4A) (24V / 0.5A) (18V /0.5A) (12V /1A) (V /A) 1N4937 EGP20J (600V/2A) EGP20D (200V/2A) EGP20D (200V/2A) EGP20D (200V/2A) 153 500 99 75 51 0 V V V V V V ID(n)rms 0.10 0.95 1.14 1.12 2.17 ##### Ultra fast recovery Ultra fast recovery Ultra fast recovery Ultra fast recovery Ultra fast recovery A A A A A A Vcc winding Vo1 (125V) Vo2 (24V) Vo3 (18V) Vo4 (12V) 11. Determine the output capacitor Co(n) 100 1000 1000 1000 RC(n) 100 100 100 100 Icap(n) mΩ 0.9 mΩ 1.0 mΩ 1.0 mΩ 1.9 mΩ ##### ΔVo(n) 0.3 0.3 0.3 0.6 #### Output Output Output Output Output capacitor capacitor capacitor capacitor capacitor for for for for for Vo1 Vo2 Vo3 Vo4 Vo5 (125V / 0.4A) (24V / 0.5A) (18V / 0.5A) (12V / 1A) (V / A) uF uF uF uF uF A A A A A V V V V V 12. Design the synchronization network Peak value of Sync voltage (Vsyncpk) Sync voltage divider resistor (Rsy1) Sync voltage divider resistor (Rsy2) Effective output capacitance of MOSFET Sync capacitor (Csy) 9.0 V 1500 Ω 4.6 < Vsyncpk < 12V (VOVP) 470 Ω 1.0 nF ( Coss + Cr ) 3.9 nF - Since the output capacitance of MOSFET is 100pF (typical), external capacitor (Cr) of 1nF is used. 13. Design voltage drop circuit for the burst operation Vo2 in standby mode (Vo2stby) 8.0 V Breakdown voltage of zener diode, Dz 5.0 V - Zener diode with a breakdown voltage of 5.1V is chosen. 16 ©2005 Fairchild Semiconductor Corporation APPLICATION NOTE AN4146 14. Design the feedback control circuit Control-to-output DC gain = Control-to-output zero (wz) = Control-to-output RHP zero (wrz)= Control-to-output pole (wp)= Voltage divider resistor (R1) Voltage divider resistor (R2)= Opto coupler diode resistor (RD) KA431 Bias resistor (Rbias) Feeback pin capacitor (CB) = Feedback Capacitor (CF) = Feedback resistor (RF) = Current transfer ratio of opto coupler (CTR) Feedback integrator gain (wi) = Compensator zero (wzc)= Compensator pole (wpc)= 50 100.0 krad/s => fz= 136.0 krad/s => frz= 82 rad/s => FPS 15,924 Hz 21,650 Hz 13 Hz vo2 vo1 ibias Rbias fp= vFB iD CTR:1 100 ㏀ 2.0 ㏀ 1㏀ 1.2 ㏀ 47 nF 22 nF 39 ㏀ 100 % 1273 rad/s => 1166 rad/s => 7599 rad/s => RD CB CF RF R1 KA431 R2 f i= fzc= fpc= 203 Hz 186 Hz 1,210 Hz 100 80 60 40 Gain (dB) 20 0 1 -20 -40 -60 frequency (Hz) 10 control-to-output Compens ator Clos ed loop gain (T) 100 1000 10000 ©2005 Fairchild Semiconductor Corporation 17 AN4146 APPLICATION NOTE 0 1 -30 10 100 1000 10000 -60 Phase (degree) -90 -120 Control-to-output -150 Compens ator Clos ed loop gain (T) -180 frequency (Hz) - The control bandwidth (crossover frequency) is about 600Hz with a phase margin of 50 degrees. 18 ©2005 Fairchild Semiconductor Corporation APPLICATION NOTE AN4146 Design Summary • • • • • • High efficiency (>80% at 85Vac input) Wider load range through the extended quasi-resonant operation Low standby mode power consumption (