CD4022BCM

CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by-8 Counter/Divider with 8 Decoded Outputs October 1987 Revised January 2004 CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by-8 Counter/Divider with 8 Decoded Outputs General Description The CD4017BC is a 5-stage divide-by-10 Johnson counter with 10 decoded outputs and a carry out bit. The CD4022BC is a 4-stage divide-by-8 Johnson counter with 8 decoded outputs and a carry-out bit. These counters are cleared to their zero count by a logical “1” on their reset line. These counters are advanced on the positive edge of the clock signal when the clock enable signal is in the logical “0” state. The configuration of the CD4017BC and CD4022BC permits medium speed operation and assures a hazard free counting sequence. The 10/8 decoded outputs are normally in the logical “0” state and go to the logical “1” state only at their respective time slot. Each decoded output remains high for 1 full clock cycle. The carry-out signal completes a full cycle for every 10/8 clock input cycles and is used as a ripple carry signal to any succeeding stages. Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VDD (typ.) s Low power Fan out of 2 driving 74L TTL compatibility: or 1 driving 74LS s Medium speed operation: 5.0 MHz (typ.) with 10V VDD s Low power: 10 µW (typ.) s Fully static operation Applications • Automotive • Instrumentation • Medical electronics • Alarm systems • Industrial electronics • Remote metering Ordering Code: Order Number CD4017BCM CD4017BCN CD4022BCM CD4022BCN Package Number M16A N16E M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams CD4017B CD4022B Top View Top View © 2004 Fairchild Semiconductor Corporation DS005950 www.fairchildsemi.com CD4017BC • CD4022BC Logic Diagrams CD4017B Terminal No. 8 = GND Terminal No. 16 = VDD CD4022B Terminal No. 16 = VDD Terminal No. 8 = GND www.fairchildsemi.com 2 CD4017BC • CD4022BC Absolute Maximum Ratings(Note 1) (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260°C (Note 2) 700 mW 500 mW Recommended Operating Conditions (Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) −0.5 VDC to +18 VDC −0.5 VDC to VDD +0.5 VDC −65°C to +150°C +3 VDC to +15 VDC 0 to VDD VDC −55°C to +125°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VDD = 5V VDD = 10V VDD = 15V |IO| < 1.0 µA VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage |IO| < 1.0 µA VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage |IO| < 1.0 µA Conditions −55°C Min Max 5 10 20 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.64 1.6 4.2 −0.25 −0.62 −1.8 −0.1 0.1 3.5 7.0 11.0 0.51 1.3 3.4 −0.2 −0.5 −1.5 4.95 9.95 14.95 Min +25° Typ 0.3 0.5 1.0 0 0 0 5 10 15 1.5 3.0 4.0 Max 5 10 20 0.05 0.05 0.05 +125°C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 Units µA V V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V V VIH HIGH Level Input Voltage |IO| < 1.0 µA VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V V IOL LOW Level Output Current (Note 3) VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V 0.88 2.25 8.8 −0.36 −0.9 −3.5 −10−5 10−5 −0.1 0.1 0.36 0.9 2.4 −0.14 −0.35 −1.1 −1.0 1.0 µA mA mA IOH HIGH Level Output Current (Note 3) IIN Input Current Note 3: IOL and IOH are tested one output at a time. 3 www.fairchildsemi.com CD4017BC • CD4022BC AC Electrical Characteristics Symbol CLOCK OPERATION tPHL, tPLH Propagation Delay Time Carry Out Line Parameter (Note 4) Conditions VDD = 5V VDD = 10V VDD = 15V Min Typ 415 160 130 240 CL = 15 pF 85 70 500 200 160 200 100 80 100 50 40 Measured with Respect to Carry Output Line 1.0 2.5 3.0 2 5 6 125 45 35 250 90 70 20 15 5 120 40 32 5 240 80 65 7.5 pF ns µs ns MHz Max 800 320 250 480 170 140 1000 400 320 360 180 130 200 100 80 ns ns ns ns ns Units TA= 25°C, CL= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified Carry Out Line VDD = 5V VDD = 10V VDD = 15V Decode Out Lines VDD = 5V VDD = 10V VDD = 15V tTLH, tTHL Transition Time Carry Out and Decode Out Lines tTLH VDD = 5V VDD = 10V VDD = 15V tTHL VDD = 5V VDD = 10V VDD = 15V fCL Maximum Clock Frequency VDD = 5V VDD = 10V VDD = 15V tWL, tWH Minimum Clock Pulse Width VDD = 5V VDD = 10V VDD = 15V trCL, tfCL Clock Rise and Fall Time VDD = 5V VDD = 10V VDD = 15V tSU Minimum Clock Inhibit Data Setup Time VDD = 5V VDD = 10V VDD = 15V CIN Average Input Capacitance Note 4: AC Parameters are guaranteed by DC correlated testing. AC Electrical Characteristics RESET OPERATION tPHL, tPLH Propagation Delay Time Carry Out Line (Note 4) Min Typ Max Units TA = 25°C, CL = 50 pF, RL = 200k, trCL and tfCL = 20 ns, unless otherwise specified Symbol Parameter Conditions VDD = 5V VDD = 10V VDD = 15V 415 160 130 240 CL = 15 pF 85 70 500 200 160 200 70 55 75 30 25 800 320 250 480 170 140 1000 400 320 400 140 110 150 60 50 ns ns ns ns ns Carry Out Line VDD = 5V VDD = 10V VDD = 15V Decode Out Lines VDD = 5V VDD = 10V VDD = 15V tW Minimum Reset Pulse Width VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V tREM Minimum Reset Removal Time www.fairchildsemi.com 4 CD4017BC • CD4022BC Timing Diagrams CD4017B CD4022B 5 www.fairchildsemi.com CD4017BC • CD4022BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 6 CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by-8 Counter/Divider with 8 Decoded Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com