FAN6861TY

FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management May 2009 FAN6861 Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Features Low Startup Current: 15µA Maximum Green-Mode and Burst-Mode Operation for Low Standby Power Consumption Internal Soft Start: 10ms Frequency Hopping for EMI Reduction Peak-Current Mode Control with Cycle-by-Cycle Current Limiting Constant Output Power Limit (Full AC Input Range) Built-in Slope Compensation Two-Level Over-Current Protection (OCP) with Delayed Shutdown (780ms) for Peak Power Management Open-Loop / Over-Load Protection (OLP) VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Description Highly integrated PWM controller, FAN6861 is optimized for applications with motor load; such as printer and scanner, which inherently impose some kind of overload condition on the power supply during acceleration mode. The two-level OCP function allows the SMPS to stably deliver peak power during the motor acceleration mode without causing premature shutdown and while protecting the SMPS from overload condition. The green-mode and burst-mode functions with a low operating current (2.2mA maximum in green mode) maximize the light load efficiency so that the power supply can meet most stringent standby power regulations. The frequency-hopping function helps reduce electromagnetic interference (EMI) of a power supply by spreading the energy over a wider frequency range. The constant power limit function; minimizes the components stress in abnormal condition and helps designer to optimize the power stage more easily. Many protection functions such; as OCP, OLP, OVP and OTP, are fully integrated into FAN6861, which improves the SMPS reliability without increasing the system cost. Applications Switched Mode Power Supply (SMPS) with Motor Load; such as for printer, scanner, motor drivers, etc. AC/DC Adapters Open-Frame SMPS Ordering Information Part Number FAN6861TY Operating Temperature Range -40 to +105°C Eco Status Green Package SSOT-6 Packing Method Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Typical Application Figure 1. Typical Application Block Diagram GND 1 OVP 25V OLP OCP OVP OTP Auto Recovery Protection Latch-off Protection Soft Driver S R OSC Green Mode Controller Vlimit ramp (Include Soft-Start) VDD 6 Q GATE Latch-Off release 4V Internal BIAS VDD 5 UVLO FB Blanking Circuit Slope Compensation 3R R 0.5V 5.2V 4 SENSE 17.5V/9.5V OCP OCP Delay SENSE 2 FB OTP1 Debounce IRT 1V OTP2 Debounce 0.7V OTP OLP OLP Delay 4.6V RT 3 Figure 2. Block Diagram © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 2 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Marking Information AAR: FAN6861 TT: Wafer lot code • • •: Year code _ _ _: Week code Figure 3. Top Mark Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # 1 2 Name Description GND FB Ground. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin is higher than 4.6V for longer than 780ms, the overload protection is triggered and PWM output is disabled. This pin is for programmable over-temperature protection. An external NTC thermistor is connected between this pin and GND pin. Once the voltage of this pin drops below a threshold of 0.7V, PWM output is disabled. This pin is for current sense. This pin senses the voltage across a resistor. The voltage of this pin is compared with the feedback information determining the PWM duty cycle. This pin is the positive supply voltage input. The totem-pole output driver to drive the gate of power MOSFET. Soft driving waveform is implemented to reduce EMI. 3 4 5 6 RT SENSE VDD GATE © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 3 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to GND pin. Symbol VDD VL PD ΘJC TJ TSTG TL ESD Supply Voltage Parameter Input Voltage to FB, SENSE, VIN, RT,RI Pin Power Dissipation at TA 51% Duty = 0% Duty = DCYMAX 0.85 0.65 0.47 0.30 7.5 700 360 0.89 0.70 0.50 0.33 10.0 780 0.93 0.75 0.53 0.36 12.5 860 25 4 8 3 26 5 15 4 2.2 26 240 55 1/3.5 18 5.4 4.9 860 30 250 Feedback Input Section Current Sense Section Continued on following page… © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 5 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Electrical Characteristics (Continued) VDD = 15V and TA = 25°C, unless otherwise noted. Symbol Oscillator Section Parameter Center Frequency Jitter Range Test Condition Min. Typ. Max. Unit VFB > VFB-N VFB ≥ VFB-N VFB = VFB-G VFB ≥ VFB-N VFB = VFB-G 60 ±3.7 ±1.27 3.9 10.2 18.0 2.60 2.0 65 ±4.2 ±1.45 4.4 11.5 22.5 2.85 2.2 65 70 ±4.7 ±1.63 4.9 12.8 25.0 3.10 2.4 ms ms kHz V V Hz/mV 2.1 2.00 2 V % % kHz fOSC Normal PWM Frequency thop-1 thop-3 fOSC-G VFB-N VFB-G SG VFB-ZDC fDV fDT Jitter Period 1 Jitter Period 3 Green-Mode Minimum Frequency Beginning of Green-On Mode at FB Level Beginning of Green-Off Mode at FB Level Pin, FB Voltage Pin, FB Voltage Slope for Green-Mode Modulation FB Threshold Voltage for Zero-duty Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation Maximum Duty Cycle Output Voltage LOW Output Voltage HIGH Rising Time Falling Time Gate Output Clamping Voltage Output Current of RT Pin RT Pin Open Voltage Threshold Voltage for Over-Temperature Protection Over-Temperature Latch-Off Debounce Second Threshold Voltage for OverTemperature Protection Second Over-Temperature Latch-Off Debounce VFB = VFB-N VFB = VFB-G 0.92 15 40 0.65 50 VDD = 15V, IO = 50mA VDD = 12V, IO = 50mA GATE = 1nF GATE = 1nF VDD = 20V 15.00 90 8 VDD = 11.5V to 20V TA = -30 to 85°C 1.7 0 1.9 0.02 PWM Output Section DCYMAX VOL VOH tR tF VCLAMP IRT VRTO VOTP1 tDOTP-LATCH VOTP2 tDOTP2-LATCH 65 70 75 1.5 % V V 230 30 16.75 99 3.7 1.00 17 51 0.70 100 1.08 19 62 0.75 150 V μs 18.50 108 ns ns V μA V V ms Over-Temperature Protection (OTP) Section © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 6 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Electrical Characteristics (Continued) VDD = 15V and TA = 25°C, unless otherwise noted. Symbol PWM Output Section DCYMAX VOL VOH tR tF VCLAMP IRT VRTO VOTP1 tDOTP-LATCH VOTP2 tDOTP2-LATCH Parameter Maximum Duty Cycle Output Voltage LOW Output Voltage HIGH Rising Time Falling Time Gate Output Clamping Voltage Output Current of RT Pin RT Pin Open Voltage Threshold Voltage for Over-Temperature Protection Over-Temperature Latch-Off Debounce Second Threshold Voltage for OverTemperature Protection Second Over-Temperature Latch-Off Debounce Test Condition Min. 65 Typ. 70 Max. 75 1.5 Unit % V V ns ns VDD = 15V, IO = 50mA VDD = 12V, IO = 50mA GATE = 1nF GATE = 1nF VDD = 20V 15.00 90 8 230 30 16.75 99 3.7 0.92 VFB = VFB-N VFB = VFB-G 15 40 0.65 50 1.00 17 51 0.70 100 18.50 108 V μA V Over-Temperature Protection (OTP) Section 1.08 19 62 0.75 150 V ms V μs © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 7 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Typical Performance Characteristics VDD-ON vs Temperature (℃ ) 18 17.8 17.6 9.6 17.4 17.2 17 16.8 16.6 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ 9 10 VDD-OFF vs Temperature (℃ ) 9.8 VDD-OFF (V) VDD-ON (V) 9.4 9.2 8.8 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature (℃ ) Temperature (℃ ) Figure 5. Turn-On Threshold Voltage (VDD-ON) vs. Temperature Figure 6. Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature IDD-OP vs Temperature (℃ ) 3.2 3.15 3.1 FOSC vs Temperature (℃ ) 66 65.5 65 64.5 IDD-OP (mA) 3 2.95 2.9 2.85 2.8 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ FOSC (kHz) 3.05 64 63.5 63 62.5 62 61.5 61 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature (℃ ) Temperature (℃ ) Figure 7. Operating Current (IDD-OP) vs. Temperature Figure 8. Normal PWM Frequency (fOSC) vs. Temperature VOCP vs Temperature (℃ ) 0.535 0.525 0.515 70 D CYMAX vs Temperature (℃ ) 69.9 0.495 0.485 0.475 0.465 0.455 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ DCYMAX (%) 0.505 69.8 VOCP (V) 69.7 69.6 69.5 69.4 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature (℃ ) Temperature (℃ ) Figure 9. OCP Trigger Level (VOCP) vs. Temperature Figure 10. Maximum Duty Cycle (DCYMAX) vs. Temperature www.fairchildsemi.com 8 © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Typical Performance Characteristics VFB-N vs Temperature (℃ ) 2.92 VFB-G vs Temperature (℃ ) 2.3 2.91 2.25 2.9 2.2 VFB-N (V) VFB-G (V) 2.89 2.15 2.88 2.1 2.87 2.05 2.86 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ 2 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature (℃ ) Temperature (℃ ) Figure 11. FB Threshold Voltage For Frequency Reduction (VFB-N) vs. Temperature Figure 12. FB Voltage at fOSC-G (VFB-N) vs. Temperature VZDC vs Temperature (℃ ) 2 1.1 VOTP1 vs Temperature (℃ ) 1.95 1.05 1.9 1.85 VOTP1 (V) VZDC (V) 1 0.95 1.8 0.9 1.75 1.7 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ 0.85 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature (℃ ) Temperature (℃ ) Figure 13. FB Threshold Voltage for Zero Duty (VFB-ZDC) vs. Temperature Figure 14. Threshold Voltage for Over-Temperature Protection (VOTP1) vs. Temperature VOTP2 vs Temperature (℃ ) 0.72 104 102 0.715 100 98 IRT vs Temperature (℃ ) 0.71 VOTP2 (V) IRT (µA) 96 94 92 90 88 86 0.705 0.7 0.695 0.69 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ 84 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature (℃ ) Temperature (℃ ) Figure 15. Second Threshold Voltage for OverTemperature Protection (VOPT2) vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 Figure 16. Output Current of RT Pin (IRT) vs. Temperature www.fairchildsemi.com 9 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Operation Description Startup Operation Figure 17 shows the typical startup circuit and transformer auxiliary winding for FAN6861 application. Before FAN6861 begins switching operation, it consumes only startup current (typically 8μA) and the current supplied through the startup resistor charges the VDD capacitor (CDD). When VDD reaches turn-on voltage of 17.5V (VDD-ON), FAN6861 begins switching and the current consumed increases to 3mA. Then, the power required is supplied from the transformer auxiliary winding. The large hysteresis of VDD (8V) provides more holdup time, which allows using small capacitor for VDD. The startup resistor is typically connected to AC line for a fast reset of latch protection. Figure 18. PWM Frequency Figure 17. Startup Circuit Figure 19. Burst Mode Operation Green-Mode Operation The FAN6861 uses feedback voltage (VFB) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 18, such that the switching frequency decreases as load decreases. In heavy load conditions, the switching frequency is 65KHz. Once VFB decreases below VFB-N (2.85V), the PWM frequency starts to linearly decrease from 65KHz to 22kHz to reduce the switching losses. As VFB decreases below VFB-G (2.2V), the switching frequency is fixed at 22.5kHz and FAN6861 enters into deep green mode, where the operating current reduces to 2.2mA (maximum), further reducing the standby power consumption. As VFB decreases below VFB-ZDC (1.9V), FAN6861 enters into burst-mode operation. When VFB drops below VFB-ZDC, FAN6861 stops switching and the output voltage starts to drop, which causes the feedback voltage to rise. Once VFB rises above VFB-ZDC, switching resumes. Burst mode alternately enables and disables switching, thereby reducing switching loss in standby mode, as shown in Figure 19. Frequency Hopping EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. An internal frequency hopping circuit changes the switching frequency between 60.8kHz and 69.2kHz with a period of 4.4ms, as shown in Figure 20. Figure 20. Frequency Hopping © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 10 FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Protections Self-protective functions include VDD Over-Voltage Protection (OVP), Open-Loop/Overload Protection (OLP), Over-Current Protection (OCP), OverTemperature Protection (OTP). Among them, OLP, OCP, and SCP are auto-restart mode protections; while OVP and OTP are latch-mode protections. Auto-Restart Mode Protection: Once a fault condition is detected, switching is terminated and the MOSFET remains off. This causes VDD to fall because no more power is delivered from auxiliary winding. When VDD falls to VDD-OFF (9.5V), the protection is reset and the operating current reduces to startup current, which causes VDD to rise. FAN6861 resumes normal operation when VDD reaches VDD-ON (17.5V). In this manner, the auto-restart can alternately enable and disable the switching of the MOSFET until the fault condition is eliminated (see Figure 21). Latch-Mode Protection: Once this protection is triggered, switching is terminated and the MOSFET remains off. The latch is reset only when VDD is discharged below 4V by unplugging AC power line. Vds Power On Protection Triggers Fault Removed acceleration mode. Therefore, the protection circuit should be triggered after a specified time to determine whether it is a transient situation or an abnormal situation. Figure 22. Two-Level OCP Operation Open-Loop / Over-Load Protection (OLP) VDD 17.5V W hen the upper branch of the voltage divider for the shunt regulator (KA431 shown) is broken, as shown in Figure 23, there is no current flowing through the optocoupler transistor, which pulls up the feedback voltage to 5.2V. When the feedback voltage is above 4.6V longer than 780ms, OLP is triggered. This protection is also triggered when the SMPS output drops below the nominal value longer than 780ms due to the overload condition. 9.5V Operating Current 3mA 8uA Normal Operation Fault Situation Normal Operation Figure 21. Auto Restart Operation Two-Level Over-Current Protection (OCP) FAN6861 has two levels of over-current protection thresholds. One is for pulse-by-pulse current limit, which turns off MOSFET for the remainder of the switching cycle when the sensing voltage of MOSFET drain current reaches the threshold. The other threshold is for the over-current protection, which shuts down the MOSFET gate when the sensing voltage of MOSFET drain current is above the threshold longer than the shutdown delay time (780ms). This two-level OCP protection is designed for applications with peak load characteristics, such as printers and scanners. These applications have motor load and inherently impose over-load condition on the power supply during © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 11 VFB 5.2V VFB-OLP (4.6V) OLP Shutdown Delay Time OLP Triggers Figure 23. OLP Operation www.fairchildsemi.com FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents IC damage caused by over voltage on the VDD pin. The OVP is triggered when VDD voltage reaches 25V. It has a debounce time (typically 250µs) to prevent false trigger by switching noise. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs across the sense-resistor caused by primary-side capacitance and secondary-side rectifier reverse recovery. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period (360ns), the PWM comparator is disabled and cannot switch off the gate driver. Thus, RC filter with a small RC time constant is enough for current sensing. Over-Temperature Protection (OTP) The OTP circuit is composed of current source and voltage comparators. Typically NTC thermistor is connected between the RT pin and the GND pin. Once the voltage of this pin drops below a threshold of 0.7V, PWM output is disabled. Another comparator with 1V threshold is used to introduce hysteresis of OTP. Constant Output Power Limit FAN6861 has saw-limiter for pulse-by-pulse current limit, which guarantees almost constant power limit over different line voltages of universal input range. The conventional pulse-by-pulse current limiting scheme has a constant threshold for current limit comparator, which results in higher power limit for high line voltage. FAN6861 has a sawtooth current limit threshold that increases progressively within a switching cycle, which provides lower current limit for high line and makes the actual power limit level almost constant over different line voltages of universal input range, as shown in Figure 24. Figure 25. Current Sense R-C Filter Soft-Start The FAN6861 has an internal soft-start circuit that increases pulse-by-pulse current-limit comparator inverting input voltage slowly after it starts. The typical soft-start time is 10ms. The pulsewidth to the power MOSFET is progressively increased to establish the correct working conditions for transformers, rectifier diodes, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. Figure 24. Sawtooth Current Limiter © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 12 FAN6861 — Highly Integrated Green-Mode PWM Controller Typical Application Circuit (Flyback Converter for Printer Application) Application SMPS for Printer Fairchild Devices FAN6861 Input Voltage Range 90~264VAC Output 32V/0.6254A Nominal (20W) 32V/1.56A Peak (50W) Figure 26. Schematic of Application Circuit Transformer Core: EF-25/13/11 Primary-Side Inductance: 500µH Figure 27. Transformer Structure © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management Physical Dimensions Figure 28. 6-Pin SSOT-6 Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 www.fairchildsemi.com 14 www.fairchildsemi.com FAN6861 — Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management © 2009 Fairchild Semiconductor Corporation FAN6861 • Rev. 1.0.1 15