FDS6690

January 2000 FDS6690 Single N-Channel Logic Level PWM Optimized PowerTrench® MOSFET General Description This N Channel Logic Level MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. The MOSFET features faster switching and lower gate charge than other MOSFETs with comparable RDS(ON) specifications. The result is a MOSFET that is easy and safer to drive (even at very high frequencies), and DC/DC power supply designs with higher overall efficiency. Features 10 A, 30 V. RDS(ON) = 0.0135 Ω @ VGS = 10 V RDS(ON) = 0.0200 Ω @ VGS = 4.5 V. Optimized for use in switching DC/DC converters with PWM controllers. Very fast switching . Low gate charge (Qg typ = 13 nC). SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 D D D D S FD 9 0 66 S G 5 6 7 8 4 3 2 1 SO-8 pin 1 S S Absolute Maximum Ratings Symbol VDSS VGSS ID PD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed TA = 25oC unless other wise noted FDS6690 30 ±20 (Note 1a) Units V V A 10 50 Power Dissipation for Single Operation (Note 1a) (Note 1b) (Note 1c) 2.5 1.2 1 -55 to 150 W TJ,TSTG RθJA RθJC Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 50 25 °C/W °C/W © 1998 Fairchild Semiconductor Corporation FDS6690 Rev.C Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA ID = 250 µA, Referenced to 25 C VDS = 24 V, VGS = 0 V TJ = 55°C IGSSF IGSSR VGS(th) Gate - Body Leakage, Forward Gate - Body Leakage, Reverse (Note 2) o 30 21 1 10 100 -100 V mV /oC µA µA nA nA ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient IDSS Zero Gate Voltage Drain Current VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 µA ID = 250 µA, Referenced to 25 C VGS = 10 V, I D = 10 A TJ =125°C VGS = 4.5 V, I D = 9 A o ON CHARACTERISTICS Gate Threshold Voltage Gate Threshold Voltage Temp. Coefficient Static Drain-Source On-Resistance 1 2 -4.5 0.011 0.018 0.017 3 V mV /oC ∆VGS(th)/∆TJ RDS(ON) 0.0135 0.023 0.02 Ω ID(ON) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd IS VSD Notes: On-State Drain Current Forward Transconductance VGS = 10 V, VDS = 5 V VDS = 10 V, I D= 10 A VDS = 15 V, VGS = 0 V, f = 1.0 MHz 50 27 A S DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) 1340 340 125 pF pF pF SWITCHING CHARACTERISTICS Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS= 15 V, I D= 1 A VGS = 10 V , RGEN = 6Ω 12 13 38 10 22 24 60 18 18 ns ns ns ns nC nC nC VDS = 15 V, I D = 10 A, VGS = 5 V 13 5 4 DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.1 A (Note 2) 2.1 0.73 1.2 A V 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 50OC/W on a 0.5 in2 pad of 2oz copper. b. 105OC/W on a 0.02 in2 pad of 2oz copper. c. 125OC/W on a 0.003 in2 pad of 2oz copper. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDS6690 Rev.C Typical Electrical Characteristics 50 ID , DRAIN-SOURCE CURRENT (A) DRAIN-SOURCE ON-RESISTANCE R DS(on) , NORMALIZED VGS = 10V 6.0V 5.0V 4.5V 40 4.0V 3 VGS = 3.5V 2.5 30 2 4.0V 4.5V 20 1.5 5.0V 5.5V 7.0V 10V 3.5V 10 1 0 0 0.5 1 1.5 2 2.5 3 0.5 0 10 20 30 40 50 VDS , DRAIN-SOURCE VOLTAGE (V) I D , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.05 1.8 DRAIN-SOURCE ON-RESISTANCE VGS = 10 V R DS(ON) , ON-RESISTANCE (OHM) 1.6 1.4 1.2 1 0.8 I D = 10 A 0.04 I D = 5A R DS(ON) , NORMALIZED 0.03 0.02 TA = 125°C 0.01 TA = 25°C 0.6 -50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10 TJ , JUNCTION TEMPERATURE (°C) V GS , GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation Temperature. with Figure 4 . On Resistance Variation with Gate-to-Source Voltage. 50 IS , REVERSE DRAIN CURRENT (A) VDS = 5V I D, DRAIN CURRENT (A) 40 T = -55°C A 25°C 125°C 50 10 1 0.1 0.01 0.001 0.0001 0 0.2 V SD V GS = 0V 30 TA= 125°C 25°C -55°C 20 10 0 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) 0.4 0.6 0.8 1 1.2 1.4 , BODY DIODE FORWARD VOLTAGE (V) Figure 5 . Transfer Characteristics. Figure 6 . Body Diode Forward Voltage Variation with Source Current and Temperature. FDS6690 Rev.C Typical Electrical And Thermal Characteristics 10 V GS , GATE-SOURCE VOLTAGE (V) 2000 I D = 10A 8 V DS = 5V 10V CAPACITANCE (pF) C iss 1000 15V 6 500 4 C oss 200 2 f = 1 MHz V GS = 0V 0.5 V DS C rss 1 2 5 10 30 , DRAIN TO SOURCE VOLTAGE (V) 0 0 5 10 15 20 25 100 0.1 Q g , GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 100 30 ID , DRAIN CURRENT (A) 10 3 MIT ) LI (ON DS R 30 100 us 1m s 10m s 100 ms 1s 10s DC POWER (W) 25 20 15 10 5 0 0.01 SINGLE PULSE R θJA =125° C/W TA = 25°C 0.5 0.1 VGS = 10V SINGLE PULSE RθJA =125°C/W TA = 25°C 0.1 0.2 V DS 0.01 0.05 0.5 1 2 5 10 20 30 50 0.1 0.5 1 10 50 100 300 , DRAIN-SOURCE VOLTAGE (V) SINGLE PULSE TIME (SEC) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001 0.001 0.01 0.1 t1 , TIME (sec) 1 D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk) R θJA (t) = r(t) * R θJA R θJA = 125°C/W t1 t2 TJ - TA = P * R θJA(t) Duty Cycle, D = t1 /t2 10 100 300 Figure 11. Transient Thermal Response Curve . Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. FDS6690 Rev.C SO-8 Tape and Reel Data and Package Dimensions SOIC(8lds) Packaging Configuration: Figure 1.0 Packaging Description: EL ECT ROST AT IC SEN SIT IVE DEVICES DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms Antistatic Cover Tape ESD Label SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm diameter reel. This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. Static Dissipative Embossed Carrier Tape F63TNR Label Customized Label F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no flow code) TNR 2,500 13" Dia 343x64x343 5,000 0.0774 0.6060 L86Z Rail/Tube 95 530x130x83 30,000 0.0774 F011 TNR 4,000 13" Dia 343x64x343 8,000 0.0774 0.9696 D84Z TNR 500 7" Dia 184x187x47 1,000 0.0774 0.1182 F852 NDS 9959 Pin 1 SOIC-8 Unit Orientation 343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample LOT: CBVK741B019 FSID: FDS9953A QTY: 2500 SPEC: F63TNLabel F63TN Label ESD Label (F63TNR)3 D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: N/F: F SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0 Carrier Tape Cover Tape Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0 T E1 P0 D0 F K0 Wc B0 E2 W Tc A0 P1 D1 User Direction of Feed Dimensions are in millimeter Pkg type SOIC(8lds) (12mm) A0 6.50 +/-0.10 B0 5.30 +/-0.10 W 12.0 +/-0.3 D0 1.55 +/-0.05 D1 1.60 +/-0.10 E1 1.75 +/-0.10 E2 10.25 min F 5.50 +/-0.05 P1 8.0 +/-0.1 P0 4.0 +/-0.1 K0 2.1 +/-0.10 T 0.450 +/0.150 Wc 9.2 +/-0.3 Tc 0.06 +/-0.02 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). 20 deg maximum Typical component cavity center line 0.5mm maximum B0 20 deg maximum component rotation 0.5mm maximum Sketch A (Side or Front Sectional View) Component Rotation A0 Sketch B (Top View) Typical component center line Sketch C (Top View) Component lateral movement SOIC(8lds) Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max Dim A max Dim N See detail AA 7" Diameter Option B Min Dim C See detail AA W3 Dim D min 13" Diameter Option W2 max Measured at Hub DETAIL AA Dimensions are in inches and millimeters Tape Size 12mm Reel Option 7" Dia Dim A 7.00 177.8 13.00 330 Dim B 0.059 1.5 0.059 1.5 Dim C 512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2 Dim D 0.795 20.2 0.795 20.2 Dim N 2.165 55 7.00 178 Dim W1 0.488 +0.078/-0.000 12.4 +2/0 0.488 +0.078/-0.000 12.4 +2/0 Dim W2 0.724 18.4 0.724 18.4 Dim W3 (LSL-USL) 0.469 – 0.606 11.9 – 15.4 0.469 – 0.606 11.9 – 15.4 12mm 13" Dia © 1998 Fairchild Semiconductor Corporation July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC-8 (FS PKG Code S1) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.0774 9 September 1998, Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ DISCLAIMER ISOPLANAR™ MICROWIRE™ POP™ PowerTrench  QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. D