FDS6812

FDS6812A November 2001 FDS6812A Dual N-Channel Logic Level PWM Optimized PowerTrench® MOSFET General Description These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. Features • 6.7 A, 20 V. RDS(ON) = 22 mΩ @ VGS = 4.5 V RDS(ON) = 35 mΩ @ VGS = 2.5 V • Low gate charge (12 nC typical) • High performance trench technology for extremely low RDS(ON) • High power and current handling capability D2 D D2 D DD1 D1 D 5 6 7 Q1 4 3 2 Q2 SO-8 Pin 1 SO-8 G2 S2 S G1 S1 G S 8 1 S Absolute Maximum Ratings Symbol VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed TA=25 C unless otherwise noted o Parameter Ratings 20 ± 12 (Note 1a) Units V V A W 6.7 35 2 Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note 1a) (Note 1b) (Note 1c) 1.6 1 0.9 –55 to +150 °C TJ, TSTG Operating and Storage Junction Temperature Range Thermal Characteristics RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 78 40 °C/W °C/W Package Marking and Ordering Information Device Marking FDS6812A Device FDS6812A Reel Size 13’’ Tape width 12mm Quantity 2500 units ©2001 Fairchild Semiconductor Corporation FDS6812A Rev B (W) FDS6812A Electrical Characteristics Symbol BVDSS ∆BVDSS ∆TJ IDSS IGSSF IGSSR TA = 25°C unless otherwise noted Parameter Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage, Forward Gate–Body Leakage, Reverse (Note 2) Test Conditions VGS = 0 V, ID = 250 µ A ID = 250 µ A, Referenced to 25°C VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 55°C VGS = 12 V, VDS = 0 V VGS = –12 V, VDS = 0 V VDS = VGS, ID = 250 µ A ID = 250 µ A, Referenced to 25°C VGS = 4.5 V, ID = 6.7 A VGS = 2.5 V, ID = 5.3 A VGS = 4.5 V,ID = 7.5 A,TJ = 125°C VGS = 4.5V, VDS = 5 V VDS = 5 V, ID = 6.7 A Min 20 Typ Max Units V mV/°C 1 10 100 –100 µA nA nA Off Characteristics 14 On Characteristics VGS(th) ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance On–State Drain Current Forward Transconductance 0.6 0.8 –3.2 17 22 23 1.5 V mV/°C mΩ 22 35 29 ID(on) gFS 15 37 A S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) VDS = 10 V, f = 1.0 MHz V GS = 0 V, 1082 277 130 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge VDD = 10 V, VGS = 4.5 V, ID = 1 A, RGEN = 6 Ω 8 8 24 8 16 16 38 16 19 ns ns ns ns nC nC nC VDS = 10 V, VGS = 4.5 V ID =6.7 A, 12 2 3 Drain–Source Diode Characteristics and Maximum Ratings IS VSD Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) 1.3 0.7 1.2 A V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 78°C/W when 2 mounted on a 0.5in pad of 2 oz copper b) 125°C/W when mounted on a 0.02 2 in pad of 2 oz copper c) 135°C/W when mounted on a minimum mounting pad. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDS6812A Rev B (W) FDS6812A Typical Characteristics 30 25 ID, DRAIN CURRENT (A) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VDS, DRAIN-SOURCE VOLTAGE (V) 3.5V 3.0V 2.5V 2.0V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 4.5V 2.5 2 VGS = 2.0V 1.5 2.5V 3.0V 3.5V 4.0V 1 4.5V 0.5 0 5 10 15 20 25 30 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.07 RDS(ON), ON-RESISTANCE (OHM) 1.8 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.6 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 o ID = 6.7A VGS = 4.5V ID = 3.4 A 0.06 0.05 0.04 0.03 0.02 0.01 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) TA = 125oC TA = 25oC 125 150 175 TJ , JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. 30 TA = -55 C 25 ID, DRAIN CURRENT (A) 125 C 20 15 10 5 0 0.5 1 1.5 2 2.5 3 VGS, GATE TO SOURCE VOLTAGE (V) o Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 25oC IS, REVERSE DRAIN CURRENT (A) VDS = 5V o VGS = 0V 10 TA = 125oC 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) 25oC -55 C o Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS6812A Rev B (W) FDS6812A Typical Characteristics 5 VGS, GATE-SOURCE VOLTAGE (V) ID = 6.7A 4 15V 3 VDS = 5V 10V CAPACITANCE (pF) 1800 1500 CISS 1200 900 600 COSS 300 CRSS 0 0 2 4 6 8 10 12 14 0 4 8 12 16 20 Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V) f = 1MHz VGS = 0 V 2 1 0 Figure 7. Gate Charge Characteristics. 100 P(pk), PEAK TRANSIENT POWER (W) 50 Figure 8. Capacitance Characteristics. 100 µ ID, DRAIN CURRENT (A) 10 RDS(ON) LIMIT 1ms 10ms 100ms 1s 10s DC VGS = 4.5V SINGLE PULSE RθJA = 135oC/W TA = 25 C 0.01 0.01 0.1 1 10 100 o 40 SINGLE PULSE RθJA = 135°C/W TA = 25°C 30 1 20 0.1 10 0 0.01 0.1 1 10 100 1000 VDS, DRAIN-SOURCE VOLTAGE (V) t 1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 RθJA(t) = r(t) * RθJA RθJA = 135 C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 o 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 t1, TIME (sec) 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. FDS6812A Rev B (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT ™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ DISCLAIMER FAST ® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench ® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER ® SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET ® VCX™ STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4