FIN24CGFX

FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer October 2006 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Features ■ Low power for minimum impact on battery life tm General Description The FIN24C µSerDes™ is a low-power Serializer/ Deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. Typical reduction is 4:1 to 6:1 for unidirectional paths. For bi-directional operation, using half duplex for multiple sources, it is possible to increase the signal reduction to close to 10:1. Through the use of differential signaling, shielding and EMI filters can also be minimized, further reducing the cost of serialization. The differential signaling is also important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. Major reduction in power consumption allows minimal impact on battery life in ultra-portable applications. A unique word boundary technique assures that the actual word boundary is identified when the data is deserialized. This guarantees that each word is correctly aligned at the deserializer on a word-by-word basis through a unique sequence of clock and data that is not repeated except at the word boundary. A single PLL is adequate for most applications, including bi-directional operation. ■ ■ ■ ■ ■ ■ ■ ■ ■ – Multiple power-down modes – AC coupling with DC balance 100nA in standby mode, 5mA typical operating conditions Cable reduction: 25:4 or greater Bi-directional operation 50:7 reduction or greater Up to 24 bits in either direction Up to 20MHz parallel interface operation Voltage translation from 1.65V to 3.6V Ultra-small and cost-effective packaging High ESD protection: >7.5kV HBM Parallel I/O power supply (VDDP) range between 1.65V to 3.6V Applications ■ Micro-controller or pixel interfaces ■ Image sensors ■ Small displays – LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive Ordering Information Order Number FIN24CGFX FIN24CMLX Package Number BGA042 MLP040 Pb-Free Yes Yes Package Description 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only. µSerDesTM is a trademark of Fairchild Semiconductor Corporation. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Functional Block Diagram CKREF STROBE Register PLL cksint 0 I Word Boundary Generator + – CKS0+ CKS0- DP[m+1:24] Serializer Control Serializer + – DSO+/DSIDSO-/DSI+ oe DP[1:m] Register Note: m = 20 or 22 + Register Deserializer Deserializer cksint Control – + – 100Ω Gated Termination CKSI+ CKSI100Ω Termination I/O Control CKP WORD CK Generator Control Logic S1 S2 DIRI Power Down Control Freq. Control Direction Control oe DIRO Figure 1. Block Diagram ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 2 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Terminal Description Terminal Name DP[1:20] DP[21:24] CKREF STROBE CKP DSO+ / DSI– DSO– / DSI+ I/O Type I/O I or O IN IN OUT DIFF-I/O Number of Terminals 20 4 1 1 1 2 Description of Signals LVCMOS Parallel I/O, direction controlled by DIRI Terminal LVCMOS Parallel Unidirectional Inputs or Outputs Dependent on State of S1, S2 Terminals LVCMOS Clock Input and PLL Reference LVCMOS Strobe Signal for Latching Data into the Serializer LVCMOS Word Clock Output CTL Differential Serial I/O Data Signals(1) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I)+: Positive signal of DSO(I) pair DSO(I)–: Negative signal of DSO(I) pair CTL Differential Deserializer Input Bit Clock CKSI: Refers to signal pair CKSI+: Positive signal of CKSI pair CKSI–: Negative signal of CKSI pair CTL Differential Serializer Output Bit Clock CKSO: Refers to signal pair CKSO+: Positive signal of CKSO pair CKSO–: Negative signal of CKSO pair LVCMOS Mode Selection Pins used to define mode of operation for some terminals. The control terminals, DP[21:24] can be set as 4 terminals in the same direction or two in each direction. LVCMOS Control Input Used to control direction of Data Flow LVCMOS Control Output Inversion of DIRI Power Supply for Parallel I/O and Translation Circuitry Power supply for core circuitry and serial I/O Power Supply for Analog PLL Circuitry Use Bottom Ground Plane for Ground Signals CKSI+, CKSI– DIFF-IN 2 CKSO+, CKSO– DIFF-OUT 2 S1 S2 DIRI DIRO VDDP VDDS VDDA GND IN IN IN OUT Supply Supply Supply Supply 1 1 1 1 1 1 1 0 Note: 1. The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 3 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Connection Diagrams 32 STROBE 19 DP[9] DP[10] DP[11] DP[12] VDDP CKP DP[13] DP[14] DP[15] DP[16] 31 CKREF 30 DIRO 29 CKSO+ 28 CDSO27 DSO+ / DSI26 DSO- / DSI+ 25 CKSI24 CKSI+ 23 DIRI 22 S2 21 VDDS 20 40 DP[8] 39 DP[7] 38 DP[6] 37 DP[5] 36 DP[4] 35 DP[3] 16 34 DP[2] 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 Figure 2. Terminal Assignments for MLP (Top View) 1 A B C D E F J 2 3 4 5 6 DP[17] DP[18] DP[19] DP[20] DP[21] DP[22] DP[23] DP[24] S1 VDDA 1 A B C D E F J DP[9] DP[11] CKP DP[13] DP[15] DP[17] DP[19] 2 DP[7] DP[10] DP[12] DP[14] DP[16] DP[18] DP[20] 33 DP[1] Pin Assignments 3 DP[5] DP[6] DP[8] VDDP GND DP[21] DP[22] 4 DP[3] DP[2] DP[4] GND VDDS VDDA DP[23] 5 DP[1] STROBE CKSO+ CKSI+ S2 DP[24] 6 CKREF DIRO CKSOCKSIDIRI S1 DSO- / DSI+ DSO+ / DSI- (Top View) Figure 3. Terminal Assignments for µBGA ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 4 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Control Logic Circuitry The FIN24C has four signals that are selectable as two unidirectional inputs and two unidirectional outputs, or as four unidirectional inputs or four unidirectional outputs. These are often used by applications for control signals. The mode signals S1 and S2 determine the direction of the DP[21:24] data signals. The 00 state provides for a power-down state where all functionality of the device is disabled or reset. The DIRI terminal controls the direction of the device in Modes 1 and 3. When in Mode 2, the direction is controlled by both the DIRI and STROBE signals. Table 1 provides a complete description of the various modes of operation. For unidirectional operation, the DIRI terminal should be hardwired to a valid logic level and the DIRO terminal should be left floating. For bidirectional operation, the DIRO of the master device should be connected to the DIRI of the slave device. When operating in a bi-directional mode, the turn-around functionality is dependent on the mode of the device. For Modes 1 and 3, the device asynchronously passes and inverts the DIRI signal through the device to the DIRO signal. Care must be taken during design to ensure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be in a HIGHimpedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. This value only changes if the device is once again turned around into a deserializer and the values are overwritten. When the device is in Mode 2 (S2 = 1, S1 = 0), the direction of operation is dependent upon both the STROBE signal and the DIRI signal. At power-up, the mode select signals are both LOW and the DIRO signal is the inversion of the DIRI signal. After power-up, the DIRI and STROBE signal should initially both be HIGH. When STROBE goes LOW the device is configured as a serializer and DIRO will be forced LOW. The device remains a serializer until the DIRI signal goes LOW. When DIRI goes LOW, the device is re-configured as a deserializer and the DIRO signal is asserted HIGH. When operating the SerDes in pairs, not all operating modes are compatible. Regardless of the mode of operation, the serializer is always sending 24 bits of data and two word boundary bits. The deserializer is always receiving 24 bits of data and two word boundary bits. For some modes of operation, not all of the data bits are valid because some pins are dedicated inputs or outputs. A value of “0” is sent in the serial stream for all invalid data bits. Table 1. Control Logic Circuitry Mode Number 0 Inputs S2 0 Output DIRI 0 1 0 1 0 1 0 1 S1 0 STROBE x x DIRO 1 0 1 0 1 0 1 DIRO (n-1) Device State na na Des Ser Des Ser Des Previous Description Power-Down State. The device is powered down and disabled regardless of all other signals. 4-Bit Unidirectional Control Mode DP[21:24] are outputs 4-Bit Unidirectional Control Mode DP[21:24] are inputs STROBE and DIRI operate as an RS-Latch to change the state of operation. In general, DIRI and Strobe should not be LOW at the same time. 1 2 0 1 1 0 x x 0 0 1 1 3 1 1 x 0 1 Des 2-Bit Unidirectional Control Mode DP[21:22] are Inputs DP[23:24] Outputs 2-Bit Unidirectional Control Mode DP[21:22] are Inputs DP[23:24] Outputs 1 1 x 1 0 Ser ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 5 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer 4-Bit Control Mode When operating in 4-bit control mode, the master device must be configured as MODE 2 (S2 = 1, S1 = 0) and the slave device must be configured as MODE 1 (S2 = 0, S1 = 1). When operating in this mode, 24 data and control bits can be sent from the master to the slave and 20 data bits can be sent from the slave to the master. Unidirectional control signals should be connected to DP[21:24]. Power-Down Mode: (Mode 0) Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state, the PLL and references are disabled, differential input buffers are shut off, differential output buffers are placed into a HIGH-impedance state, LVCMOS outputs are placed into a HIGH-impedance state, LVCMOS inputs are driven to a valid level internally, and all internal circuitry is reset. The loss of CKREF state is also enabled to ensure that the PLL only powers up if there is a valid CKREF signal. In a typical application, the device only changes between the power-down mode and the selected mode of operation. This allows for system-level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a “logic 0” should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a “logic 1” should be connected to a system level power-down signal. 2-Bit Control Mode When operating in 2-bit control mode, both devices must be configured in MODE 3 (S2 = S1 = “1”). In this mode, 22 bits can be sent in either direction. When operating in a 2-bit control mode, serialized bits 21 and 22 appear on outputs 23 and 24 of the deserializer. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 6 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Serializer Operation Mode The serializer configuration is described in the following sections. The basic serialization circuitry works essentially the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the STROBE signal or not. When CKREF equals STROBE, the CKREF and STROBE signals are hardwired together as one signal. When CKREF does not equal STROBE, each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. Serializer Operation: (Figure 4) DIRI = 1, CKREF = STROBE The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal, provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked, the device can begin to capture and serialize data. Data is captured on the rising edge of the STROBE signal and then serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. Serialized data is sent at 26 times the CKREF clock rate. Two additional data bits are sent that define the word boundary. When in this mode, the internal deserializer circuitry is disabled; including the serial clock, serial data input buffers, the bidirectional parallel outputs, and the CKP word clock. The CKP word clock is driven HIGH. DPI[1:24] CKREF DSO CKS0 WORD n-2 WORD n-1 WORD n b24 b25 b26 b1 b2 b3 b4 b22 b23 b24 b25 b26 b1 b2 b3 b4 b5 WORD n-1 WORD n WORD n+1 Figure 4. Serializer Timing Diagram (CKREF equals STROBE) Serializer Operation: (Figure 5), DIRI = 1, CKREF does not = STROBE If the same signal is not used for CKREF and STROBE, the CKREF signal must be run at a higher frequency than the STROBE rate to serialize the data correctly. The actual serial transfer rate remains at 26 times the CKREF frequency. A data bit value of zero is sent when no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same. The exact frequency that the reference clock needs is dependent upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal implements spread spectrum technology, the maximum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-tocycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. CKREF DP[1:24] STROBE DSO CKS0 No Data WORD n-1 No Data WORD n b1 b2 b 3 b 4 b 5 b 6 b7 b22 b23 b24 b25 b26 b 1 b 2 b3 WORD n-1 WORD n WORD n+1 Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 7 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Serializer Operation Mode (Continued) Serializer Operation: (Figure 6), DIRI = 1, No CKREF A third method of serialization can be accomplished with a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up, the device is configured to accept a serialization clock from CKSI. If a CKREF is received, the device enables the CKREF serialization mode. The device remains in this mode even if CKREF is stopped. To re-enable this mode, the device must be powered down and powered back up with “logic 0” on CKREF. CKSI DP[1:24] STROBE DSO CKS0 No Data WORD n-1 No Data WORD n b 1 b 2 b3 b 4 b 5 b 6 b 7 b22 b23 b24 b25 b26 b1 b2 b3 WORD n-1 WORD n WORD n+1 Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 8 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Deserializer Operation Mode The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 = 1), all deserializer output data pins are driven LOW until valid data is passed through the deserializer. Deserializer Operation: DIRI = 0 (Serializer Source: CKREF = STROBE) When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through use of the bit clock sent with the data. The word boundary is defined in the actual clock and data signal. Parallel data is generated at the time the word boundary is detected. The falling edge of CKP occurs approximately six bit times after the next falling edge of CKSI. The rising edge of CKP goes HIGH approximately 13 bit times after CKP goes LOW. When no embedded word boundary occurs, no pulse is generated on CKP and CKP remains HIGH. WORD n b1 b6 b7 b8 b9 b19 b20 b24 b25 b26 WORD n+1 b1 b2 WORD n-1 DSI b24 b25 b26 CKSI CKPO DP[1:24] WORD n-2 WORD n-1 WORD n Figure 7. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE) Deserializer Operation: DIRI = 0 (Serializer Source: CKREF does not = STROBE) The logical operation of the deserializer remains the same if the CKREF is equal in frequency to the STROBE or at a higher frequency than the STROBE. The actual serial data stream presented to the deserializer, however, differs because it has non-valid data bits sent between words. The duty cycle of CKP varies based on the ratio of the frequency of the CKREF signal to the STROBE signal. The frequency of the CKP signal is equal to the STROBE frequency. The falling edge of CKP occurs six bit times after the data transition. The LOW time of the CKP signal is equal to half (13 bit times) of the CKREF period. The CKP HIGH time is equal to STROBE period – half of the CKREF period. Figure 8 is representative of a waveform that could be seen when CKREF is not equal to STROBE. If CKREF is significantly faster, additional non-valid data bits occur between data words. WORD n WORD n+1 bj+13 bj+14 b24 b25 b26 0 0 WORD n-1 DSI b24 b25 b26 CKSI CKPO DP[1:24] WORD n-2 0 0 bj bj+1 13 bit times 6 bit times WORD n-1 WORD n Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 9 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Embedded Word Clock Operation The FIN24C sends and receives serial data source synchronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has been implemented by skipping a LOW clock pulse. This appears in the serial clock stream as three consecutive bit times where signal CKSO remains HIGH. To implement this sort of scheme, two extra data bits are required. During the word boundary phase, the data toggles either HIGH-then-LOW or LOW-then-HIGH dependent upon the last bit of the actual data word. Table 2 provides some examples of the actual data word and the data word with the word boundary bits added. Note that a 24-bit word is extended to 26 bits during serial transmission. Bit 25 and Bit 26 are defined with-respect-to Bit 24. Bit 25 is always the inverse of Bit 24 and Bit 26 is always the same as Bit 24. This ensures that a “0” → “1” and a “1” → “0” transition always occurs during the embedded word phase where CKSO is HIGH. The serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. The deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. The deserializer only uses the embedded word boundary information to find and capture the data. These boundary bits are stripped prior to the word being sent out the parallel port. bidirectional pins should be connected to GND through a high-value resistor. If a FIN24C devices is configured as an unidirectional serializer, unused data I/O can be treated as unused inputs. If the FIN24C is hardwired as a deserializer, unused date I/O can be treated as unused outputs. From Deserializer DP[n] To Serializer From Control Figure 9. LVCMOS I/O Differential I/O Circuitry The FIN24C employs FSC proprietary CTL I/O technology. CTL is a low-power, low-EMI differential swing I/O technology. The CTL output driver generates a constant output source and sink current. The CTL input receiver senses the current difference and direction from the output buffer to which it is connected. This differs from LVDS, which uses a constant current source output, but a voltage sense receiver. Like LVDS, an input source termination resistor is required to properly terminate the transmission line. The FIN24C device incorporates an internal termination resistor on the CKSI receiver and a gated internal termination resistor on the DS input receiver. The gated termination resistor ensures proper termination regardless of direction of data flow. The relatively greater sensitivity of the current sense receiver of CTL allows it to work at much lower current drive and a much lower voltage. During power-down mode, the differential inputs are disabled and powered down and the differential outputs are placed in a HIGH-Z state. CTL inputs have an inherent fail-safe capability that supports floating inputs. When the CKSI input pair of the serializer is unused, it can reliably be left floating. Alternately both of the inputs can be connected to ground. CTL inputs should never be connected to VDD. When the CKSO output of the deserializer is unused, it should be allowed to float. LVCMOS Data I/O The LVCMOS input buffers have a nominal threshold value equal to half VDDP. The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer, the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source/sink current of 2mAs at 1.8V. The outputs are active when the DIRI signal is asserted LOW. When the DIRI signal is asserted HIGH, the bi-directional LVCMOS I/Os are in a HIGH-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. Unused LVCMOS input buffers must be tied off to either a valid logic LOW or a valid logic HIGH level to prevent static current draw due to a floating input. Unused LVCMOS outputs should be left floating. Unused Table 2. Word Boundary Data Bits 24-Bit Data Words Hex FFFFFFh 555555h xxxxxxh xxxxxxh 24-Bit Data Word with Word Boundary Hex 2FFFFFFh 1555555h 1xxxxxxh 2xxxxxxh Binary 1111 1111 1111 1111 1111 1111b 0101 0101 0101 0101 01010 0101b 0xxx xxxx xxxx xxxx xxxx xxxxb 1xxx xxxx xxxx xxxx xxxx xxxxb Binary 10 1111 1111 1111 1111 1111 1111b 01 0101 0101 0101 0101 0101 0101b 01 0xxx xxxx xxxx xxxx xxxx xxxxb 10 1xxx xxxx xxxx xxxx xxxx xxxxb www.fairchildsemi.com ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 10 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer From Serializer From Control To Deserializer + – DS+ DS- + – Gated Termination (DS Pins Only) Figure 10. Bi-Directional Differential I/O Circuitry Mode 0 state (S1 = S2 = 0) or upon detecting a LOW on both the S1 and S2 signals. Any of the other modes are entered by asserting either S1 or S2 HIGH and by providing a CKREF signal. The PLL powers up and goes through a lock sequence. Wait the specified number of clock cycles prior to capturing valid data into the parallel port. When the µSerDes chipset transitions from a power-down state (S1, S2 = 0, 0) to a powered state (example S1, S2 = 1, 1), CKP on the deserializer transitions LOW for a short duration, then returns HIGH. Following this, the signal level of the deserializer at CKP corresponds to the serializer signal levels. An alternate way of powering down the PLL is by stopping the CKREF signal either HIGH or LOW. Internal circuitry detects the lack of transitions and shuts the PLL and serial I/O down. Internal references, however, are not disabled, allowing the PLL to power-up and re-lock in a lesser number of clock cycles than when exiting Mode 0. When a transition is seen on the CKREF signal, the PLL is reactivated. PLL Circuitry The CKREF input signal is used to provide a reference to the PLL. The PLL generates internal timing signals capable of transferring data at 26 times the incoming CKREF signal. The output of the PLL is a bit clock sent with the serial data stream. There are two ways to disable the PLL: by entering the Application Mode Diagrams MODE = 3: Unidirectional Data Transfer PLL BIT CK Gen. + – CKSO + – CKSI Work CK Gen Deserializer Control Register CKREF_M CKP_S Serializer Control STROBE_M DP[1:22]_M Register DS Serializer + – + – Deserializer DP[1:20, 23:24]_S Master Device Operating as a Serializer DIR = “1” S2 = S1 = “0” Slave Device Operating as a Deserializer DIR = “0” S2 = S1 = “0” Figure 11. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure 11 shows basic operation when a pair of SerDes is configured in an unidirectional operation mode. In Master Operation, the device: 1. Is configured as a serializer at power-up based on the value of the DIRI signal. 2. Accepts CKREF_M word clock and generate a bit clock with embedded word boundary. This bit clock is sent to the slave device through the CKSO port. 3. Receives parallel data on the rising edge of STROBE_M. 4. Generates and transmits serialized data on the DS signals source synchronous with CKSO. 5. Generates an embedded word clock for each strobe signal. In Slave Operation, the device: 1. Is configured as a deserializer at power-up based on the value of the DIRI signal. 2. Accepts an embedded word boundary bit clock on CKSI. 3. Deserializes the DS data stream using the CKSI input clock. 4. Writes parallel data onto the DP_S port and generates the CKP_S. CKP_S is only generated when a valid data word occurs. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 11 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer REFCK FIN24C CKREF STROBE Sending Unit DS DATA [0:23] FIN24C CKSI DS DP[1:24] DATA [0:23] CKSO CKP DP[1:24] Receiving Unit VDD DIRI S1 S2 DIRO DIRO DIRI S1 S2 PwrDwn Figure 12. 24-Bit Unidirectional Serializer and Deserializer REFCK FIN24C CKREF STROBE Control Unit CNTL[0:3] DATA [0:19] FIN24C CKSI DS CKP STROBE DP[21:24] DP[1:20] CKSI CKSO S2 CNTL[0:3] DATA [0:19] CKSO DS DP[21:24] DP[1:20] S2 S1 DIRI DIRO DIRI Slave Unit PwrDwn S1 DIRO Figure 13. Unidirectional Control, Bi-directional Data Interface Flex Circuit Design Guidelines The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB: ■ Keep all four differential wires the same length. ■ Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires. ■ Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. ■ Do not place test points on differential serial wires. ■ Use differential serial wires a minimum of 2cm away from the antenna. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 12 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the conditions for actual device operation. Symbol VDD Supply Voltage All Input/Output Voltage Parameter Min. -0.5 -0.5 -65 Max. +4.6 +4.6 +150 +150 +260 Unit V V °C °C °C kV kV LVDS Output Short-Circuit Duration TSTG TJ TL Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, 4 seconds) ESD Rating Human Body Model, 1.5k¾, 100pF All Pins CKSO, CKSI, DSO to GND Continuous >2 > 7.5 Recommended Operating Conditions Symbol VDDA, VDDS VDDP TA VDDA-PP Supply Voltage Supply Voltage Operating Temperature Supply Noise Voltage Parameter Min. 2.5 1.65 -30 Max. 2.9 3.6 +70 100 Unit V V °C mVp-p ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 13 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer DC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol LVCMOS I/O VIH VIL VOH Parameter Input High Voltage Input Low Voltage Output High Voltage Test Conditions Min. 0.65 x VDDP GND Typ.(2) Max. VDDP 0.35 x VDDP Unit V V V IOH = –2.0 mA VDDP = 3.3 ± 0.3 VDDP = 2.5 ± 0.2 VDDP = 1.8 ± 0.15 0.75 x VDDP VOL Output Low Voltage IOL = 2.0 mA VDDP = 3.3 ± 0.3 VDDP = 2.5 ± 0.2 VDDP = 1.8 ± 0.15 0.25 x VDDP V IIN IODH IODL IOZ IIZ VICM VGO RTRM Input Current Output High Source Current Output Low Sink Current Disabled Output Leakage Current Disabled Input Leakage Current Input Voltage Ground Off-set Relative to Driver(3) CKSI Internal Receiver Termination Resistor DSI Internal Receiver, Termination Resistor VIN = 0V to 3.6V VOS = 1.0V, Figure 14 VOS = 1.0V, Figure 14 CKSO, DSO = 0V to VDDS, S2 = S1 = 0V CKSI, DSI = 0V to VDDS, S2 = S1 = 0V See Figure 15 VID = 50mV, VIC = 925mV, DIRI = 0, | CKSI+ – CKSI- | = VID VID = 50mV, VIC = 925mV, DIRI = 0, | DSI+ – DSI- | = VID –5.0 1.75 0.95 ±0.1 ±0.1 VGO + 0.80 0 80.0 100 5.0 µA mA mA DIFFERENTIAL I/O ±5.0 ±5.0 µA µA V V Input Common Mode Range VDDS = 2.775 ± 5% 120 ¾ RTRM 80.0 100 120 ¾ Notes: 2. Typical Values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage is referenced to GROUND unless otherwise specified (except ΔVOD and VOD). 3. VGO is the difference in device ground levels between the CTL driver and the CTL receiver. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 14 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Power Supply Currents Symbol IDDA1 IDDA2 IDDS1 Parameter VDDA Serializer Static Supply Current VDDA Deserializer Static Supply Current VDDS Serializer Static Supply Current VDDS Deserializer Static Supply Current Test Conditions All DPI and Control Inputs at 0V or VDDP, NO CKREF, S2 = 0, S1 = 1, DIRI = 1 All DPI and Control Inputs at 0 or VDDP, NO CKREF, S2 = 0, S1 = 1, DIRI = 1 All DPI and Control Inputs at 0V or VDDP, NO CKREF, S2 = 0, S1 = 1, DIRI = 1 All DPI and Control Inputs at 0V or VDDP, NO CKREF, S2 = 0, S1 = 1, DIRI = 0 Min. Typ. 450 550 4.0 4.5 0.1 11.0 16.0 7.5 10.0 10.0 12.0 Max. Units µA µA mA IDD_PD VDD Power-Down Supply Current S1 = S2 = 0, All Inputs at GND or VDDP IDD_PD = IDDA + IDDS + IDDP CKREF = STROBE DIRI = H See Figure 16 CKREF = STROBE DIRI = L See Figure 16 10MHz 20MHz 10MHz 20MHz µA mA IDD_SER1 26:1 Dynamic Serializer Power Supply Current IDD_SER1 = IDDA + IDDS + IDDP IDD_DES1 1:26 Dynamic Deserializer Power Supply Current IDD_DES1 = IDDA + IDDS + IDDP IDD_SER2 26:1 Dynamic Serializer Power Supply Current IDD_SER2 = IDDA + IDDS + IDDP mA NO CKREF, STROBE Active 10 MHz CKSI = 15X Strobe 15 MHz DIRI = H, See Figure 16 mA ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 15 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer AC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol tTCP fREF tCPWH tCPWL tCLKT tSPWH fMAX tSTC tHTC fREF Parameter CKREF Clock Period (10 MHz–20 MHz) Test Conditions See Figure 20 Min. 50.0 1.1 x fST 0.2 0.2 Typ.(4) T Max. 100 20.0 Units ns MHz T T SERIALIZER INPUT OPERATING CONDITIONS CKREF Frequency Relative to CKREF does not equal STROBE Strobe Frequency CKREF Clock High Time CKREF Clock Low Time LVCMOS Input Transition Time STROBE Pulse Width HIGH/LOW Maximum Serial Data Rate DP(n) Setup to STROBE DP(n) Hold to STROBE CKREF Frequency Relative to CKREF Does Not Equal STROBE Strobe Frequency Transmitter Clock Input to Clock Output Delay See Figure 23, DIRI = 1, CKREF = STROBE See Figure 20 See Figure 20 CKREF x 26 DIRI = 1, See Figure 9 (f = 5MHz) 0.5 0.5 90.0 ns ns Mb/s ns ns (T x 4) / 26 260 2.5 2.0 1.1 x fSTROBE 33a + 1.5 –50.0 (T x 22) / 26 520 20.0 MHz SERIALIZER AC ELECTRICAL CHARACTERISTICS tTCCD tSPOS tTPLLS0 tTPLLD0 tTPLLD1 tS_DS tH_DS 35a + 6.5 250 200 30.0 20.0 1.4 –250 ns ps µs µs ns ns ps CKSO Position Relative to DS See Figure 27(5) Serializer PLL Stabilization Time PLL Disable Time Loss of Clock PLL Power-Down Time Serial Port Setup Time, DS-to-CKSI Serial Port Hold Time, DS-to-CKS Deserializer Clock Output (CKP OUT) Period CKP OUT Low Time CKP OUT High Time Data Valid to CKP LOW Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) See Figure 22 See Figure 27 See Figure 28(6) See Figure 25(7) See Figure 25(7) PLL AC ELECTRICAL CHARACTERISTICS DESERIALIZER INPUT OPERATION CONDITIONS DESERIALIZER AC ELECTRICAL CHARACTERISTICS tRCOP tRCOL tRCOH tPDV tROLH tROHL See Figure 21 See Figure 21 (Rising Edge Strobe) Serializer Source STROBE = CKREF Where a = (1 / f) / 26(8) See Figure 21 (Rising Edge Strobe) Where a = (1 / f) / 26(8) CL = 5pF See Figure 18 50.0 13a-3 13a-3 8a-6 2.5 2.5 T 500 13a+3 13a+3 8a+1 ns ns ns ns ns ns ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 16 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Notes: 4. Typical Values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise specified (except ΔVOD and VOD). 5. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO). Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid. 6. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies based on the operating mode of the device. 7. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the clock remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew is a combination of output skew from the serializer, load variations, and ISI and jitter effects. 8. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP occurs approximately eight bit times after a data transition or six bit times after the first falling edge of CSKO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path and propagation delay differences on the various data pins. If the CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of the CKP remains 13 bit times. Control Logic Timing Controls Symbol tPHL_DIR, tPLH_DIR Parameter Propagation Delay DIRI-to-DIRO Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW Min. Typ. Max. Units 17.0 25.0 25.0 25.0 2.0 25.0 65.0 ns ns ns ns µs ns ns tPLZ, tPHZ Propagation Delay DIRI-to-DP tPZL, tPZH Propagation Delay DIRI-to-DP tPLZ, tPHZ Deserializer Disable Time: DIRI = 0, S0 or S1 to DP S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30 tPZL, tPZH Deserializer Enable Time: S0 or S1 to DP tPLZ, tPHZ Serializer Disable Time: S0 or S1 to CKSO, DS tPZL, tPZH Serializer Enable Time: S0 or S1 to CKSO, DS DIRI = 0,(10) S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30 DIRI = 1, S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 28 DIRI = 1, S1(2) and S2(1) = LOW-to-HIGH, Figure 28 Note: 9. Deserializer enable time includes the amount of time required for internal voltage and current references to stabilize. This time is significantly less than the PLL lock time and does not impact overall system startup time. Capacitance Symbol CIN CIO CIO-DIFF Parameter Capacitance of Input Only Signals, CKREF, STROBE, S1, S2, DIRI Capacitance of Parallel Port Pins DP[1:12] Capacitance of Differential I/O Signals Test Conditions DIRI = 1, S1 = S2 = 0, VDDP = 2.5V DIRI = 1, S1 = S2 = 0, VDDP = 2.5V DIRI = 0, S1 = S2 = 0, VDDP = 2.775V Min. Typ. 2.0 2.0 2.0 Max. Units pF pF pF ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 17 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer AC Loading and Waveforms DS+ RL/2 Input RL/2 DSVOS VOD – – + – VGO DUT + DUT + 100Ω Termination Figure 14. Differential CTL Output DC Test Circuit Figure 15. CTL Input Common Mode Test Circuit T DP[1:12] CKREF CKS0CKS0+ DS+ DSb13 b14 b1 0 b2 1 b6 0 b7 1 b8 0 b11 0 b12 1 b1 1 b2 0 b6 1 b7 0 b8 1 b11 1 b12 0 b1 b2 666h 999h 666h Note: The “worst-case” test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference frequency, unless otherwise specified. Maximum power is measured at the maximum VDD values. Minimum values are measured at the minimum VDD values. Typical values are measured at VDD = 2.775V. Figure 16. “Worst Case” Serializer Test Pattern tTLH 80% VDIFF 20% 80% tTHL 20% tROLH 80% DPn 20% 80% tROHL 20% VDIFF = (DS+) – (DS-) DS+ + – DPn 5pF 1000Ω 5 pF DS- 100Ω Figure 17. CTL Output Load and Transition Times Figure 18. LVCMOS Output Load and Transition Times ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 18 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer AC Loading and Waveforms (Continued) Setup Time STROBE DP[1:12] Data 10% tHTC CKREF 50% Data VIH VIL tTCH tTCL tTCP 50% 10% tSTC tCLKT 90% 90% tCLKT Hold Time STROBE DP[1:12] Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1” Figure 19. Serial Setup and Hold Time Figure 20. LVCMOS Clock Parameters Data Valid CKP DP[1:12] Data tPDV tTPLS0 tRCOP VDD/VDDA 50% 25% tRCOL S1 or S2 CKREF CKS0 Note: CKREF signal is free running. CKP 50% 75% tRCOH Setup: EN_DES = “1”, CKSI, and DSI are valid signals. Figure 21. Deserializer Data Valid Window Time and Clock Output Parameters Figure 22. Serializer PLL Lock Time tTCCD STROBE CKS0CKS0+ Note: STROBE = CKREF VDD/2 VDIFF = 0 CKSICKSI+ CKP VDIFF = 0 tRCCD VDD/2 Figure 23. Serializer Clock Propagation Delay Figure 24. Deserializer Clock Propagation Delay ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 19 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer AC Loading and Waveforms (Continued) CKSOtS_DS CKSICKSI+ DSI+ DSIVDIFF=0 VID/2 VDIFF=0 tH_DS CKSO+ DSO+ DSO- VDIFF = 0 VDIFF = 0 VID / 2 tSK(P-P) Note: Data is typically edge aligned with the clock. Figure 25. Differential Input Setup and Hold Times Figure 26. Differential Output Signal Skew tTPPLD0 CKREF tTPPLD1 S1 or S2 CKS0 CKS0 Note: CKREF Signal can be stopped either HIGH or LOW. Figure 27. PLL Loss of Clock Disable Time Figure 28. PLL Power-Down Time tPLZ(HZ) S1 or S2 tPZL(ZH) tPLZ(HZ) S1 or S2 tPZL(ZH) DS+,CKS0+ DS-,CKS0HIGH-Z DP Note: CKREF must be active and PLL must be stable. Note: If S1(2) transitioning, S2(1) must = 0 for test to be valid. Figure 29. Serializer Enable and Disable Time Figure 30. Deserializer Enable and Disable Times ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 20 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Tape and Reel Specification Dimensions are in millimeters unless otherwise noted. BGA Embossed Tape Dimension T P0 D P2 E F K0 Wc B0 W Tc A0 P1 D1 User Direction of Feed Package 3.5 x 4.5 A0 D D1 E B0 ±0.1 ±0.1 ±0.05 Min. ±0.1 TBD TBD 1.55 1.5 1.75 F ±0.1 5.5 K0 P1 P0 P2 T TC W WC ±0.1 Typ. Typ. ±0/05 Typ. ±0.005 ±0.3 Typ. 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3 Note: 10. A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). 10° maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum 1.0mm maximum Sketch C (Top View) B0 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Component lateral movement Component Rotation Shipping Reel Dimension W2 max Measured at Hub W1 Measured at Hub B Min Dia C Dia D min Dia A max Dia N DETAIL AA See detail AA W3 Tape Width 8 12 16 Dia A Max. 330 330 330 Dim B Min. 1.5 1.5 1.5 Dia C +0.5/–0.2 13.0 13.0 13.0 Dia D Min. 20.2 20.2 20.2 Dim N Min. 178 178 178 Dim W1 +2.0/–0 8.4 12.4 16.4 Dim W2 Max. 14.4 18.4 22.4 Dim W3 (LSL–USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4 ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 21 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Tape and Reel Specification (Continued) Dimensions are in millimeters unless otherwise noted. MLP Embossed Tape Dimension T P0 D P2 E F K0 Wc B0 W Tc A0 P1 D1 User Direction of Feed Package 5x5 6x6 A0 D D1 E B0 ±0.1 ±0.1 ±0.05 Min. ±0.1 5.35 6.30 5.35 6.30 1.55 1.55 1.5 1.5 1.75 1.75 F ±0.1 5.5 5.5 K0 P1 P0 P2 T TC W WC ±0.1 Typ. Typ. ±0/05 Typ. ±0.005 ±0.3 Typ. 1.4 1.4 8 8 4 4 2.0 2.0 0.3 0.3 0.07 0.07 12 12 9.3 9.3 Note: 11. Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). 10° maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum B0 10° maximum component rotation Sketch A (Side or Front Sectional View) 1.0mm maximum Sketch C (Top View) Component Rotation Component lateral movement Component Rotation Shipping Reel Dimension W2 max Measured at Hub W1 Measured at Hub B Min Dia C Dia D min Dia A max Dia N DETAIL AA See detail AA W3 Tape Width 8 12 16 Dia A Max. 330 330 330 Dim B Min. 1.5 1.5 1.5 Dia C +0.5/–0.2 13 13 13 Dia D Min. 20.2 20.2 20.2 Dim N Min. 178 178 178 Dim W1 +2.0/–0 8.4 12.4 16.4 Dim W2 Max. 14.4 18.4 22.4 Dim W3 (LSL–USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4 www.fairchildsemi.com ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 22 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Physical Dimensions Dimensions are in millimeters unless otherwise noted. 2X 0.10 C 3.50 2X 0.10 C (0.35) (0.6) 2.5 (0.5) (0.75) TERMINAL A1 CORNER INDEX AREA 4.50 0.5 3.0 0.5 Ø0.3±0.05 BOTTOM VIEW X42 0.15 0.05 CAB C (QA CONTROL VALUE) 0.89±0.082 0.45±0.05 0.21±0.04 1.00 MAX 0.10 C C SEATING PLANE 0.08 C 0.23±0.05 0.2+0.1 -0.0 LAND PATTERN RECOMMENDATION Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 23 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. (DATUM A) Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 24 FIN24C µSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. FACT Quiet Series™ GlobalOptoisolator™ GTO™ HiSeC™ I2C™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ Across the board. Around the world.™ The Power Franchise® Programmable Active Droop™ ACEx™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ DOME™ EcoSPARK™ E2CMOS™ EnSigna™ FACT™ FAST® FASTr™ FPS™ FRFET™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerEdge™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ μSerDes™ ScalarPump™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ TinyBoost™ TinyBuck™ TinyPWM™ TinyPower™ TinyLogic® TINYOPTO™ TruTranslation™ UHC™ UniFET™ UltraFET® VCX™ Wire™ LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I20 Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 www.fairchildsemi.com 25