FM93C56AM8

FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus) General Description Features FM93C56A is a 2048-bit CMOS non-volatile EEPROM organized as 128 x 16-bit array. This device features MICROWIRE interface which is a 4-wire serial bus with chipselect (CS), clock (SK), data input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors. This device offers a pin (ORG), using which, the user can select the format of the data (16-bit or 8-bit). If ORG is tied to GND, then 8-bit format is selected, while if ORG is tied to VCC, then 16-bit format is selected. There are 7 instructions implemented on the FM93C56A for various Read, Write, Erase, and Write Enable/ Disable operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption. ■ Wide VCC 2.7V - 5.5V “LZ” and “L” versions of FM93C56A offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space considerations. ■ Endurance: 1,000,000 data changes ■ User selectable organization x16 (ORG = 1) x8 (ORG = 0) ■ Typical active current of 200µA 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) ■ No Erase instruction required before Write instruction ■ Self timed write cycle ■ Device status during programming cycles ■ 40 year data retention ■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP Functional Diagram VCC CS INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS SK DI INSTRUCTION REGISTER HIGH VOLTAGE GENERATOR AND PROGRAM TIMER ADDRESS REGISTER ORG DECODER EEPROM ARRAY 16 READ/WRITE AMPS VSS 16 DATA IN/OUT REGISTER 16/8 BITS DO © 2000 Fairchild Semiconductor International FM93C56A Rev. C.1 DATA OUT BUFFER 1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) July 2000 FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Connection Diagram Dual-In-Line Package (N) 8–Pin SO (M8) and 8–Pin TSSOP (MT8) CS 1 8 VCC SK 2 7 NC DI 3 6 ORG DO 4 5 GND Top View Package Number N08E, M08A and MTC08 Pin Names CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground ORG Organization NC No Connect VCC Power Supply NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation. Ordering Information FM 93 C XX A LZ E XXX Letter Package Description N M8 MT8 8-pin DIP 8-pin SO 8-pin TSSOP Temp. Range None V E 0 to 70°C -40 to +125°C -40 to +85°C Voltage Operating Range Blank L LZ 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and 1µA when in x8 mode due to the internal pull-up transistor. Note 4: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation. Note 5: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode diagram on the following page.) Note 6: This parameter is periodically sampled and not 100% tested. AC Test Conditions VCC Range VIL/VIH Input Levels VIL/VIH Timing Level VOL/VOH Timing Level IOL/IOH 2.7V ≤ VCC ≤ 5.5V 0.3V/1.8V 1.0V 0.8V/1.5V ±10µA 4.5V ≤ VCC ≤ 5.5V 0.4V/2.4V 1.0V/2.0V 0.4V/2.4V 2.1mA/-0.4mA (Extended Voltage Levels) (TTL Levels) Output Load: 1 TTL Gate (CL = 100 pF) 4 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Absolute Maximum Ratings (Note 1) Refer Table 1 and Table 2 for more details. This pin is internally pulled-up to VCC. Hence leaving this pin unconnected would default to 16-bit data format. Chip Select (CS) This is an active high input pin to FM93C56A EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. All activity on the SK, DI and DO pins are ignored while CS is held low. Microwire Interface Serial Clock (SK) Each of the above 7 instructions is explained under individual instruction descriptions. A typical communication on the Microwire bus is made through the CS, SK, DI and DO signals. To facilitate various operations on the Memory array, a set of 7 instructions are implemented on FM93C56A. The format of each instruction is listed under Table 1 (for 16-bit format) and Table 2 (for 8-bit format). Instruction This is an input pin to the device and is generated by the master that is controlling the device. This is a clock signal that synchronizes the communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input, while output data (DO) from the device is driven from the rising edge of this clock input. This pin is gated by CS signal. Start bit This is a 1-bit field and is the first bit that is clocked into the device when a Microwire cycle starts. This bit has to be “1” for a valid cycle to begin. Any number of preceding “0” can be clocked into the device before clocking a “1”. Serial Input (DI) Opcode This is an input pin to the device and is generated by the master that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via this pin into the device. This Input information is latched on the rising edge of the SCK. This pin is gated by CS signal. This is a 2-bit field and should immediately follow the start bit. These two bits (along with 2 MSB of address field) select a particular instruction to be executed. Address Field Serial Output (DO) Depending on the selected organization, this is a 8-bit or 9-bit field and should immediately follow the Opcode bits. In FM93C56A, only the LSB 7 bits (or 8 bits) are used for address decoding during READ, WRITE and ERASE instructions. During all other instructions, the MSB 2 bits are used to decode instruction (along with Opcode bits). This is an output pin from the device and is used to transfer Output data via this pin to the controlling master. Output data is serially shifted out on this pin from the rising edge of the SCK. This pin is active only when the device is selected. Organization (ORG) Data Field This is an input pin to the device and is used to select the format of data (16-bit or 8-bit). If this pin is tied high, 16-bit format is selected, while if it is tied low, 8-bit format is selected. Depending on the format selected, FM93C56A requires 7-bit address field (for 16-bit data format) or 8-bit address field (for 8-bit data format). Depending on the selected organization, this is a 16-bit or 8-bit field and should immediately follow the Address bits. Only the WRITE and WRALL instructions require this field. MSB bit (D15 or D7) is clocked first and LSB bit (D0) is clocked last (both during writes as well as reads). Table 1. Instruction set (16-bit organization) Instruction Start Bit Opcode Field Address Field Data Field READ 1 10 X A6 A5 A4 A3 A2 A1 A0 WEN 1 00 1 1 X X X X X X WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15-D0 WRALL 1 00 0 1 X X X X X X D15-D0 WDS 1 00 0 0 X X X X X X ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 ERAL 1 00 1 0 X X X X X X 5 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Pin Description Instruction Start Bit Opcode Field Address Field Data Field READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 WEN 1 00 1 1 X X X X X X X WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7-D0 WRALL 1 00 0 1 X X X X X X X D7-D0 WDS 1 00 0 0 X X X X X X X ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 ERAL 1 00 1 0 X X X X X X X Functional Description 3) Write (WRITE) A typical Microwire cycle starts by first selecting the device (bringing the CS signal high). Once the device is selected, a valid Start bit (“1”) should be issued to properly recognize the cycle. Following this, the 2-bit opcode of appropriate instruction should be issued. After the opcode bits, the 8-bit (or 9-bit) address information should be issued. For certain instructions, some of the bits of this field are don’t care values (can be “0” or “1”), but they should still be issued. Following the address information, depending on the instruction (WRITE and WRALL), 16-Bit data (or 8-Bit) is issued. Otherwise, depending on the instruction (READ), the device starts to drive the output data on the DO line. Other instructions perform certain control functions and do not deal with data bits. The Microwire cycle ends when the CS signal is brought low. However during certain instructions, falling edge of the CS signal initiates an internal cycle (Programming), and the device remains busy till the completion of the internal cycle. Each of the 7 instructions is explained in detail in the following sections. WRITE instruction allows write operation to a specified location in the memory with a specified data. This instruction is valid only when device is write-enabled (Refer WEN instruction). Input information (Start bit, Opcode, Address and Data) for this WRITE instruction should be issued as listed under Table 1 or Table 2. After inputting the last bit of data (D0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. The status of the internal programming cycle can be polled at any time by bringing the CS signal high again, after tCS interval. When CS signal is high, the DO pin indicates the READY/BUSY status of the chip. DO = logical 0 indicates that the programming is still in progress. DO = logical 1 indicates that the programming is finished and the device is ready for another instruction. It is not required to provide the SK clock during this status polling. While the device is busy, it is recommended that no new instruction be issued. Refer Write cycle diagram. 1) Read (READ) READ instruction allows data to be read from a selected location in the memory array. Input information (Start bit, Opcode and Address) for this instruction should be issued as listed under Table 1 or Table 2. Upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. This 16-bit data (or 8-bit data) is then shifted out on the DO pin. MSB of the data (D15 or D8) is shifted out first and LSB (DO) is shifted out last. A dummy-bit (logical 0) precedes this data output string. Output data changes are initiated on the rising edge of the SK clock. After reading the 16-bit (or 8-bit) data, the CS signal can be brought low to end the Read cycle. Refer Read cycle diagram. It is also recommended to follow this instruction (after the device becomes READY) with a Write Disable (WDS) instruction to safeguard data against corruption due to spurious noise, inadvertent writes etc. 4) Write All (WRALL) Write all (WRALL) instruction is similar to the Write instruction except that WRALL instruction will simultaneously program all memory locations with the data pattern specified in the instruction. This instruction is valid only when device is write-enabled (Refer WEN instruction). 2) Write Enable (WEN) Input information (Start bit, Opcode, Address and Data) for this WRALL instruction should be issued as listed under Table 1 or Table 2. After inputting the last bit of data (D0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Write All cycle diagram. When VCC is applied to the part, it “powers up” in the Write Disable (WDS) state. Therefore, all programming operations must be preceded by a Write Enable (WEN) instruction. Once a Write Enable instruction is executed, programming remains enabled until a Write Disable (WDS) instruction is executed or VCC is completely removed from the part. Input information (Start bit, Opcode and Address) for this WEN instruction should be issued as listed under Table 1 or Table 2. The device becomes writeenabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WEN instruction. Refer Write Enable cycle diagram. 6 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Table 2. Instruction set (8-bit organization) Write Disable (WDS) instruction disables all programming operations and should follow all programming operations. Executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table 2. The device becomes write-disabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WDS instruction. Refer Write Disable cycle diagram. Note: The Fairchild CMOS EEPROMs do not require an “ERASE” or “ERASE ALL” instruction prior to the “WRITE” or “WRITE ALL” instruction, respectively. The “ERASE” and “ERASE ALL” instructions are included to maintain compatibility with earlier technology EEPROMs. 6) Erase (ERASE) Clearing of Ready/Busy status The ERASE instruction will program all bits in the specified location to logical “1” state. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table 2. After inputting the last bit of data (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Erase cycle diagram. When programming is in progress, the Data-Out pin will display the programming status as either BUSY (low) or READY (high) when CS is brought high (DO output will be tri-stated when CS is low). To restate, during programming, the CS pin may be brought high and low any number of times to view the programming status without affecting the programming operation. Once programming is completed (Output in READY state), the output is ‘cleared’ (returned to normal tri-state condition) by clocking in a Start Bit. After the Start Bit is clocked in, the output will return to a tri-stated condition. When clocked in, this Start Bit can be the first bit in a command string, or CS can be brought low again to reset all internal circuits. Refer Clearing Ready Status diagram. 7) Erase All (ERAL) Related Document The Erase all instruction will program all locations to logical “1” state. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table Application Note: AN758 - Using Fairchild’s MICROWIRE™ EEPROM. 7 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) 2. After inputting the last bit of data (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Erase All cycle diagram. 5) Write Disable (WDS) FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Timing Diagrams SYNCHRONOUS DATA TIMING CS tCSS tSKH tSKL tCSH SK tDIS tDIH Valid Input DI Valid Input Valid Output DO (Data Read) tDF tPD tDH tPD Valid Output tDF tSV Valid Status DO (Status Read) READ CYCLE (READ) tCS CS SK DI 1 1 Star t Bit An 0 A n-1 Opcode Bits(2) A1 ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;; ;;; A0 Address Bits(8/9) High - Z DO Dn 0 D1 D0 D u m my Bit 9 3 C 5 6 A ( O R G = 1 ; A n =A7; D n =D15 ) : Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0 ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ; A 6 - t o - A 0 - > U s e r d e f i n e d ) 9 3 C 5 6 A ( O R G = 0 ; A n =A8; D n =D7 ) : Address bits pattern -> x-A7-A6-A5-A4-A3-A2-A1-A0; User defined ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ; A 7 - t o - A 0 - > U s e r d e f i n e d ) WRITE ENABLE CYCLE (WEN) tCS CS SK DI 1 Start Bit DO 0 0 Opcode Bits(2) An A n-1 A1 A0 Address Bits(8/9) High - Z 93C56A (ORG=1; A n =A7 ): Address bits pattern -> 1-1-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1) 93C56A (ORG=0; A n =A8 ): Address bits pattern -> 1-1-x-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1) 8 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Timing Diagrams (Continued) WRITE DISABLE CYCLE (WDS) tCS CS SK DI 1 0 Start Bit An 0 A n-1 Opcode Bits(2) A1 A0 Address Bits(8/9) High - Z DO 9 3 C 5 6 A ( O R G = 1 ; A n =A7 ) : Address bits pattern -> 0-0-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1) 9 3 C 5 6 A ( O R G = 0 ; A n =A8 ) : Address bits pattern -> 0-0-x-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1) WRITE CYCLE (WRITE) tCS CS SK DI 1 0 Star t Bit 1 An A n-1 Opcode Bits(2) A1 A0 Dn D n-1 Address Bits(8/9) D1 D0 tWP Data Bits(16/8) High - Z DO Ready Busy 93C56A (ORG=1; A n =A7; D n =D15 ): Address bits patter n -> x-A6-A5-A4-A3-A2-A1-A0 (x -> Don't Care, can be 0 or 1; A6-to-A0 -> User defined) Data bits patter n -> D15-to-D0; User defined 93C56A (ORG=0; A n =A8; D n =D7 ): Address bits patter n -> x-A7-A6-A5-A4-A3-A2-A1-A0 (x -> Don't Care, can be 0 or 1; A7-to-A0 -> User defined) Data bits patter n -> D7-to-D0; User defined WRITE ALL CYCLE (WRALL) tCS CS SK DI 1 Star t Bit 0 0 Opcode Bits(2) An A1 A n-1 A0 Dn Address Bits(8/9) D n-1 D1 Data Bits(16/8) D0 tWP High - Z DO Ready Busy 93C56A (ORG=1; A n =A7; D n =D15 ): Address bi t s pat t er n -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Dat a bi t s pat t er n -> D15-to-D0; User defined 93C56A (ORG=0; A n =A8; D n =D7 ): Address bi t s pat t er n -> 0-1-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1) Dat a bi t s pat t er n -> D7-to-D0; User defined 9 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Timing Diagrams (Continued) ERASE CYCLE (ERASE) tCS CS SK 1 DI Star t Bit 1 1 Opcode Bits(2) DO An A1 A n-1 A0 tWP Address Bits(8/9) High - Z Ready Busy 9 3 C 5 6 A ( O R G = 1 ; A n =A7): Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0 ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ; A 6 - t o - A 0 - > U s e r d e f i n e d ) 9 3 C 5 6 A ( O R G = 0 ; A n =A8 ) : Address bits pattern -> x-A7-A6-A5-A4-A3-A2-A1-A0; User defined ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ; A 7 - t o - A 0 - > U s e r d e f i n e d ) ERASE ALL CYCLE (ERAL) tCS CS SK 1 DI Start Bit DO 0 0 Opcode Bits(2) An A n-1 High - Z A1 A0 tWP Address Bits(8/9) Ready Busy 9 3 C 5 6 A ( O R G = 1 ; A n =A7 ) : A d d r e s s b i t s p a t t e r n - > 1 - 0 - x - x - x - x - x - x ; ( x - > D o n’ t C a r e , c a n b e 0 o r 1 ) 9 3 C 5 6 A ( O R G = 0 ; A n =A8 ) : A d d r e s s b i t s p a t t e r n - > 1 - 0 - x - x - x - x - x - x - x ; ( x - > D o n’ t C a r e , c a n b e 0 o r 1 ) CLEARING READY STATUS CS SK DI Star t Bit DO High - Z Ready High - Z Busy N o t e : T h i s S t a r t b i t c a n a l s o b e p a r t o f a n ex t i n s t r u c t i o n . H e n c e t h e c y c l e c a n b e c o n t i nu e d ( i n s t e a d o f g e t t i n g t e r m i n a t e d , a s s h ow n ) a s i f a n ew instruction is being issued. 10 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Physical Dimensions inches (millimeters) unless otherwise noted 0.189 - 0.197 (4.800 - 5.004) 8 7 6 5 0.228 - 0.244 (5.791 - 6.198) 1 2 3 4 Lead #1 IDENT 0.010 - 0.020 x 45¡ (0.254 - 0.508) 0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads 0.150 - 0.157 (3.810 - 3.988) 8¡ Max, Typ. All leads 0.004 (0.102) All lead tips 0.053 - 0.069 (1.346 - 1.753) 0.004 - 0.010 (0.102 - 0.254) Seating Plane 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508) Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8) Package Number M08A 11 FM93C56A Rev. C.1 www.fairchildsemi.com 0.114 - 0.122 (2.90 - 3.10) 8 5 (4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) 0.246 - 0.256 (6.25 - 6.5) (1.78) Typ (0.42) Typ 0.123 - 0.128 (3.13 - 3.30) (0.65) Typ 1 Land pattern recommendation 4 Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. 0.0035 - 0.0079 See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0118 (0.19 - 0.30) Gage plane 0¡-8¡ DETAIL A Typ. Scale: 40X 0.020 - 0.028 (0.50 - 0.70) Seating plane 0.0075 - 0.0098 (0.19 - 0.25) Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 8-Pin Molded TSSOP, JEDEC (MT8) Package Number MTC08 12 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Physical Dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 8 0.092 DIA (2.337) 7 6 0.250 - 0.005 + Pin #1 IDENT 8 0.032 ± 0.005 (6.35 ± 0.127) Pin #1 IDENT 1 Option 1 1 0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128) 7 (0.813 ± 0.127) RAD 5 2 3 0.040 Typ. (1.016) 0.030 MAX (0.762) 20° ± 1° 4 Option 2 0.145 - 0.200 0.039 (0.991) (3.683 - 5.080) 0.130 ± 0.005 (3.302 ± 0.127) 95° ± 5° 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM 0.125 - 0.140 (3.175 - 3.556) 0.065 (1.651) 90° ± 4° Typ 0.018 ± 0.003 (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) 0.045 ± 0.015 (1.143 ± 0.381) 0.020 (0.508) Min 0.060 (1.524) 0.050 (1.270) Molded Dual-In-Line Package (N) Package Number N08E Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 13 FM93C56A Rev. C.1 www.fairchildsemi.com FM93C56A 2K-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus) Physical Dimensions inches (millimeters) unless otherwise noted