FQG4904

FQG4904 QFET FQG4904 400V Dual N & P-Channel MOSFET General Description These dual N and P-channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on half bridge. TM Features • N-Channel 0.46A, 400V, RDS(on) = 3.0 Ω @ VGS = 10 V P-Channel -0.46A, -400V, RDS(on) = 3.0 Ω @ VGS = -10 V • Low gate charge ( typical N-Channel 7.6 nC) ( typical P-Channel 20.0 nC) • Fast switching • Improved dv/dt capability D2 D2 D1 D1 G2 S2 G1 S1 Pin #1 5 4 6 3 7 2 8-DIP 8 1 Absolute Maximum Ratings Symbol VDSS ID IDM VGSS dv/dt PD TJ, TSTG TA = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TA = 25°C) Drain Current - Continuous (TA = 100°C) Drain Curent - Pulsed (Note 1) N-Channel 400 0.46 0.29 3.68 ± 30 (Note 2) P-Channel -400 -0.46 -0.29 -3.68 -4.5 Units V A A A V V/ns W W/°C °C Gate-Source Voltage Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) - Derate above 25°C Operating and Storage Temperature Range 4.5 1.6 0.013 -55 to +150 Thermal Characteristics Symbol RθJA Parameter Thermal Resistance, Junction-to-Ambient (Note 5a) Typ -- Max 78 Units °C/W ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Electrical Characteristics Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Type Min Typ Max Units Off Characteristics BVDSS ∆BVDSS / ∆TJ Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA ID = 250 µA, Referenced to 25°C ID = -250 µA, Referenced to 25°C VDS = 400 V, VGS = 0 V VDS = 320 V, TA = 125°C VDS = -400 V, VGS = 0 V VDS = -320 V, TA = 125°C IGSSF IGSSR Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 30 V, VDS = 0 V VGS = -30 V, VDS = 0 V N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch All All 400 -400 ----------0.47 -0.3 ----------10 100 -10 -100 100 -100 V V V/°C V/°C µA µA µA µA nA nA IDSS Zero Gate Voltage Drain Current On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 µA VDS = VGS, ID = -250 µA VGS = 10 V, ID = 0.23 A VGS = -10 V, ID = -0.23 A VDS = 40 V, ID = 0.23 A VDS = -40 V, ID = -0.23 A N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 2.0 -2.0 ------2.0 2.2 0.8 1.1 4.0 -4.0 3.0 3.0 --V V Ω Ω S S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance N-Channel VDS = 25 V, VGS = 0 V, f = 1.0 MHz P-Channel VDS = -25 V, VGS = 0 V, f = 1.0 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch ------235 500 40 85 6.5 14 300 645 55 110 8.5 18.5 pF pF pF pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge N-Channel VDD = 200 V, ID = 0.46 A, RG = 25 Ω P-Channel VDD = -200 V, ID = -0.46 A, RG = 25 Ω (Note 3,4) N-Channel VDS = 320 V, ID = 0.46 A, VGS = 10 V P-Channel VDS = -320 V, ID = -0.46 A, (Note 3,4) VGS = -10 V N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch --------------- 6.5 10 16 21 28 85 34 56 7.6 20 1.2 2.7 3.3 9.9 25 30 40 52 65 180 80 120 10 26 ----- ns ns ns ns ns ns ns ns nC nC nC nC nC nC ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Electrical Characteristics (Continued) Symbol Parameter Test Conditions Type Min Typ Max Units Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 0.46 A VGS = 0 V, IS = -0.46 A VGS = 0 V, IS = 0.46 A, (Note 3) dIF / dt = 100 A/µs VGS = 0 V, IS = -0.46 A, (Note 3) dIF / dt = 100 A/µs N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch ----------------104 248 117 497 0.46 -0.46 3.68 -3.68 1.4 -5.0 ----A A A A V V ns nC ns nC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. ISD ≤ 0.46A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 3. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 4. Essentially independent of operating temperature 5. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RθCA is determined by the user’s board design Maximum RθJA using the different board layouts on 3”x4.5” FR-4 PCB in a still air environment : a. 78°C/W when mounted without any pad copper b. 60°C/W when mounted on a 4.5 in2 pad of 2oz copper. In such an environment, the power dissipation can be enhanced up to 2.1W ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Typical Characteristics : N-Channel 10 0 ID , Drain Current [A] ID, Drain Current [A] VGS 15.0 V 10.0 V 8.0 V 6.0 V 5.5 V 5.0 V 4.5 V Bottom : 4.0 V Top : 10 0 150℃ 25℃ -55℃ 10 -1 ※ Notes : 1. 250μ s Pulse Test 2. TA = 25℃ ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test 10 -1 10 0 10 1 10 -1 0 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 10 8 RDS(ON) [Ω ], Drain-Source On-Resistance VGS = 10V 6 IDR, Reverse Drain Current [A] 10 0 VGS = 20V 4 2 ※ Note : TJ = 25℃ 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test 0 0 2 4 6 8 10 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID, Drain Current [A] VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 500 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 VDS = 80V 10 400 VDS = 200V VDS = 320V Ciss VGS, Gate-Source Voltage [V] 8 Capacitance [pF] 300 Coss 200 6 Crss 100 ※ Note ; 1. VGS = 0 V 2. f = 1 MHz 4 2 ※ Note : ID = 0.46 A 0 -1 10 10 0 10 1 0 0 2 4 6 8 10 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Typical Characteristics : N-Channel (Continued) 1.2 2.5 2.0 BV DSS , (Norm alized) Drain-Source Breakdown Voltage RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 1.5 1.0 1.0 0.9 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.5 ※ Notes : 1. VGS = -10 V 2. ID = -0.23 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.5 Operation in This Area is Limited by R DS(on) 10 1 0.4 10 0 10 ms -1 10 100 ms 1s DC ※ Notes : 10 -2 1. TA = 25 C 2. TJ = 150 C 3. Single Pulse o o 10 -3 10 0 10 1 10 2 10 3 ID, Drain Current [A] ID, Drain Current [A] 100 µs 1 ms 0.3 0.2 0.1 0.0 25 50 75 100 125 150 VDS, Drain-Source Voltage [V] TA, Ambient Temperature [℃] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Ambient Temperature Z (t) , T h e r m a l R e s p o n s e 10 2 D = 0 .5 0 .2 10 1 0 .1 0 .0 5 0 .0 2 PDM t1 t2 s i n g le p u l s e ※ N o te s : 1 . Z θ J A ( t) = 7 8 ℃ / W M a x . 2 . D u t y F a c t o r , D = t 1 /t 2 3 . T J M - T A = P D M * Z θ J A ( t) θJ A 10 0 0 .0 1 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a r e W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Typical Characteristics : P-Channel -I D , Drain Current [A] 10 0 -ID, Drain Current [A] VGS -15.0 V -10.0 V -8.0 V -6.0 V -5.5 V -5.0 V -4.5 V Bottom : -4.0 V Top : 10 0 150℃ 25℃ -55℃ 10 -1 ※ Notes : 1. 250μ s Pulse Test 2. TA = 25℃ ※ Notes : 1. VDS = -40V 2. 250μ s Pulse Test 10 -1 10 0 10 1 10 -1 0 2 4 6 8 10 -VDS, Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 10 8 RDS(ON) [Ω ], Drain-Source On-Resistance VGS = -10V 6 -I DR, Reverse Drain Current [A] 10 0 VGS = -20V 4 2 ※ Note : TJ = 25℃ 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test 0 0 2 4 6 8 10 12 10 -1 0.0 0.5 1.0 1.5 2.0 -ID, Drain Current [A] -VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 1400 1200 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 VDS = -80V 10 VDS = -200V VDS = -320V 1000 Ciss Coss -VGS, Gate-Source Voltage [V] 8 Capacitance [pF] 800 6 600 Crss 400 ※ Note ; 1. VGS = 0 V 2. f = 1 MHz 4 200 2 ※ Note : ID = -0.46 A 0 -1 10 10 0 10 1 0 0 5 10 15 20 25 -VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Typical Characteristics : P-Channel (Continued) 1.2 2.5 2.5 2.0 2.0 -BV DSS , (Normalized) Drain-Source Breakdown Voltage RDS(ON) , (Normalized) DS(O N) On-Resistance Drain-Source On-Resistance 1.1 1.5 1.5 1.0 1.0 1.0 0.9 ※ Notes : 1. VGS = 0 V 2. ID = -250 μ A 0.5 0.5 ※ Notes :: ※ Notes 1. VGS = -10 V 1. VGS = -10 V 2. IDD= -0.23 A 2. I = -0.26 A 0.8 -100 -50 0 50 100 o 150 200 0.0 0.0 -100 -100 -50 0 50 100 100 o o 150 150 200 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [[ C] Temperature C] Figure 7. Breakdown Voltage Variation vs. Temperature 0.5 Operation in This Area is Limited by R DS(on) Figure 8. On-Resistance Variation vs. Temperature 10 1 0.4 10 0 10 ms -1 10 100 ms 1s DC ※ Notes : 10 -2 1. TA = 25 C o 2. TJ = 150 C 3. Single Pulse o 10 -3 10 0 10 1 10 2 10 3 -ID, Drain Current [A] -ID, Drain Current [A] 100 µs 1 ms 0.3 0.2 0.1 0.0 25 50 75 100 125 150 -VDS, Drain-Source Voltage [V] TA, Ambient Temperature [℃] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Ambient Temperature Z (t) , T h e r m a l R e s p o n s e 10 2 D = 0 .5 0 .2 10 1 0 .1 0 .0 5 0 .0 2 PDM t1 t2 s i n g le p u l s e ※ N o te s : 1 . Z θ J A ( t) = 7 8 ℃ / W M a x . 2 . D u t y F a c t o r , D = t 1 /t 2 3 . T J M - T A = P D M * Z θ J A ( t) θJ A 10 0 0 .0 1 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a r e W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Gate Charge Test Circuit & Waveform (N-Channel) 50KΩ 12V 200nF 300nF Same Type as DUT VDS VGS Qg 10V Qgs Qgd VGS DUT 3mA Charge Resistive Switching Test Circuit & Waveforms (N-Channel) VDS VGS RG RL VDD VDS 90% 10V DUT VGS 10% td(on) t on tr td(off) t off tf Gate Charge Test Circuit & Waveform (P-Channel) 50KΩ 12V 200nF 300nF Same Type as DUT VDS VGS Qg -10V Qgs Qgd VGS DUT -3mA Charge Resistive Switching Test Circuit & Waveforms (P-Channel) VDS VGS RG RL VDD td(on) t on tr td(off) t off tf VGS 10% -10V DUT VDS 90% ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Peak Diode Recovery dv/dt Test Circuit & Waveforms (N-Channel) DUT + VDS _ I SD L Driver RG Same Type as DUT VDD VGS • dv/dt controlled by RG • ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Peak Diode Recovery dv/dt Test Circuit & Waveforms (P-Channel) + VDS DUT _ I SD L Driver RG Compliment of DUT (N-Channel) VDD VGS • dv/dt controlled by RG • ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V I SD ( DUT ) Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop Body Diode Recovery dv/dt VDD ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 FQG4904 Package Dimensions 8-DIP 6.40 ±0.20 0.252 ±0.008 0.79 ) 0.031 #1 #8 9.20 ±0.20 0.362 ±0.008 9.60 MAX 0.378 #4 #5 2.54 0.100 5.08 MAX 0.200 7.62 0.300 3.40 ±0.20 0.134 ±0.008 3.30 ±0.30 0.130 ±0.012 0.33 MIN 0.013 0.25 –0.05 0~15° +0.10 0.010 –0.002 +0.004 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. A1, April 2002 0.018 ±0.004 1.524 ±0.10 0.060 ±0.004 0.46 ±0.10 ( TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production ©2002 Fairchild Semiconductor Corporation Rev. H5