FSCQ0765RT

www.fairchildsemi.com Green Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Switching Converter Features • Optimized for Quasi-Resonant Converter (QRC) • Advanced Burst-Mode operation for under 1 W standby power consumption • Pulse by Pulse Current Limit (11.5A) • Over load protection (OLP) - Auto restart • Over voltage protection (OVP) - Auto restart • Abnormal Over Current Protection (AOCP) - Latch • Internal Thermal Shutdown (TSD) - Latch • Under Voltage Lock Out (UVLO) with hysteresis • Low Startup Current (typical : 25uA) • Low Operating Current (typical : 7mA) • Internal High Voltage SenseFET • Built-in Soft Start (20ms) • Extended Quasi-resonant Switching for Wide Load Range OUTPUT POWER TABLE PRODUCT FSCQ0765RT FSCQ1265RT FSCQ1565RT FSCQ1565RP 230VAC ±15%(2) Open Frame(1) 100 W 170 W 210 W 250 W 85-265VAC Open Frame(1) 85 W 140 W 170 W 210 W FSCQ1565RP Table 1. Notes: 1. Maximum practical continuous power in an open frame design at 50°C ambient. 2. 230 VAC or 100/115 VAC with doubler. Application • CTV • DVD Receiver • Audio Power Supply Typical Circuit Vo Description In general, Quasi-Resonant Converter (QRC) shows lower EMI and higher power conversion efficiency compared to the conventional hard switched converter with a fixed switching frequency. Therefore, it is well suited for applications that are sensitive to the noise, such as color TV and audio. The FSCQ1565RP is an integrated Pulse Width Modulation (PWM) controller and Sense FET specifically designed for Quasi-resonant off-line Switch Mode Power Supplies (SMPS) with minimal external components. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of Quasi resonant switching flyback converters. AC IN Drain FSCQ1565RP PWM Sync VFB GND Vcc Figure 1. Typical Flyback Application Rev.1.0.0 ©2005 Fairchild Semiconductor Corporation FSCQ1565RP Internal Block Diagram Sync 5 + Vcc 3 Quasi-resonant (QR) switching controller Drain 1 Threshold - fs + - 9V/15V Soft start 4.6V/2.6V : Normal QR 3.0V/1.8V : Extended QR Vcc good Auxiliary Vref Normal operation VBurst Normal operation Vref IBFB Vcc Idelay Burst mode Controller Burst Switching Vref IFB Vref IB OSC Main bias Internal bias FB 4 PWM S Q 2.5R R R Q Gate driver LEB 600ns VSD Sync Vovp Vcc good S Q Q S AOCP 2 GND TSD Power off Reset Vocp R Q Q R Figure 2. Functional Block Diagram of FSCQ1565RP 2 FSCQ1565RP Pin Definitions Pin Number 1 2 3 Pin Name Drain GND Vcc Pin Function Description High voltage power SenseFET drain connection. This pin is the control ground and the SenseFET source. This pin is the positive supply input. This pin provides internal operating current for both start-up and steady-state operation. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 7.5V, the over load protection triggers resulting in shutdown of the FPS. This pin is internally connected to the sync detect comparator for quasi resonant switching. In normal quasi-resonant operation, the threshold of the sync comparator is 4.6V/2.6V. Meanwhile, the sync threshold is changed to 3.0V/1.8V in extended quasi-resonant operation. 4 Vfb 5 Sync Pin Configuration TO-3PF-7L 5.Sync 4.Vfb 3.Vcc 2.GND 1.Drain Figure 3. Pin Configuration (Top View) 3 FSCQ1565RP Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Drain-Source (GND) Voltage Gate-Source (GND) Voltage Drain Current Pulsed (2) (1) Symbol VDSS VDGR VGS IDM EAS ID ID VCC Vsync VFB PD TJ TA TSTG Rthjc - Value 650 650 ±30 45 1050 8.3 5.5 20 -0.3 to 13V -0.3 to VCC 98 +150 -25 to +85 -55 to +150 1.28 2.0 (Vfb=1.7kV) 300 (Vfb=170V) Unit V V V ADC mJ ADC ADC V V V W °C °C °C °C/W kV V Drain-Gate Voltage (RGS=1MΩ) Single Pulsed Avalanche Energy (3) Continuous Drain Current (Tc = 25°C) Continuous Drain Current (TC=100°C) Supply Voltage Analog Input Voltage Range Total Power Dissipation Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range Thermal Resistance ESD Capability, HBM Model (All pins excepts for Vfb) ESD Capability, Machine Model (All pins excepts for Vfb) Notes: 1. Tj = 25°C to 150°C 2. Repetitive rating: Pulse width limited by maximum junction temperature 3. L = 21mH, VDD = 50V, RG = 25Ω, starting Tj = 25°C 4 FSCQ1565RP Electrical Characteristics (SenseFET Part) (Ta=25°C unless otherwise specified) Parameter Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Symbol BVDSS IDSS Condition VGS = 0V, ID = 250µA VDS = Max, Rating, VGS = 0V VDS= 0.8*Max., Rating VGS = 0V, TC = 85°C VGS = 10V, ID = 2.3A VGS = 0V, VDS = 25V, f = 1MHz VDD= 0.5BVDSS, ID= 7.0A (MOSFET switching times are essentially independent of operating temperature) VGS = 10V, ID = 7.0A, VDS = 0.5BVDSS (MOSFET Switching times are essentially independent of operating temperature) Min. 650 Typ. Max. 0.53 220 40 50 130 430 135 127 16 52 200 300 0.7 286 52 75 179 569 186 165 21 68 nC ns Unit V µA µA Ω Static Drain-source on Resistance (Note) RDS(ON) Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn on Delay Time Rise Time Turn Off Delay Time Fall Time Total Gate Charge (Gate-Source+Gate-Drain) Gate-Source Charge Gate-Drain (Miller) Charge Note: 1. Pulse test : Pulse width ≤ 300µS, duty ≤ 2% Ciss Coss Crss td(on) tr td (off) tf Qg Qgs Qgd 3050 3965 pF 5 FSCQ1565RP Electrical Characteristics (Continued) (Ta=25°C unless otherwise specified) Parameter UVLO SECTION Vcc Start Threshold Voltage Vcc Stop Threshold Voltage SENSEFET SECTION Drain To PKG Breakdown Voltage (Note4) Drain To Source Breakdown Voltage Drain To Source Leakage Current OSCILLATOR SECTION Initial Frequency Voltage Stability Temperature Stability (Note2) Maximum Duty Cycle Minimum Duty Cycle FEEDBACK SECTION Feedback Source Current Shutdown Feedback Voltage Shutdown Delay Current PROTECTION SECTION Over Voltage Protection Over Current Latch Voltage (Note2) Thermal Shutdown Temp (Note4) VOVP VOCL TSD Vsync ≥ 11V 11 0.9 140 12 1.0 13 1.1 V V °C IFB VSD IDELAY VFB = 0.8V Vfb ≥ 6.9V VFB = 5V 0.5 7.0 4 0.65 7.5 5 0.8 8.0 6 mA V µA FOSC FSTABLE ∆FOSC DMAX DMIN 12V ≤ Vcc ≤ 23V -25°C ≤ Ta ≤ 85°C 18 0 0 92 20 1 ±5 95 22 3 ±10 98 0 kHz % % % % BVpkg BVdss Idss 60HZ AC, Ta = 25°C Ta = 25°C Vdrain = 400V, Ta = 25°C 3500 650 200 V V uA VSTART VSTOP VFB = GND VFB = GND 14 8 15 9 16 10 V V Symbol Condition Min. Typ. Max. Unit Note: 1. These parameters is the current flowing in the Control IC. 2. These parameters, although guaranteed, are tested only in EDS (wafer test) process. 3. These parameters indicate Inductor Current. 4. These parameters, although guaranteed at the design, are not tested in mass production. 6 FSCQ1565RP Electrical Characteristics (Continued) (Ta=25°C unless otherwise specified) Parameter Sync SECTION Sync Threshold in normal QR (H) Sync Threshold in normal QR (L) Sync Threshold in extended QR (H) Sync Threshold in extended QR (L) Extended QR enable frequency Extended QR disable frequency BURST MODE SECTION Burst Mode Enable Feedback Voltage Burst Mode Feedback Source Current Burst Mode switching Time Burst Mode Hold Time SOFTSTART SECTION Soft start Time (Note2) Peak Current Limit (Note3) Burst Mode Peak Current Limit (Note4) TOTAL DEVICE SECTION Startup Current Sustain Latch Current Operating Supply Current (Note1) - In normal operation - In burst mode (without switching) IOP IOB Vfb = 2V, VCC = 18V Vfb = GND, VCC = 18V 7 0.25 9 0.50 mA mA ISTART ISL VCC = VSTART-0.1V VCC = VSTOP-0.1V 25 50 50 100 uA uA TSS ILIM IBPK 18 20 22 ms A A CURRENT LIMIT(SELF-PROTECTION)SECTION 10.12 11.5 12.88 0.6 1.0 1.4 VBEN IBFB TBS TBH VFB = 0V VFB = 0V 0.25 60 1.2 1.2 0.40 100 1.4 1.4 0.55 140 1.6 1.6 V uA ms ms VSH1 VSL1 VSH2 VSL2 FSYH FSYL Vcc = 16V, Vfb = 5V Vcc = 16V, Vfb = 5V Vcc = 16V, Vfb = 5V Vcc = 16V, Vfb = 5V 4.2 2.3 2.7 1.6 4.6 2.6 3.0 1.8 90 45 5.0 2.9 3.3 2.0 V V V V kHz kHz Symbol Condition Min. Typ. Max. Unit Note: 1. These parameters is the current flowing in the Control IC. 2. These parameters, although guaranteed, are tested only in EDS (wafer test) process. 3. These parameters indicate Inductor Current. 4. These parameters, although guaranteed at the design, are not tested in mass production. 7 FSCQ1565RP Comparison Between KA5Q1565RF and FSCQ1565RP Function Startup Current Operating supply Current KA5Q1565RF Max. 200uA Typ. 10mA FSCQ1565RP Max. 50uA Typ. 7mA FSCQ1565RP Advantages Lower standby power consumption Operating current is reduced in burst operation to minimize standby power consumption - Normal operation : 7mA - Burst mode with switching : 7mA - Burst mode without switching : 0.25mA Switching in Burst mode Output regulation in standby mode Output Voltage drop in burst mode Primary side regulation Soft start Extended Quasiresonant switching Package Type Quasi-resonant switching Vcc control with hysteresis about half Available N/A N/A TO-3PF-5L Fixed frequency switching (20kHz) Output voltage feedback control Any level N/A Available Available TO-3PF-7L Internal soft-start (20ms) - Guarantees wide load range - Improved efficiency at high line input Easy to determine the output voltage in the standby mode Lower power consumption in the standby mode through larger output voltage drop 8 FSCQ1565RP Electrical characteristics Operating Supply Current 1.2 Burst-mode Supply Current( Non-Switching) 1.4 Normalized to 25℃ Normalized to 25℃ 0 50 100 150 1.2 1.0 1.0 0.8 0.8 -50 0.6 -50 0 50 100 150 Temp[℃ ] Temp[℃ ] Start-Up Current 1.4 Start Threshold Voltage 1.10 Normalized to 25℃ 1.2 Normalized to 25℃ 1.05 1.0 1.00 0.8 0.95 0.6 -50 0 50 Temp[℃ ] 100 150 0.90 -50 0 50 100 150 Temp[℃ ] Stop Threshold Voltage 1.10 Initial Frequency 1.10 Normalized to 25℃ Normalized to 25℃ 1.05 1.05 1.00 1.00 0.95 0.95 0.90 -50 0 50 100 150 0.90 -50 0 50 100 150 Temp[℃ ] Temp[℃] 9 FSCQ1565RP Electrical characteristics (Continued) Maximum Duty Cycle 1.10 1.10 Over Voltage Protection Normalized to 25℃ Normalized to 25℃ 1.05 1.05 1.00 1.00 0.95 0.95 0.90 -50 0 50 100 150 0.90 -50 0 50 100 150 Temp[℃ ] Temp[℃ ] Shutdown Delay Current 1.2 Shutdown Feedback Voltage 1.10 Normalized to 25℃ 1.1 Normalized to 25℃ 0 50 100 150 1.05 1.0 1.00 0.9 0.95 0.8 -50 0.90 -50 0 50 100 150 Temp[℃ ] Temp[℃ ] Feedback Source Current 1.2 Burst_mode Feedback Source Current 1.2 Normalized to 25℃ 0 50 Temp[℃ ] 100 150 Normalized to 25℃ 1.1 1.1 1.0 1.0 0.9 0.9 0.8 -50 0.8 -50 0 50 100 150 Temp[℃ ] 10 FSCQ1565RP Electrical characteristics (Continued) Feedback Offset Voltage 1.4 Burst_Mode Enable Feedback Voltage 1.4 Normalized to 25℃ 0 50 100 150 Normalized to 25℃ 1.2 1.2 1.0 1.0 0.8 0.8 0.6 -50 Temp[℃ ] 0.6 -50 0 50 100 150 Temp[℃] Sync. Threshold in Normal QR(H) 1.10 1.10 Sync. Threshold in Normal QR(L) Normalized to 25℃ 1.05 Normalized to 25℃ 0 50 100 150 1.05 1.00 1.00 0.95 0.95 0.90 -50 0.90 -50 0 50 100 150 Temp[℃] Temp[℃ ] Sync. Threshold in Extended QR(H) 1.10 1.10 Sync. Threshold in Extended QR(L) Normalized to 25℃ 1.05 Normalized to 25℃ 0 50 100 150 1.05 1.00 1.00 0.95 0.95 0.90 -50 0.90 -50 0 50 100 150 Temp[℃ ] Temp[℃ ] 11 FSCQ1565RP Electrical characteristics (Continued) Extended QR Enable Freqency Extended QR Disable Frequency 1.10 1.10 Normalized to 25℃ 1.00 0.95 0.90 -50 Normalized to 25℃ 0 1.05 1.05 1.00 0.95 Temp[℃ ] 50 100 150 0.90 -50 0 50 100 150 Tem p[ ℃ ] 1.10 Pulse-by-pulse Current Limit 10 2 Maximum Safe Operating Aree Operation in This Area is Limited by R DS(on) Normalized to 25℃ 100 us ID, Drain Current [A] 1.05 10 1 1 ms 10 ms DC 1.00 10 0 0.95 10 -1 ? Notes : o 1. T C = 25 C 2. T J = 150 C 3. Single Pulse o 0.90 -50 10 -2 0 50 100 150 10 0 10 1 10 2 10 3 Temp[℃ ] [℃ ] VDS, Drain-Source Voltage [V] Transieus Thermal Response 10 0 Maximum Avalanch Energy 1200 D=0.5 -1 AVALANCHE ENERGY, EAS[mJ] 1 1000 Z? JC Thermal Response (t), 10 0.2 0.1 0.05 0.02 0.01 ? Notes : (t) 1. Z? JC = 0.46 ? /W Max. 2. Duty Factor, D=t1/t2 3. TJM - TC = PDM * Z? JC (t) 800 600 400 10 -2 200 single pulse 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 0 25 50 75 100 o 125 150 t1, Square Wave Pulse Duration [sec] Initial Junction Temperature, TJ [ C] 12 FSCQ1565RP Functional Description 1. Startup : Figure 4 shows the typical startup circuit and transformer auxiliary winding for FSCQ1565RP application. Before FSCQ1565RP begins switching, FSCQ1565RP consumes only startup current (typically 25uA) and the current supplied from the AC line charges the external capacitor (Ca1) that is connected to the Vcc pin. When Vcc reaches start voltage of 15V (VSTART), FSCQ1565RP begins switching, and the current consumed by FSCQ1565RP increases to 4mA. Then, FSCQ1565RP continues its normal switching operation and the power required for this device is supplied from the transformer auxiliary winding, unless Vcc drops below the stop voltage of 9V (VSTOP). To guarantee the stable operation of the control IC, Vcc has under voltage lockout (UVLO) with 6V hysteresis. Figure 5 shows the relation between the FSCQ1565RP operating supply current and the supply voltage (Vcc). The minimum average of the current supplied from the AC is given by  2 ⋅ V ac V start 1 =  ----------------------------- – -------------  ⋅ --------2  R str π  min I sup avg where Vacmin is the minimum input voltage, Vstart is the FSCQ1565RP start voltage (15V) and Rstr is the startup resistor. The startup resistor should be chosen so that Isupavg is larger than the maximum startup current (50uA). Once the resistor value is determined, the maximum loss in the startup resistor is obtained as  ) + V start 2 2 ⋅ V start ⋅ V ac 1 -  ( V ac Loss = --------- ⋅  -------------------------------------------------- – -----------------------------------------------------  R str  π 2  max 2 2 max where Vacmax is the maximum input voltage. The startup resistor should have proper rated dissipation wattage. C DC 1N4007 AC line (V acmin - V acmax) Rstr Da Isup Vcc 2. Synchronization : FSCQ1565RP employs quasi-resonant switching technique to minimize the switching noise and loss. In this technique, a capacitor (Cr) is added between the MOSFET drain and source as shown in Figure 6. The basic waveforms of quasi-resonant converter are shown in Figure 7. The external capacitor lowers the rising slop of drain voltage to reduce the EMI caused when the MOSFET turns off. In order to minimize the MOSFET switching loss, the MOSFET should be turned on when the drain voltage reaches its minimum value as shown in Figure 7. FSCQ1565RP C a1 C a2 + V DC Np Ns Lm Vo C DC Figure 1. Startup circuit Drain Cr Ids GND + V ds - Icc Sync V cc R cc C a1 V co C a2 Da Na D SY 4mA R SY1 Power Down 25uA Vstop=9V Power Up C SY R SY2 Vcc Vstart=15V Vz Figure 3. Synchronization circuit Figure 2. Relation between operating supply current and Vcc voltage 13 FSCQ1565RP Vds MOSFET off MOSFET on Vgs 2V R O TQ VRO Vds VRO VDC Vs ync V sypk Vrh (4 .6V) Vrf (2 .6V) TR Ids Ipk MOS FET Gate Figure 4. Quasi-resonant operation waveforms ON ON Figure 5. Normal quasi-resonant operation waveforms The minimum drain voltage is indirectly detected by monitoring the Vcc winding voltage as shown in Figure 6 and 8. The voltage divider RSY1 and RSY2 should be chosen so that the peak voltage of sync signal (Vsypk) is lower than the OVP voltage (12V) in order to avoid triggering OVP in normal operation. It is typical to set Vsypk to be lower than OVP voltage by 3-4 V. In order to detect the optimum time to turn on MOSFET, the sync capacitor (CSY) should be determined so that TR is the same with TQ as shown in Figure 8. The TR and TQ are given as, respectively V co R SY2 = R SY2 ⋅ C SY ⋅ ln  -------- ⋅ ----------------------------------   2.6 R SY1 + R SY2 Switching frequency Extended QR operation 90kHz Normal QR operation 45kHz TR T Q = π ⋅ L m ⋅ C eo N a ⋅ ( V o + V FO ) V co = ---------------------------------------- – V Fa Ns Output power Figure 6. Extended quasi-resonant operation where Lm is the primary side inductance of the transformer, Ns and Na are the number of turns for the output winding and Vcc winding, respectively, VFo and VFa are the diode forward voltage drops of the output winding and Vcc winding, respectively, and Ceo is the sum of the output capacitance of MOSFET and external capacitor Cr. In general, quasi-resonant converter has a limitation in a wide load range application, since the switching frequency increases as the output load decreases, resulting in a severe switching loss in the light load condition. In order to get over this limitation, FSCQ1565RP employs extended quasiresonant switching operation. Figure 9 shows the mode change between normal quasi-resonant operation and extended quasi-resonant operation. In the normal quasiresonant operation, the FSCQ1565RP enters into the extended quasi-resonant operation when the switching frequency exceeds 90kHz as the load reduces. Then, the MOSFET is turned on, when the drain voltage reaches the second minimum level as shown in Figure 10, which reduces the switching frequency. 14 FSCQ1565RP Once FSCQ1565RP enters into extended quasi-resonant operation, the first sync signal is ignored. After the first sync signal is applied, the sync threshold levels are changed from 4.6V and 2.6V to 3V and 1.8V, respectively, and the MOSFET turn-on time is synchronized to the second sync signal. The FSCQ1565RP goes back to its normal quasiresonant operation when the switching frequency reaches 45kHz as the load increases. Vds 2VRO internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by external resonant capacitor across the MOSFET and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FSCQ1565RP employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. Vcc Idelay Vref IFB OSC Vo Vfb H11A817A CB 4 D1 D2 2.5R + Vfb* SenseFET Vsync KA431 R Gate driver - 4.6V 3V 2.6V 1.8V MOSFET Gate VSD OLP Rsense Figure 8. Pulse width modulation (PWM) circuit ON ON Figure 7. Extended quasi-resonant operation waveforms 3. Feedback Control : FSCQ1565RP employs current mode control, as shown in Figure 11. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 3.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of PWM comparator (Vfb*) as shown in Figure 11. The feedback current (IFB) and internal resistors are designed so that the maximum cathode voltage of diode D2 is about 2.8V, which occurs when all IFB flows through the internal resistors. Since D1 is blocked when the feedback voltage (Vfb) exceeds 2.8V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the current through the Sense FET is limited. 3.2 Leading edge blanking (LEB) : At the instant the 4. Protection Circuit : The FSCQ1565RP has several self protective functions such as over load protection (OLP), abnormal over current protection (AOCP), over voltage protection (OVP) and thermal shutdown (TSD). OLP and OVP are auto-restart mode protection, while TSD and AOCP are latch mode protection. Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. -Auto-restart mode protection: Once the fault condition is detected, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc falls down to the under voltage lockout (UVLO) stop voltage of 9V, the protection is reset and FSCQ1565RP consumes only startup current (25uA). Then, Vcc capacitor is charged up, since the current supplied through the startup resistor is larger than the current that FPS consumes. When Vcc reaches the start voltage of 15V, FSCQ1565RP resumes its normal operation. If the fault condition is not removed, the SenseFET remains off and Vcc drops to stop voltage again. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see Figure 12). -Latch mode protection: Once protection triggers, switching is terminated and the Sense FET remains off until the AC power line is un-plugged. Then, Vcc continues charging and discharging between 9V and 15V. The latch is reset only when Vcc is discharged to 6V by un-plugging the Ac power line. 15 FSCQ1565RP Vds Power on Fault occurs Fault removed V FB 7.5V Over load protection Vcc 2.8V 15V 9V T12= CB*(7.5-2.8)/Idelay T1 T2 t Figure 10. Over load protection Iop 4mA 25uA t Normal operation Fault situation Normal operation Figure 9. Auto restart mode protection AOCP Vaocp - Figure 11. AOCP block 4.3 Over voltage Protection (OVP) : If the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, 16 + 4.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be triggered during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to trigger after a specified time to determine whether it is a transient situation or an overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.8V, D1 is blocked and the 5uA current source starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 7.5V, when the switching operation is terminated as shown in Figure 13. The delay time for shutdown is the time required to charge CB from 2.8V to 7.5V with 5uA. In general, a 20 ~ 50 ms delay time is typical for most applications. This protection is implemented in auto restart mode. 4.2 Abnormal Over Current Protection (AOCP) : When the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the SenseFET during the LEB time. Even though the FSCQ1565RP has OLP (Over Load Protection), it is not enough to protect the FSCQ1565RP in that abnormal case, since sever current stress will be imposed on the SenseFET until OLP triggers. The FSCQ1565RP has an internal AOCP (Abnormal Over Current Protection) circuit as shown in Figure 14. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the set signal is applied to the latch, resulting in the shutdown of SMPS. This protection is implemented in latch mode. 2.5R OSC PWM S Q R Q Gate driver R LEB Rsense 2 GND FSCQ1565RP forcing the preset maximum current to be supplied to the SMPS until the over load protection triggers. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection triggers, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, the peak voltage of the sync signal is proportional to the output voltage and the FSCQ1565RP uses sync signal instead of directly monitoring the output voltage. If sync signal exceeds 12V, an OVP is triggered resulting in a shutdown of SMPS. In order to avoid undesired triggering of OVP during normal operation, the peak voltage of sync signal should be designed to be below 12V. This protection is implemented in auto restart mode. 4.4 Thermal Shutdown (TSD) : The SenseFET and the control IC are built in one package. This makes it easy for the control IC to detect the abnormal over temperature of the SenseFET. When the temperature exceeds approximately 150°C, the thermal shutdown triggers. This protection is implemented in latch mode. 5. Soft Start : The FSCQ1565RP has an internal soft start circuit that increases PWM comparator inverting input voltage together with the SenseFET current slowly after it starts up. The typical soft start time is 20msec. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. For a fast build up of the output voltage, an offset is introduced in the soft-start reference current. 6. Burst operation : In order to minimize the power consumption in the standby mode, FSCQ1565RP employs burst operation. Once FSCQ1565RP enters into burt mode, FSCQ1565RP allows all output voltages and effective switching frequency to be reduced. Figure 15 shows the typical feedback circuit for C-TV applications. In normal operation, the picture on signal is applied and the transistor Q1 is turned on, which de-couples R3, Dz and D1 from the feedback network. Therefore, only Vo1 is regulated by the feedback circuit in normal operation and determined by R1 and R2 as V o1 norm V o2 stby = V Z + 0.7 + 2.5 VO2 VO1 (B+) RD Rbias R1 CF C R Linear Regulator Micom Dz R3 RF D1 Q1 Picture ON KA431 A R2 Figure 12. Typical feedback circuit to drop output voltage in standby mode Figure 16 shows the burst mode operation waveforms. When the picture ON signal is disabled, Q1 is turned off and R3 and Dz are connected to the reference pin of KA431 through D1. Before Vo2 drops to Vo2stby, the voltage on the reference pin of KA431 is higher than 2.5V, which increases the current through the opto LED. This pulls down the feedback voltage (VFB) of FSCQ1565RP and forces FSCQ1565RP to stop switching. If the switching is disabled longer than 1.4ms, FSCQ1565RP enters into burst operation and the operating current is reduced from 4mA (IOP) to 0.35mA (IOB). Since there is no switching, Vo2 decrease until it reaches Vo2stby. As Vo2 reaches Vo2stby, the current through the opto LED decreases allowing the feedback voltage to rise. When the feedback voltage reaches 0.4V, FSCQ1565RP resumes switching with a predetermined peak drain current of 0.9A. After burst switching for 1.4ms, FSCQ1565RP stops switching and checks the feedback voltage. If the feedback voltage is below 0.4V, FSCQ1565RP stops switching until the feedback voltage increases to 0.4V. If the feedback voltage is above 0.4V, FSCQ1565RP goes back to the normal operation. R1 + R2 = 2.5 ⋅  --------------------   R2  In standby mode, the picture on signal is disabled and the transistor Q1 is turned off, which couples R3, Dz and D1 to the reference pin of KA431. Then, Vo2 is determined by the zener diode breakdown voltage. Assuming that the forward voltage drop of D1 is 0.7V, Vo2 in standby mode is approximately given by 17 FSCQ1565RP (a) Vo2 norm (b) (c) V o2 stby V FB 0.4V Iop I OP ( 4m A) I OB ( 0.35m A) Vds Picture On Picture Off Burst Mode Picture On VFB 0.4V 0.3V 0.4V 0.4V Vds 1.4ms Ids 0.9A 0.9A 1.4ms 1.4ms (a) M ode change to Burst operation (b) Burst operation (c) M ode change to Normal operation Figure 13. Waveforms of burst operation 18 FSCQ1565RP Typical application circuit Application Output power Input voltage Universal input (85-265Vac) Output voltage (Max current) 8.5V (1A) C-TV 210W 15V (1A) 126V (0.9A) 24V (2A) Features • • • • • • High efficiency (>80% at 85Vac input) Wider load range through the extended quasi-resonant operation Low standby mode power consumption (