FSTU16862QSP

FSTU16862 20-Bit Bus Switch with 2V Undershoot Protection May 2002 Revised October 2006 FSTU16862 20-Bit Bus Switch with 2V Undershoot Protection General Description The Fairchild Switch FSTU16862 provides 20-bits of highspeed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The device is organized as a 20-bit bus switch. When OEX is LOW, the switch is ON and Port A is connected to Port B. When OEX is HIGH, a high impedance state exists between the A and B Ports. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild's integrated Undershoot Hardened Circuit (UHC®¥) senses undershoot at the I/O and responds by preventing voltage differentials from developing and turning the switch on. Features s Undershoot hardened to 2V (A and B Ports) s 4: switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Application Note AN-5008 for details on FSTU - Undershoot Protected Fairchild Switch Family Ordering Code: Order Number FSTU16862QSP FSTU16862MTD Package Number MQA48A MTD48 Package Description 48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. UHC®¥ is a registered trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS500703 www.fairchildsemi.com FSTU16862 Logic Diagram Connection Diagram Pin Descriptions Pin Name OEx A B Description Bus Switch Enables Bus A Bus B Truth Table Inputs OEx L H H HIGH Voltage Level L LOW Voltage Level Z High Impedance Inputs/Outputs A, B A Z B www.fairchildsemi.com 2 FSTU16862 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Switch Voltage (VS) (Note 2) DC Input Voltage (VIN) (Note 3) DC Input Diode Current (lIK) VIN  0V DC Output Current (IOUT) DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) 0.5V to 7.0V 2.0V to 7.0V 0.5V to 7.0V 50 mA 128 mA Recommended Operating Conditions (Note 4) Power Supply Operating (VCC) Input Voltage (VIN) Output Voltage (VOUT) Input Rise and Fall Time (tr, tf) Switch Control Input Switch I/O Free Air Operating Temperature (TA) 0 ns/V to 5 ns/V 0 ns/V to DC -40 qC to 85 qC 4.0V to 5.5V 0V to 5.5V 0V to 5.5V r100 mA 65qC to 150 qC Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: VS is the voltage observed/applied at either the A or B Ports across the switch. Note 3: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 4: Unused control inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics VCC Symbol VIK VIH VIL II IOZ RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 6) (V) 4.5 4.0–5.5 4.0–5.5 5.5 0 5.5 4.5 4.5 4.5 4.0 ICC Quiescent Supply Current Increase in ICC per Input (Note 7) VIKU Voltage Undershoot 5.0V and TA TA Min 40 qC to 85 qC Typ (Note 5) Max Units V V 0.8 V IIN Conditions 1.2 2.0 18 mA r1.0 10 PA PA PA : : : : PA mA V 0 d VIN d 5.5V VIN VIN VIN VIN VIN VIN 5.5V 0V, IIN 0V, IIN 2.4V, IIN 2.4V, IIN 64 mA 30 mA 15 mA 15 mA 0 0 d A, B d VCC r1.0 4 4 8 11 7 7 14 20 3 2.5 5.5 5.5 5.5 25qC VCC or GND, IOUT ' ICC One Input at 3.4V Other Inputs at VCC or GND 0.0 mA t IIN t 50 mA OE 5.5V 2.0 Note 5: Typical values are at VCC Note 6: M easured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins. Note 7: Per TTL driven input, control pins only. 3 www.fairchildsemi.com FSTU16862 AC Electrical Characteristics TA Symbol Parameter VCC Min tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Propagation Delay Bus-to-Bus (Note 8) Output Enable Time Output Disable Time 1.0 1.0 CL 40 qC to 85 qC, RD 500: 4.0V Max 0.25 6.4 7.4 ns ns ns VI VI VI 6.9 VI VI OPEN 7V for tPZL OPEN for tPZH 7V for tPLZ OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Units Conditions Figure Number VCC Min 50pF, RU 4.5 – 5.5V Max 0.25 5.9 Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). Capacitance Symbol CIN CI/O Note 9: TA (Note 9) Parameter Typ 3 6 Max Units pF pF VCC Conditions 5.0V, VIN 0V 0V Control Pin Input Capacitance Input/Output Capacitance “OFF State” 25qC, f VCC, OE 5.0V, VIN 1 MHz, Capacitance is characterized but not tested. Undershoot Characteristic (Note 10) Symbol VOUTU Parameter Output Voltage During Undershoot Min 2.5 Typ VOH - 0.3 Max Units V Conditions Figure 1 Note 10: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. FIGURE 1. Device Test Conditions Parameter VIN R1 R2 VTRI VCC Value see Waveform 100K 11.0 5.5 Units V Transient Input Voltage (VIN) Waveform : V V www.fairchildsemi.com 4 FSTU16862 AC Loading and Waveforms Note: Input driven by 50: source terminated in 50: Note: C L includes load and stray capacitance Note: Input PRR 1.0 MHz, tW 500 ns FIGURE 2. AC Test Circuit FIGURE 3. AC Waveforms 5 www.fairchildsemi.com FSTU16862 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150" Wide Package Number MQA48A www.fairchildsemi.com 6 FSTU16862 20-Bit Bus Switch with 2V Undershoot Protection Physical Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384(FST3384) bus switch product. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com