FSTUD32211GX

Preliminary FSTUD32211 40/48-Bit Bus Switch with -2V Undershoot Protection and Level Shifting (Preliminary) February 2001 Revised August 2001 FSTUD32211 40/48-Bit Bus Switch with -2V Undershoot Protection and Level Shifting (Preliminary) General Description The Fairchild Switch FSTUD32211 provides up to 48-bits of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs. The device can be organized as four 12-bit, two 24-bit, or one 48-bit bus switch. When routed as a 40-bit bus switch, the device can be organized as four 10-bit, two 20-bit or one 40-bit bus switch. When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, the switch is ON and Port 2A is connected to Port 2B. When OE3 is LOW, the switch is ON and Port 3A is connected to Port 3B. When OE4 is LOW, the switch is ON and Port 4A is connected to Port 4B. When OE1, OE2, OE3, or OE4 are HIGH, a high impedance state exists between the A and B Ports. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild’s integrated Undershoot Hardened Circuit (UHC) senses undershoot at the I/O’s, and responds by preventing voltage differentials from developing and turning on the switch. Features s Undershoot protected to −2V (A and B Ports) s Voltage level shifting s 4Ω switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Notes AN-5008 and AN-5021 for UHC details s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number FSTUD32211GX (Note 1) Package Number BGA114A (Preliminary) Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] Note 1: BGA package available in Tape and Reel only. © 2001 Fairchild Semiconductor Corporation DS500537 www.fairchildsemi.com Preliminary FSTUD32211 Logic Diagram Pin Descriptions Pin Name OE1, OE2, OE3, OE4 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B NC Description Bus Switch Enables Bus A Bus B No Connect FBGA Pin Assignments (40-Bit Routing) 1 A B C D E F 1A2 1A4 1A6 1A8 1A10 2A2 2A4 2A6 2A8 2A10 3A9 3A7 3A5 3A3 3A1 4A9 4A7 4A5 4A3 2 1A1 1A3 1A5 1A7 1A9 2A1 2A3 2A5 2A7 3A10 3A8 3A6 3A4 3A2 4A10 4A8 4A6 4A4 4A2 3 NC GND GND GND VCC VCC VCC GND 2A9 GND GND GND VCC VCC GND GND GND 4A1 OE3 4 OE2 OE1 GND GND VCC VCC GND GND 2B9 GND GND VCC VCC VCC GND GND 4B1 OE4 NC 5 1B1 1B3 1B5 1B7 1B9 2B1 2B3 2B5 2B7 3B10 3B8 3B6 3B4 3B2 4B10 4B8 4B6 4B4 4B2 6 1B2 1B4 1B6 1B8 1B10 2B2 2B4 2B6 2B8 2B10 3B9 3B7 3B5 3B3 3B1 4B9 4B7 4B5 4B3 Connection Diagram G H J K L M N P R T U V W Truth Tables Inputs OE1 L L (Top Thru View) H H Inputs OE3 L L H H OE4 L H L H OE2 L H L H Inputs/Outputs 1A, 1B 1A = 1B 1A = 1B Z Z 2A, 2B 2A = 2B Z 2A = 2B Z Inputs/Outputs 3A, 3B 3A = 3B 3A = 3B Z Z 4A, 4B 4A = 4B Z 4A = 4B Z www.fairchildsemi.com 2 Preliminary FSTUD32211 Connection Diagram Pin Descriptions Pin Name OE1, OE2, OE3, OE4 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B NC Description Bus Switch Enables Bus A Bus B No Connect FBGA Pin Assignments (48-Bit Routing) 1 A B C D E F G H J (Top Thru View) K L M N P R T U V W 1A2 1A4 1A6 1A10 1A12 2A4 2A6 2A8 2A10 2A12 3A11 3A9 3A7 3A5 3A3 4A11 4A9 4A5 4A3 2 1A1 1A3 1A5 1A9 1A11 2A3 2A5 2A7 2A9 3A12 3A10 3A8 3A6 3A4 4A12 4A10 4A6 4A4 4A2 3 NC 1A7 GND 1A8 2A1 2A2 VCC GND 2A11 GND GND GND 3A2 3A1 4A8 4A7 GND 4A1 OE3 4 OE2 OE1 1B7 1B8 2B1 2B2 GND GND 2B11 GND GND VCC 3B2 3B1 4B8 4B7 4B1 OE4 NC 5 1B1 1B3 1B5 1B9 1B11 2B3 2B5 2B7 2B9 3B12 3B10 3B8 3B6 3B4 4B12 4B10 4B6 4B4 4B2 6 1B2 1B4 1B6 1B10 1B12 2B4 2B6 2B8 2B10 2B12 3B11 3B9 3B7 3B5 3B3 4B11 4B9 4B5 4B3 Truth Tables Inputs OE1 L L H H Inputs OE3 L L H H OE4 L H L H OE2 L H L H Inputs/Outputs 1A, 1B 1A = 1B 1A = 1B Z Z 2A, 2B 2A = 2B Z 2A = 2B Z Inputs/Outputs 3A, 3B 3A = 3B 3A = 3B Z Z 4A, 4B 4A = 4B Z 4A = 4B Z 3 www.fairchildsemi.com Preliminary FSTUD32211 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Switch Voltage (VS) (Note 3) DC Input Control Pin Voltage (VIN)(Note 4) DC Input Diode Current (lIK) VIN < 0V DC Output (IOUT) DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) 0.5V to +7.0V Recommended Operating Conditions (Note 5) Power Supply Operating (VCC) Input Voltage (VIN) Output Voltage (VOUT) Input Rise and Fall Time (tr, tf) Switch Control Input Switch I/O Free Air Operating Temperature (TA) 0 ns/V to 5 ns/V 0 ns/V to DC -40°C to +85°C 4.5V to 5.5V 0V to 5.5V 0V to 5.5V −2V to +7.0V −0.5V to +7.0V −50 mA 128 mA +/− 100 mA −65°C to +150 °C Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: VS is the voltage observed/applied at either A or B Ports across the switch. Note 4: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 5: Unused control inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIK VIH VIL VOH II IOZ RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 7) ICC Quiescent Supply Current 5.5 10 ∆ ICC VIKU Increase in ICC per Input Voltage Undershoot 5.5 5.5 2.5 −2.0 µA mA V VCC (V) 4.5 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 5.5 0 5.5 4.5 4.5 4.5 4 4 35 See Figure 4 ±1.0 10 ±1.0 7 7 50 1.5 2.0 0.8 TA = −40 °C to +85 °C Min Typ (Note 6) Max −1.2 Units V V V V µA µA µA Ω Ω Ω mA 0 ≤ VIN ≤ 5.5V VIN = 5.5V 0 ≤ A, B ≤ VCC VIN = 0V, IIN = 64 mA VIN = 0V, IIN = 30 mA VIN = 2.4V, IIN = 15 mA OE1 = OE2 = GND VIN = VCC or GND, IOUT = 0 OE1 = OE2 = V CC VIN = VCC or GND, IOUT = 0 One Input at 3.4V Other Inputs at VCC or GND 0.0 mA ≥ IIN ≥ −50 mA OE1,2 = 5.5V Note 6: Typical values are at VCC = 5.0V and T A= +25°C Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins. Conditions IIN = −18 mA www.fairchildsemi.com 4 Preliminary FSTUD32211 AC Electrical Characteristics TA = −40 °C to +85 °C, Symbol Parameter CL = 50pF, RU = RD = 500Ω VCC = 4.5 – 5.5V Min tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Propagation Delay Bus to Bus (Note 8) Output Enable Time Output Disable Time 1.5 1.5 Max 0.25 10.0 9.0 ns ns ns VI = OPEN VI = 7V for tPZL VI = OPEN for tPZH VI = 7V for tPLZ VI = OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Units Conditions Figure Number Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). Capacitance Symbol CIN CI/O (Note 9) Parameter Typ 3 6 Max Units pF pF Conditions VCC = 5.0V VCC, OE = 5.0V Control Pin Input Capacitance Input/Output Capacitance Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested. Undershoot Characteristic (Note 10) Symbol VOUTU Parameter Output Voltage During Undershoot Min 2.5 Typ VOH - 0.3 Max Units V Conditions Figure 1 Note 10: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. FIGURE 1. Device Test Conditions Parameter VIN R1 = R2 VTRI VCC Value see Waveforms 100K 11.0 5.5 Units V Ω V V Transient Input Voltage (VIN) Waveform 5 www.fairchildsemi.com Preliminary FSTUD32211 AC Loading and Waveforms Note: Input driven by 50Ω source terminated in 50Ω Note: CL includes load and stray capacitance Note: Input PRR = 1.0 MHz, tW = 500 ns FIGURE 2. AC Test Circuit FIGURE 3. AC Waveforms www.fairchildsemi.com 6 Preliminary FSTUD32211 Output Voltage HIGH vs. Supply Voltage FIGURE 4. 7 www.fairchildsemi.com Preliminary FSTUD32211 40/48-Bit Bus Switch with -2V Undershoot Protection and Level Shifting (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Preliminary Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com