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MM74HC688MTC

MM74HC688MTC

  • 厂商:

    FAIRCHILD(仙童半导体)

  • 封装:

  • 描述:

    MM74HC688MTC - 8-Bit Magnitude Comparator (Equality Detector) - Fairchild Semiconductor

  • 数据手册
  • 价格&库存
MM74HC688MTC 数据手册
MM74HC688 8-Bit Magnitude Comparator (Equality Detector) September 1983 Revised May 2005 MM74HC688 8-Bit Magnitude Comparator (Equality Detector) General Description The MM74HC688 equality detector utilizes advanced silicon-gate CMOS technology to compare bit for bit two 8-bit words and indicates whether or not they are equal. The P Q output indicates equality when it is LOW. A single active low enable is provided to facilitate cascading of several packages and enable comparison of words greater than 8 bits. This device is useful in memory block decoding applications, where memory block enable signals must be generated from computer address information. The comparator’s output can drive 10 low power Schottky equivalent loads. This comparator is functionally and pin compatible to the 74LS688. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features s Typical propagation delay: 20 ns s Wide power supply range: 2–6V s Low quiescent current: 80 PA (74 Series) s Large output current: 4 mA (74 Series) s Same as HC521 Ordering Code: Order Number MM74HC688WM MM74HC688SJ MM74HC688MTC MM74HC688N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP Logic Diagram Top View Truth Table Inputs Data P,Q P Q P!Q PQ X Enable G L L L H P L H H H Q © 2005 Fairchild Semiconductor Corporation DS005018 www.fairchildsemi.com MM74HC688 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW (ICC) Storage Temperature Range (TSTG) Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC VCC VCC 2.0V 4.5V 6.0V 1000 500 400 ns ns ns 2 0 Max 6 VCC Units V V 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r25 mA r50 mA 65qC to 150qC 40 85 qC Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package:  12 mW/qC from 65qC to 85qC. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN VIH or VIL Conditions (Note 4) VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 2 5 qC TA 40 to 85qC TA 55 to 125qC Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 Units V V V V V V V V V V V V V V V V |IOUT| d 20 PA 2.0V 4.5V 6.0V VIN VIH or VIL 4.5V 6.0V 2.0V 4.5V 6.0V |IOUT| d 4.0 mA |IOUT| d 5.2 mA VOL Maximum LOW Level Output Voltage VIN VIH or VIL |IOUT| d 20 PA VIN VIH or VIL 4.5V 6.0V 6.0V 6.0V |IOUT| d 4.0 mA |IOUT| d 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN IOUT VCC or GND 0 PA VIN VCC or GND r0.1 8.0 r1.0 80 r1.0 160 PA PA Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 MM74HC688 AC Electrical Characteristics VCC 5V, TA 25qC, CL 15 pF, tr Parameter tf 6 ns Conditions Typ 21 14 Guaranteed Limit 30 20 Units ns ns Symbol tPHL, tPLH tPLH, tPHL Maximum Propagation Delay, any P or Q to Output Maximum Propagation Delay, Enable to any Output AC Electrical Characteristics VCC 2.0V to 6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified) Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA 25qC Typ 60 22 19 45 15 13 30 8 7 45 5 10 10 10 175 35 30 120 24 20 75 15 13 TA Symbol tPHL, tPLH Parameter Maximum Propagation Delay, P or Q to Output 40 to 85qC TA 55 to 125qC Guaranteed Limits 220 44 38 150 30 25 95 19 16 263 53 45 180 36 30 110 22 19 Units ns ns ns ns ns ns ns ns ns pF pF tPHL, tPLH Maximum Propagation Delay, Enable to Output tTHL, tTLH Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f  ICC. CPD VCC2 f  ICC VCC, and the no load dynamic current consumption, 3 www.fairchildsemi.com MM74HC688 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 4 MM74HC688 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com MM74HC688 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 MM74HC688 8-Bit Magnitude Comparator (Equality Detector) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com
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