MM74HCT573N

MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop February 1990 Revised May 2005 MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic and pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. When the MM74HCT573 Latch Enable input is HIGH, the Q outputs will follow the D inputs. When the Latch Enable goes LOW, data at the D inputs will be retained at the outputs until Latch Enable returns HIGH again. When a high logic level is applied to the Output Control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the Clock (CK) input. When a high logic level is applied to the Output Control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Features s TTL input characteristic compatible s Typical propagation delay: 18 ns s Low input current: 1 PA maximum s Low quiescent current: 80 PA maximum s Compatible with bus-oriented systems s Output drive capability: 15 LS-TTL loads Ordering Codes: Order Number MM74HCT573WM MM74HCT573SJ MM74HCT573MTC MM74HCT573N MM74HCT574WM MM74HCT574SJ MM74HCT574MTC MM74HCT574N Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation DS010627 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Connection Diagrams Truth Tables MM74HCT573 Output Control L L L H LE H H L X Data H L X X Output H L Q0 Z H H IGH Level L LOW Level Q0 Level of output before steady-state input conditions were established. Z High Impedance State Top View MM74HCT573 MM74HCT574 Output Control L L L H H L Q0 X Z LE Data H L X X Output H L Q0 Z n n L X n H IGH Level LOW Level Level of output before steady-state input conditions were established. Don’t Care High Impedance State Transition from LOW-to-HIGH Top View MM74HCT574 www.fairchildsemi.com 2 MM74HCT573 • MM74HCT574 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S. O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times tr, tf 500 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package:  12 mW/qC from 65qC to 85qC. 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r 20 mA r 35 mA r 70 mA 65qC to 150qC Max 5.5 VCC Units V V 4.5 0 40 85 qC DC Electrical Characteristics VCC 5V r 10% (unless otherwise specified) Parameter Minimum HIGH Level Input Voltage VIL VOH Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN |IOUT| |IOUT| |IOUT| VOL Maximum LOW Level Voltage VIN |IOUT| |IOUT| |IOUT| IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN IOUT VIN VCC or GND 0 PA 2.4V or 0.5V (Note 4) 1.5 1.8 2.0 mA 8.0 80 160 VIN VOUT Enable VIH or VIL 20 PA 6.0 mA, VCC 7.2 mA, VCC VIH or VIL 20 PA 6.0 mA, VCC 7.2 mA, VCC VCC or GND, VCC or GND VIH or VIL 4.5V 5.5V 0 0.2 0.2 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.4 0.4 V 4.5V 5.5V VCC 4.2 5.7 VCC  0.1 3.98 4.98 VCC  0.1 3.84 4.84 VCC  0.1 3.7 4.7 V 0.8 0.8 0.8 V Conditions TA Typ 2.0 2 5 qC TA Symbol VIH 40 to 85qC TA 55 to 125qC Guaranteed Limits 2.0 2.0 Units V r0.1 r0.5 r1.0 r5.0 r1.0 r10 PA PA VIH or VIL PA Note 4: M easured per pin. All others tied to VCC or ground. 3 www.fairchildsemi.com MM74HCT573 • MM74HCT574 AC Electrical Characteristics MM74HCT573 VCC tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ tW tS tH 5.0V, tr tf 6 ns, TA 25qC (unless otherwise specified) Parameter Conditions CL CL 45 pF 45 pF 45 pF 1 k: 5 pF 1 k: 15 5 12 ns ns ns 14 23 ns Typ 17 16 21 Guaranteed Limit 27 27 30 Units ns ns ns Symbol Maximum Propagation Delay Data to Output Maximum Propagation Delay Latch Enable to Output Maximum Enable Propagation Delay CL Control to Output Control to Output Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data RL RL Maximum Disable Propagation Delay CL AC Electrical Characteristics MM74HCT573 VCC 5.0V Symbol tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ tTHL tTLH tW tS tH CIN COUT CPD r 10%, tr tf 6 ns (unless otherwise specified) Conditions CL CL CL RL CL RL CL 50 pF 50 pF 50 pF 1 k: 50 pF 1 k: 50 pF 6 12 15 15 20 6 15 10 20 18 24 8 18 10 20 ns ns ns ns pF pF pF 15 30 38 45 ns TA Typ 18 17 22 30 30 30 25 q TA Parameter Maximum Propagation Delay Data to Output Maximum Propagation Delay Latch Enable to Output Maximum Enable Propagation Delay Control to Output Maximum Disable Propagation Delay Control to Output Maximum Output Rise and Fall Time Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Maximum Input Capacitance Maximum Output Capacitance Power Dissipation Capacitance (Note 5) OC OC 40 to 85qC TA Guaranteed Limits 38 44 38 55 to 125qC 45 53 45 Units ns ns ns 3 4 5 12 10 20 VCC GND 5 52 CPD VCC2 fICC VCC, and the no load dynamic current consumption, Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC fICC. www.fairchildsemi.com 4 MM74HCT573 • MM74HCT574 AC Electrical Characteristics VCC fMAX tPHL tPLH tPZH tPZL tPHZ tPLZ tW tS tH MM74HCT574 Conditions Typ 60 17 19 14 Guaranteed Limit 33 27 28 25 15 12 5 Units MHz ns ns ns ns ns ns 5.0V, tr tf 6 ns, TA 25qC Parameter Symbol Maximum Clock Frequency Maximum Propagation Delay to Output Maximum Enable Propagation Delay Control to Output Maximum Disable Propagation Delay Control to Output Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data CL RL CL RL 45 pF 1 k: 45 pF 1 k: CL 45 pF AC Electrical Characteristics MM74HCT574 VCC 5.0V r 10%, tr tf 6 ns (unless otherwise specified) Parameter Conditions TA Typ 25qC 33 CL CL RL CL RL CL 50 pF 50 pF 1 k: 50 pF 1 k: 50 pF 6 12 15 6 12 5 10 20 OC OC V CC GND 5 58 CPD VCC f  ICC. Symbol fMAX tPHL tPLH tPZH tPZL tPHZ tPLZ tTHL tTLH tW tS tH CIN COUT CPD TA 40 to 85qC TA 28 38 38 38 15 20 15 6 10 20 55 to 125qC 23 45 45 45 18 24 18 8 10 20 Units MHz ns ns ns ns ns ns ns pF pF pF Guaranteed Limits 30 30 30 Maximum Clock Frequency Maximum Propagation Delay Clock to Output Maximum Enable Propagation Delay Control to Output Maximum Disable Propagation Delay Control to Output Maximum Output Rise and Fall Time Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Maximum Input Capacitance Maximum Output Capacitance Power Dissipation Capacitance (Note 6) 22 15 18 1 Note 6: CPD determines the no load power consumption, PD CPD VCC2 f  ICC VCC, and the no load dynamic current consumption, IS 5 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 8 MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop Physical Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com