NDM3001

February 1997 NDM3001 3 Phase Brushless Motor Driver General Description The NDM3001 three phase brushless motor driver consists of three N-Channel and P-Channel MOSFETs in a half bridge configuration. These devices are produced using Fairchild's proprietary, high cell density DMOS technology. This very high density process is tailored to minimize on-state resistance which reduces power loss, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage 3 phase motor driver such as disk drive spindle motor control and other half bridge applications. Features ±2.9 A, ±30 V, 2.5W High density cell design for extremely low RDS(ON). High power and current handling capability. Industry standard SOIC-16 surface mount package. ________________________________________________________________________________ 11,14 10 12 15 Q1 1,16 4,13 8,9 Q3 Q5 Q2 2 5 7 3,6 Q4 Q6 Absolute Maximum Ratings Symbol VDSS VGSS ID Parameter T A = 25°C unless otherwise noted NDM3001 ±30 ±20 ±2.9 ±10 2.5 1.6 (Note 1c) Units V V A Drain-Source Voltage (All Types) Gate-Source Voltage (All Types) Drain Current Q1+Q4 or Q1+Q6 or Q3+Q2 Continuous Q3+Q6 or Q5+Q2 or Q5+Q4 - Pulsed (Note 1a & 2) (Note 1a) (Note 1b) PD Total Power Dissipation Q1+Q4 or Q1+Q6 or Q3+Q2 or Q3+Q6 or Q5+Q2 or Q5+Q4 W 1.4 -55 to 150 °C TJ,TSTG Operating and Storage Temperature Range © 1997 Fairchild Semiconductor Corporation NDM3001 Rev.C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient Q1+Q4 or Q1+Q6 or Q3+Q2 or Q3+Q6 or Q5+Q2 or Q5+Q4 (Note 1a) Thermal Resistance, Junction-to-Case Q1+Q4 or Q1+Q6 or Q3+Q2 or Q3+Q6 or Q5+Q2 or Q5+Q4 (Note 1) 50 °C/W RθJC 20 °C/W Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Type Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSS VGS(th) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = ± 250 µA VDS = ±24 V, VGS = 0 V TJ=55 C Gate - Body Leakage, Forward (Note 3) o All All ±30 ±1 ±10 V µA µA nA VGS = ±20 V, VDS = 0 V VDS = VGS, ID = -250 µA TJ=125 C VDS = VGS, ID = 250 µA TJ=125 C o o All ±100 ON CHARACTERISTICS Gate Threshold Voltage Q1, Q3, Q5 -1 - 0.75 -1.6 -1.3 1.5 1.2 0.19 0.27 0.3 -2 -1.5 2 1.5 0.24 0.45 0.36 0.115 0.221 0.16 V Q2, Q4, Q6 1 0.75 RDS(ON) Static Drain-Source On-Resistance VGS = -10 V, ID = -2.9 A TJ=125 C VGS = -4.5 V, ID = -2.2 A VGS = 10 V, ID = 2.9 A TJ=125oC VGS = 4.5 V, ID = 2.2 A o Q1, Q3, Q5 Ω Q2, Q4, Q6 0.09 0.126 0.13 ID(on) On-State Drain Current VGS = 10 V, VDS = -5 V VGS = 10 V, VDS = 5 V Q1, Q3, Q5 Q2, Q4, Q6 -10 10 A DYNAMIC CHARACTERISTICS Ciss Coss Crss Input Capacitance Q1, Q3, Q5 VDS = -15 V, VGS = 0 V, f = 1.0 MHz Q2, Q4, Q6 15 V, VGS = 0 V, f = 1.0 MHz VDS = Q1, Q3, Q5 Q2, Q4, Q6 Q1, Q3, Q5 Q2, Q4, Q6 Q1, Q3, Q5 Q2, Q4, Q6 260 185 140 115 50 40 pF pF pF Output Capacitance Reverse Transfer Capacitance NDM3001 Rev.C Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter (Note 3) Conditions Type Min Typ Max Units SWITCHING CHARACTERISTICS tD(on) tr tD(off) tf Qg Qgs Qgd Turn - On Delay Time Turn - On Rise Time Q1, Q3, Q5 VDD = -15 V, ID = -1 A, VGEN = -10 V, RGEN = 6 Ω Q2, Q4, Q6 VDD = 15 V, ID = 1 A, VGEN = 10 V, RGEN = 6 Ω Q1, Q3, Q5 Q2, Q4, Q6 Q1, Q3, Q5 Q2, Q4, Q6 10 9 13 21 21 21 5 8 10 9.5 1.6 1.5 3 2.5 40 40 40 40 90 90 50 50 25 25 ns ns Turn - Off Delay Time Q1, Q3, Q5 Q2, Q4, Q6 Q1, Q3, Q5 Q2, Q4, Q6 ns Turn - Off Fall Time ns Total Gate Charge Gate-Source Charge Q1, Q3, Q5 VDS = -10 V, ID = -3.0 A, VGS = -10 V Q2, Q4, Q6 VDS = 10 V, ID = 3.0 A, VGS = 10 V Q1, Q3, Q5 Q2, Q4, Q6 Q1, Q3, Q5 Q2, Q4, Q6 Q1, Q3, Q5 Q2, Q4, Q6 nC nC Gate-Drain Charge nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD trr Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage Reverse Recovery Time Q1, Q3, Q5 Q2, Q4, Q6 Q1, Q3, Q5 Q2, Q4, Q6 All -0.8 0.8 -1.2 1.2 -1.3 1.3 100 A V VGS = 0 V, IS = -3.0 A VGS = 0 V, IS = 3.0 A VGS = 0 V, I F = ±3.0 A, dI F /dt = 100 A/µs (Note 3) (Note 3) ns PD (t ) = R θJ At ) ( T J−TA = R θJ C RθCA t ) + ( T J−TA = I 2 (t ) × RDS(ON ) D TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 50oC/W when mounted on a 1 in2 pad of 2oz cpper. b. 80oC/W when mounted on a 0.027 in2 pad of 2oz cpper. c. 90 C/W when mounted on a 0.0028 in pad of 2oz cpper. o 2 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDM3001 Rev. C Typical Electrical Characteristics 10 V GS =10V I D , DRAIN-SOURCE CURRENT (A) 8 , DRAIN-SOURCE CURRENT (A) 7 .0 6 .0 5.0 4 .5 4 .0 -10 V GS = -10V -7.0 - 6.0 - 5.5 -8 - 5.0 -6 - 4.5 - 4.0 - 3.5 -2 -3.0 0 0 -1 V DS 6 3.5 4 -4 2 3 .0 0 0 0.5 1 1.5 2 VDS , DRAIN-SOURCE VOLTAGE (V) 2.5 3 I D -2 -3 -4 -5 , DRAIN-SOURCE VOLTAGE (V) Figure 1. N-Channel On-Region Characteristic. Figure 2. P-Channel On-Region Characteristics. 2 .6 2 .4 DRAIN-SOURCE ON-RESISTANCE 2 .2 2 1 .8 1 .6 1 .4 1 .2 1 0 .8 0 2 4 6 I D , DRAIN CURRENT (A) 8 10 2.6 VGS = 3.5V R DS(on) NORMALIZED , DRAIN-SOURCE ON-RESISTANCE 2.4 V GS = -4.0V 2.2 2 1.8 1.6 1.4 1.2 R DS(on), NORMALIZED 4 .0 4 .5 5 .0 6 .0 7 10 -4.5 -5.0 - 5.5 -6.0 - 7.0 - 10 1 0.8 0 -2 -4 -6 I D , DRAIN CURRENT (A) -8 -10 Figure 3. N-Channel On-Resistance Variation with Gate Voltage and Drain Current. Figure 4. P-Channel On-Resistance Variation with Gate Voltage and Drain Current. 1.6 1 .6 DRAIN-SOURCE ON-RESISTANCE ID = 2.9A V GS = 10V DRAIN-SOURCE ON-RESISTANCE 1.4 R DS(ON), NORMALIZED R DS(ON), NORMALIZED I D = -2.9A 1 .4 V GS = -10V 1.2 1 .2 1 1 0.8 0 .8 0.6 -50 -25 0 J 25 50 75 100 125 150 0 .6 -50 -25 T , JUNCTION TEMPERATURE (°C) 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) J 125 150 Figure 5. N-Channel On-Resistance Variation with Temperature. Figure 6. P-Channel On-Resistance Variation with Temperature. NDM3001 Rev.C Typical Electrical Characteristics 2 VGS = 10 V R DS(on) NORMALIZED , DRAIN-SOURCE ON-RESISTANCE 1 .8 DRAIN-SOURCE ON-RESISTANCE 1 .6 1 .4 1 .2 1.8 V GS = -10V 1.6 TJ = 125°C R DS(on) , NORMALIZED TJ = 125°C 1.4 1.2 2 5°C 2 5°C 1 0 .8 0 .6 0 .4 0 1 I D 2 3 , DRAIN CURRENT (A) 4 5 1 0.8 0.6 - 55°C - 55°C 0 -1 I D -2 -3 -4 -5 , DRAIN CURRENT (A) Figure 7. N-Channel On-Resistance Variation with Drain Current and Temperature. Figure 8. P-Channel On-Resistance Variation with Drain Current and Temperature. 5 V DS =10V 4 I D, DRAIN CURRENT (A) I D, DRAIN CURRENT (A) -5 V DS = -10V -4 T J = -55°C 25°C 125°C 3 -3 2 -2 T = -55°C J 1 25°C 125°C -1 0 1 1.5 V GS 0 2 2.5 3 , GATE TO SOURCE VOLTAGE (V) 3.5 4 -1 -2 V GS -3 -4 , GATE TO SOURCE VOLTAGE (V) -5 Figure 9. N-Channel Transfer Characteristics. Figure 10. P-Channel Transfer Characteristics. 1.2 GATE-SOURCE THRESHOLD VOLTAGE GATE-SOURCE THRESHOLD VOLTAGE 1.2 1.1 V DS = V GS I D = 250µA V GS(th) , NORMALIZED VDS = V 1.1 GS I D =- 250µA V th, NORMALIZED 1 1 0.9 0.9 0.8 0.7 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 0.7 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) J 125 150 Figure 11. N-Channel Gate Threshold Variation with Temperature. Figure 12. P-Channel Gate Threshold Variation with Temperature. NDM3001 Rev.C Typical Electrical Characteristics DRAIN-SOURCE BREAKDOWN VOLTAGE 1.12 DRAIN-SOURCE BREAKDOWN VOLTAGE 1.08 I D = 250µA 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 I D = - 250µA BV DSS , NORMALIZED 1.08 , NORMALIZED 1.04 1 0.96 0.92 -50 -25 0 25 50 75 100 125 150 BV DSS -25 TJ , JUNCTION TEMPERATURE (°C) 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) J 125 150 Figure 13. N-Channel Breakdown Voltage Variation with Temperature. Figure 14. P-Channel Breakdown Voltage Variation with Temperature. 500 600 400 300 300 200 CAPACITANCE (pF) CAPACITANCE (pF) C i ss C o ss Ci ss 200 100 Co ss 100 60 40 f = 1 MHz V GS = 0V C r ss f = 1 MHz 50 Cr ss V GS = 0 V 20 0.1 0.2 V DS 0.5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) 20 30 30 0.1 0.2 -V DS 0.5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) 20 30 Figure 15. N-Channel Capacitance Characteristics. Figure 16. P-Channel Capacitance Characteristics. 10 10 I D = 2.9A , GATE-SOURCE VOLTAGE (V) 8 V DS = 5V 10V 15V -VGS , GATE-SOURCE VOLTAGE (V) 8 V DS = -5V I D = -2.9A -15V 6 -10V 6 4 4 2 2 V GS 0 0 2 Qg 4 , GATE CHARGE (nC) 6 8 0 0 1 2 3 4 5 6 7 Q g , GATE CHARGE (nC) Figure 17. N-Channel Gate Charge Characteristics. Figure 18. P-Channel Gate Charge Characteristics. NDM3001 Rev.C Typical Electrical Characteristics 5 1 5 I S , REVERSE DRAIN CURRENT (A) V GS = 0V -I , REVERSE DRAIN CURRENT (A) TJ = 125°C 0.1 2 1 0 .5 0 .1 VGS = 0V T J = 125°C 25°C - 55°C 25°C 0 .0 1 0.01 - 55°C 0.001 0 .0 0 1 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 S 0 .0 0 0 1 0 0 .2 -V SD V SD , BODY DIODE FORWARD VOLTAGE (V) 0 .4 0.6 0 .8 1 , BODY DIODE FORWARD VOLTAGE (V) 1 .2 Figure19. N-Channel Body Diode Forward Voltage Variation with Source Current and Temperature. Figure 20. P-Channel Body Diode Forward Voltage Variation with Source Current and Temperature. V DS = 10V , TRANSCONDUCTANCE (SIEMENS) 6 gFS , TRANSCONDUCTANCE (SIEMENS) 7 5 V DS =-10V 4 T J = -55°C 2 5°C 3 1 25°C 2 T J = -55°C 2 5°C 5 1 25°C 4 3 2 1 0 0 2 4 6 I D , DRAIN CURRENT (A) 8 10 1 g FS 0 0 -1 D -2 -3 -4 -5 I , DRAIN CURRENT (A) Figure 21. N-Channel Transconductance Variation with Drain Current and Temperature. Figure 22. P-Channel Transconductance Variation with Drain Current and Temperature. VDD t d(on) t on tr 90% t off t d(off) 90% tf V IN D RL V OUT DUT VO U T VGS 10% 10% 90% R GEN G V IN S 10% 50% 50% PULSE WIDTH Figure 23. N or P-Channel Switching Test Circuit. Figure 24. N or P-Channel Switching Waveforms. NDM3001 Rev.C Typical Thermal and Electrical Characteristics 3.5 3.5 3 DC POWER DISSIPATION (W) I D , DC DRAIN CURRENT (A) 3 1a 2.5 1a 2 2.5 1b 1c 1.5 1b 1c 4.5"x5" FR-4 PCB Ta = 25C Still Air 2 4.5"x5" FR-4 PCB Ta = 25C Still Air Vgs = -10V 1 0.5 0 0.2 0.4 0.6 0.8 1 1.5 0 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 25. SOIC-16 3 Leadframe Device DC Power Dissipation versus Copper Mounting Pad Area. Figure 26. P-Ch DC Drain Current Capability versus Copper Mounting Pad Area. 4.5 20 10 1a I D , DC DRAIN CURRENT (A) ±I , DRAIN CURRENT (A) 4 3 1 R (O DS N) LIM IT 1m s 10 ms 10 0m 3.5 1b 1c 0.3 0.1 VGS = ±10V SINGLE PULSE R θJ A = See Note 1c T 0.8 1 A 1s 10 s DC s 3 4.5"x5" FR-4 PCB Ta = 25C Still Air Vgs =10V D 0.03 0.01 0.5 = 25°C 30 50 2.5 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 2 5 10 ±VDS , DRAIN-SOURCE VOLTAGE (V) Figure 27. N-Ch DC Drain Current Capability versus Copper Mounting Pad Area. Figure 28. P-Ch Typical Safe Operating Area. 1 TRANSIENT THERMAL RESISTANCE 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0001 0.001 0.01 0.1 1 D = 0 .5 0 .2 0 .1 0 .05 0 .02 0 .01 S ingle Pulse P(pk) r(t), NORMALIZED EFFECTIVE R JA ( t) = r(t) * R JA θ θ R JA = See Note 1c θ t1 TJ - T t2 = P * R JA (t) θ D uty Cycle, D = t 1 / t 2 A 10 100 300 t1 , TIME (sec) Figure 29. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDM3001 Rev.C SOIC-16 Tape and Reel Data and Package Dimensions SOIC(16lds) Packaging Configuration: Figure 1.0 Packaging Description: EL ECT ROST AT IC SEN SIT IVE DEVICES DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms Antistatic Cover Tape ESD Label SOIC-16 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. Static Dissipative Embossed Carrier Tape F63TNR Label Customized Label SOIC (16lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no flow code) TNR 2,500 13" Dia 343x64x343 5,000 0.1437 0.7735 L86Z Rail/Tube 45 530x130x83 13,500 0.1437 - FD85AB NDM3001 FD85AB NDM3001 FD85AB NDM3001 FD85AB NDM3001 SOIC-16 Unit Orientation FD85AB NDM3001 Pin 1 343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample LOT: CBVK741B019 FSID: NDM3000 QTY: 2500 SPEC: F63TNR Label F63TNR Label ESD Label D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: N/F: F (F63TNR)3 SOIC(16lds) Tape Leader and Trailer Configuration: Figure 2.0 Carrier Tape Cover Tape Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets October 1999, Rev. B SOIC-16 Tape and Reel Data and Package Dimensions, continued SOIC(16lds) Embossed Carrier Tape Configuration: Figure 3.0 T E1 P0 D0 F K0 Wc B0 E2 W Tc A0 P1 D1 User Direction of Feed Dimensions are in millimeter Pkg type SOIC(16lds) (16mm) A0 6.60 +/-0.30 B0 10.35 +/-0.25 W 16.0 +/-0.3 D0 1.55 +/-0.05 D1 1.60 +/-0.10 E1 1.75 +/-0.10 E2 14.25 min F 7.50 +/-0.05 P1 8.0 +/-0.1 P0 4.0 +/-0.1 K0 2.40 +/-0.40 T 0.450 +/-0.150 Wc 13.0 +/-0.3 Tc 0.06 +/-0.02 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). 10 deg maximum Typical component cavity center line 0.9mm maximum B0 10 deg maximum component rotation 0.9mm maximum Sketch A (Side or Front Sectional View) Component Rotation A0 Sketch B (Top View) Typical component center line Sketch C (Top View) Component lateral movement SOIC(16lds) Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max B Min Dim C Dim A max Dim D min Dim N DETAIL AA See detail AA W3 13" Diameter Option W2 max Measured at Hub Dimensions are in inches and millimeters Tape Size 16mm Reel Option 13" Dia Dim A 13.00 330 Dim B 0.059 1.5 Dim C 512 +0.020/-0.008 13 +0.5/-0.2 Dim D 0.795 20.2 Dim N 4.00 100 Dim W1 0.646 +0.078/-0.000 16.4 +2/0 Dim W2 0.882 22.4 Dim W3 (LSL-USL) 0.626 – 0.764 15.9 – 19.4 July 1999, Rev. B SOIC-16 Tape and Reel Data and Package Dimensions, continued SOIC-16 (FS PKG Code S3) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.1437 October 1999, Rev. A1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ DISCLAIMER ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™ UHC™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.