NM25W040EN

NM25C040 4K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus) March 1999 NM25C040 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) General Description The NM25C040 is a 4096-bit CMOS EEPROM with an SPI compatible serial interface. The NM25C040 is designed for data storage in applications requiring both non-volatile memory and insystem data updates. This EEPROM is well suited for applications using the 68HC11 series of microcontrollers that support the SPI interface for high speed communication with peripheral devices via a serial bus to reduce pin count. The NM25C040 is implemented in Fairchild Semiconductor’s floating gate CMOS process that provides superior endurance and data retention. The serial data transmission of this device requires four signal lines to control the device operation: Chip Select (CS), Clock (SCK), Data In (SI), and Serial Data Out (SO). All programming cycles are completely self-timed and do not require an erase before WRITE. BLOCK WRITE protection is provided by programming the STATUS REGISTER with one of four levels of write protection. Additionally, separate WRITE enable and WRITE disable instructions are provided for data protection. Hardware data protection is provided by the WP pin to protect against inadvertent programming. The HOLD pin allows the serial communication to be suspended without resetting the serial sequence. Features s 2.1 MHz clock rate @ 2.7V to 5.5V s 4096 bits organized as 512 x 8 s Multiple chips on the same 3-wire bus with separate chip select lines s Self-timed programming cycle s Simultaneous programming of 1 to 4 bytes at a time s Status register can be polled during programming to monitor READY/BUSY s Write Protect (WP) pin and write disable instruction for both hardware and software write protection s Block write protect feature to protect against accidental writes s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP Block Diagram CS HOLD SCK SI Instruction Register Instruction Decoder Control Logic and Clock Generators VCC VSS WP Address Counter/ Register Program Enable VPP EEPROM Array 4096 Bits (512 x 8) High Voltage Generator and Program Timer Decoder 1 of 512 Read/Write Amps Data In/Out Register 8 Bits Data Out Buffer SO Non-Volatile Status Register DS012401-1 © 1999 Fairchild Semiconductor Corporation NM25C040 Rev. D.1 1 www.fairchildsemi.com NM25C040 4K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus) Connection Diagram Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8) CS SO WP VSS 1 2 NM25C040 3 4 6 5 SCK SI DS012401-2 8 7 VCC HOLD Top View See Package Number N08E (N), M08A (M8), and MTC08 (MT8) Pin Names CS SO WP VSS SI SCK HOLD VCC Chip Select Input Serial Data Output Write Protect Ground Serial Data Input Serial Clock Input Suspends Serial Data Power Supply Ordering Information NM 25 C XX LZ E XX Package Letter N M8 MT8 None V E Blank L LZ 040 C W Interface 25 NM Description 8-pin DIP 8-pin SO 8-pin TSSOP 0 to 70°C -40 to +125°C -40 to +85°C 4.5V to 5.5V 2.7V to 4.5V 2.7V to 4.5V and