RFD16N05L

RFD16N05L, RFD16N05LSM Data Sheet December 2003 16A, 50V, 0.047 Ohm, Logic Level, N-Channel Power MOSFETs These are N-Channel logic level power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09871. Features • 16A, 50V • rDS(ON) = 0.047Ω • UIS SOA Rating Curve (Single Pulse) • Design Optimized for 5V Gate Drives • Can be Driven Directly from CMOS, NMOS, TTL Circuits • Compatible with Automotive Drive Requirements • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Majority Carrier Device • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PART NUMBER RFD16N05L RFD16N05LSM PACKAGE TO-251AA TO-252AA BRAND RFD16N05L RFD16N05LSM Symbol D NOTE: When ordering, include the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RFD16N05LSM9A G S Packaging JEDEC TO-251AA SOURCE DRAIN GATE DRAIN (FLANGE) JEDEC TO-252AA DRAIN (FLANGE) GATE SOURCE ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD16N05L, RFD16N05LSM Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 50 50 16 45 ±10 60 0.48 -55 to 150 300 260 UNITS V V A A V W W/oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250mA, VGS = 0V, Figure 10 VGS = VDS, ID = 250mA, Figure 9 VDS = 40V, VGS = 0V TC = 150oC MIN 50 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 40V, ID = 16A, RL = 2.5Ω Figures 17, 18 TYP 14 30 42 14 MAX 2 1 50 100 0.047 0.056 60 100 80 45 3 2.083 100 UNITS V V µA µA nA Ω Ω ns ns ns ns ns ns nC nC nC oC/W oC/W Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS rDS(ON) VGS = ±10V, VDS = 0V ID = 16A, VGS = 5V ID = 16A, VGS = 4V Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(5) Qg(TH) RθJC RθJA VDD = 25V, ID = 8A, VGS = 5V, RGS = 12.5Ω Figures 15, 16 Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width ≤300ms, Duty Cycle ≤2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. SYMBOL VSD trr ISD = 16A ISD = 16A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 15 0.8 20 0.6 0.4 10 5 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 102 IAS, AVALANCHE CURRENT (A) TC = 25oC TJ = MAX RATED ID MAX CONTINUOUS 102 Idm STARTING TJ = 25oC STARTING TJ = 150oC ID, DRAIN CURRENT (A) 10 OPERATION IN THIS AREA LIMITED BY rDS(ON) 1 DC 10 If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1] 1 0.01 0.10 1 tAV, TIME IN AVALANCHE (ms) 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 10 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA (SINGLE PULSE UIS SOA) 45 IDS, DRAIN TO SOURCE CURRENT (A) VGS = 10V VGS = 4V VGS = 5V 30 IDS(ON), DRAIN TO SOURCE ON CURRENT (A) TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 45 VDS = 15V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 30 VGS = 3V 15 15 VGS = 2V 0 0 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 7.5 0 0 1.5 3.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V) 6.0 FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified (Continued) 1.4 NORMALIZED DRAIN TO SOURCE ON RESISTANCE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 4 5 6 7 VGS, GATE TO SOURCE VOLTAGE (V) ID = 16V VDS = 15V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 2.5 ID = 16A 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 1.5 1.0 0.5 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.4 1.3 NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.1 1.0 0.9 0.8 0.7 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA VGS = VDS 1.4 ID = 250µA 1.2 1.0 0.8 0.6 0.6 -50 0 50 100 150 200 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION TEMPERATURE 2000 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VDS , DRAIN TO SOURCE VOLTAGE (V) 1600 C, CAPACITANCE (pF) CISS CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD COSS CRSS 0 0 5 10 15 20 25 37.5 8 1200 6 25 800 GATE SOURCE VOLTAGE 4 12.5 2 DRAIN SOURCE VOLTAGE 0 I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (µs) I G ( REF ) 80 -----------------------I G ( ACT ) 0 400 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 VGS , GATE TO SOURCE VOLTAGE (V) VGS = 0V f = 1MHz 50 RL = 3.125Ω, VGS = 5V IG(REF) = 0.60mA PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS V = 0.75 BV VDD = BVDSS VDD = 0.50 BVDSS VDD = BVDSS DD DSS VDD = 0.25 BVDSS 10 RFD16N05L, RFD16N05LSM Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01Ω 0 tAV FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2µF 50kΩ 0.3µF G DUT 0 IG(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM PSPICE Electrical Model .SUBCKT RFD16N05L 2 1 3 ; REV 4/8/92 Ca 12 8 3.33e-9 Cb 15 14 3.11e-9 Cin 6 8 1.21e-9 DPLCAP 5 LDRAIN RSCL1 RSCL2 + 51 5 ESCL 51 50 RDRAIN 16 VTO 6 + 21 MOS1 RIN CIN 8 RSOURCE 7 LSOURCE 3 SOURCE DBREAK Dbody 7 5 DBDMOD Dbreak 5 11 DBKMOD Dplcap 10 5 DPLCAPMOD Ebreak 11 7 17 18 70.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evto 20 6 18 8 1 IT 8 17 1 GATE 10 DRAIN 2 ESG + EVTO + 18 8 6 8 11 17 EBREAK 18 MOS2 + DBODY - Lgate 1 9 1.38e-9 Ldrain 2 5 1.0e-12 Lsource 3 7 1.0e-9 Mos1 16 6 8 8 MOSMOD M=0.99 Mos2 16 21 8 8 MOSMOD M=0.01 Rin 6 8 1e9 Rbreak 17 18 RBKMOD 1 Rdrain 5 16 RDSMOD 27.38e-3 Rgate 9 20 2.98 Rsource 8 7 RDSMOD 0.614e-3 Rvto 18 19 RVTOMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 8 19 DC 1 Vto 21 6 0.448 1 LGATE 9 20 RGATE S1A 12 13 8 S1B CA EGS + 6 8 S2A 14 13 S2B 13 CB + EDS 5 8 14 IT 15 17 RBREAK 18 RVTO 19 VBAT + .MODEL DBDMOD D (IS=1.34e-13 RS=1.21e-2 TRS1=1.64e-3 TRS2=2.59e-6 +CJO=1.13e-9 TT=4.14e-8) .MODEL DBKMOD D (RS=8.82e-2 TRS1=-2.01e-3 TRS2=7.32e-10) .MODEL DPLCAPMOD D (CJO=0.522e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=2.054 KP=24.73 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.01e-3 TC2=5.21e-8) .MODEL RDSMOD RES (TC1=3.66e-3 TC2=1.46e-5) .MODEL RVTOMOD RES (TC1=-1.81e-3 TC2=1.41e-6) .MODEL S1AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-4.25 VOFF=-2.25) .MODEL S1BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-2.25 VOFF=-4.25) .MODEL S2AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-0.65 VOFF=4.35) .MODEL S2BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=4.35 VOFF=-0.65) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOSTM I2C™ TM EnSigna ImpliedDisconnect™ FACT™ ISOPLANAR™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I6