RMPA1765

RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module October 2006 RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Features ■ Single positive-supply operation and low power and ■ ■ ■ ■ ■ General Description The RMPA1765 power amplifier module (PAM) is designed for Korean CDMA, CDMA2000-1X, WCDMA, and HSDPA personal communications system (PCS) applications. The 2 stage PAM is internally matched to 50 Ohms to minimize the use of external components and features a low-power mode to reduce standby current and DC power consumption during peak phone usage. High power-added efficiency and excellent linearity are achieved using Fairchild RF’s InGaP Heterojunction Bipolar Transistor (HBT) process. shutdown modes 38% CDMA/WCDMA efficiency at +28 dBm average output power Compact lead-free compliant LCC package3.0 x 3.0 x 1.0mm with industry standard pinout Internally matched to 50 Ohms and DC blocked RF input/output. Meets CDMA2000-1XRTT/WCDMA performance requirements Meets HSDPA performance requirements Device Functional Block Diagram (Top View) PA MODULE Vcc1 RF IN Vmode Vref 1 2 3 4 Input Match MMIC Output Match 8 7 6 5 Vcc2 RF OUT GND GND DC Bias Control (paddle ground on package bottom) ©2005 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com RMPA1765 Rev. E RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Absolute Maximum Ratings(1) Symbol Vcc1, Vcc2 Vref Vmode Pin Tstg Parameter Supply Voltages Reference Voltage Power Control Voltage RF Input Power Storage Temperature Value 5.0 2.6 to 3.5 3.5 +10 -55 to +150 Units V V V dBm °C Note: 1. No permanent damage with one parameter set at extreme limit. Other parameters set to typical values. Electrical Characteristics(1) Symbol f SSg Gp Po PAEd Parameter Operating Frequency Small-Signal Gain Power Gain Linear Output Power PAEd (digital) @ +28dBm PAEd (digital) @ +16dBm PAEd (digital) @ +16dBm Min. Typ. Max. Units 1720 26 28 26 28 16 38 9 25 490 130 -50 -52 -60 -68 1780 MHz dB dB dB dBm dBm % % % mA mA dBc dBc dBc dBc Po = 0dBm Comments CDMA OPERATION Po = +28dBm; Vmode = 0V Po = +16dBm; Vmode = 2.0V Vmode = 0V Vmode ≥ 2.0V Vmode = 0V Vmode ≥ 2.0V Vmode ≥ 2.0V, Vcc = 1.4V Po = +28dBm, Vmode = 0V Po = +16dBm, Vmode = 2.0V Po = +28dBm; Vmode = 0V Po = +16dBm; Vmode = 2V Po = +28dBm; Vmode = 0V, IS-95 Po = +16dBm; Vmode = 2V Itot High Power Total Current Low Power Total Current Adjacent Channel Power Ratio ACPR1 ACPR2 ±1.25MHz Offset ±2.25MHz Offset GENERAL CHARACTERISTICS VSWR NF Rx No 2fo-5fo S Input Impedance Noise Figure Receive Band Noise Power Harmonic Suppression Spurious Outputs (2)(3) 2.0:1 4 -139 -30 -60 10:1 -30 45 5 1 8 5 85 °C mA mA µA Vmode ≥ 2.0V Po < +28dBm No applied RF signal. dB dBm/ Hz dBc dBc Po ≤ +28dBm; 1840MHz to 1870MHz Po ≤ +28dBm Load VSWR ≤ 5.0:1 No permanent damage. Ruggedness w/ Load Mismatch(3) Tc Iccq Iref Icc(off) Case Operating Temperature Quiescent Current Reference Current Shutdown Leakage Current DC CHARACTERISTICS Notes: 1. All parameters met at Tc = +25°C, Vcc = +3.4V, Vref = 2.85V, f = 1750 MHz and load VSWR ≤ 1.2:1, unless otherwise noted. 2. All phase angles. 3. Guaranteed by design. 2 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Performance Data RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm 33.0 32.0 31.0 30.0 RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm 43.0 42.0 41.0 40.0 Gain (dB) 29.0 28.0 27.0 26.0 25.0 24.0 23.0 1720 1740 1760 1780 PAE (%) 39.0 38.0 37.0 36.0 35.0 34.0 33.0 1720 1740 1760 1780 Frequency (MHz) Frequency (MHz) RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm -40.0 -42.0 -44.0 -46.0 -48.0 -50.0 -52.0 -54.0 -56.0 -58.0 -60.0 1720 1740 1760 1780 -50.0 -52.0 -54.0 -56.0 -58.0 -60.0 -62.0 -64.0 -66.0 -68.0 -70.0 RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm ACPR1 (dBc) ACPR2 (dBc) 1720 1740 1760 1780 Frequency (MHz) Frequency (MHz) 3 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Efficiency Improvement Applications In addition to high-power/low-power bias modes, the efficiency of the PA module can be significantly increased at backed-off RF power levels by dynamically varying the supply voltage (Vcc) applied to the amplifier. Since mobile handsets and power amplifiers frequently operate at 10-20 dB back-off, or more, from maximum rated linear power, battery life is highly dependent on the DC power consumed at antenna power levels in the range of 0 to +16dBm. The reduced demand on transmitted RF power allows the PA supply voltage to be reduced for improved efficiency, while still meeting linearity requirements for CDMA modulation with excellent margin. High-efficiency DC-DC converters are now available to implement switched-voltage operation. With the PA module in low-power mode (Vmode = +2.0V) at+16dBm output power and supply voltages reduced from 3.4V nominal down to 1.2V, power-added efficiency is more than doubled from 9.5 percent to nearly 25 percent (Vcc = 1.2V) while maintaining a typical ACPR1 of –52dBc and ACPR2 of less than –61dBc. Operation at even lower levels of Vcc supply voltage are possible with a further restriction on the maximum RF output power. Recommended Operating Conditions Symbol f Vcc1, Vcc2 Vref Vmode Pout Tc Parameter Operating Frequency Supply Voltage Reference Voltage (operating) (shutdown) Bias Control Voltage (low-power) (high-power) Linear Output Power (high-power) (low-power) Case Operating Temperature Min. 1720 3.0 2.7 0 1.8 0 Typ. 3.4 2.85 2.0 Max. 1780 4.2 3.1 0.5 3.0 0.5 +28 +16 Units MHz V V V V V dBm dBm °C -30 +85 DC Turn-On Sequence 1) Vcc1 = Vcc2 = 3.4V (typical) 2) Vref = 2.85V (typical) 3) High-Power: Vmode = 0V (Pout > 16dBm) Low-Power: Vmode = 2V (Pout < 16dBm) 4 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Evaluation Board Layout 1 5 6 3 6 5 2 Z XYTT 1765 4 7 5 Materials List Qty 1 2 7 Ref 3 3 2 1 1 A/R A/R Item No. 1 2 3 4 5 5 (Alt) 6 7 7 (Alt) 8 9 Part Number G657691-1 V1 #142-0701-841 #2340-5211TN GRM39X7R102K50V ECJ-1VB1H102K C3216X5R1A335M GRM39Y5V104Z16V ECJ-1VB1C104K SN63 SN96 PC Board Description SMA Connector Terminals Assembly, RMPA1765 1000pF Capacitor (0603) 1000pF Capacitor (0603) 3.3µF Capacitor (1206) 0.1µF Capacitor (0603) 0.1µF Capacitor (0603) Solder Paste Solder Paste Vendor Fairchild Johnson 3M Fairchild Murata Panasonic TDK Murata Panasonic Indium Corp. Indium Corp. Evaluation Board Schematic 3.3 µF Vcc1 SMA1 RF IN Vmode 1000 pF Vref 1000 pF 1 2 1000 pF 8 3.3 µF Vcc2 50 Ohm TRL SMA2 RF OUT 50 Ohm TRL 3 Z XYTT 1765 9 7 4 0.1 µF 5, 6 (package base) 5 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Package Outline TOP VIEW 1 8 2 3.00 +.100 mm SQ. –.050 3 4 Z XYTT 1765 FRONT VIEW 7 6 5 X Z 17 YTT 65 I/O 1 INDICATOR 1.10mm MAX. 4X R.25mm 4 BACK SIDE SOLDER MASK 3 6 2.60mm 2 9 7 8 0.20mm DETAIL A TYP. 0.40mm 0.10mm 1 0.40mm 0.10mm 5 2 0.40mm SEE DETAIL A 1.00mm 1 1.00mm BOTTOM VIEW Signal Descriptions Pin # 1 2 3 4 5 6 7 8 Signal Name Vcc1 RF In Vmode Vref GND GND RF Out Vcc2 RF Input Signal Description Supply Voltage to Input Stage Reference Voltage High-Power/Low-Power Mode Control Reference Voltage Ground Ground RF Output Signal Supply Voltage to Output Stage 6 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Applications Information CAUTION: THIS IS AN ESD SENSITIVE DEVICE. Precautions to Avoid Permanent Device Damage: • Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC and ground contact areas. • Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. • Static Sensitivity: Follow ESD precautions to protect against ESD damage: – A properly grounded static-dissipative surface on which to place devices. – Static-dissipative floor or mat. – A properly grounded conductive wrist strap for each person to wear while handling devices. • General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, and ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. • Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. Device Usage: Fairchild recommends the following procedures prior to assembly. • Assemble the devices within 7 days of removal from the dry pack. • During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30°C • If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure, at 125°C for 24 hours minimum, must be performed. Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. Reflow Profile • Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A maximum heating rate is 3°C/sec. • Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 60-180 seconds at 150-200°C. • Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of inter-metallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 20 seconds. Soldering temperatures should be in the range 255–260°C, with a maximum limit of 260°C. • Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crack-resistant solder joint. The illustration below indicates the recommended soldering profile. Solder Joint Characteristics: Proper operation of this device depends on a reliable void-free attachment of the heat sink to the PWB. The solder joint should be 95% void-free and be a consistent thickness. Rework Considerations: Rework of a device attached to a board is limited to reflow of the solder with a heat gun. The device should be subjected to no more than 15°C above the solder melting temperature for no more than 5 seconds. No more than 2 rework operations should be performed. Recommended Solder Reflow Profile 260 Ramp-Up R ate 3 °C/sec max Peak tem p 260 +0/-5 °C 10 - 20 sec Temperature (°C) 217 200 Time above li quidus temp 60 - 150 sec 150 Preheat, 150 to 200 °C 60 - 180 sec 100 Ramp-Up R ate 3 °C/sec max 50 25 Time 25 °C/sec t o peak tem p 6 mi nutes max Ramp-Do wn Rate 6 °C/sec max Time (Sec) 7 RMPA1765 Rev. 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Around the world.™ The Power Franchise® Programmable Active Droop™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerEdge™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ ScalarPump™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ TinyBoost™ TinyBuck™ TinyPWM™ TinyPower™ TinyLogic® TINYOPTO™ TruTranslation™ UHC® UniFET™ UltraFET® VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production Rev. I21