SCAN18373T

SCAN18373T Transparent Latch with 3-STATE Outputs October 1991 Revised May 2000 SCAN18373T Transparent Latch with 3-STATE Outputs General Description The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). Features s IEEE 1149.1 (JTAG) Compliant s Buffered active-low latch enable s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP (Shrink Small Outline Package) s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products Ordering Code: Order Number SCAN1837TSSC Package Number MS56A Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names AI(0–8), BI(0–8) ALE, BLE AOE1, BOE1 AO(0–8), BO(0–8) Data Inputs Latch Enable Inputs 3-STATE Output Enable Inputs 3-STATE Latch Outputs Description Truth Tables Inputs ALE X H H L AOE1 H L L L Inputs BLE X H H L BOE1 H L L L BI(0–8) X L H X BO(0–8) Z L H BO 0 AI(0–8) X L H X AO(0–8) Z L H AO 0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE © 2000 Fairchild Semiconductor Corporation DS010962 www.fairchildsemi.com SCAN18373T Functional Description The SCAN18373T consists of two sets of nine D-type latches with 3-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs (AI(0–8) or BI(0–8)) enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on the inputs a set-up time preceding the HIGH-to-LOW transition of the Latch Enable. The 3-STATE standard outputs are controlled by the Output Enable (AOE1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Block Diagrams Byte-A www.fairchildsemi.com 2 SCAN18373T Block Diagrams (Continued) Tap Controller Byte-B Note: BSR stands for Boundary Scan Register. 3 www.fairchildsemi.com SCAN18373T Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 MSB → LSB Instruction Code 00000000 10000001 10000010 The INSTRUCTION register is an eight-bit register which captures the value 00111101. The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique 00000011 All Others Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGHZ BYPASS to the SCAN18373T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition Scan Cell TYPE1 Scan Cell TYPE2 www.fairchildsemi.com 4 SCAN18373T Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Scan Chain Definition (42 Bits in Length) 5 www.fairchildsemi.com SCAN18373T Description of Boundary-Scan Circuitry Bit No. Pin Name 41 AOE1 40 ACP 39 AOE 38 BOE1 37 BCP 36 BOE 35 AI0 34 AI1 33 AI2 32 AI3 31 AI4 30 AI5 29 AI6 28 AI7 27 AI8 26 BI0 25 BI1 24 BI2 23 BI3 22 BI4 21 BI5 20 BI6 19 BI7 18 BI8 17 AO0 16 AO1 15 AO2 14 AO3 13 AO4 12 AO5 11 AO6 10 AO7 9 AO8 8 BO0 7 BO1 6 BO2 5 BO3 4 BO4 3 BO5 2 BO6 1 BO7 0 BO8 55 53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32 30 2 4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25 27 26 31 Pin No. 3 54 (Continued) Boundary-Scan Register Definition Index Pin Type Input Input Internal Input Input Internal Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Scan Cell Type TYPE1 TYPE1 TYPE2 TYPE1 TYPE1 TYPE2 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 B–out A–out B–in A–in Control Signals www.fairchildsemi.com 6 SCAN18373T Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Junction Temperature SSOP Storage Temperature ESD (Min) −0.5V to +7.0V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC + 0.5V ±70 mA ±70 mA +140°C −65°C to +150°C 2000V Recommended Operating Conditions Supply Voltage (VCC) SCAN Products Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of SCAN circuits outside databook specifications. 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage (Note 2) VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage (Note 2) 4.5 5.5 4.5 5.5 4.5 5.5 IIN IIN TDI, TMS IOLD IOHD IOZ IOS ICC Maximum Input Leakage Current Maximum Input Leakage Minimum Input Leakage Minimum Dynamic Output Current (Note 3) Maximum Output Leakage Current Output Short Circuit Current Maximum Quiescent Supply Current 5.5 750 820 µA 5.5 5.5 5.5 5.5 5.5 5.5 5.5 TA = +25°C Typ 1.5 1.5 1.5 1.5 2.0 2.0 0.8 0.8 3.15 4.15 2.4 2.4 2.4 2.4 0.1 0.1 0.55 0.55 0.55 0.55 ±0.1 2.8 −385 −160 94 −40 ±0.5 −100 16.0 ±1.0 3.6 −385 −160 94 −40 ±5.0 −100 88 0.1 0.1 0.55 0.55 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 3.15 4.15 2.4 2.4 Units V V V V V V V V µA µA µA µA mA mA µA mA Min µA Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH IOH = −32 mA VIN = VIL or VIH IOH = −24 mA IOUT = 50 µA VIN = VIL or VIH IOL = 64 mA VIN = VIL or VIH IOL = 48 mA VI = VCC, GND VI = VCC VI = GND VI = GND VOLD = 0.8V Max VOHD = 2.0V Min VI (OE) = VIL, VIH VO = 0V VO = Open TDI, TMS = VCC VO = Open TDI, TMS = GND 7 www.fairchildsemi.com SCAN18373T DC Electrical Characteristics Symbol ICCt Parameter Maximum ICC per Input VCC (V) 5.5 5.5 (Continued) TA = +25°C Typ 2.0 2.15 TA = −40°C to +85°C Guaranteed Limits 2.0 2.15 mA mA VI = VCC − 2.1V VI = VCC − 2.1V TDI/TMS Pin, Test One with the Other Floating Units Conditions Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Symbol VOLP VOLV VOHP VOHV VIHD VILD Parameter Maximum HIGH Output Noise (Note 4)(Note 5) Minimum LOW Output Noise (Note 4)(Note 5) Maximum Overshoot (Note 5)(Note 6) Minimum VCC Droop (Note 5)(Note 6) Minimum HIGH Dynamic Input Voltage Level (Note 6)(Note 7) Maximum LOW Dynamic Input Voltage Level (Note 6)(Note 7) VCC (V) 5.0 5.0 5.0 5.0 5.5 5.5 Typ 1.0 −0.6 VOH + 1.0 VOH − 1.0 1.6 1.4 1.5 −1.2 VOH + 1.5 VOH − 1.8 2.0 0.8 2.0 0.8 TA = +25°C TA = −40°C to +85°C Guaranteed Limits Units V V V V V V Note 4: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched LOW and one output held LOW. Note 5: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched HIGH and one output held HIGH. Note 6: Worst case package. Note 7: Maximum number of data inputs (n) switching. (n−1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). AC Electrical Characteristics Normal Operation VCC Symbol Parameter (V) (Note 8) tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. TA= +25°C CL = 50 pF Min 2.5 2.5 2.5 2.5 1.5 1.5 2.0 2.0 Typ Max 9.0 9.0 10.0 10.5 9.0 9.5 10.9 9.0 TA= −40°C to +85°C CL = 50 pF Min 2.5 2.5 2.5 2.5 1.5 1.5 2.0 2.0 Max 9.8 9.8 10.5 11.3 9.5 10.0 11.9 9.7 ns ns ns ns Units Propagation Delay, D to Q Propagation Delay, LE to Q Disable Time Enable Time 5.0 5.0 5.0 5.0 www.fairchildsemi.com 8 SCAN18373T AC Operating Requirements Normal Operation VCC Symbol Parameter (V) (Note 9) tS tH tW Setup Time, H or L Data to LE Hold Time, H or L LE to Data LE Pulse Width Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units Guaranteed Minimum 3.0 1.5 5.0 3.0 1.5 5.0 ns ns ns 5.0 5.0 5.0 AC Electrical Characteristics Scan Test Operation VCC Symbol Parameter (V) (Note 10) tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tPLH, tPHL tPLH, tPHL tPLH, tPHL Propagation Delay TCK to TDO Disable Time TCK to TDO Enable Time TCK to TDO Propagation Delay TCK to Data Out during Update-DR State Propagation Delay TCK to Data Out during Update-IR State Propagation Delay TCK to Data Out during Test Logic Reset State tPLZ, tPHZ tPLZ, tPHZ tPLZ, tPHZ Propagation Delay TCK to Data Out during Update-DR State Propagation Delay TCK to Data Out during Update-IR State Propagation Delay TCK to Data Out during Test Logic Reset State tPZL, tPZH tPZL, tPZH tPZL, tPZH Propagation Delay TCK to Data Out during Update-DR State Propagation Delay TCK to Data Out during Update-IR State Propagation Delay TCK to Data Out during Test Logic Reset State Note 10: Voltage Range 5.0 is 5.0V ± 0.5V. Note: All propagation delays involving TCK are measured from the falling edge of TCK. TA= +25°C CL = 50 pF Min 3.5 3.5 2.5 2.5 3.0 3.0 5.0 Typ Max 13.2 13.2 11.5 11.5 14.5 14.5 18.0 18.0 18.6 18.6 19.9 19.9 16.4 16.4 19.5 19.5 19.9 19.9 18.9 18.9 22.4 22.4 23.8 23.8 TA = −40°C to +85°C CL = 50 pF Min 3.5 3.5 2.5 2.5 3.0 3.0 5.0 5.0 5.0 5.0 5.5 5.5 4.0 4.0 5.0 5.0 5.0 5.0 5.0 5.0 6.5 6.5 7.0 7.0 Max 14.5 14.5 11.9 11.9 15.8 15.8 19.8 19.8 20.2 20.2 21.5 ns 21.5 18.2 18.2 20.8 20.8 21.5 ns 21.5 20.9 20.9 24.2 24.2 25.7 ns 25.7 ns ns ns ns ns ns ns ns ns Units 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.5 5.0 5.5 4.0 5.0 4.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 6.5 5.0 6.5 7.0 5.0 7.0 9 www.fairchildsemi.com SCAN18373T AC Operating Requirements Scan Test Operation VCC Symbol Parameter (V) (Note 11) tS tH tS tH tS Setup Time, Data to TCK (Note 12) Hold Time, TCK to Data (Note 12) Setup Time, H or L AOE1, BOE1 to TCK (Note 13) Hold Time, H or L TCK to AOE1, BOE1 (Note 13) Setup Time, H or L Internal AOE, BOE, to TCK (Note 14) tH Hold Time, H or L TCK to Internal AOE, BOE (Note 14) tS tH tS tH tS tH tW Setup Time ALE, BLE (Note 15) to TCK Hold Time TCK to ALE, BLE (Note 15) Setup Time, H or L TMS to TCK Hold Time, H or L TCK to TMS Setup Time, H or L TDI to TCK Hold Time, H or L TCK to TDI Pulse Width TCK H L fMAX Tpu Tdn Maximum TCK Clock Frequency Wait Time, Power Up to TCK Power Down Delay 5.0 5.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 15.0 5.0 25 100 100 15.0 5.0 25 100 100 MHz ns ms ns 3.0 3.5 8.0 2.0 4.0 4.5 3.0 3.5 8.0 2.0 4.0 4.5 ns ns ns ns ns ns 5.0 3.0 3.0 ns 5.0 3.0 3.0 ns 5.0 5.0 5.0 5.0 TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units Guaranteed Minimum 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 ns ns ns ns Note 11: Voltage Range 5.0 is 5.0V ± 0.5V. Note 12: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 13: Timing pertains to BSR 38 and 41 only. Note 14: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note 15: Timing pertains to BSR 37 and 40 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK. www.fairchildsemi.com 10 SCAN18373T Extended AC Electrical Characteristics T A = 2 5 °C VCC = 5.0V CL = 50 pF Symbol Parameter 18 Outputs Switching (Note 16) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 20) tOSLH (Note 20) Pin to Pin Skew HL Data to Output Pin to Pin Skew LH Data to Output Output Disable Time Propagation Delay Latch Enable to Output Propagation Delay Data to Output Output Enable Time 3.0 3.0 3.0 3.0 2.5 2.5 2.0 2.0 0.5 0.5 Typ Max 12.0 12.8 11.5 11.5 10.5 12.5 10.5 10.5 1.0 1.0 4.0 4.0 4.0 4.0 TA = −40°C to +85°C VCC = 5.0V ± 0.5V CL = 250 pF (Note 17) Min Max 13.5 16.0 13.0 14.5 (Note 18) (Note 19) 1.0 1.0 ns ns ns ns ns ns Units Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 17: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 18: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 19: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 20: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH. Capacitance Symbol CIN COUT CPD Parameter Input Pin Capacitance Output Pin Capacitance Power Dissipation Capacitance Typ 4.0 13.0 34.0 Units pF pF pF Conditions VCC = 5.0V VCC = 5.0V VCC = 5.0V 11 www.fairchildsemi.com SCAN18373T Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 12 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com