SG5842JASY

SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller December 2009 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Features Green-Mode PWM Controller Low Startup Current: 14µA Low Operating Current: 4mA Programmable PWM Frequency with Hopping (SG5842JA) Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Synchronized Slope Compensation Leading-Edge Blanking (LEB) Constant Output Power Limit Totem-Pole Output with Soft Driving VDD Over-Voltage Protection (OVP) Programmable Over-Temperature Protection (OTP) Internal Latch Circuit (OTP, OVP) Internal Open-Loop Protection VDD Under-Voltage Lockout (UVLO) GATE Output Maximum Voltage Clamp: 18V Description The highly integrated SG5842A/JA series of PWM controllers provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. To further reduce power consumption, SG5842A/JA is manufactured using the BiCMOS process. This allows a low startup current, around 14µA, and an operating current of only 4mA. As a result, a large startup resistance can be used. The SG5842A/JA built-in synchronized slope compensation achieves stable peak-current-mode control. SG5842JA integrates a frequency-hopping function that helps reduce EMI emission of a power supply with minimum line filters. SG5842A/JA provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. PWM output is disabled until VDD drops below the UVLO lower limit, then the controller starts again. As long as VDD exceeds about 24V, the internal OVP circuit is triggered. An external NTC thermistor can be applied for overtemperature protection. SG5842A/JA is available in an 8-pin DIP or SOP package. Applications General-purpose switch-mode power supplies and flyback power converters, including: Notebook Power Adapters Open-Frame SMPS © 2007 Fairchild Semiconductor Corporation SG5842A/SG5842JA • Rev. 1.4.3 www.fairchildsemi.com SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Ordering Information Part Number SG5842JASZ SG5842JADZ SG5842JASY SG5842ASZ (Preliminary) SG5842ASY (Preliminary) Operating Temperature Range -40°C to +105°C -40°C to +105°C -40°C to +105°C -40°C to +105°C -40°C to +105°C Eco Status RoHS RoHS Green RoHS Green Package 8-Pin Small Outline Package (SOP) 8-Pin Dual Inline Package (DIP) 8-Pin Small Outline Package (SOP) 8-Pin Small Outline Package (SOP) 8-Pin Small Outline Package (SOP) OTP Latch Yes Yes Yes Yes Yes OVP Frequency Latch Hopping Yes Yes Yes Yes Yes Yes Yes Yes No No For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Application Diagram Figure 1. Application Diagram © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 2 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Block Diagram Figure 2. Function Block Diagram Marking Information H: J = with Frequency Hopping Null = without Frequency Hopping T: D = DIP, S = SOP P: Z = Lead Free Null = Regular Package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location SG5842HATP XXXXXXXXYWWV Marking for SG5842JASZ (pb-free) Marking for SG5842JADZ (pb-free) Marking for SG5842ASZ (pb-free) Marking for SG5842ADZ (pb-free) ZXYTT SG5842HA TPM Marking for SG5842JASY (green-compound) Marking for SG5842ASY (green-compound) F- Fairchild Logo Z- Plant Code X- 1 Digit Year Code Y- 1 Digit week Code TT: 2 Digits Die Run Code T: Package Type (S=SOP, D=DIP) P: Y: Green Package M: Manufacture Flow Code Figure 3. Top Mark © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 3 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # 1 2 Name GND FB Ground Description The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal from this pin and the current-sense signal from Pin 6. If FB voltage exceeds the threshold, the internal protection circuit disables PWM output after a predetermined delay time. For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since the startup current requirement is very small, a large startup resistance can be used to minimize power loss. A resistor connected from the RI pin to GND provides a constant current source. This determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor results in a 65KHz center PWM frequency. For over-temperature protection. An external NTC thermistor is connected from this pin to the GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below a fixed limit, PWM output is latched off. Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. Power supply. The internal protection circuit disables PWM output if VDD is over-voltage. The totem-pole output driver for the power MOSFET, which is internally clamped below 18V. 3 4 VIN RI 5 6 7 8 RT SENSE VDD GATE © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 4 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VVDD VVIN VFB VSENSE VRT VRI PD ΘJA TJ TSTG TL ESD Supply Voltage Input Terminal Input Voltage to FB Pin (1) Parameter Min. Max. 30 30 Unit V V V V V V mW °C/W °C °C °C KV -0.3 -0.3 -0.3 -0.3 7.0 7.0 7.0 7.0 DIP 800 SOP 400 DIP 82.5 SOP 141 +125 +150 +260 3 1 Input Voltage to SENSE Pin Input Voltage to RT Pin Input Voltage to RI Pin Power Dissipation (TA < 50°C ) Thermal Resistance (Junction-to-Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or Infrared, 10 Seconds) Electrostatic Discharge Capability Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 -40 -55 Notes: 1. All voltage values, except differential voltage, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Min. -20 Max. +85 Unit °C © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 5 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Electrical Characteristics VDD=15V and TJ=TA= -40~125°C, unless otherwise noted. Symbol VDD Section VDD-OP VDD-ON VDD-OFF IDD-ST IDD-OP VDD-OVP tD-OVP IDD-H RI Section RINOR RIMAX RIMIN Parameter Continuously Operating Voltage Start Threshold Voltage Minimum Operation Voltage Startup Current Operating Supply Current VDD Over-Voltage Protection VDD Over-Voltage Protection Debounce Time Holding Current After OVP/OTP Latchup RI Operating Range Maximum RI Value for Protection Minimum RI Value for Protection Center Frequency Hopping Range Conditions Min. Typ. Max. 20 Units V V V µA mA V µs 15.5 9.5 VDD=VDD-ON–0.16V VDD=15V, RI=26KΩ, GATE=OPEN 23.2 RI=26KΩ VDD=5V 40.0 16.5 10.5 14 4 24.2 100 52.5 17.5 11.5 30 5 25.2 65.0 µA 15.5 230 10 36.0 KΩ KΩ KΩ Oscillator Section Normal PWM Frequency Hopping Period Green-Mode Minimum Frequency Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation FB Input to Current Comparator Attenuation Input Impedance Output High Voltage FB Open-Loop Trigger Level FB Open-Loop Protection Delay Green-Mode Entry FB Voltage Green-Mode Ending FB Voltage RI=26KΩ RI=26KΩ RI=26KΩ FB Pin Open RI=26KΩ RI=26KΩ SG5842JA Only RI=26KΩ SG5842JA Only RI=26KΩ VDD=11.5V to 20V TA=-20 to 85°C 62 ±3.7 3.9 18 65 ±4.2 4.4 22 68 KHz ±4.7 4.9 25 5 5 ms KHz % % fOSC tHOP fOSC-G fDV fDT Feedback Input Section AV ZFB VFB-OPEN VFB-OLP tD-OLP VFB-N VFB-G 1/4.5 4 5.5 5.0 50 1.9 56 2.1 VFB-N-0.5 5.4 62 2.3 1/4.0 1/3.5 7 V/V KΩ V V ms V V Continued on the following page… © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 6 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) VDD= 15V and TJ=TA= -40~125°C, unless otherwise noted. Figure 5. VFB vs. PWM Frequency Symbol Current Sense Section ZSENSE VSTHFL VSTHVA DCYSAW tPD tLEB DCYMAX VGATE-L VGATE-H tr tf IO VGATECLAMP Parameter Input Impedance Current Limit Flatten Threshold Voltage Current Limit Valley Threshold Voltage Duty Cycle of SAW Limit Propagation Delay to GATE Output Leading-Edge Blanking Time Maximum Duty Cycle Output Voltage Low Output Voltage High Rising Time Falling Time Peak Output Current Gate Output Clamping Voltage Output Current of RT Pin Over-Temperature Protection Threshold Voltage Over-Temperature Debounce Conditions Min. Typ. 12 Max. Units KΩ 0.85 VSTHFL–VSTHVA Maximum Duty Cycle RI=26KΩ RI=26KΩ GATE Section 60 VDD=15V, IO=50mA VDD=12.5V, IO=-50mA VDD=15V, CL=1nF VDD=15V, CL=1nF VDD=15V, GATE=6V VDD=20V RT Section RI=26KΩ 67 1.015 RI=26KΩ 60 7.5 150 30 230 200 0.90 0.22 45 150 270 65 0.95 V V % 200 350 70 1.5 ns ns % V V ns ns mA 250 50 350 90 18 70 1.050 100 19 73 1.085 140 V µA V µs IRT VRTTH tD-OTP © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 7 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Performance Characteristics 30 26 5.0 4.5 18 14 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 IDD-OP (mA) IDD-ST (µA) 22 4.0 3.5 3.0 2.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature °C Temperature °C Figure 6. Startup Current (IDD-ST) vs. Temperature 15 12 Figure 7. Operating Supply Current (IDD-OP) vs. Temperature 17.5 17.0 VDD-ON (V) IDD-OP (mA) 9 GATE=1000pF 6 3 16.5 16.0 GATE=OPEN 0 12 13 14 15 16 17 18 19 20 21 22 23 24 15.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 VDD Voltage (V) Temperature °C Figure 8. Operation Current (IDD-OP) vs. VDD Operation 11.5 Figure 9. Start Threshold (VDD-ON) vs. Temperature 68 67 11.0 VDD-OFF (V) 10.5 fOSC (Khz) -40 -25 -10 5 20 35 50 65 80 95 110 125 66 65 64 63 10.0 9.5 62 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature °C Temperature °C Figure 10. Minimum Operating Voltage (VDD-OFF) vs. Temperature Figure 11. PWM Frequency (fOSC) vs. Temperature © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 8 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Performance Characteristics (Continued) 70 68 1.085 1.075 1.065 DCYmax (%) 66 64 62 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 VRTTH (V) 1.055 1.045 1.035 1.025 1.015 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature °C Temperature °C Figure 12. Maximum Duty Cycle (DCYmax) vs. Temperature Figure 13. Trigger Voltage for Over-Temperature Protection (VRTTH) vs. Temperature 73 72 IRT (µA) 71 70 69 68 67 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature °C Figure 14. Output Current of RT Pin (IRT) vs. Temperature © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 9 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Functional Description Startup Current The typical startup current is only 14µA, which allows a high-resistance, low-wattage startup resistor to be used to minimize power loss. A 1.5MΩ/0.25W startup resistor and a 10µF/25V VDD hold-up capacitor are sufficient for an AC/DC adapter with a universal input range. Under-Voltage Lockout (UVLO) The turn-on/turn-off thresholds are fixed internally at 16.5V/10.5V. To enable a SG5842A/JA controller during startup, the hold-up capacitor must first be charged to 16.5V through the startup resistor. The hold-up capacitor continues to supply VDD before energy can be delivered from the auxiliary winding of the main transformer. VDD must not drop below 10.5V during this startup process. This UVLO hysteresis window ensures that the hold-up capacitor can adequately supply VDD during startup. Operating Current The required operating current has been reduced to 4mA. This results in higher efficiency and reduces the VDD hold-up capacitance requirement. Green-Mode Operation The proprietary green-mode function provides off-time modulation to continuously decrease the PWM frequency under light-load conditions. To avoid acoustic noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function dramatically reduces power consumption under light-load and zeroload conditions. Power supplies using this controller can meet even the strictest international standby power regulations. Gate Output / Soft Driving The SG5842A/JA BiCMOS output stage is a fast totempole gate driver. Cross-conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect the power MOSFET transistors from harmful over-voltage gate signals. A soft-driving waveform is implemented to minimize EMI. Slope Compensation The sensed voltage across the current sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. The built-in slope compensation function improves power supply stability and prevents peak-current-mode control from causing sub-harmonic oscillations. Within every switching cycle, the SG5842A/JA controller produces a positively sloped, synchronized ramp signal. Oscillator Operation A resistor connected from the RI pin to the GND pin generates a constant current source for the controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor, RI, results in a corresponding 65KHz PWM frequency. The relationship between RI and the switching frequency is: fPWM = 1690 (KHz) RI (KΩ ) (1) Constant Output Power Limit W hen the SENSE voltage across the sense resistor, RS, reaches the threshold voltage, around 0.85V; the output GATE drive is turned off after a small delay, tPD. This delay introduces additional current proportional to tPD • VIN / LP. The delay is nearly constant regardless of the input voltage VIN. Higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for a wide AC input range, a sawtooth power-limiter (saw limiter) is designed to solve the unequal power-limit problem. The saw limiter is designed as a positive ramp signal (VLIMIT_RAMP) fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at lowline inputs. The range of the PWM oscillation frequency is designed as 47KHz ~ 109KHz. SG5842JA also integrates a frequency hopping function internally. The frequency variation ranges from around 62KHz to 68KHz for a center frequency of 65KHz. The frequency hopping function helps reduce EMI emission of a power supply with minimum line filters. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs at the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate drive. VDD Over-Voltage Protection (OVP) VDD over-voltage protection is built in to prevent damage due to abnormal conditions. Once the VDD voltage is over the VDD over-voltage protection voltage (VDD-OVP) and lasts for tD-OVP, the PWM pulse is latched off. The PWM pulses stay latched off until the power supply is unplugged from the mains outlet. © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 10 SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller Functional Description (Continued) Limited Power Control The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold longer than tDOLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing. Thermal Protection An external NTC thermistor can be connected from the RT pin to ground. A fixed current, IRT, is sourced from the RT pin. Because the impedance of the NTC decreases at high temperatures, when the voltage of the RT pin drops below 1.05V, PWM output is latched off. The RT pin output current is related to the PWM frequency programming resistor RI. t D - OLP (ms) = 2 . 154 × R I (K Ω ) (2) When VDD goes below the turn-off threshold (eg. 10.5V), the controller is totally shut down. VDD is charged up to the turn-on threshold voltage of 16.5V through the startup resistor until PWM output is restarted. This protection feature remains activated as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. Noise Immunity Noise from the current sense or the control signal may cause significant pulse width jitter, particularly in continuous-conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoid long PCB traces and component leads. Compensation and filter components should be located near the SG5842A/JA. Increasing the power-MOS gate resistance is advised. Protection Latch Circuit The built-in latch function provides a versatile protection feature that does not require external components (see ordering information for a detailed description). To reset the latch circuit, disconnect the AC line voltage of the power supply. © 2007 Fairchild Semiconductor Corporation SG5842A/SG582JA • Rev. 1.4.3 www.fairchildsemi.com 11 SG5842A/JA — Highly Integrated Green-Mode PWM Controller Reference Circuit 2 Q1 1 2 4 2 4 L1 VZ1 C1 L2 C2 4 1 2 C4 TR1 1 3 1 3 3 + C3 1 R3 2 2 D3 + C8 R6 C6 R4 C7 + T1 3 2 1 L3 2 1 Vo+ D1 CN1 1 2 3 BD1 C5 R1 R5 1 1 1 D2 2 2 D4 R2 R7 2 U1 1 2 3 4 R9 GND GATE FB VDD 8 7 6 5 R11 R10 C11 THER2 C9 2 + R8 1 R16 1 R12 3 Q2 VIN SENSE RI RT SG5842A/JA 1 4 U2 1 R13 3 K2 C10 R14 R15 A U3 R VO+ Figure 15. Reference Circuit BOM Reference BD1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 F1 L1 L2 L3 Q1 Component BD 4A/600V XC 0.68µF/300V XC 0.1µF/300V CC 0.01µF/500V EC 120µ/400V YC 222p/250V CC 1000pF/100V EC 1000µF/25V EC 470µF/25V EC 10µF/50V CC 222pF/50V CC 470pF/50V LED Diode BYV95C TVS P6KE16A Diode FR103 FUSE 4A/250V Choke (900µH) Choke (10mH) Inductor (2µH) Diode 20A/100V Reference Q2 R1, R2, R5, R7 R3 R4 R6 R8 R9 R10 R11 R12 R13 R14 R15 R16 THER2 T1 U1 U2 U3 VZ1 Component MOS 7A/600V R 470KΩ 1/4W R 100KΩ 1/2W R 47Ω 1/4W R 2KΩ 1/8W R 0.3Ω 2W R 33KΩ 1/8W R 4.7KΩ 1/8W R 470Ω 1/8W R 0Ω 1/8W R 4.7KΩ 1/8W R 154KΩ 1/8W 1% R 39KΩ 1/8W 1% R 100Ωm 1/8W Thermistor TTC104 Transformer (600µH-PQ2620) IC SG5842A/JA IC PC817 IC TL431 VZ 9G © 2007 Fairchild Semiconductor Corporation SG5842A/SG5842JA • Rev. 1.4.3 www.fairchildsemi.com 12 2 SG5842A/JA — Highly Integrated Green-Mode PWM Controller Physical Dimensions 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 16. 8-Pin, Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2007 Fairchild Semiconductor Corporation SG5842A/SG5842JA • Rev. 1.4.3 www.fairchildsemi.com 13 SG5842A/JA — Highly Integrated Green-Mode PWM Controller Physical Dimensions (Continued) 9.83 9.00 6.67 6.096 8.255 7.61 5.08 MAX 3.683 3.20 7.62 0.33 MIN (0.56) 2.54 3.60 3.00 0.56 0.355 1.65 1.27 7.62 0.356 0.20 9.957 7.87 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 17. 8-Pin, Dual Inline Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2007 Fairchild Semiconductor Corporation SG5842A/SG5842JA • Rev. 1.4.3 www.fairchildsemi.com 14 SG5842A/JA — Highly Integrated Green-Mode PWM Controller © 2007 Fairchild Semiconductor Corporation SG5842A/SG5842JA • Rev. 1.4.3 www.fairchildsemi.com 15