PKS606P

PKS603-607 PeakSwitch® Family Product Highlights EcoSmart – Extremely Energy-Efficient • Standby output power ≥0.6 W for 1 W input (high line) • Sleep mode power ≥2.4 W at 3 W input (high line) • No-load consumption 25 µA) at the time switching is disabled, 1. Startup 2. UV Resistor Present? No 9. Start Switching Yes No No 3. AC Input Present? (IEN>25 µA) 10. No Feedback >30 ms? Yes Yes 11. Stop Switching (for 5 s) 4. Start Switching No 5. No Feedback >30 ms? Yes 6. Stop Switching Yes 7. AC Input Present? (IEN>25 µA) Note: Normal operation (no fault present) is denoted by looping with a “No” response at decision box 5 or 10. No 8. Reset A/R Latch PI-4014-062305 Figure 5. PeakSwitch Line Sense Function Flow Chart.  Rev. I 02/07 PKS603-607 VDRAIN PI-3943-031506 300 200 100 0 10 peak output power was required in low line conditions. On-time extension is disabled during the startup of the power supply. PeakSwitch Operation PeakSwitch devices operate in the current-limit mode. When enabled, the oscillator turns the power MOSFET on at the beginning of each cycle. The MOSFET is turned off when the current ramps up to the current limit or when the DCMAX limit is reached. Since the highest current limit level and frequency VDC-OUTPUT 5 0 V EN CLOCK D 0 5 10 Time (s) Figure 6. PeakSwitch Auto-Restart Operation. t he line under-voltage sense circuit prevents a restart attempt until the AC input voltage is removed (IEN 25 µA). This effectively provides a latching shutdown function with AC reset during such a fault condition. When a brownout or line sag occurs, output regulation may be lost and the EN/UV pin will receive no feedback (it is pulled low). After 30 ms of no feedback, MOSFET switching is disabled. Since the AC line is abnormally low (IEN 25 µA). This effectively disables the latching shutdown function during such a condition. Auto-Restart (UV resistor not present) In the event of a fault condition such as output overload, output short circuit or an open loop condition, PeakSwitch enters into auto-restart operation. An internal counter clocked by the oscillator is reset every time the EN/UV pin is pulled low. When the EN/UV pin receives no feedback for 30 ms, the power MOSFET switching is disabled for 5 seconds (150 ms for the first auto-restart event). The auto-restart alternately enables and disables the switching of the power MOSFET until the fault condition is removed. Figure 6 illustrates auto-restart circuit operation in the presence of an output short circuit. Adaptive Switching Cycle On-time Extension Adaptive switching cycle on-time extension keeps the MOSFET on until current limit is reached, instead of terminating after the DCMAX signal goes low. This on-time extension is adaptive because it only occurs after the ENABLE pin has been high for approximately 750 µs, a condition that would arise if the MAX I DRAIN V DRAIN PI-2749-050301 Figure 7. PeakSwitch Operation at Near Maximum Loading. V EN CLOCK D MAX I DRAIN V DRAIN PI-2667-090700 Figure 8. PeakSwitch Operation at Moderately Heavy Loading. 5 Rev. I 02/07 PKS603-607 of a PeakSwitch design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. Hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. If the chosen PeakSwitch family member is appropriate for the power level, the current in the calculated inductance will ramp up to current limit before the DCMAX limit is reached. Enable Function PeakSwitch senses the EN/UV pin to determine whether or not to proceed with the next switching cycle as described earlier. The sequence of cycles is used to determine the current limit. Once a cycle is started, it always completes the cycle (even when the EN/UV pin changes state half way through the cycle). This operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle and the delay of the feedback. The EN/UV pin signal is produced on the secondary by comparing the power supply output voltage with a reference voltage. The EN/UV pin signal is high when the power supply output voltage is less than the reference voltage. In a typical implementation, the EN/UV pin is driven by an optocoupler. The collector of the optocoupler transistor is connected to the EN/UV pin and the emitter is connected to the SOURCE pin. The optocoupler LED is connected in series with a Zener diode across the DC output voltage to be regulated. When the output voltage exceeds the target regulation voltage level (optocoupler LED voltage drop plus Zener voltage), the optocoupler LED will start to conduct, pulling the EN/UV pin low. The Zener diode can be replaced by a TL431 reference circuit for improved accuracy. ON/OFF Operation with Current-Limit State Machine The internal clock of the PeakSwitch runs all the time. At the beginning of each clock cycle, it samples the EN/UV pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines the appropriate current limit. At high loads, when the EN/UV pin is high (less than 240 µA out of the pin), a switching cycle with the full current limit occurs. At lighter loads, when EN/UV is high, a switching cycle with a reduced current limit occurs. V EN CLOCK D MAX I DRAIN V DRAIN PI-2661-072400 V EN CLOCK D Figure 10. PeakSwitch Operation at Very Light Loading. PI-4331-031506 200 100 0 5 I DRAIN V DC-INPUT MAX 0 300 200 100 V BYPASS V DRAIN V DRAIN 0 0 PI-2377-091100 5 10 Time (ms) Figure 9. PeakSwitch Operation at Medium Loading. Figure 11. PeakSwitch Power Up with Optional External UV Resistor (4 MW) Connected to EN/UV Pin. 6 Rev. I 02/07 PKS603-607 PI-4332-031506 PI-2395-030801 200 100 0 5 0 300 200 100 0 0 V DRAIN V BYPASS V DC-INPUT 200 100 0 400 300 200 100 0 V DRAIN V DC-INPUT Modifying current schematic 5 10 0 2.5 5 Time (ms) Figure 12. PeakSwitch Power Up Without Optional External UV Resistor Connected to EN/UV Pin. Time (s) Figure 14. Slow Power Down Timing With Optional External (4 MW) UV Resistor Connected to EN/UV Pin. 200 100 0 400 300 200 100 0 0 .5 V DRAIN V DC-INPUT Power Up/Down The PeakSwitch requires only a 0.33 µF capacitor on the BYPASS pin. Because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically less than 1.5 ms. Due to the fast nature of the ON/OFF feedback, there is no overshoot at the power supply output. When an external resistor is connected from the positive DC input to the EN/UV pin, the power MOSFET switching will be delayed during power up until the DC line voltage exceeds the threshold (100 V). Figures 11 and 12 show the power up timing waveform in applications with and without an external resistor (4 MW) connected to the EN/UV pin. During power down, when an external resistor is used, the power MOSFET will switch for 30 ms after the output loses regulation. The power MOSFET will then remain off without any glitches since the under-voltage function prohibits restart when the line voltage is low. Figure 13 illustrates a typical power-down timing waveform. Figure 14 illustrates a very slow power-down timing waveform as in standby applications. An external resistor is connected to the EN/UV pin in this case to prevent unwanted restarts. Current Limit Operation Each switching cycle is terminated when the DRAIN current reaches the current limit of the PeakSwitch. Current limit operation provides good line ripple rejection. BYPASS Pin Capacitor The BYPASS pin uses a small 0.33 uF ceramic capacitor for decoupling the internal power supply. 1 Time (s) Figure 13. Normal Power Down Timing (Without UV). At maximum peak load, PeakSwitch will conduct during nearly all of its clock cycles (Figure 7). At the rated continuous load, it will “skip” additional cycles in order to maintain voltage regulation at the power supply output (Figure 8). At medium loads, cycles will be skipped and the current limit will be reduced (Figure 9). At very light loads, the current limit will be reduced even further (Figure 10). Only a small percentage of cycles will occur to satisfy the internal power consumption of the power supply at no-load. The response time of the ON/OFF control scheme is very fast compared to normal PWM control. This provides tight regulation and excellent transient response. PI-2348-030801 7 Rev. I 02/07 PKS603-607 C10 1 nF 250 VAC R8 68 Ω C11 1/2 W 330 pF D9 1N4148 C17 4.7 nF 1 kV D1-D4 1N4007 C4 150 µF 400 V R15 2.2 Ω R4 22 Ω 1/2 W D6 FR106 D5 1N4007 t RT1 10 Ω O R9 C13 47 µF 0.33 Ω 2W 16 V Q1 2N3906 30 V @ C14 L2 220 nF 1.07 A Cont. 2.7 A Peak 5.3 µH 50 V C5 2.2 nF 1 kV VR1 1N4764A 100 V 1 9,10 D8 STPS3150 C12 330 µF 50 V 7,8 R3 10 kΩ 1/2 W 3 4 C6 47 µF 35 V 5 T1 EE25 VR2 1N5255B 28 V R11 3 kΩ R10 1.5 kΩ RTN L1 5.3 mH R2 R1 1.3 MΩ 1.3 MΩ C3 680 nF X1 R5 2.2 MΩ PeakSwitch D U1 PKS606Y C7 100 nF 400 V S 2 R12 1 kΩ R7 4.7 kΩ C15 100 nF 50 V D10 UF4003 VR3 1N5258B 36 V Q2 FS202DA R6 2.4 MΩ D7 1N4148 C16 100 nF R14 100 Ω R13 1 kΩ R16 2.7 MΩ EN/UV BP GND F1 3.15 A J1 L PE N C1-C2 100 pF 250 VAC C8 220 nF 50 V U2 PC817X4 RTN Connected to PE via Flying Lead C19 1 nF, 250 VAC J3 PCB Term 18 AWG PI-4170-060706 Figure 15. PeakSwitch PKS606Y, 32 W Continuous, 81 W Peak, Universal Input Power Supply. Application Example The circuit shown in Figure15 is a low cost, high efficiency, flyback power supply designed to provide a 30 V, 1.06 A continuous, 2.7 A peak output from universal input using the PKS606Y. The supply features under-voltage lockout and smart C sense with A fast reset. Latching overload, open loop, and hysteretic thermal shutdown protect both the supply and load under fault conditions while high efficiency (>80%) and very low no-load consumption (25 µA into the EN/UV pin) the PeakSwitch will latch 8 Rev. I 02/07 PKS603-607 off the power supply. This protects the load and supply from a continuous fault condition. Removing the AC input resets this condition. The output voltage is determined by the Zener diode VR2, the voltage drop across R12 and the forward drop of D9 and the LED of optocoupler U2. Resistor R13 provides bias current through D9 and VR2, to ensure that VR2 is operating close to its knee voltage, while R12 sets the overall gain of the feedback loop. Capacitor C15 boosts high frequency loop gain to help distribute the enabled switching cycles and reduce pulse grouping. When the output voltage exceeds the feedback threshold voltage, current will flow in the optocoupler LED, causing current flow in the transistor of the optocoupler. When this exceeds the ENABLE pin threshold current the next switching cycle is inhibited, as the output voltage falls (below the feedback threshold) a conduction cycle is allowed to occur and by adjusting the number of enabled cycles output regulation is maintained. As the load reduces the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. This provides almost constant efficiency down to very light loads, ideal for meeting energy efficiency requirements. PeakSwitch device U1 is supplied from an auxillary winding on the transformer which is rectified and filtered by D7 and C6. Resistor R7 provides approximately 2 mA of supply current into the BYPASS pin capacitor C8. During startup or fault conditions when the bias voltage is low, the BYPASS pin is supplied from a high voltage current source within U1, eliminating the need for separate startup components. Components Q1-2, R9-11, R14, C13, C16, and VR3 form an overvoltage and overcurrent protection circuit. An output overvoltage or overcurrent condition fires SCR Q2, clamping the output voltage and forcing PeakSwitch U1 into latching shutdown after 30 ms. The low pass filter formed by R10 and C13 adds a delay to the over-current sense. The shutdown condition can be reset by briefly removing AC power for ~3 seconds (maximum). The latching function within PeakSwitch significantly reduces the size of the SCR and output rectifier, D8, as the short circuit current only flows for 50 ms before the supply latches off. This design meets EN55022 Class B conducted EMI with >10 dB margin even with the output RTN directly connected to earth ground. the maximum practical continuous output power level that can be obtained under the following assumed conditions: 1. The minimum DC input voltage is 100 V or higher for 85 VAC input, or 220 V or higher for 230 VAC input or single 100/115 VAC with a voltage doubler. 2. Efficiency of 70% for Y/F packaged devices, 75% for P packaged devices at 85-265 VAC, 75% for 230 VAC input all packages 3. Minimum datasheet value of I2f 4. Transformer primary inductance tolerance of ±10% 5. Reflected output voltage (VOR) of 135 V 6. Voltage only output of 15 V with an ultra fast PN rectifier diode 7. Continuous conduction mode operation with transient KP* value of 0.25 8. Sufficient heatsinking is provided, either externally (Y/F packages) or through an area of PC board copper (P package) to keep the SOURCE pin or tab temperature at or below 110 °C. 9. Device ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters *Below a value of 1, KP is the ratio of ripple to peak primary current. To prevent reduced power capability due to premature termination of switching cycles, a transient KP limit of ≥0.25 is recommended. This avoids the initial current limit (IINIT) being exceeded at MOSFET turn on. Peak vs. Continuous Power PeakSwitch devices have current limit values that allow the specified peak power values in the power table. With sufficient heatsinking, these power levels could be provided continuously, however this may not be practical in many applications. PeakSwitch is optimized for use in applications that have short duration, high peak power demand, but a significantly lower continuous or average power. Typical ratios would be PPEAK ≥ 2 × PAVE. The high switching frequency of PeakSwitch allows a small core size to be selected to deliver the peak power, but the short duration prevents the transformer winding from overheating. As average power increases, it may be necessary to select a larger transformer to allow increased copper area for the windings based on the measured transformer temperature. The power table provides some guidance between peak power and continuous power in sealed adapters, however specific applications may differ. For example, if the peak power condition is very low duty cycle, say a 2 second peak occurring only at power up to accelerate a hard disk drive, then the transformer’s thermal rise is only a function of the continuous power. However, if the peak power occurs every 200 ms for 50 ms then it would need to be considered. In all cases, the acceptable temperature rise of the PeakSwitch and transformer should be verified under worst case ambient and load conditions. Key Application Considerations PeakSwitch Design Considerations Output Power Table The data sheet maximum output power table (Table 1) represents  Rev. I 02/07 PKS603-607 Power (W) P3 provides sufficient margin to prevent core saturation under startup or output short circuit conditions. Optocoupler CTR To minimize the delay introduced by the optocoupler, it is recommended that a high (300-600%) CTR optocoupler is used in PeakSwitch designs. PI-4329-030906 P2 P1 ∆t1 T ∆t2 Time (t) Bias Winding All PeakSwitch designs must use a bias winding to feed operating current into the BYPASS pin once the supply is operational. It is recommended that the value of the resistor from the bias winding to the BYPASS pin be selected such that it supplies the same current as the maximum datasheet drain supply current (IS2) for the specific device being used. PeakSwitch Layout Considerations See Figure 17 for a recommended circuit board layout for PeakSwitch. Single Point Grounding Devices in Y and F packages have separate return pins for the MOSFET source (S) and the controller (GND) connections which are internally connected. Therefore connecting these pins on the PC board is not recommended. Devices in the P package do not have separate return pins, but in both cases the low current feedback signals and IC decoupling, high MOSFET current and bias winding primary return connection should route through separate traces to the Kelvin connection. The bias winding return connection is treated separately, even though it carries low current. To route high currents away from the device when the supply is subjected to line surge transients, the bias winding should be returned directly to the input bulk capacitor. Bypass Capacitor (CBP) The BYPASS pin capacitor should be located as close as possible to the BYPASS and SOURCE pins. Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary and PeakSwitch together should be kept as small as possible. Primary Clamp Circuit A clamp is used to limit the peak voltage on the DRAIN pin at turn off. This can be achieved by using an RCD clamp or a Zener (~200 V) and diode clamp across the primary winding. In all cases to minimize EMI care should be taken to minimize the circuit path from the clamp components to the transformer and PeakSwitch. Figure 16. Continuous (Average) Output Power Calculation Example. Figure 16 shows how to calculate the average power requirements for a design with two different peak load conditions. Where PX are the different output power conditions, ΔtX are the durations of each peak power condition, and T is the period of one cycle of the pulse load condtion. Audible Noise The cycle skipping mode of operation used in PeakSwitch can generate audio frequency components in the transformer. To limit this audible noise generation, the transformer should be designed such that the peak core flux density is below 3000 Gauss (300 mT). Following this guideline and using the standard transformer production technique of dip varnishing practically eliminates audible noise. Vacuum impregnation of the transformer should not be used due to the high primary capacitance and increased losses that result. Ceramic capacitors that use dielectrics such as Z5U, when used in clamp circuits, may also generate audio noise. If this is the case try replacing them with a capacitor having a different type of dielectric or construction, for example a film type capacitor. Maximum Flux Density A maximum value of 3000 Gauss during normal operation is recommended to limit the maximum flux density under start up and output short circuit. Under these conditions the output voltage is low and little reset of the transformer occurs during the MOSFET off time. This allows the transformer flux density to staircase above the normal operating level. A value of 3000 Gauss at the peak current limit of the selected device, together with the built in protection features of PeakSwitch 10 Rev. I 02/07 PKS603-607 Safety Spacing Y1Capacitor Maximize hatched copper areas ( ) for optimum heatsinking Output Rectifier Output Filter Capacitor + HV Input Filter Capacitor PRI BIAS D PRI T r a n s f o r m e r SEC - S S PeakSwitch EN/UV BP S BIAS TOP VIEW S CBP Optocoupler - (a) Safety Spacing + Input Filter Capacitor Y1Capacitor DC + OUT PI-4326-060706 Maximize hatched copper areas ( ) for optimum heatsinking HV Output Rectifier PRI T r a n s f o r m e r Output Filter Capacitor - SEC NC EN/UV GND D PRI BIAS BIAS BP TOP VIEW CBP Heat Sink Optocoupler (b) Figure 17. Recommended Layout for PeakSwitch in (a) P and (b) Y/F Packages. - DC + OUT PI-4327-031706 11 Rev. I 02/07 PKS603-607 Thermal Considerations For the P package, the four SOURCE pins are internally connected to the IC lead frame and provide the main path to remove heat from the device. Therefore, all the SOURCE pins should be connected to a copper area underneath the PeakSwitch to act not only as a single point ground, but also as a heatsink. As this area is connected to the quiet source node, it should be maximized for good heatsinking. Similarly, for axial output diodes, maximize the PCB area connected to the cathode. Y-Capacitor The placement of the Y-type cap should be directly from the primary input filter capacitor positive terminal to the common/ return terminal of the transformer secondary. If a second Y- type cap is required from primary to secondary return, connect the primary side directly to the negative terminal of the input capacitor. Such a placement will route high magnitude common mode surge currents away from the PeakSwitch device. Note – if an input π (C, L, C) EMI filter is used, then the inductor in the filter should be placed between the negative terminals on the input filter capacitors. Optocoupler Place the optocoupler physically close to the PeakSwitch to minimize the primary side trace lengths. Keep the high current high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. Output Diode For best performance, the area of the loop connecting the secondary winding, the output diode and the output filter capacitor should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminal of the diode for heatsinking. A larger area is preferred at the quite cathode terminal. A large anode area can increase high frequency radiated EMI. Quick Design Checklist As with any power supply design, all PeakSwitch designs should be verified on the bench to make sure that component specifications are not exceeded under worst case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that the VDS does not exceed 650 V at highest input voltage and peak (overload) output power. The 50 V margin to the 700 V BVDSS specification allows margin for design variation. 2. Maximum drain currents – Verify the simultaneous drain voltage and current levels are within the curve provided in Figure 29 under worst case conditions. Typically this occurs at start up (and during an output short circuit), highest input line voltage and maximum ambient temperature. When making this measurement using a current probe, to monitor the drain current, ensure the results are corrected for the 10-20 ns current probe delay. 3. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms show no signs of transformer saturation. If the transformer shows signs of saturation, it should be redesigned with a lower flux density, or a higher quality core material should be used. To prevent false triggering of the current limit, verify the leading edge current spike event is below IINIT(MIN) at the end of the tLEB(MIN). Under all conditions, the maximum drain current should be below the absolute maximum limit specified in the Absolute Maximum Ratings section. 4. Thermal Check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for PeakSwitch, transformer, output diode and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of PeakSwitch as specified in the data sheet. Under low line, maximum power, a maximum PeakSwitch SOURCE pin or tab temperature of 110 °C is recommended to allow for these variations. Design Tools Up-to-date information on design tools can be found at the Power Integrations web site: www.powerint.com. 12 Rev. I 02/07 PKS603-607 ABSOLUTE MAXIMUM RATINGS(1,) DRAIN Voltage .................................. .............-0.3 V to 700 V . DRAIN Peak Current: ....................... ...... 2 × ILIMIT (Typical)(5) EN/UV Voltage ....................................................-0.3 V to 9 V EN/UV Current .................................................... ....... 100 mA BYPASS Voltage .................................................. 0.3 V to 9 V Storage Temperature ......................................-65 °C to 150 °C Operating Junction Temperature(2) .................-40 °C to 150 °C Lead Temperature(3)................ ....................................... 260 °C Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. Normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. Maximum ratings specified may be applied one at a time, without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. 5. Peak DRAIN current is allowed while the DRAIN voltage is simultaneously less than 400 V. See also Figure 29. Thermal Impedance: Y/F Package: (qJA)(1) ........................................80 °C/W (qJC)(2) ..........................................2 °C/W P Package: (qJA) .....................70 °C/W(3); 60 °C/W(4) (qJC)(5) ..................................... 10 °C/W(5) THERMAL IMPEDANCE Notes: 1. Free standing with no heatsink. 2. Measured at the back surface of tab. 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad. 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad. 5. Measured on the SOURCE pin close to plastic interface. Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) TJ = 25 °C See Figure 4 Average Peak-Peak Jitter S1 Open Conditions Min Typ Max Units CONTROL FUNCTIONS Output Frequency Maximum Duty Cycle EN/UV Pin Turn Off Threshold Current EN/UV Pin Voltage fOSC DCMAX IDIS IEN/UV = -125 µA IEN/UV = 25 µA VEN/UV = 0 V EN/UV Open (MOSFET Switching) See Note A, B VBP = 0 V, TJ = 25 °C See Note C VBP = 4 V, TJ = 25 °C See Note C PKS603 PKS604 PKS605 PKS606 PKS607 PKS603-604 PKS605-607 PKS603-604 PKS605-607 250 62 277 16 65 68 304 kHz % -350 0.4 1.3 350 460 600 700 950 1160 -7.5 -10.0 -4.5 -6.5 -240 1.0 2.0 475 570 725 875 1175 1430 -5.0 -6.6 -3.0 -4.5 -200 1.5 2.7 600 690 870 1050 1400 1700 -2.5 -3.2 -1.5 -2.5 µA VEN IS1 V DRAIN Supply Current IS2 µA BYPASS Pin Charge Current ICH1 ICH2 mA 13 Rev. I 02/07 PKS603-607 Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) Min Typ Max Units CONTROL FUNCTIONS (cont.) BYPASS Pin Shunt V BP(SH) Regulator Voltage BYPASS Pin VBP Voltage BYPASS Pin VBPH Voltage Hysteresis EN/UV Pin Line ILUV Under-Voltage Threshold CIRCUIT PROTECTION See Note D 6.0 5.5 0.8 6.3 5.8 1.0 25 6.7 6.15 1.3 27.5 V V V µA TJ = 25 °C 22.5 PKS603 P TJ = 25 °C PKS604 P/Y/F TJ = 25 °C PKS605 P TJ = 25 °C di/dt = 200 mA/µs See Note E di/dt = 290 mA/µs See Note E di/dt = 290 mA/µs See Note E di/dt = 325 mA/µs See Note E di/dt = 255 mA/µs See Note E di/dt = 660 mA/µs See Note E di/dt = 800 mA/µs di/dt = 200 mA/µs di/dt = 290 mA/µs di/dt = 290 mA/µs di/dt = 325 mA/µs di/dt = 255 mA/µs di/dt = 660 mA/µs di/dt = 800 mA/µs 0.75 1.35 1.35 1.76 1.40 2.60 2.79 164 524 524 890 569 1955 2242 0.81 1.45 1.45 1.89 1.51 2.80 3.00 182 582 582 989 632 2172 2493 0.87 1.55 1.55 2.02 1.62 3.00 3.21 204 652 652 1108 708 2433 2793 A2kHz A Current Limit ILIMIT PKS605 Y/F TJ = 25 °C PKS606 P TJ = 25 °C PKS606 Y/F TJ = 25 °C PKS607 Y/F TJ = 25 °C PKS603 P TJ = 25 °C PKS604 P/Y/F TJ = 25 °C PKS605 P TJ = 25 °C Power Coefficient I2f PKS605 Y/F TJ = 25 °C PKS606 P TJ = 25 °C PKS606 Y/F TJ = 25 °C PKS607 Y/F TJ = 25 °C 1 Rev. I 02/07 PKS603-607 Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) See Figure 21 See Note F TJ = 25 °C See Note F TJ = 25 °C See Notes F, G Min Typ Max Units CIRCUIT PROTECTION (cont.) Initial Current Limit Leading Edge Blanking Time Current Limit Delay Thermal Shutdown Temperature Thermal Shutdown Hysteresis OUTPUT PKS603 ID = 81 mA PKS604 ID = 150 mA TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C TJ = 25 °C TJ = 100 °C 7.8 11.7 5.2 7.8 3.9 5.8 2.6 3.9 2.0 3.0 9.0 13.5 6.0 9.0 4.5 6.7 3.0 4.5 2.3 3.5 W IINIT tLEB tILD 0.75 × ILIMIT(Min) 170 215 150 135 142 75 150 mA ns ns °C °C ON-State Resistance RDS(ON) PKS605 ID = 200 mA PKS606 ID = 300 mA PKS607 ID = 300 mA OFF-State Drain Leakage Current IDSS1 VBP = 6.2 V VEN/UV = 0 V VDS = 560 V TJ = 125 °C See Note H VBP = 6.2 V VEN/UV = 0 V VDS = 375 V TJ = 50 °C See Note H 700 50 15 200 µA IDSS2 Breakdown Voltage Drain Supply Voltage Output EN/UV Delay Output Disable Setup Time BVDSS VBP = 6.2 V, VEN/UV = 0 V, See Note I, TJ = 25 °C V V 5 0.5 µs µs tEN/UV tDST See Figure 20 15 Rev. I 02/07 PKS603-607 Conditions Parameter OUTPUT (cont.) Auto-Restart ON Time Auto-Restart OFF Time Symbol SOURCE = 0 V; TJ = -40 to 125 °C See Figure 18 (Unless Otherwise Specified) TJ = 25 °C See Note J See Note K Min Typ Max Units tAR tAROFF 30 5 ms s NOTES: A. Total current consumption is the sum of IS1 and IDSS when EN/UV pin is shorted to ground (MOSFET not switching) and the sum of IS2 and IDSS when EN/UV pin is open (MOSFET switching). B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BYPASS pin current at 6.1 V. C. See Typical Performance Characteristics section for BYPASS pin startup charging waveform. D. BYPASS pin is externally supplied (bias winding). E. For current limit at other di/dt values, refer to Figure 25. F. This parameter is derived from characterization. G. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT specification. H. IDSS1 is the worst case OFF state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical specification under worst case application conditions (rectified 265 VAC) for no-load consumption calculations. I. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not exceeding minimum BVDSS. J. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). Auto-restart on time is extended during startup and certain fault conditions because the controller reduces its oscillator clock frequency to prevent excessive drain currents. If excessive drain currents are still occuring half way through the auto-restart on time, output MOSFET switching is disabled for the remainder of that auto-restart on time episode (if the line is not sensed) or the supply latches off (if the line is sensed and adequate line voltage is present). K. Only applicable if no UV resistor is present at the EN/UV pin. 5 s applies only if the preceding switching autorestart event did not result in EN/UV pin going low. In that event, the first auto-restart off-time is 150 ms. 16 Rev. I 02/07 PKS603-607 470 W 5W 470 W S S S EN/UV BP D S2 S1 4 MW 10 V 0.33 µF 150 V 50 V S NOTE: This test circuit is not applicable for current limit or output characteristic measurements. PI-4317-030606 Figure 18. PeakSwitch General Test Circuit. (internal signal) tP DCMAX EN/UV VDRAIN tP = 1 fOSC PI-2364-012699 tEN/UV Figure 19. Duty Cycle Measurement. Figure 20. Output Enable Timing. tLEB (Blanking Time) 0.8 IINIT(MIN) ILIMIT(MIN) @ 100 °C Figure 21. Current Limit Envelope. PI-4328-030806 17 Rev. I 02/07 PKS603-607 Typical Performance Characteristics PI-2213-012301 PI-4294-022806 1.1 1.2 1.0 0.8 0.6 0.4 0.2 0 Breakdown Voltage (Normalized to 25 °C) 1.0 0.9 -50 -25 0 25 50 75 100 125 150 Output Frequency (Normalized to 25 °C) -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Figure 22. Breakdown vs. Temperature. PI-4295-020806 Figure 23. Frequency vs. Temperature. 1.4 Junction Temperature (°C) Standard Current Limit (Normalized to 25 °C) 1 0.8 0.6 0.4 0.2 0 -50 Normalized Current Limit 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 1 2 3 4 Junction Temperature (°C) Figure 24. Standard Current Limit vs. Temperature. PI-4307-091206 Normalized di/dt Figure 25. Current Limit vs. di/dt. PI-4308-091206 1.2 1.0 1000 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 Scaling Factors: PKS603 1.0 PKS604 1.5 PKS605 2.0 PKS606 3.0 PKS607 4.0 TJ = 25 °C TJ = 100 °C Drain Capacitance (pF) Drain Current (A) 100 Scaling Factors: PKS603 1.0 PKS604 1.5 PKS605 2.0 PKS606 3.0 PKS607 4.0 10 1 0 100 200 300 400 500 600 Drain Voltage (V) Figure 26. Output Characteristic. Drain Voltage (V) Figure 27. COSS vs. Drain Voltage. 18 Rev. I 02/07 PI-4297-020806 1.2 PKS603-607 Typical Performance Characteristics (cont.) PI-4296-020806 PI-4330-031606 1.2 2.5 Under-Voltage Theshold (Normalized to 25 °C) 1 0.8 0.6 0.4 0.2 0 -50 Drain Current (Normalized to Typical ILIMIT) 2 1.5 1 0.5 0 50 100 150 0 0 100 200 300 400 500 600 700 800 Junction Temperature (°C) Figure 28. Under-Voltage Threshold vs. Temperature. Drain Voltage (V) Figure 29. Maximum Allowable Drain Current vs. Drain Voltage. 1 Rev. I 02/07 PKS603-607 PART ORDERING INFORMATION PeakSwitch Product Family Series Number Package Identifier P Y F Plastic DIP-8C Plastic TO-220-7C Plastic TO-262-7C Pure Matte Tin (Pb-Free) Lead Finish PKS 60 P N N TO-220-7C .390 (9.91) .420 (10.67) + .165 (4.19) .185 (4.70) .146 (3.71) .156 (3.96) .045 (1.14) .055 (1.40) .108 (2.74) REF .234 (5.94) .261 (6.63) .570 (14.48) REF. 7° TYP. .080 (2.03) .120 (3.05) .670 (17.02) REF. .461 (11.71) .495 (12.57) .860 (21.84) .880 (22.35) .068 (1.73) MIN PIN 1 PIN 1 & 7 PIN 2 & 4 .024 (.61) .010 (.25) M .034 (.86) .050 (1.27) BSC .150 (3.81) BSC .012 (.30) .024 (.61) .190 (4.83) .210 (5.33) .040 (1.02) .060 (1.52) .040 (1.02) .060 (1.52) .050 (1.27) .050 (1.27) .050 (1.27) .050 (1.27) .200 (5.08) .100 (2.54) PIN 1 PIN 7 Notes: 1. Controlling dimensions are inches. Millimeter dimensions are shown in parentheses. 2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front. 3. Dimensions do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. Minimum metal to metal spacing at the package body for omitted pin locations is .068 in. (1.73 mm). 5. Position of terminals to be measured at a location .25 (6.35) below the package body. 6. All terminals are solder plated. .180 (4.58) .150 (3.81) .150 (3.81) Y07C MOUNTING HOLE PATTERN PI-2644-122004 20 Rev. I 02/07 PKS603-607 DIP-8C -E- ⊕D S .004 (.10) .240 (6.10) .260 (6.60) Pin 1 -D.367 (9.32) .387 (9.83) .057 (1.45) .068 (1.73) (NOTE 6) .125 (3.18) .145 (3.68) .015 (.38) MINIMUM Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clockwise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. -T- SEATING PLANE .120 (3.05) .140 (3.56) .048 (1.22) .053 (1.35) .137 (3.48) MINIMUM .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .100 (2.54) BSC .014 (.36) .022 (.56) ⊕T E D P08C PI-3933-100504 S .010 (.25) M 21 Rev. I 02/07 PKS603-607 TO-262-7C .390 (9.91) .420 (10.67) .055 (1.40) .066 (1.68) .326 (8.28) .336 (8.53) .795 (20.18) REF. .165 (4.17) .185 (4.70) .045 (1.14) .055 (1.40) 7° TYP. .080 (2.03) .120 (3.05) .495 (12.56) REF. .595 (15.10) REF. PIN 1 .068 (1.73) MIN .024 (.61) .010 (.25) M .034 (.86) .050 (1.27) BSC .150 (3.81) BSC PIN 1 & 7 PIN 2 & 4 .012 (.30) .024 (.61) .190 (4.83) .210 (5.33) .040 (1.02) .060 (1.52) .040 (1.06) .060 (1.52) .050 (1.27) .050 (1.27) .050 (1.27) .050 (1.27) .200 (5.08) .100 (2.54) PIN 1 PIN 7 .180 (4.58) .150 (3.81) .150 (3.81) F07C MOUNTING HOLE PATTERN Notes: 1. Controlling dimensions are inches. Millimeter dimensions are shown in parentheses. 2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front. 3. Dimensions do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. Minimum metal to metal spacing at the package body for omitted pin locations is .068 inch (1.73 mm). 5. Position of terminals to be measured at a location .25 (6.35) below the package body. 6. All terminals are solder plated. PI-2757-122004 22 Rev. I 02/07 PKS603-607 23 Rev. I 02/07 PKS603-607 Revision Notes G H I F Date 3/06 4/06 6/06 2/07 1) Final Release Data Sheet. Revised device symbol in Figures 1 and 15 to be consistent with other PI documentation (added second ground connection). Revised layout of Figure 17 (PI-4326). Revised grounding in Figure 1 to match actual implementation. Added PKS607. For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. PATENT INFORMATION The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. LIFE SUPPORT POLICY POWER INTEGRATIONS’ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, Clampless, EcoSmart, E-Shield, Filterfuse, StackFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©Copyright 2007, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations WORLD HEADQUARTERS 5245 Hellyer Avenue San Jose, CA 95138, USA. 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