F71869

F71869 Super I/O + Hardware Monitor Release Date: Jul, 2009 Version: V1.1 Fintek Feature Integration Technology Inc. F71869 F71869 Datasheet Revision History Version V1.0 V1.1 Date Jun, 2009 Jul, 2009 Page Official released 16 Revise ST2 pin description Revision History Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales. 1 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Table of Contents 1. GENERAL DESCRIPTION............................................................................................................................................ 4 2. FEATURE ...................................................................................................................................................................... 4 3. PIN CONFIGURATION.................................................................................................................................................. 7 4. PIN DESCRIPTION ....................................................................................................................................................... 8 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 POWER PINS .............................................................................................................................................................8 LPC INTERFACE ........................................................................................................................................................9 FDC .........................................................................................................................................................................9 UART AND SIR .......................................................................................................................................................10 PARALLEL PORT ......................................................................................................................................................12 HARDWARE MONITOR ..............................................................................................................................................13 ACPI FUNCTION PINS ..............................................................................................................................................14 BIT SELECT AND OTHERS .........................................................................................................................................16 KBC FUNCTION .......................................................................................................................................................17 5. FUNCTIONAL DESCRIPTION ......................................................................................................................................18 5.1 5.2 5.3 5.4 5.5 5.6 POWER TRAP OPERATION ........................................................................................................................................18 HARDWARE MONITOR ..............................................................................................................................................18 ACPI FUNCTION ......................................................................................................................................................28 TIMING CONTROL SEQUENCE ...................................................................................................................................29 ST1, ST2 AND ATX_PWRGDSW TIMING ................................................................................................................30 AMD TSI AND INTEL PECI FUNCTION .......................................................................................................................32 5. REGISTER DESCRIPTION.........................................................................................................................................34 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 GLOBAL CONTROL REGISTERS .................................................................................................................................38 FDC REGISTERS (CR00) ........................................................................................................................................45 UART1 REGISTERS (CR01) ....................................................................................................................................47 UART2 REGISTERS (CR02) ....................................................................................................................................48 PARALLEL PORT REGISTER (CR03)..........................................................................................................................50 HARDWARE MONITOR REGISTERS (CR04)................................................................................................................51 KBC REGISTERS (CR05) ........................................................................................................................................84 GPIO REGISTERS (CR06).......................................................................................................................................85 BIT SELECT REGISTERS (CR07) ...........................................................................................................................99 PME AND ACPI REGISTERS (CR0A) ..................................................................................................................101 2 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 7. ELECTRICAL CHARACTERISTIC .............................................................................................................................107 8. ORDERING INFORMATION........................................................................................................................................108 9. PACKAGE DIMENSIONS (128-PQFP) .......................................................................................................................108 10. APPLICATION CIRCUIT............................................................................................................................................ 110 3 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 1. General Description The F71869 which is the featured IO chip for PC system is equipped with one IEEE 1284 Parallel Port, two UART Ports, Hardware Keyboard Controller, SIR and one FDC. The F71869 integrates with hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the accurate dual current type temperature measurement for CPU thermal diode or external transistors 2N3906. Others, the F71869 supports newest AMD TSI and Intel PECI interfaces and INTEL Ibex PEAK SMBus for temperature sensing and provides the power sequence controller function for AMD platform The F71869 provides flexible features for multi-directional application. For instance, supports 3-in/out pins North Bridge Bit select controlling with offset implement., provides 45 GPIO pins (multi-pin), IRQ sharing function also designed in UART feature for particular usage and accurate current mode H/W monitor will be worth in measurement of temperature, provides 3 modes fan speed control mechanism included Manual Mode/Stage Auto Mode/Linear Auto Mode for users’ selection. These features as above description will help you more and improve product value. Finally, the F71869 is powered by 3.3V voltage, with the LPC interface in the green package of 128-PQFP. 2. Feature General Functions Comply with LPC Spec. 1.0 Support DPM (Device Power Management), ACPI Support AMD power sequence controller 3 In/Out Bit Select Provides one FDC, two UARTs, Hardware KBC and Parallel Port H/W monitor functions Support AMD TSI Interface, Intel PECI interface, Intel Block Read/Write SMBus Interface 45 GPIO Pins for flexible application 24/48 MHz clock input Packaged in 128-PQFP and powered by 3.3VCC FDC Compatible with IBM PC AT disk drive systems 4 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and under run conditions Built-in address mark detection circuit to simplify the read electronics Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate UART Two high-speed 16C550 compatible UART with 16-byte FIFOs Fully programmable serial-interface characteristics Baud rate up to 115.2K Support IRQ sharing Support Ring-In Wakeup Infrared Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Parallel Port One PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification Enhanced printer port back-drive current protection Keyboard Controller LPC interface support serial interrupt channel 1, 12. Two 16bit Programmable Address fully decoder, default 0x60 and 0x64. Support two PS/2 interface, one for PS/2 mouse and the other for keyboard. Keyboard’s scan code support set1, set2. Programmable compatibility with the 8042. Support both interrupt and polling modes. Fast Gate A20 and Hardware Keyboard Reset. Hardware Monitor Functions 5 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 3 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors Temperature range -40℃~127℃ 9 sets voltage monitoring (6 external and 3 internal powers) High limit signal (PME#) for Vcore level 3 fan speed monitoring inputs 3 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans) Stage auto mode ( 2-Limit and 3-Stage)/Linear auto mode/Manual mode Issue PME# and OVT# hardware signals output Case intrusion detection circuit WATCHDOG comparison of all monitored values Integrate AMD TSI Interface Integrate Intel PECI Interface PECI Spec. 1.1A Ready Support AMD Power Sequence Controller Intel Block Read/Write SMBus Interface Package 128-pin PQFP Green Package 6 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 3. Pin Configuration Figure1. F71869 pin configuration 7 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 4. Pin Description I/O12t I/O16t-u47k I/OOD12t5v I/OD16t5v OD16-5v-u10k I/OOD8st5v I/OOD12st5v I/OD14st5v ILv/OD8-S1 ILv/OD12 O8t5v-u47k O8 O12 O16 AOUT OD12 OD14-5v OD12-5v INt5v INst-u47k INst5v AIN P - TTL level bi-directional pin with 12 mA source-sink cap ability. - TTL level bi-directional pin with 16 mA source-sink cap ability. With internal 47k pull-up. - TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA source-sink capability. - TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V tolerance. - Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 8 mA sink capability, 5V tolerance. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink capability, 5V tolerance. - TTL level bi-directional pin and schmitt trigger, Open-drain output with 14 mA sink capability, 5V tolerance. - Low level bi-directional pin (VIH 0.9V, VIL 0.6V.). Output with 8mA drive and 1mA sink capability. - Low level bi-directional pin (VIH 0.9V, VIL 0.6V.). Output with 12mA sink capability. - Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance. - Output pin with 8 mA source-sink capability. - Output pin with 12 mA source-sink capability. - Output pin with 16 mA source-sink capability. - Output pin(Analog). - Open-drain output pin with 12 mA sink capability. - Open-drain output pin with 14 mA sink capability, 5V tolerance. - Push-pull/open-drain output pin with 12 mA sink capability, 5V tolerance. - TTL level input pin,5V tolerance. - TTL level input pin and schmitt trigger. With internal pull-up 47k resistor. - TTL level input pin and schmitt trigger, 5V tolerance. - Input pin(Analog). - Power. 4.1 Power Pins Pin No. 4,37 68 99 86 88 20, 48, 73, 117 Pin Name VCC VSB VDDA VBAT AGND(D-) GND Type P P P P P P Description Power supply voltage input with 3.3V Stand-by power supply voltage input 3.3V Stand-by power supply voltage input 3.3V Battery voltage input Analog GND Digital GND 8 2009 V1.1 Fintek 4.2 LPC Interface Feature Integration Technology Inc. F71869 Pin No. 29 30 31 32 36-33 38 39 Pin Name LRESET# LDRQ# SERIRQ LFRAM# LAD[3:0] PCICLK CLKIN Type INst5v O16 I/O16t-u47k INst-u47k I/O16t-u47k INst INst PWR VCC VCC VCC VCC VCC VCC VCC Description Reset signal. It can connect to PCIRST# signal on the host. Encoded DMA Request signal. Serial IRQ input/Output. Indicates start of a new cycle or termination of a broken cycle. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. 33MHz PCI clock input. System clock input. According to the input frequency 24/48MHz. 4.3 FDC Pin No. Pin Name GPIO30 Type I/OD14st5v PWR Description Default General Purpose IO. 7 DENSEL# GPIO31 8 MOA# GPIO32 9 DRVA# GPIO33 10 WDATA# GPIO34 11 OD14-5v I/OD14st5v OD14-5v I/OD14st5v OD14-5v I/OD14st5v OD14-5v I/OD14st5v VCC VCC VCC Drive Density Select. Set to 1 - High data rate.(500Kbps, 1Mbps) Set to 0 – Low data rate. (250Kbps, 300Kbps) FDC function is selected by register setting. Default General Purpose IO. Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. FDC function is selected by register setting. Default General Purpose IO. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. FDC function is selected by register setting. Default General Purpose IO. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. FDC function is selected by register setting. Default General Purpose IO. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion FDC function is selected by register setting. Default General Purpose IO. VCC DIR# GPIO35 OD14-5v I/OD14st5v VCC 12 VCC 9 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 STEP# GPIO36 13 HDSEL# OD14-5v OD14-5v I/OD14st5v VCC Step output pulses. This active low open drain output produces a pulse to move the head to another track. FDC function is selected by register setting. Default General Purpose IO. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 FDC function is selected by register setting. Default General Purpose IO. Write enable. An open drain output. FDC function is selected by register setting. Default General Purpose IO. The read data input signal from the FDD. FDC function is selected by register setting. Default General Purpose IO. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. FDC function is selected by register setting. Default General Purpose IO. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. FDC function is selected by register setting. Default General Purpose IO. Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. FDC function is selected by register setting. Default General Purpose IO. Diskette change. This signal is active low at power on and whenever the diskette is removed. FDC function is selected by register setting. GPIO37 14 WGATE# GPIO50 15 RDATA# GPIO51 16 TRK0# I/OD14st5v OD14-5v I/OOD12st5v INst5v I/OOD12st5v VCC INst5v VCC VCC GPIO52 17 INDEX# GPIO53 18 WPT# GPIO54 19 DSKCHG# I/OOD12st5v VCC INst5v I/OOD12st5v INst5v I/OOD12st5v INst5v VCC VCC 4.4 UART and SIR Pin No. 27 Pin Name GPIO42 IRTX GPIO43 IRRX Type I/OOD12t5v O12 I/OOD12t5v INst5v PWR VCC Description Default General Purpose IO. Infrared Transmitter Output. The function is selected by register setting. Default General Purpose IO. Infrared Receiver input. The function is selected by register 28 VCC 10 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 118 119 120 DCD1# RI1# CTS1# DTR1# 121 FAN40_100 INt5v INst5v INst5v INst5v O8t5v-u47k VCC VCC VSB VCC setting. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. Clear To Send is the modem control input. UART 1 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping pin: 1(Default): (Internal pull high) Power on fan speed default duty is 40%.(PWM) 0: (External pull down) Power on fan speed default duty is 100%.(PWM) UART 1 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART 1 Serial Output. Used to transmit serial data out to the communication link. Internal 47k ohms pulled high and disable after power on strapping. Power on strapping: 1(Default): Configuration register 4E 0: Configuration register 2E Serial Input. Used to receive serial data through the communication link. Default General Purpose IO. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. The function is selected by register setting. Default General Purpose IO. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. The function is selected by register setting. Default General Purpose IO. Clear To Send is the modem control input. The function is selected by register setting. Default General Purpose IO. UART 2 Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Internal 47k ohms pulled high and disable after 122 RTS1# O8t5v-u47k VCC 123 DSR1# INst5v VCC SOUT1 124 Config4E_2E O8t5v-u47k VCC INt5v 125 SIN1 GPIO20 INst5v I/OOD8st5v INst5v I/OOD8st5v INst5v I/OOD8st5v INst5v I/OOD8st5v VCC 126 DCD2# GPIO21 VCC 127 RI2# GPIO22 VSB 128 CTS2# GPIO23 VCC 1 DTR2# O8t5v-u47k VCC 11 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 power on strapping. The function is selected by register setting. GPIO24 2 RTS2# I/OOD8st5v O8t5v-u47k I/OOD8st5v INst5v I/OOD8st5v VCC VCC VCC Default General Purpose IO. .UART 2 Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Internal 47k ohms pulled high and disable after power on strapping. The function is selected by register setting. Default General Purpose IO. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. The function is selected by register setting. Default General Purpose IO. UART 2 Serial Output. Used to transmit serial data out to the communication link. Internal 47k ohms pulled high and disable after power on strapping. The function is selected by register setting. Default General Purpose IO. Serial Input. Used to receive serial data through th e communication link. The function is selected by register setting. GPIO25 3 DSR2# GPIO26 5 SOUT2 O8t5v-u47k GPIO27 6 SIN2 I/OOD8st5v INst5v VCC 4.5 Parallel Port Pin No. 100 Pin Name SLCT Type INst5v PWR VCC 101 PE INst5v VCC 102 BUSY INst5v VCC 103 ACK# INst5v VCC 104 105 SLIN# INIT# I/OOD12st5v I/OOD12st5v VCC VCC Description An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for detection of printer selection. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Output line for the printer initialization. Refer to the description of the parallel port for the definition of this pin in 12 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 106 ERR# INst5v VCC ECP and EPP mode. An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Parallel port data bus bit 1. Parallel port data bus bit 2. Parallel port data bus bit 3. Parallel port data bus bit 4. Parallel port data bus bit 5. Parallel port data bus bit 6. Parallel port data bus bit 7. 107 AFD# I/OOD12st5v VCC 108 STB# I/OOD12st5v VCC 109 110 111 112 113 114 115 116 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 I/O12st5v I/O12st5v I/O12st5v I/O12st5v I/O12st5v I/O12st5v I/O12st5v I/O12st5v VCC VCC VCC VCC VCC VCC VCC VCC 4.6 Hardware Monitor Pin No. 93 94 95 Pin Name VIN6 VIN5 VIN4 (VDIMM) Type AIN AIN AIN PWR VDDA VDDA VDDA 96 VIN3 (VDDA) AIN VDDA 97 98 21 22 23 24 VIN2 (VLDT) VIN1 (Vcore) FANIN1 FANCTL1 FANIN2 FANCTL2 AIN AIN INs t 5 v OOD12-5v AOUT INs t 5 v OOD12-5v VDDA VDDA VCC VCC VCC VCC Description Voltage input 6. Voltage input 5. Voltage input 4 or VDIMM input used in AMD platform. The input voltage level for timing control usage must be over 1V after voltage divider. Voltage input 3 or VDDA input used in AMD platform. The input voltage level for timing control usage must be over 1V after voltage divider. Voltage input 2 or VLDT input used in AMD platform. The input voltage level for timing control usage must be over 1V after voltage divider. Voltage Input for Vcore. The input voltage level for timing control usage must be over 0.7V. Fan 1 tachometer input. Fan 1 control output. This pin provides PWM duty-cycle output or a voltage output. Fan 2 tachometer input. Fan 2 control output. This pin provides PWM duty-cycle 13 2009 V1.1 Fintek AOUT I/OOD12st5v INs t 5 v I/OOD12st5v VCC FANCTL3* PECI_REQ# 57 TSI_CLK IBX_SCL PECI OOD12-5v AOUT OD12 I/OD125v OD12 ILv/OD8-S1 VSB VCC Feature Integration Technology Inc. F71869 GPIO40 25 FANIN3 GPIO41 26 output or a voltage output. Default General Purpose IO. Fan 3 speed input. This function is selected by register setting. Default General Purpose IO. This pin default function is GPIO function. Please take care the application if user want to implement FANCTL function. Fan 3 control output. This pin provides PWM duty-cycle output or a voltage output. PECI REQUEST signal. Selected by TIMING_GPIO trap pin. AMD TSI interface clock output. Selected by TIMING_GPIO trap pin. INTEL IBex PEAK platform hardware monitor interface clock output. Selected by register. Intel PECI hardware monitor interface. When TIMING_GPIO pin is set in GPIO function (INTEL mode). PECI function can be set by the register. AMD TSI interface data input. When TIMING_GPIO pin is set in TIMING function (AMD mode). TSI function can be set by the register. INTEL IBex PEAK platform hardware monitor interface input. When TIMING_GPIO pin is set in GPIO function (INTEL mode). IBX function can be set by the register. Thermal diode/transistor temperature sensor input for system use. Thermal diode/transistor temperature sensor input. CPU thermal diode/transistor temperature sensor input. This pin is for CPU use. Voltage sensor output. Generated PME event. It supports the PCI PME# interface. This signal allows the peripheral to request the system to wake up from the S3 state. Watch dog timer signal output. General Purpose IO. GPIO function is selected by register setting Over temperature signal output. 58 TSI_DAT ILv/OD12 VSB IBX_SDA 89 90 91 92 79 D3+(System) D2+ D1+(CPU) VREF PME# WDTRST# 63 67 GPIO14 OVT# ILv/OD12 AIN AIN AIN AOUT OD12-5v-u47k OD12-5v I/OOD12st5v OD12-5v VSB VSB VDDA VDDA VDDA VDDA VSB 4.7 ACPI Function Pins Pin No. 59 Pin Name GPIO10 Type I/OOD12st5v PWR VSB Description Default General Purpose IO. GPIO function is selected by register setting 14 2009 V1.1 Fintek PCI_RST4# IBX_SCL GPIO11 60 PCI_RST5# IBX_SDA GPIO12 RSTCON# 61 FANCTL1 GPIO15 64 LED_VSB ALERT# GPIO16 65 LED_VCC CPU_PWRGD 66 GPIO15 74 75 76 77 78 84 80 81 82 83 85 87 PCIRST1# PCIRST2# PCIRST3# S5# GPIO44 ATXPG_IN PWROK PWSIN# PWSOUT# S3# PS_ON# RSMRST# COPEN# I/OOD12st5v OD12-5v O12-5v O12-5v INst5v-u47k I/OOD12st5v INst5v OD12-5v INts5v OD12-5v-u47k INst5v-u47k OD12-5v OD12-5v-u10k INst5v VSB VSB VSB VSB VSB VBAT VSB VSB VSB VSB VBAT VBAT OOD12-5v AOUT I/OOD12st5v Feature Integration Technology Inc. F71869 O12-5v I/OD125v I/OOD12st5 O12-5v I/OD125v I/OOD12st5v VSB INs t 5 v VSB OD12-5v OD12-5v I/OOD12st5v OD12-5v OD12-5v VSB It is an output buffer of LRESET#. This function is selected by register setting. INTEL IBex PEAK platform hardware monitor interface clock output. This function is selected by register setting. Default General Purpose IO. It is an output buffer of LRESET#. This function is selected by register setting. INTEL IBex PEAK platform hardware monitor interface input. This function is selected by register setting. Default General Purpose IO. It is an output buffer of RSTCON#. This function is selected by register setting. Fan 1 control output. This pin provides PWM duty-cycle output or a voltage output. This function is selected by register setting. Default General Purpose IO. Power LED for VSB. This function is selected by register setting. Alert a signal when temperature over limit setting. This function is selected by register setting. Default General Purpose IO. Power LED for VCC. This function is selected by register setting. CPU Power Good signal output (Detected by VIN1~VIN4 level good) General Purpose IO. GPIO function is selected by register setting It is an output buffer of LRESET#. It is an output buffer of LRESET#. It is an output buffer of LRESET#. S5# signal input. Default General Purpose IO. ATX Power Good input. PWROK function, It is power good signal of VCC, which is delayed 400ms (default) as VCC arrives at 2.8V. Main power switch button input. Panel Switch Output. This pin is low active and pulse output. It is power on request output#. S3# Input is Main power on-off switch input. Power supply on-off control output. Connect to ATX power supply PS_ON# signal. Resume Reset# function, It is power good signal of VSB, which is delayed 66ms as VSB arrives at 2.8V. Case Open Detection #. This pin is connected to a specially designed low power CMOS flip-flop backed by the battery for case open state preservation during power loss. VSB VSB 15 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 4.8 Bit Select and Others Pin No. 42-44 Pin Name BITSEL_IN[1:3] GPIO[60:62] Type INst-lv PWR VSB I/OOD12st5v INst5v-u47k OD12-5v VSB I/OOD12st5v OD12-5v VSB I/OOD12st5v OD12-5v VSB I/OOD12t INst5v-u47k VSB VSB Description North bridge bit select input pins. Special level input VIH 0.9, VIL 0.6 General Purpose IO. GPIO function is selected by register setting Bit select or GPIO trap pin Active high. Timing sequence 3 of power on/off sequence pins. The external pull high resistor is required. (Detected by VIN3 level good) General Purpose IO. GPIO function is selected by register setting Active high. Timing sequence 4 of power on/off sequence pins. The external pull high resistor is required. (Detected by VIN1 level good) General Purpose IO. GPIO function is selected by register setting North bridge bit select output pins. Special level input VIH 0.9, VIL 0.6 General Purpose IO. GPIO function is selected by register setting Timing sequence or GPIO trap pin Active high. Timing sequence 2 of power on/off sequence pins. The external pull high resistor is required. (Detected by VIN4 level good) General Purpose IO. GPIO function is selected by register setting Active high. Timing sequence 1 of power on/off sequence pins. The external pull high resistor is required. (Output detected by VCCOK level good, ref Figure 16 ) General Purpose IO. GPIO function is selected by register setting Status Pin2 for S0#/S3#/S5# states application. (Default function) In S0# ST2 pin status is Tri-state. In S3# ST2 pin status is Low level. In S5# ST2 pin status is Tri-state, and can be programmed Low level. CPU SLOTOCC# input. 45 BITSEL_GPIO TIMING_3 46 GPIO00 TIMING_4 47 GPIO01 BITSEL_OUT [1:3] GPIO[63:65] 52 TIMING_GPIO 49-51 TIMING_2 53 GPIO02 TIMING_1 54 GPIO03 OD12-5v VSB I/OOD12st5v OD12-5v VSB I/OOD12st5v 55 ST2 OD12 VSB SLOTOCC# INst5v 16 2009 V1.1 Fintek GPIO04 OD12-5v Feature Integration Technology Inc. F71869 General Purpose IO. GPIO function is selected by register setting Status Pin1 for S0#/S3#/S5# states application. (Default function) In S0# ST1 pin status is Tri-state. In S3# ST1 pin status is Low level. In S5# ST1 pin status is Tri-state. General Purpose IO. GPIO function is selected by register setting Watch dog timer signal output. ATX_PWRGDSW for S0#/S3#/S5# states application. In S0# ATX_PWRGDSW pin status is Low-state. In S3# ATX_PWRGDSW pin status is Tri-state. In S5# ATX_PWRGDSW pin status is Tri-state, and can be programmed Low-state. General Purpose IO. GPIO function is selected by register setting Beep pin. ST1 56 GPIO03 WDTRST# OD12 VSB I/OOD12st5v OD12-5v ATX_ PWRGDSW 62 GPIO13 BEEP OD24-5v VSB I/OOD24st5v OD24-5v 4.9 KBC Function Pin No. 40 41 69 70 71 72 Pin Name KBRST# GA20 KDATA KCLK MDATA MCLK Type OD16-5v-u10k OD16-5v-u10k I/OD16st5V I/OD16st5V I/OD16st5V I/OD16st5V PWR VCC VCC VSB VSB VSB VSB Description Keyboard reset. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. (KBC P20) Gate A20 output. This pin is high after system reset. Internal pull high 3.3V with 10k ohms. (KBC P21) Keyboard Data. Keyboard Clock. PS2 Mouse Data. PS2 Mouse Clock. 17 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 5. Functional Description 5.1 Power Trap Operation The F71869 provides four pins for power on hardware strapping to select functions. There is a form to describe how to set the functions you want. Table1. Power on trap configuration Symbol Value Description 1 Set pin 46, 47, 53, 54 as timing sequence output TIMING_GPIO 0 Set pin 46, 47, 53, 54 as GPIO (Default) Set pin 42, 43, 44 as bit select input and pin 49, 50, 51 1 as bit select output (Default) BITSEL_GPIO 0 Set pin 42~44, 49~51 as GPIO Power on Fan speed default duty is 1 FAN40_100 40%(PWM)(Default) 0 Power on Fan speed default duty is 100%(PWM) 1 Configuration Register I/O port is 4E/4F. (Default) Config4E_2E 0 Configuration Register I/O port is 2E/2F. 1 FANCTRL1 is PWM mode. FAN1_PWM_DC 0 FANCTLR1 is DAC mode. 1 FANCTRL2 is PWM mode. FAN2_PWM_DC 0 FANCTLR2 is DAC mode. 1 FANCTRL3 is PWM mode. FAN3_PWM_DC 0 FANCTLR3 is DAC mode. Pin No. 52 45 121 124 22 24 26 5.2 Hardware Monitor For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.048V. Therefore the voltage under 2.048V (ex: 1.5V) can be directly connected to these analog inputs. The voltage higher than 2.048V should be reduced by a factor with external resistors so as to obtain the input range. Only 3VCC/VSB/VBAT is an exception for it is main power of the F71869. Therefore 3VCC/VSB/VBAT can directly connect to this chip’s power pin and need no external resistors. There are two functions in this pin with 3.3V. The first function is to supply internal analog power of the F71863 and the second function is that voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The internal serial resistors are two 150K ohm, so that the internal reduced voltage is half of +3.3V. There are four voltage inputs in the F71869 and the voltage divided formula is shown as follows: 18 2009 V1.1 Fintek VIN = V+12V × R2 R1 + R2 Feature Integration Technology Inc. F71869 where V+12V is the analog input voltage, for example. If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is within the tolerance. As for application circuit, it can be refer to the figure shown as follows. 3VCC/VSB Voltage Inputs VIN (Lower than 2.048V) VIN(Higher than 2.048V) (directly connect to the chip) (directly connect to the chip) VIN1(Max2.048V) R1 R2 150K VIN3.3 150K VREF R 10K, 1% D+ Typical BJT Connection 2N3906 Typical Thermister Connection RTHM 10K, 25 C D- 8-bit ADC with 8 mV LSB Figure 2. Hardware monitor configuration The F71869 monitors three remote temperature sensors. These sensors can be measured from -40°C to 127°C. More detail please refer register description. Table 3. Remote-sensor transistor manufacturers Manufacturer Panasonic Philips Model Number 2SB0709 2N3906 PMBT3906 5.2.1 Table Range: Table 4. Display range is from -40°C to 127°C in 2’s complement format. Temperature -40°C -1°C 1°C 90°C Digital Output 1101 1000 1111 1111 0000 0001 0101 1010 19 2009 V1.1 Fintek 127°C Open Feature Integration Technology Inc. F71869 1111 1111 1000 0000 5.2.2 Monitor Temperature from “Thermistor” The F71869 can connect three thermistors to measure environment temperature or remote temperature. The specification of thermistor should be considered to (1) β value is 3435K (2) resistor value is 10K ohm at 25°C. In the Figure 2, the thermistor is connected by a serial resistor with 10K ohm, then being connected to VREF. 5.2.3 Monitor Temperature from “Thermal diode” Also, if the CPU, GPU or external circuits provide thermal diode for temperature measurement, the F71869 is capable to these situations. The build-in reference table is for PNP 2N3906 transistor. In the Figure 2, the transistor is directly connected into temperature pins. 5.2.4 ADC Noise Filtering The ADC is integrating type with inherently good noise rejection. Micro-power operation places constraints on high-frequency noise rejection; therefore, careful PCB board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. High frequency EMI is best filtered at D+ and D- with an external 2200pF capacitor. Too high capacitance may introduce errors due to the rise time of the switched current source. Nearly all noise sources tested cause the ADC measurement to be higher than the actual temperature, depending on the frequency and amplitude. 5.2.5 Monitor Temperature from “SMBus device” F71869 provides SMBus block read/write compatible Platform Control Hub (PCH) EC SMBus protocol, and provides byte read/write protocol to read CPU and chipset thermal temperature information. For byte read /write protocol, F71869 supports 4-suit device address to read or write from device information. For block read/write, F71869 support 1 suits device address and maximum 17 byte count for read protocol to read from device information, and 4 byte count for write protocol to write information to device. 5.2.6 Monitor Temperature from “PECI” F71869 support Intel PECI1.1/PECI_Request/PECI_Available interfaces to read temperature from PECI 1.1 device. 20 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 5.2.7 Temperature HM_IRQ Signal (HM_IRQ# and PME#) There are two mode of temperature (t1 to t4) HM_IRQ function, and refer t1 to t4 temperature in the Figure 3 and 4. 1. Hysteresis mode: Over temperature event will trigger HM_IRQ# that shown as figure. In hysteresis mode, when monitored temperature exceeds the high temperature threshold value, HM_IRQ# will be asserted until the temperature goes below the hysteresis temperature. T High THYST HM_IRQ# t1 t2 t3 t4 Figure 3 2. High low limit mode: (default): When in high low limit mode HM_IRQ# for temperature is shown as figure. When monitored temperature exceeds the over-temperature threshold value, HM_IRQ# will be asserted until the temperature goes below the low limit temperature. THIGH TLOW HM_IRQ# t1 t2 t3 t4 Figure 4 5.2.8 Temperature PME# There are two mode of temperature PME# function: 1. Hysteresis mode: 21 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 PME# interrupt for temperature is shown as figure. Temperature exceeding high limit (low limit) or going below high hysteresis (low hysteresis) will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. T HIGH T Hhys T LOW T Lhys PME# (pulse mode) * * * * *Interrupt Reset when Interrupt Status Registers are written 1 Figure 5 Hysteresis mode illustration 2. High low limit mode: (default): PME# interrupt for temperature is shown as figure. Temperature exceeding high limit or going below low limit will cause an interrupt if the previous interrupt has been reset by writing “1” all the interrupt Status Register. T HIGH T LOW PME# (pulse mode) * * *Interrupt Reset when Interrupt Status Registers are written 1 Figure 6 High low limit mode illustration 22 2009 V1.1 Fintek 5.2.9 Fan Speed Count Feature Integration Technology Inc. F71869 Inputs are provided by the signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage cannot be over 5V. If the input signals from the tachometer outputs are over the 5V, the external trimming circuit should be added to reduce the voltage to obtain the input specification. Determine the fan counter according to: Count = 1.5 × 10 6 RPM In other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. As for fan, it would be best to use 2 pulses tachometer output per round. RPM = 1.5 × 10 6 Count 5.2.10 Fan Speed Control The F71869 provides 2 fan speed control methods: one is DAC FAN control and the other is PWM duty cycle. 1. DAC Fan Control The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V. The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN OPERATION VOLTAGE, 12V. The output voltage will be given as followed: Output_voltage (V) = 3.3 × Programmed 8bit Register Value 255 And the suggested application circuit for DAC fan control would be: +12V R 4.7K 8 3 DC OUTPUT VOLTAGE 2 U1A 1 LM358 PMOS Q1 D1 1N4148 R 4.7K JP1 + 4 R 10K C 47u 3 2 1 CON3 R C 0.1u 27K R 10K F ANIN MONITOR R 3.6K Figure 7 DAC fan control application circuit 23 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 2. PWM duty Fan Control The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Duty_cycle(%) = Programmed 8bit Register Value × 100% 255 +12V R1 R2 D G NMOS S + C FAN PNP Transistor Figure 8 +12/5V PWM fan control application circuit 5.2.11 Fan Speed Control Mechanism There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto mode 3. Linear auto mode. More detail, please refer the description of registers. Each fan can be controlled by up to 8 kinds of temperature input. (1)D1+ temperature (2)D2+ temperature (3) D3+ temperature (4) PECI temperature (5) 4 suits SMBus master temperature. Please refer below structure diagram. After the T0 ~T7 setting ready, select S1 ~ S4 temperature machine from T0 ~ T7, these 4-set temperature data are for maximum temperature comparison. 24 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 PECI D1+ T (T1) D2+ T (T2) D3+ T (T2) IBX Byte1 IBX Byte3:2 IBX Byte4 IBX Byte5 Expect speed1 Fan1 Expect speed 2 Fan2 Expect speed 3 Fan3 [ Figure 9 Relative temperature fan control 1. Manual mode For manual mode, it generally acts as software fan speed control. 2. Stage auto mode At this mode, the F71869 provides automatic fan speed control related to temperature variation of CPU/GPU or the system. The F71869 can provide two temperature boundaries and three intervals, and each interval has its related fan speed PWM duty. All these values should be set by BIOS first. Take figure 6-10 as example. When temperature boundaries are set as 45 and 75°C and there are three intervals. The related desired fan speed for every interval is 40%, 80% and 100% (fixed). When the temperature is within 45~75’C, the fan speed will follow 80% PWM duty and that define in registers. It can be said that the fan will be turned on with a specific speed set by BIOS and automatically controlled with the temperature variation. The F71869 will take charge of all the fan speed control without software support. 25 2009 V1.1 Fintek Temperature Feature Integration Technology Inc. F71869 PWM Duty 100% 75 Degree C 80% 45 Degree C 40% Temperature Fan Speed Figure 10 Stage mode fan control illustration-1 Below is a sample for Stage auto mode: Set temperature as 60°C, 40°C and Duty as 100%, 70%, 50% PWM duty 100% 60 Degree C hysteresis 57 Degree C 40 Degree C 50% 70% Temp. Fan Speed a b c d Figure 11 Stage mode fan control illustration-2 a. Once temp. is under 40°C, the lowest fan speed keeps 50% PWM duty b. Once temp. is over 40°C,60°C, the fan speed will vary from 70% to 100% PWM duty and increase with temperature c. Once temp. keeps in 55°C, fan speed keeps in 70% PWM duty to 70% PWM duty and stays there. 3. Linear auto mode Otherwise, F71869 supports linear auto mode. Below has an example to describe this mode. More detail, please refer the register description. Set temperature as 70°C, 40°C and Duty as 100%, 70%, 40% d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 57°C, fan speed reduces 26 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 PWM duty 70 Degree C hysteresis 65 Degree C 100% 70% 40 Degree C Temp. Fan Speed 40% a b c d Figure 12 Linear mode fan control illustration a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty b. Once temp. is over 40°C and under 70°C, the fan speed will vary from 40% to 70% PWM duty and linearly increase with temp. variation. is 1sec. c. Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full speed) d. If set the hysteresis as 5°C (default is 4°C), once temp reduces under 65°C (not 70°C), fan speed reduces from 100% PWM duty and decrease linearly with temp.. The temp.-fan speed monitoring and flash interval 5.2.12 FAN_FAULT# Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to PWM duty-cycle which should be able to turn on the fan. There are two conditions may cause the FAN_FAULT# event. (1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected count in time. 11 sec(default) Current Fan Count Expected Fan Count 100% Duty-cycle Fan_Fault# Figure 13 FAN_FAULT# event (2). After the period of detecting fan full speed, PWM_Duty > Min. Duty, fan count is still in 0xFFF. 27 2009 V1.1 Fintek 5.3 Feature Integration Technology Inc. F71869 ACPI Function The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a computer. It lets computer manufacturer and user to determine the computer’s power usage dynamically. There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The other two are called sleep states and reflect different power consumption when power-down. S3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. S5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. Take S3 and S5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3. It is anticipated that only the following state transitions may happen: S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5. Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is necessary to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only as an immediate state during state transition from S5→S0. It isn’t allowed in the normal state transition. The below diagram described the timing, the always on and always off, keep last state could be set in control register. In keep last state mode, one register will keep the status of before power loss. If it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V Figure 14 Default timing: Always off 28 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 VBAT VSB RSMRST# S3# PS_ON# PSIN# PSOUT# VCC3V Figure 15 Optional timing: Always on PCI Reset and PWROK Signals The F71869 supports 5 output buffers for 5 reset signals. +3.3V Delay PWROK LRESET# Buffer PCIRST1~5# ATXPG So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as VCC arrives 2.8V, and the delay timing can be programmed by register (100ms ~ 400ms). An additional delay could be added to PWROK (0ms, 100ms, 200ms and 400ms). Default is 0ms. If RSTCION# and PCIRST4#/PCIRST5# are enabled, RSTCON# could be programmed to be asserted via PWROK or PCIRST4#/PCIRST5#. 5.4 Timing Control Sequence The F71869 offers 4 timing pins which are designed for AMD platform power sequence control including VDIMM, VDDA, Vcore, and VLDT (default) or other timing application purposes. All the timings on/off are relative to S3#/S5# and can be programmed by the register 0x0AF7. As shown in the Figure 20, the default timings of TIMING_1~4 are displayed in blue lines, and all the timings are enabled in the 29 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 S0 state except TIMING_1. However, TIMING_2~4 can be programmed to enable in the S3 state, and TIMING_1 can also be programmed to disable in the S3 state, like the dotted blue line shown in the Figure 20. VDDOK_D400 is the PWROK delay timing from VDD3VOK. The default setting is that delay 400ms, there are 100ms, 200ms, and 300ms for option. It can be set in the register 0x0AF5. S5 S5# S3# PSON# ATXPWGD VDDOK_D400 TIMING_1 TIMING_2 TIMING_3 TIMING_4 CPU_PWRGD S0 S3 S0 S3 S5 Figure 16 Timing on/off sequence 5.5 ST1, ST2 and ATX_PWRGDSW Timing The F71869 provides three additional timing switching pins which are named as ST1, ST2 and ATXPWRGDSW. They can be applied in the certain applications about power switch which depends on the ACPI states. The detail timing can be referred in the following diagrams. The default timing of ATX_PWRGDSW in the S5 state is low, but it can be programmed high by the register 0x0AF6. 30 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 S5 S5# S3# 10us 10us S0 S3 PSON# VDD3V VDDOK VDDOK_D400 ATXPG PWROK ATX_PWRGDSW could be programmed low 400ms ST1 ST2 could be programmed low Figure 17 Timing chart of S5->S0->S3 31 2009 V1.1 Fintek S3 S5# S3# 10us Feature Integration Technology Inc. F71869 S0 S5 10us PSON# VDD3V VDDOK VDDOK_D400 ATXPG PWROK ATX_PWRGDSW ST1 ST2 could be programmed low 400ms Figure 17 Timing chart of S3->S0->S5 5.6 AMD TSI and Intel PECI Function The F71869 provides Intel PECI/AMD TSI interfaces for new generational CPU temperature sensing. In AMDSI interface, there are SIC and SID signals for temperature information reading from AMD CPU. The SIC signal is for clocking use, the other is for data transferring. More details, please refer register description. VDDIO 300 300 TSI_CLK AMD CPU TSI_CLK TSI_DAT F71869 TSI_DAT Figure 18 AMD TSI typical application 32 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 In Intel PECI interface, the F71869 can connect to CPU directly. The F71869 can read the temperature data from CPU, than the fan control machine of F71869 can implement the Fan to cool down CPU temperature. The application circuit is as below. More details, please refer the register description. Intel CPU PECI avoid pre-BIOS floating F71869 PECI 100K Figure 19 INTEL PECI typical application 33 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 5. Register Description The configuration register is used to control the behavior of the corresponding devices. To configure the register, using the index port to select the index and then writing data port to alter the parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA to the index port. Following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 -o 4e aa (enable configuration) (disable configuration) The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their default value. Please refer each device chapter if you want more detail information. Global Control Registers “-“ Reserved or Tri-State Global Control Registers Register 0x[HEX] 02 07 20 21 22 23 24 25 26 27 28 29 2A Register Name Software Reset Register Logic Device Number Register (LDN) Chip ID Register Chip ID Register Reserved Reserved Reserved Software Power Down Register UART IRQ Sharing Register Configuration Port Select Register Multi-function Select Register1 Multi-function Select Register2 Multi-function Select Register3 Default Value MSB 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1/0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1/0 1 1 LSB 0 0 0 0 0 0 1/0 1 1 34 2009 V1.1 Fintek 2B 2C 2D 2E 2F Multi-function Select Register4 VBAT Dummy Register Wakeup Control Register Reserved Reserved Feature Integration Technology Inc. F71869 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 - Device Configuration Registers “-“ Reserved or Tri-State FDC Device Configuration Registers (LDN CR00) Register 0x[HEX] 30 60 61 70 74 F0 F2 F4 Register Name FDC Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register DMA Channel Select Register FDD Mode Register FDD Drive Type Register FDD Selection Register Default Value MSB 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 1 1 0 LSB 1 1 0 0 0 0 1 0 UART1 Device Configuration Registers (LDN CR01) Register 0x[HEX] 30 60 61 70 F0 Register Name UART1 Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register RS485 Enable Register Default Value MSB 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 1 1 0 0 LSB 1 1 0 0 - UART2 Device Configuration Registers (LDN CR02) Register 0x[HEX] 30 60 61 70 F0 Register Name UART2 Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register RS485 Enable Register Default Value MSB 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 LSB 1 0 0 1 - 35 2009 V1.1 Fintek F1 SIR Mode Control Register Feature Integration Technology Inc. F71869 0 0 0 1 0 0 Parallel Port Device Configuration Registers (LDN CR03) Register 0x[HEX] 30 60 61 70 74 F0 Register Name Parallel Port Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register DMA Channel Select Register PRT Mode Select Register Default Value MSB 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 LSB 1 1 0 1 1 0 Hardware Monitor Device Configuration Registers (LDN CR04) Register 0x[HEX] 30 60 61 70 Register Name H/W Monitor Device Enable Register Base Address High Register Base Address Low Register IRQ Channel Select Register Default Value MSB 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 LSB 1 0 1 0 KBC Device Configuration Registers (LDN CR05) Register 0x[HEX] 30 60 61 70 72 F0 FE FF Register Name KBC Device Enable Register Base Address High Register Base Address Low Register KB IRQ Channel Select Register Mouse IRQ Channel Select Register Clock Select Register Swap Register User Wakeup Code Register Default Value MSB 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 LSB 1 0 0 1 0 1 1 1 GPIO Device Configuration Registers (LDN CR06) Register 0x[HEX] 30 60 61 70 Register Name GPIO Device Enable Register Base Address High Register Base Address Low Register GPIRQ Channel Select Register Default Value MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 0 0 0 0 36 2009 V1.1 Fintek F0 F1 F2 F3 E0 E1 E2 E3 E4 E5 E6 D0 D1 D2 D3 C0 C1 C2 B0 B1 B2 B3 A0 A1 A2 A3 90 91 92 93 GPIO Output Enable Register GPIO Output Data Register GPIO Pin Status Register GPIO Drive Enable Register GPIO1 Output Enable Register GPIO1 Output Data Register GPIO1 Pin Status Register GPIO1 Drive Enable Register GPIO1 PME Enable Register GPIO1 Detect Edge Select Register GPIO1 PME Status Register GPIO2 Output Enable Register GPIO2 Output Data Register GPIO2 Pin Status Register GPIO2 Drive Enable Register GPIO3 Output Enable Register GPIO3 Output Data Register GPIO3 Pin Status Register GPIO4 Output Enable Register GPIO4 Output Data Register GPIO4 Pin Status Register GPIO4 Drive Enable Register GPIO5 Output Enable Register GPIO5 Output Data Register GPIO5 Pin Status Register GPIO5 Drive Enable Register GPIO6 Output Enable Register GPIO6 Output Data Register GPIO6 Pin Status Register GPIO6 Drive Enable Register Feature Integration Technology Inc. F71869 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 BSEL Device Configuration Registers (LDN CR07) Register 0x[HEX] 30 60 Register Name BSEL Device Enable Register Base Address High Register Default Value MSB 0 0 0 0 0 0 0 LSB 0 0 37 2009 V1.1 Fintek 61 F0 F2 F3 F4 F5 F6 F7 Base Address Low Register Watchdog Timer Enable Register BUS Manual Register Key Data Register BUSIN Status Register WDT Unit Select Register WDT Count Register Watchdog Timer PME Register Feature Integration Technology Inc. F71869 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 PME and ACPI Device Configuration Registers (LDN CR0A) Register 0x[HEX] 30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FE FF Register Name PME Device Enable Register PME Event Enable Register 1 PME Event Enable Register 2 PME Event Status Register 1 PME Event Status Register 2 Keep Last State Select Register VDDOK Delay Select Register PCIRST Control Register Power Sequence Control Register LED VCC Control Register LED VSB Control Register RI De-bounce Select Register ACPI Test Mode Register Default Value MSB 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 LSB 0 0 0 0 0 1 0 0 0 0 0 6.1 Global Control Registers 6.1.1 Software Reset Register ⎯ Index 02h Bit 7-1 0 Name Reserved SOFT_RST R/W Default R/W 0 Reserved Write 1 to reset the register and device powered by VDD ( VCC ). Description 6.1.2 Logic Device Number Register (LDN) ⎯ Index 07h Bit Name R/W Default Description 38 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 00h: Select FDC device configuration registers. 01h: Select UART 1 device configuration registers. 02h: Select UART 2 device configuration registers. 03h: Select Parallel Port device configuration registers. 7-0 LDN R/W 00h 04h: Select Hardware Monitor device configuration registers. 05h: Select KBC device configuration registers. 06h: Select GPIO device configuration registers. 07h: Select BSEL device configuration registers. 0ah: Select PME & ACPI device configuration registers. 6.1.3 Reserved ⎯ Index 20h~24h Bit 7-0 Name Reserved R/W Default R Reserved Description 6.1.4 UART IRQ Sharing Register ⎯ Index 26h Bit 7 6-3 2 Name CLK24M_SEL Reserved TX_DEL_1BIT R/W Default R/W R/W 0 0 0: CLKIN is 48MHz 1: CLKIN is 24MHz Reserved. 0: UART transmits data immediately after writing THR. 1: UART transmits data delay one bit time after writing THR. 0: PCI IRQ sharing mode (low level). 1: ISA IRQ sharing mode (low pulse). 0: disable IRQ sharing of two UART devices. 1: enable IRQ sharing of two UART devices. Description 1 IRQ_MODE R/W 0 0 IRQ_SHAR R/W 0 6.1.5 Configuration Port Select Register ⎯ Index 27h Bit 7-5 Name Reserved R/W Default Reserved. Description 39 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 0: The configuration register port is 2E/2F. 4 PORT_4E_EN R/W 1: The configuration register port is 4E/4F. This register is power on trapped by SOUT1/ Config4E_2E. Pull down to select port 2E/2F. 3-2 Reserved Reserved. This bit is the pin status of BITSEL_GPIO pin. 1 BSEL_EN R 0: Disable BSEL functions and enable GPIO6. 1: Enable BSEL functions and disable GPIO6. This bit is the pin status of TIMING_GPIO pin. 0 TIMING_EN R 0: Disable power sequence control. 1: Enable power sequence control. 6.1.6 Multi-Function Select Register 1⎯ Index 28h (Powered by VSB3V) Bit 7-6 Name Reserved R/W Default R/W 0 Reserved 0:ST1/GPIO05/WDTRST# 5 PWR_ST1_EN R/W 1 functions as GPIO05/WDTRST# Description determined by GPIO05_EN. 1: ST1/GPIO05/WDTRST# functions as ST1. 0:ST2/SLOTOCC#/GPIO04 functions as SLOTOCC#/GPIO04 4 PWR_ST2_EN R/W 1 determined by GPIO04_EN. 1: ST2/SLOTOCC#/GPIO04 functions as ST2. 0: ST1/GPIO05/WDTRST# functions as WDTRST if PWR_ST1_EN is 3 GPIO05_EN R/W 1 not set. 1: ST1/GPIO05/WDTRST# functions as GPIO05 is PWR_ST1_EN is not set. 0:ST2/SLOTOCC#/GPIO04 functions as SLOTOCC# if 2 GPIO04_EN R/W 0 PWR_ST2_EN is not set. 1: ST2/SLOTOCC#/GPIO04 functions as GPIO04 if PWR_ST2_EN is not set. 1-0 Reserved R/W 0 Reserved 40 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 6.1.7 Multi-Function Select Register 2 ⎯ Index 29h (Powered by VSB3V) Bit Name R/W Default Description CPU_PWRGD/GPIO17function select. 7 GPIO17_EN R/W 0 0: The pin function is CPU_PWRGD. 1: The pin function is GPIO17. GPIO16/LED_VCC function select. 6 GPIO16_EN R/W 1 0: The pin function is LED_VCC. 1: The pin function is GPIO16. GPIO15/LED_VSB/ALERT# function select. If LED_VSB_EN is set, the ping function is LED_VSB, otherwise the 5 GPIO15_EN R/W 1 pin function is determined by this bit: 0: The pin function is ALERT#. 1: The pin function is GPIO15. WDTRST#/GPIO14 function select. 4 GPIO14_EN R/W 0 0: The pin function is WDTRST#. 1: The pin function is GPIO14. ATX_PWRGDSW/GPIO13/BEEP function select. If ATX_PWRGDSW_EN is set , the ping function is ATX_PWRGDSW, 3 GPIO13_EN R/W 1 otherwise the pin function is determined by this bit: 0: The pin function is BEEP. 1: The pin function is GPIO13. RSTCON#/GPIO12 function select. 2 GPIO12_EN R/W 1 0: The pin function is RSTCON#. 1: The pin function is GPIO12. PCIRST5#/GPIO11/IBX_SDA function select. If IBX_ALT_EN is set , the ping function is IBX_SDA, otherwise the 1 GPIO11_EN R/W 1 pin function is determined by this bit: 0: The pin function is PCIRST5#. 1: The pin function is GPIO11. 41 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 PCIRST4#/GPIO10/IBX_SCL function select. If IBX_ALT_EN is set , the ping function is IBX_SCL, otherwise the pin 0 GPIO10_EN R/W 1 function is determined by this bit: 0: The pin function is PCIRST4#. 1: The pin function is GPIO10. 6.1.8 Multi-Function Select Register 3 ⎯ Index 2Ah (Powered by VSB3V) Bit 7 Name Reserved R/W Default R/W 0 Reserved Alternative IBX pin enable. 6 IBX_ALT_EN R/W 0 0: Disable IBX alternative pins. 1: Enable IBS alternative pins. See GPIO11_EN and GPIO10_EN for detail. 5 LED_VSB_EN R/W 0 0: disable LED_VSB from GPIO15/LED_VSB/ALERT# 1: Enable LED_VSB from GPIO15/LED_VSB_ALERT#. RSTCON# Enable Register: 4 RSTCON_PIN_EN R/W 0 0: The pin function of RSTCON#/GPIO12 is GPIO12. 1: The pin function of RSTCON#/GPIO12 is RSTCON#. ATX_PWRGDSW Enable Register: 3 ATX_ PWRGDSW _EN R/W 1 0: The pin function of ATX_PWRGDSW /GPIO13/BEEP is determined by GPIO13_EN. 1: The pin function is ATX_PWRGDSW. 2 1 0 FDC_GP_EN UR2_GP_EN2 UR2_GP_EN1 R/W R/W R/W 1 1 1 Set “1” will disable FDC and change the FDC pins to GPIOs. Set “1” will change UART2 Modem control pins to GPIOs. Set “1” will change UART2 SIN/SOUT pins to GPIOs. Set UR2_GP_EN1 and UR2_GP_EN2 will also disable UART2. Description 6.1.9 Multi-Function Select Register 4 ⎯ Index 2Bh (Powered by VSB3V) Bit Name R/W Default Description 42 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 PSON#/GPIO47 function select. 7 GPIO47_EN R/W 0 0: The pin function is PSON#. 1: The pin function is GPIO47. PWSOUT#/GPIO46 function select. 6 GPIO46_EN R/W 0 0: The pin function is PWSOUT#. 1: The pin function is GPIO46. PWSIN#/GPIO45 function select. 5 GPIO45_EN R/W 0 0: The pin function is PWSIN#. 1: The pin function is GPIO45. ATXPG_IN/GPIO44 function select. 4 GPIO44_EN R/W 0 0: The pin function is ATXPG_IN. 1: The pin function is GPIO44. GPIO43/IRRX function select. 3 GPIO43_EN R/W 1 0: The pin function is IRRX. 1: The pin function is GPIO43. GPIO42/IRTX function select. 2 GPIO42_EN R/W 1 0: The pin function is IRTX. 1: The pin function is GPIO42. FANCTRL3/GPIO41 function select. 1 GPIO41_EN R/W 1 0: The pin function is FANCTRL3. 1: The pin function is GPIO41. FANIN3/GPIO40 function select. 0 GPIO40_EN R/W 1 0: The pin function is FANIN3. 1: The pin function is GPIO40. 6.1.10 VBAT Dummy Register ⎯ Index 2Ch (Powered by VBAT) Bit 7-0 Name Reserved R/W Default R/W 0 Reserved Description 6.1.11 Wakeup Control Register ⎯ Index 2Dh (Powered by VBAT) Bit Name R/W Default Description 43 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 7 6 5 4 3 SLOT_PWR_SEL R/W VSBOK_HYS_DIS R/W VSBOK_LEVEL _SEL KEY_SEL_ADD WAKEUP_EN R/W R/W R/W 0 0 1 0 1 0: SLOTOCC# is pull-up to VSB3V. 1: SLOTOCC# is pull-up to VBAT. Set “1” to disable VSBOK hysteresis. 0: The VSB3V Power good level is 3.05V typically. 1: The VSB3V Power good level is 2.8V typically This bit is added to add more wakeup key function. 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up. This registers select the keyboard wake up key. Accompanying with KEY_SEL_ADD, there are eight wakeup keys: KEY_SEL_ADD 0 0 2-1 KEY_SEL R/W 00 0 0 1 1 1 1 KEY_SEL 00 01 10 11 00 01 10 11 Ctrl + Esc Ctrl + F1 Ctrl + Space Any Key Windows Wakeup Windows Power Ctrl + Alt + Space Space Wakeup Key This register selects the mouse wake up key. 0 MO_SEL R/W 0 0: Wake up by click. 1: Wake up by click and movement. 6.1.12 Reserved ⎯ Index 2Eh ~ 2Fh Bit 7-0 Name Reserved R/W Default R/W 0 Reserved Description 44 2009 V1.1 Fintek 6.2 FDC Registers (CR00) Feature Integration Technology Inc. F71869 6.2.1 FDC Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved FDC_EN R/W Default R/W 1 Reserved 0: disable FDC. 1: enable FDC. Description 6.2.2 Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of FDC base address. 6.2.3 Base Address Low Register ⎯ Index 61h Bit 7-0 Name R/W Default F0h Description The LSB of FDC base address. BASE_ADDR_LO R/W 6.2.4 IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELFDCIRQ R/W Default R/W 06h Reserved. Select the IRQ channel for FDC. Description 6.2.5 DMA Channel Select Register ⎯ Index 74h Bit 7-3 2-0 Name Reserved SELFDCDMA R/W Default R/W 010 Reserved. Select the DMA channel for FDC. Description 6.2.6 FDD Mode Register ⎯ Index F0h Bit 7 6-5 4 Name FDC_SW_PD Reserved FDC_SW_WP R/W Default R/W R/W 0 0 Description Write “1” to software power down FDC. Reserved. Write “1” to this bit will force FDC to write protect. Otherwise, write protect is controlled by hardware pin WP#. 45 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 00: Model 30 mode. 3-2 IF_MODE R/W 11 01: PS/2 mode. 10: Reserved. 11: AT mode (default). 1 FDMAMODE R/W 1 0: enable burst mode. 1: non-busrt mode (default). 0: normal floppy mode (default). 1: enhanced 3-mode FDD. 0 EN3MODE R/W 0 6.2.7 FDD Drive Type Register ⎯ Index F2h Bit 7-2 1-0 Name Reserved FDD_TYPE R/W Default R/W 11 Reserved. FDD drive type. Description 6.2.8 FDD Selection Register ⎯ Index F4h Bit 7-5 Name Reserved R/W Default Reserved. Data rate table select, refer to table A. 00: select regular drives and 2.88 format. 4-3 FDD_DRT R/W 00 01: 3-mode drive. 10: 2 mega tape. 11: reserved. 2 1-0 Reserved FDD_DT R/W 00 Reserved. Drive type select, refer to table B. Description TABLE A Data Rate Table Select FDD_DRT[1] FDD_DRT[0] Data Rate DATARATE1 0 0 0 0 1 1 DATARATE0 0 1 0 1 Selected Data Rate MFM 500K 300K 250K 1Meg FM 250K 150K 125K --1 0 0 1 DENSEL 46 2009 V1.1 Fintek 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 Feature Integration Technology Inc. F71869 500K 500K 250K 1Meg 500K 2Meg 250K 1Meg 250K 250K 125K --250K --125K --1 0 0 1 1 0 0 1 TABLE B Drive Type FDD_DT1 FDD_DT0 0 0 DRVDEN0 DENSEL Remark 4/2/1 MB 3.5” 2/1 MB 5.25” 1/1.6/1 (3-Mode ) 0 1 1 1 0 1 DATARATE1 DENSEL# DATARATE0 MB 3.5” 6.3 UART1 Registers (CR01) 6.3.1 UART 1 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR1_EN R/W Default R/W 1 Reserved 0: disable UART 1. 1: enable UART 1. Description 6.3.2 Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of UART 1 base address. 6.3.3 Base Address Low Register ⎯ Index 61h Bit Name R/W Default Description 47 2009 V1.1 Fintek 7-0 BASE_ADDR_LO R/W F8h Feature Integration Technology Inc. F71869 The LSB of UART 1 base address. 6.3.4 IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELUR1IRQ R/W Default R/W 4h Reserved. Select the IRQ channel for UART 1. Description 6.3.5 RS485 Enable Register ⎯ Index F0h Bit 7-6 5 4 3-0 Name Reserved RS485_INV RS485_EN Reserved R/W Default R/W 0 Reserved. Write “1” will invert the RTS# if RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# low when transmitting data. Reserved. Description 6.4 UART2 Registers (CR02) 6.4.1 UART 2 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved UR2_EN R/W Default R/W 1 Reserved 0: disable UART 2. 1: enable UART 2. Description 6.4.2 Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 02h Description The MSB of UART 2 base address. 6.4.3 Base Address Low Register ⎯ Index 61h Bit 7-0 Name R/W Default F8h Description The LSB of UART 2 base address. BASE_ADDR_LO R/W 6.4.4 IRQ Channel Select Register ⎯ Index 70h Bit Name R/W Default Description 48 2009 V1.1 Fintek 7-4 3-0 Reserved SELUR2IRQ R/W 3h Reserved. Feature Integration Technology Inc. F71869 Select the IRQ channel for UART 2. 6.4.5 RS485 Enable Register ⎯ Index F0h Bit 7-6 5 4 Name Reserved RS485_INV RS485_EN R/W Default R/W 0 Reserved. Write “1” will invert the RTS# if RS485_EN is set. 0: RS232 driver. 1: RS485 driver. Auto drive RTS# low when transmitting data. 0: No reception delay when SIR is changed form TX to RX. 3 RXW4C_IR R/W 0 1: Reception delays 4 characters time when SIR is changed form TX to RX. 0: No transmission delay when SIR is changed form RX to TX. 2 TXW4C_IR R/W 0 1: Transmission delays 4 characters time when SIR is changed form RX to TX. 1-0 Reserved Reserved. Description 6.4.6 SIR Mode Control Register ⎯ Index F1h Bit 7 6 5 Name Reserved Reserved Reserved R/W Default Reserved. Reserved. Reserved. 00: disable IR function. 4-3 IRMODE R/W 00 01: disable IR function. 10: IrDA function, active pulse is 1.6uS. 11: IrDA function, active pulse is 3/16 bit time. 0: SIR is in full duplex mode for loopbak test. TXW4C_IR and 2 HDUPLX R/W 1 RXW4C_IR are of no use. 1: SIR is in half duplex mode. 1 TXINV_IR R/W 0 0: IRTX is in normal condition. 1: inverse the IRTX. 0: IRRX is in normal condition. 1: inverse the IRRX. Description 0 RXINV_IR R/W 0 49 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 6.5 Parallel Port Register (CR03) 6.5.1 Parallel Port Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved PRT_EN R/W Default R/W 1 Reserved 0: disable Parallel Port. 1: enable Parallel Port. Description 6.5.2 Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 03h Description The MSB of Parallel Port base address. 6.5.3 Base Address Low Register ⎯ Index 61h Bit 7-0 Name R/W Default 78h Description The LSB of Parallel Port base address. BASE_ADDR_LO R/W 6.5.4 IRQ Channel Select Register ⎯ Index 70h Bit 7-5 3-0 Name Reserved SELPRTIRQ R/W Default R/W 7h Reserved. Select the IRQ channel for Parallel Port. Description 6.5.5 DMA Channel Select Register ⎯ Index 74h Bit 7-5 4 3 2-0 Name Reserved R/W Default 0 011 Reserved. 0: non-burst mode DMA. 1: enable burst mode DMA. Reserved. Select the DMA channel for Parallel Port. Description ECP_DMA_MODE R/W Reserved SELPRTDMA R/W 6.5.6 PRT Mode Select Register ⎯ Index F0h Bit Name R/W Default Description 50 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Interrupt mode in non-ECP mode. 7 SPP_IRQ_MODE R/W 0 0: Level mode. 1: Pulse mode. 6-3 ECP_FIFO_THR R/W 1000 ECP FIFO threshold. 000: Standard and Bi-direction (SPP) mode. 001: EPP 1.9 and SPP mode. 010: ECP mode (default). 2-0 PRT_MODE R/W 010 011: ECP and EPP 1.9 mode. 100: Printer mode. 101: EPP 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP1.7 mode. 6.6 Hardware Monitor Registers (CR04) 6.6.1 Hardware Monitor Configuration Registers ⎯ Index 30h Bit 7-1 0 Name Reserved HM_EN R/W Default R/W 1 Reserved 0: disable Hardware Monitor. 1: enable Hardware Monitor. Description 6.6.2 Base Address High Register ⎯ Index 60h Bit Name R/W Default R/W 02h Description The MSB of Hardware Monitor base address. 7-0 BASE_ADDR_HI 6.6.3 Base Address Low Register ⎯ Index 61h Bit Name R/W Default R/W 95h Description The LSB of Hardware Monitor base address. 7-0 BASE_ADDR_LO 6.6.4 IRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELHMIRQ R/W Default R/W 0000 Reserved. Select the IRQ channel for Hardware Monitor. Description 51 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Before the device registers, the following is a register map order which shows a summary of all registers. Please refer each one register if you want more detail information. Register CR01 ~ CR03 Register CR0A ~ CR0F Register CR10 ~ CR4F Register CR60 ~ CR8E Register CR90 ~ CRDF Configuration Registers PECI/SST/TSI Control Register Voltage Setting Register Temperature Setting Register Fan Control Setting Register Fan1 Detail Setting CRA0 ~ CRAF Fan2 Detail Setting CRB0 ~ CRBF Fan3 Detail Setting CRC0 ~ CRCF 6.6.5 Configuration Register ⎯ Index 01h Bit 7-3 2 1 Name Reserved POWER_DOWN FAN_START R/W Default R/W R/W 0 0 1 Reserved Hardware monitor function power down. Set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. Set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. Description 0 V_T_START R/W 1 6.6.6 Configuration Register ⎯ Index 02h Bit 7 6 Name Reserved R/W Default R/W 0 0 Dummy register. 0: Disable case open event output via BEEP. 1: Enable case open event output via BEEP. 00: The OVT# will be low active level mode. 01: The OVT# will be high active level mode. 10: The OVT# will indicate by 1Hz LED function. 11: The OVT# will indicate by (400/800HZ) BEEP output. Dummy register. 0: Disable case open event output via PME. 1: Enable case open event output via PME. 00: The ALERT# will be low active level mode. 01: The ALERT# will be high active level mode. 10: The ALERT# will indicate by 1Hz LED function. 11: The ALERT# will indicate by (400/800HZ) BEEP output. Description CASE_BEEP_EN R/W 5-4 3 2 OVT_MODE Reserved CASE_SMI_EN R/W R/W R/W 0 0 0 1-0 ALERT_MODE R/W 0 52 2009 V1.1 Fintek 6.6.7 Configuration Register ⎯ Index 03h Bit 7-1 0 Name Reserved CASE_STS R/W Default R/W R/W 0 0 Reserved Feature Integration Technology Inc. F71869 Description Case open event status. Write 1 to clear if case open event cleared. (This bit is powered by VBAT.) 6.6.8 Configuration Register ⎯ Index 08h Bit Name R/W Default Description When AMD TSI or Intel PCH SMBus is enabled, this byte is used as 7-1 SMBUS_ADDR R/W 7’h26 SMBUS_ADDR. SMBUS_ADDR[7:1] is the slave address sent by the embedded master to fetch the temperature. 0 Reserved Reserved 6.6.9 Configuration Register ⎯ Index 09h Bit 7-1 0 Name I2C_ADDR Reserved R/W Default R/W R/W 0 0 Description I2C_ADDR[7:1] is the slave address sent by the embedded master when using a block write command Reserved 6.6.10 Configuration Register ⎯ Index 0Ah Bit 7 Name BETA_EN R/W Default R/W 0 Description 0: disable the T1 beta compensation. 1: enable the T1 beta compensation. 0: AMD model. 1: Intel model. Reserved. PECI (Vtt) voltage select. 00: Vtt is 1.23V 3-2 VTT_SEL R/W 0 01: Vtt is 1.13V 10: Vtt is 1.00V 11: Vtt is 1.00V 6 5-4 INTEL_MODEL Reserved R/W - 1 0 53 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 0: Disable the TSI function via PECI/PECI_REQ# or PCI_RST4#/PCI_RST5# pins. 1: Enable the TSI function via PECI/PECI_REQ# or PCI_RST4#/PCI_RST5# pins. This bit accompanies with INTEL_MODEL, IBX_ALT_EN, PECI_EN, and it determines the availability of AMD TSI, Intel PCH SMBus, or PECI. 1 TSI_EN R/W 0 INTEL _MOD EL 0 0 1 1 1 0 1 0 1 1 X X 1 1 0 X X X 1 X N N Y Y N N Y N N N TSI_ EN PECI_ EN IBX_ALT_ EN PE CI AMD TSI Intel PCH SMBus N N N Y Y 0 PECI_EN R/W 0 0: Disable PECI function via PECI/PECI_REQ# pins 1: Enable PECI function via PECI/PECI_REQ# pins 6.6.11 Configuration Register ⎯ Index 0Bh Bit Name R/W Default Description Select the Intel CPU socket number. 0000: no CPU presented. PECI host will use Ping() command to find CPU address. 7-4 CPU_SEL R/W 0 0001: CPU is in socket 0, i.e. PECI address is 0x30. 0010: CPU is in socket 0, i.e. PECI address is 0x31. 0100: CPU is in socket 0, i.e. PECI address is 0x32. 1000: CPU is in socket 0, i.e. PECI address is 0x33. Others are reserved. 3-1 0 Reserved DOMAIN1_EN R/W 0 0 Reserved. If the CPU is selected as dual core. Set this register 1 to read the temperature of domain1. 54 2009 V1.1 Fintek 6.6.12 Configuration Register ⎯ Index 0Ch Bit Name R/W Default Feature Integration Technology Inc. F71869 Description TCC Activation Temperature. When PECI is enabled, the absolute value of CPU temperature is 7-0 TCC_TEMP R/W 8’h55 calculated by the equation: CPU_TEMP = TCC_TEMP + PECI Reading. The range of this register is -128 ~ 127. 6.6.13 Configuration Register ⎯ Index 0Dh Bit Name R/W Default Description TSI Temperature offset for CPU 7-0 TSI_OFFSET R/W 8’h00 When AMD TSI or Intel PCH SMBus is enabled, this byte is used as the offset to be added to the temperature reading of CPU. 6.6.14 Configuration Register ⎯ Index 0Fh Bit 7-6 5 4-2 1-0 Name Reserved PECI_REQ_EN Reserved DIG_RATE_SEL R/W Default R/W R/W 0 1 0 0 Reserved. 0: disable the PECI_REQ# function. 1: Enable the PECI_REQ# function. Reserved. Digital temperatures monitoring rate for PECI, AMD TSI, or Intel PCH SMBus. The rate is calculated by 20Hz/(DIG_RATE_SEL + 1). Description 6.6.15 Over-Voltage Shut Down Enable Register ⎯ Index 10h Bit 7 6 5 4-1 0 Name Reserved V6_OVP_EN V5_OVP_EN Reserved V0_OVP_EN R/W Default R/W R/W R/W 0 0 0 0 0 Reserved. Over-voltage shut down enable for VIN6 Over-voltage shut down enable for VIN5 Reserved Over-voltage shut down enable for VCC3V Description 6.6.16 Over-Voltage Status Register (Powered by VBAT) ⎯ Index 11h Bit Name R/W Default Description 55 2009 V1.1 Fintek 7-6 Reserved 0 Reserved. Feature Integration Technology Inc. F71869 This bit is over-voltage status. Once one of the monitored voltages 0 V_EXC_OVV R/W C 0 (VCC3V, VIN5, VIN6) over its related over-voltage limits and its related over-voltage shut down enable bit is set, this bit will be set to 1. Write a 1 to this bit will clear it to 0. (This bit is powered by VBAT) 6.6.17 Voltage reading and limit⎯ Index 20h- 4Fh Address 20h 21h 22h 23h 24h 25h 26h 27h 28h 29~30h 31h 32~35h 36h Attribute R R R R R R R R R R R/W R R/W Default Value ---------FF FF FF FF Description VCC3V reading. The unit of reading is 8mV. VIN1 (Vcore) reading. The unit of reading is 8mV. VIN2 reading. The unit of reading is 8mV. VIN3 reading. The unit of reading is 8mV. VIN4 reading. The unit of reading is 8mV. VIN5 reading. The unit of reading is 8mV. VIN6 reading. The unit of reading is 8mV. VSB3V reading. The unit of reading is 8mV. VBAT reading. The unit of reading is 8mV. Reserved VCC over-voltage limit (V0_OVV_LIMIT). The unit is 8mv. (This byte is powered by VBAT.) The unit is 9mV. Reserved VIN5 over-voltage limit (V5_OVV_LIMIT). The unit is 8mv. (This byte is powered by VBAT.) The unit is 9mV. VIN6 over-voltage limit (V6_OVV_LIMIT). The unit is 8mv. (This byte is powered by VBAT.) The unit is 9mV. Reserved 37h 38~4Fh R/W R FF FF Temperature Setting 6.6.18 Temperature PME# Enable Register ⎯ Index 60h Bit 7 Name R/W Default 0 Description If set this bit to 1, PME# signal will be issued when TEMP3 exceeds OVT limit setting. If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT setting. EN_ T3_OVT_PME R/W 6 EN_ T2_OVT_PME R/W 0 56 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 5 4 3 EN_ T1_OVT_PME R/W Reserved R/W 0 0 0 If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT setting. Reserved If set this bit to 1, PME# signal will be issued when TEMP3 exceeds high limit setting. If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high limit setting. If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high limit setting. Reserved EN_ T3_EXC_PME R/W 2 EN_ T2_EXC_PME R/W 0 1 0 EN_ T1_EXC_PME R/W Reserved R/W 0 0 6.6.19 Temperature Interrupt Status Register ⎯ Index 61h Bit 7 Name T3_OVT_STS R/W Default R/W 0 Description This bit gets 1 to indicate TEMP3 temperature sensor has exceeded OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, and write 0 to ignore. This bit gets 1 to indicate TEMP2 temperature sensor has exceeded 6 T2_OVT _STS R/W 0 OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 to ignore. This bit gets 1 to indicate TEMP1 temperature sensor has exceeded 5 T1_OVT _STS R/W 0 OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 to ignore. 4 Reserved R/W 0 Reserved This bit gets 1 to indicate TEMP3 temperature sensor has exceeded 3 T3_EXC _STS R/W 0 high limit or below the “high limit –hysteresis”. Write 1 to clear this bit, write 0 to ignore. This bit gets 1 to indicate TEMP2 temperature sensor has exceeded 2 T2_EXC _STS R/W 0 high limit or below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 to ignore. This bit gets 1 to indicate TEMP1 temperature sensor has exceeded 1 T1_EXC _STS R/W 0 high limit or below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 to ignore. 0 Reserved R/W 0 Reserved 57 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 6.6.20 Temperature Real Time Status Register ⎯ Index 62h Bit 7 Name T3_OVT R/W Default R/W 0 Description Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3 is below the “OVT limit –hysteresis” temperature. Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is below the “OVT limit –hysteresis” temperature. Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is below the “OVT limit –hysteresis” temperature. Reserved Set when the TEMP3 exceeds the high limit. Clear when the TEMP3 is below the “high limit –hysteresis” temperature. Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is below the “high limit –hysteresis” temperature. Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is below the “high limit –hysteresis” temperature. Reserved 6 T2_OVT R/W 0 5 4 3 T1_OVT Reserved T3_EXC R/W R/W R/W 0 0 0 2 T2_EXC R/W 0 1 0 T1_EXC Reserved R/W R/W 0 0 6.6.21 Temperature BEEP Enable Register ⎯ Index 63h Bit 7 Name EN_T3_ OVT_BEEP EN_ T2_ OVT_BEEP EN_ T1_ OVT_BEEP Reserved EN_ T3_EXC_BEEP EN_ T2_EXC_BEEP EN_ T1_EXC_BEEP Reserved R/W Default R/W 0 Description If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds OVT limit setting. If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT limit setting. If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT limit setting. Reserved If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds high limit setting. If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high limit setting. If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high limit setting. Reserved 6 R/W 0 5 4 3 R/W R/W R/W 0 0 0 2 R/W 0 1 0 R/W R/W 0 0 58 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 6.6.22 T1 OVT and High Limit Temperature Select Register ⎯ Index 64h Bit 7-6 Name Reserved R/W Default R/W 0 Reserved Select the source temperature for T1 OVT Limit. 0: Select T1 to be compared to Temperature 1 OVT Limit. 1: Select CPU temperature from PECI to be compared to 5-4 OVT_TEMP_SEL R/W 0 Temperature 1 OVT Limit. 2: Select CPU temperature from AMD TSI or Intel PCH SMBus to be compared to Temperature 1 OVT Limit. 3: Select the MAX temperature from Intel PCH SMBus to be compared to Temperature 1 OVT Limit. 3-2 Reserved R/W 0 Reserved Select the source temperature for T1 High Limit. 0: Select T1 to be compared to Temperature 1 High Limit. 1: Select CPU temperature from PECI to be compared to 1-0 HIGH_ TEMP_SEL R/W 0 Temperature 1 High Limit. 2: Select CPU temperature from AMD TSI or Intel PCH SMBus to be compared to Temperature 1 High Limit. 3: Select the MAX temperature from Intel PCH SMBus to be compared to Temperature 1 High Limit. Description 6.6.23 OVT and Alert Output Enable Register 1 ⎯ Index 66h Bit 7 Name EN_T3_ALERT R/W Default R 0 Description Enable temperature 3 alert event (asserted when temperature over high limit) Enable temperature 2 alert event (asserted when temperature over high limit) Enable temperature 1 alert event (asserted when temperature over high limit) Reserved. Enable over temperature (OVT) mechanism of temperature3. Enable over temperature (OVT) mechanism of temperature2. Enable over temperature (OVT) mechanism of temperature1. Reserved. 6 EN_T2_ALERT R 0 5 4 3 2 1 0 EN_T1_ALERT Reserved EN_T3_OVT EN_T2_OVT EN_T1_OVT Reserved R R R/W R/W R/W R 0 0 0 0 1 0h 59 2009 V1.1 Fintek 6.6.24 Reserved ⎯Index 67~69h Bit 7-0 Name Reserved R/W Default Reserved Feature Integration Technology Inc. F71869 Description 6.6.25 Temperature Sensor Type Register ⎯ Index 6Bh Bit 7-4 3 2 1 0 Name Reserved T3_MODE T2_MODE T1_MODE Reserved R/W Default RO R/W R/W R/W R 0 1 1 1 0 Reserved 0: TEMP3 is connected to a thermistor 1: TEMP3 is connected to a BJT.(default) 0: TEMP2 is connected to a thermistor. 1: TEMP2 is connected to a BJT. (default) 0: TEMP1 is connected to a thermistor 1: TEMP1 is connected to a BJT.(default) Reserved Description 6.6.26 TEMP1 Limit Hystersis Select Register ⎯ Index 6Ch Bit 7-4 3-0 Name TEMP1_HYS Reserved R/W Default R/W R 4h 0h Description Limit hysteresis. (0~15 degree C) Temperature and below the (boundary – hysteresis ). Reserved 6.6.27 TEMP2 and TEMP3 Limit Hystersis Select Register ⎯ Index 6Dh Bit 7-4 Name TEMP3_HYS R/W Default R/W 2h Description Limit hysteresis. (0~15 degree C) Temperature and below the ( boundary – hysteresis ). Limit hysteresis. (0~15 degree C) Temperature and below the ( boundary – hysteresis ). 3-0 TEMP2_HYS R/W 4h 6.6.28 DIODE OPEN Status Register ⎯ Index 6Fh Bit 7-6 5 Name Reserved PECI_OPEN R/W Default R R Reserved When PECI interface is enabled, “1” indicates an error code (0x0080 or 0x0081) is received from PECI slave. When TSI interface is enabled, “1” indicates the error of not receiving NACK bit or a timeout occurred. “1” indicates external diode 3 is open Description 4 3 TSI_OPEN T3_DIODE_OPEN R R - 60 2009 V1.1 Fintek 2 1 0 T2_DIODE_OPEN T1_DIODE_OPEN Reserved R R R - Feature Integration Technology Inc. F71869 “1” indicates external diode 2 is open “1” indicates external diode 1 is open Reserved 6.6.29 Temperature ⎯ Index 70h- 8Dh Address 70h 71h 72h 73h 74h 75h 76h 77-79h 7Ah Attribute Reserved Reserved R R R R R R R Default Value FFh FFh -------Reserved Reserved Temperature 1 reading. The unit of reading is 1ºC.At the moment of reading this register. Reserved Temperature 2 reading. The unit of reading is 1ºC.At the moment of reading this register. Reserved Temperature 3 reading. The unit of reading is 1ºC.At the moment of reading this register. Reserved The data of CPU temperature from digital interface after IIR filter. (Available if Intel IBX or AMD TSI interface is enabled) The raw data of PCH temperature from digital interface. (Only available if Intel IBX interface is enabled) The raw data of MCH read from digital interface. (Only available if Intel IBX interface is enabled) The raw data of maximum temperature between CPU/PCH/MCH 7Dh R -from digital interface. (Only available if Intel IBX interface is enabled) 7Eh 7Fh 80h 81h 82h 83h 84h R Reserved Reserved Reserved R/W R/W R/W -FFh FFh FFh 64h 55h 64h The data of CPU temperature from digital interface after IIR filter. (Only available if PECI interface is enabled) Reserved Reserved Reserved Temperature sensor 1 OVT limit. The unit is 1ºC. Temperature sensor 1 high limit. The unit is 1ºC. Temperature sensor 2 OVT limit. The unit is 1ºC. Description 7Bh R -- 7Ch R -- 61 2009 V1.1 Fintek 85h 86h 87h 88-8Bh 8C~8Dh R/W R/W R/W R R 55h 55h 46h -FFH Feature Integration Technology Inc. F71869 Temperature sensor 2 high limit. The unit is 1ºC. Temperature sensor 3 OVT limit. The unit is 1ºC. Temperature sensor 3 high limit. The unit is 1ºC. Reserved Reserved 6.6.30 Temperature Filter Select Register ⎯Index 8Eh Bit Name R/W Default Description The queue time for second filter to quickly update values. 00: 8 times. 7-6 IIR-QUEUR3 R/W 1h 01: 12 times. 10: 16 times. (default) 11: 24 times. The queue time for second filter to quickly update values. 00: 8 times. 5-4 IIR-QUEUR2 R/W 1h 01: 12 times. 10: 16 times. (default) 11: 24 times. The queue time for second filter to quickly update values. 00: 8 timers. 3-2 IIR-QUEUR1 R/W 1h 01: 12 times. 10: 16 times. (default) 11: 24 times. The queue time for second filter to quickly update values. (for CPU temperature from PECI or TSI interface) 1-0 IIR-QUEUR_DIG R/W 1h 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times. Fan Control Setting 6.6.31 FAN PME# Enable Register ⎯ Index 90h Bit 7-3 Name Reserved R/W Default R 0 Reserved Description 62 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 A one enables the corresponding interrupt status bit for PME# 2 EN_FAN3_PME R/W 0 interrupt Set this bit 1 to enable PME# function for Fan3. A one enables the corresponding interrupt status bit for PME# 1 EN_FAN2_PME R/W 0 interrupt. Set this bit 1 to enable PME# function for Fan2. A one enables the corresponding interrupt status bit for PME# 0 EN_FAN1_PME R/W 0 interrupt. Set this bit 1 to enable PME# function for Fan1. 6.6.32 FAN Interrupt Status Register ⎯ Index 91h Bit 7-3 2 Name Reserved FAN3_STS R/W Default R R/W 0 -Reserved This bit is set when the fan3 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan2 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. This bit is set when the fan1 count exceeds the count limit. Write 1 to clear this bit, write 0 will be ignored. Description 1 FAN2_STS R/W -- 0 FAN1_STS R/W -- 6.6.33 FAN Real Time Status Register ⎯ Index 92h Bit 7-3 Name Reserved R/W Default -0 Reserved This bit set to high mean that fan3 count can’t meet expect count over 2 FAN3_EXC R -than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan2 count can’t meet expect count over 1 FAN2_EXC R -than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. This bit set to high mean that fan1 count can’t meet expect count over 0 FAN1_EXC R -than SMI time(CR9F) or when duty not zero but fan stop over then 3 sec. 6.6.34 FAN BEEP# Enable Register ⎯ Index 93h Bit Name R/W Default Description Description 63 2009 V1.1 Fintek FULL_WITH_ T3_EN FULL_WITH_ T2_EN FULL_WITH_ T1_EN Reserved Reserved Feature Integration Technology Inc. F71869 7 R/W 0 Set one will enable FAN to force full speed when T3 over high limit. 6 R/W 0 Set one will enable FAN to force full speed when T2 over high limit. 5 4 3 2 1 0 R/W - 0 0 0 0 Set one will enable FAN to force full speed when T1 over high limit. Reserved Reserved. A one enables the corresponding interrupt status bit for BEEP. A one enables the corresponding interrupt status bit for BEEP. A one enables the corresponding interrupt status bit for BEEP. EN_FAN3_ BEEP R/W EN_FAN2_ BEEP R/W EN_FAN1_ BEEP R/W 6.6.35 FAN Type Select Register ⎯ Index 94h FAN_PROG_SEL = 0 Bit 7-6 Name Reserved R/W Default Reserved. 00: Output PWM mode (push pull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power terminal. 5-4 FAN3_TYPE R/W 2’b 0S 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. Bit 0 is power on trap by FANCTRL3 0: FANCTRL3 is pull up by external resistor. 1: FANCTRL3 is pull down by internal 100K resistor. 00: Output PWM mode (push pull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power terminal. 3-2 FAN2_TYPE R/W 2’b 0S 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. Bit 0 is power on trap by FANCTRL2 0: FANCTRL2 is pull up by external resistor. 1: FANCTRL2 is pull down by internal 100K resistor. Description 64 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 00: Output PWM mode (push pull) to control fans. 01: Use linear fan application circuit to control fan speed by fan’s power terminal. 1-0 FAN1_TYPE R/W 2’b 0S 10: Output PWM mode (open drain) to control Intel 4-wire fans. 11: Reserved. Bit 0 is power on trap by FANCTRL1 0: FANCTRL1 is pull up by external resistor. 1: FANCTRL1is pull down by internal 100K resistor. S: Register default values are decided by trapping. FAN_PROG_SEL = 1 Bit Name R/W Default Description This register is used to set the base temperature for FAN1 temperature adjustment. The FAN1 temperature is calculated according to the equation: 7-0 FAN1_BASE _TEMP Tfan1 = Tnow + (Ta – Tb)*Ct R/W 0 Where Tnow is selected by FAN1_TEMP_SEL_DIG and FAN1_TEMP_SEL. Tb is this register, Ta is selected by TFAN1_ADJ_SEL and Ct is selected by TFAN1_ADJ_UP_RATE/TFAN1_ADJ_DN_RATE. To access this register, FAN_PROG_SEL(CR9F[7]) must set to “1”. 6.6.36 FAN1 Temperature Adjust Rate Register ⎯ Index 95h (FAN_PROG_SEL = 1) Bit 7 Name Reserved R/W Default Reserved This selects the weighting of the difference between Ta and Tb if Ta is higher than Tb. 3’h1: 1 (Ct = 1) 6-4 TFAN1_ADJ_UP _RATE 3’h0 3’h2: 1/2 (Ct= 1/2) 3’h3: 1/4 (Ct = 1/4) 3’h4: 1/8 (Ct = 1/8) otherwise: 0 To access this byte, FAN_PROG_SEL must set to “1”. 3 Reserved Reserved Description 65 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 This selects the weighting of the difference between Ta and Tb if Ta is lower than Tb. 3’h1: 1 (Ct = 1) 2-0 TFAN1_ADJ_DN _RATE R/W 3’h0 3’h2: 1/2 (Ct= 1/2) 3’h3: 1/4 (Ct = 1/4) 3’h4: 1/8 (Ct = 1/8) otherwise: 0 To access this byte, FAN_PROG_SEL must set to “1”. 6.6.37 FAN mode Select Register ⎯ Index 96h FAN_PROG_SEL = 0 Bit 7-6 Name Reserved R/W Default Reserved 00: Auto fan speed control. Fan speed will follow different temperature by different RPM defined in 0xC6-0xCE. 01: Auto fan speed control. Fan speed will follow different temperature by different duty cycle defined in 0xC6-0xCE. 5-4 FAN3_MODE R/W 01 10: Manual mode fan control. User can write expected RPM count to 0xC2-0xC3, and F71869F will adjust duty cycle (PWM fan type) or voltage (linear fan type) to control fan speed automatically. 11: Manual mode fan control. User can write expected duty cycle (PWM fan type) or voltage (linear fan type) to 0xC3, and F71869F will output this desired duty or voltage to control fan speed. 00: Auto fan speed control. Fan speed will follow different temperature by different RPM defined in 0xB6-0xBE. 01: Auto fan speed control. Fan speed will follow different temperature by different duty cycle (voltage) defined in 0xB6-0xBE. 3-2 FAN2_MODE R/W 01 10: Manual mode fan control. User can write expected RPM count to 0xB2-0xB3, and F71869F will adjust duty cycle (PWM fan type) or voltage (linear fan type) to control fan speed automatically. 11: Manual mode fan control, user can write expected duty cycle (PWM fan type) or voltage (linear fan type) to 0xB3, and F71869F will output this desired duty or voltage to control fan speed. Description 66 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 00: Auto fan speed control. Fan speed will follow different temperature by different RPM defined in 0xA6-0xAE. 01: Auto fan speed control. Fan speed will follow different temperature by different duty cycle defined in 0xA6-0xAE. 1-0 FAN1_MODE R/W 01 10: Manual mode fan control, user can write expected RPM count to 0xA2-0xA3, and F71869F will auto control duty cycle (PWM fan type) or voltage (linear fan type) to control fan speed automatically. 11: Manual mode fan control, user can write expected duty cycle (PWM fan type) or voltage (linear fan type) to 0xA3, and F71869F will output this desired duty or voltage to control fan speed. FAN_PROG_SEL = 1 Bit 7-3 Name Reserved R/W Default Reserved This selects which temperature to be used as Ta for Fan1 temperature adjustment. 001: T1 (CR72h) 010: T2 (CR74h) 2-0 TFAN1_ADJ_SEL R/W 0h 011: T3 (CR76h) 101: Digital T1 (CR7Ch) 110: Digital T2 (CR7Bh) 111: Digital T3 (CR7Ah) otherwise: Ta will be 0. To access this register FAN_PROG_SEL must set to “1”. 6.6.38 Auto FAN1 and FAN2 Boundary Hystersis Select Register ⎯ Index 98h Bit Name R/W Default Description Boundary hysteresis. (0~15 degree C) 7-4 FAN2_HYS R/W 4h Segment will change when the temperature over the boundary temperature and below the ( boundary – hysteresis ). Boundary hysteresis. (0~15 degree C) 3-0 FAN1_HYS R/W 4h Segment will change when the temperature over the boundary temperature and below the ( boundary – hysteresis ). Description 67 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 6.6.39 Auto FAN3 Boundary Hystersis Select Register ⎯ Index 99h Bit 7-4 Name Reserved R/W Default Reserved. Boundary hysteresis. (0~15 degree C) 3-0 FAN3_HYS R/W 2h Segment will change when the temperature over the boundary temperature and below the ( boundary – hysteresis ). 6.6.40 Auto Fan Up Speed Update Rate Select Register⎯ Index 9Bh FAN_PROG_SEL = 0 Bit 7-6 Name Reserved R/W Default Reserved. Fan3 duty update rate: 00: 2Hz 5-4 FAN3_UP_RATE R/W 01 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan2 duty update rate: 00: 2Hz 3-2 FAN2_UP_RATE R/W 01 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan1 duty update rate: 00: 2Hz 1-0 FAN1_UP_RATE R/W 01 01: 5Hz (default) 10: 10Hz 11: 20Hz FAN_PROG_SEL = 1 Bit 7-6 Name Reserved R/W Default Reserved. Fan3 duty update rate: 00: 2Hz 5-4 FAN3_DN_RATE R/W 01 01: 5Hz (default) 10: 10Hz 11: 20Hz Description Description Description 68 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Fan2 duty update rate: 00: 2Hz 3-2 FAN2_DN_RATE R/W 01 01: 5Hz (default) 10: 10Hz 11: 20Hz Fan1 duty update rate: 00: 2Hz 1-0 FAN1_DN_RATE R/W 01 01: 5Hz (default) 10: 10Hz 11: 20Hz 6.6.41 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE ⎯ Index 9Ch Bit Name R/W Default Description When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this 7-4 FAN2_STOP _DUTY R/W 5h (value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to 3-0 FAN1_STOP _DUTY R/W 5h this (value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). 6.6.42 FAN3 START UP DUTY-CYCLE/VOLTAGE ⎯ Index 9Dh Bit 7-4 Name Reserved R/W Default Reserved. When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to 3-0 FAN3_STOP_ DUTY R/W 5h this (value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will decrease duty-cycle to 0 when the PWM duty cycle is less than this (value x 4). 6.6.43 FAN PROGRAMMABLE DUTY-CYCLE/VOLTAGE LOADED AFTER POWER-ON ⎯ Index 9Eh Bit Name R/W Default 66h Description This byte will be immediately loaded as Fan duty value after VDD is powered on if it has been programmed before shut down. Description 7-0 PROG_DUTY_VAL R/W 69 2009 V1.1 Fintek 6.6.44 Fan Fault Time Register ⎯ Index 9Fh Bit 7 6-5 Name R/W Default 0 - Feature Integration Technology Inc. F71869 Description Set this bit to “1” will enable accessing registers of other bank. Reserved 0: The Fan Duty is 100% and will be loaded immediately after VDD is powered on if CR9E is not been programmed before shut down. (pull down by external resistor) 4 FULL_DUTY_SEL R/W 1: The Fan Duty is 40% and will be loaded immediately after VDD is powered on if CR9E is not been programmed before shut down. (pull up by internal 47K resistor). This register is power on trap by DTR1#. This register determines the time of fan fault. The condition to cause fan fault event is: When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan expect count in time. 3-0 F_FAULT_TIME R/W Ah The unit of this register is 1 second. The default value is 11 seconds. (Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds. Set to 2, means 3 seconds. …. ) Another condition to cause fan fault event is fan stop and the PWM duty is greater than the minimum duty programmed by the register index 9C-9Dh. 6.6.45 FAN1 Index A0h~AFh Address Attribute Default Value Description FAN1 count reading (MSB). At the moment of reading this register, A0h RO 8’h0f the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. A1h RO 8’hff FAN1 count reading (LSB). RPM mode(CR96 bit0=0): FAN1 expect speed count value (MSB), in auto fan mode (CR96 A2h R/W 8’h00 bit1 0) this register is auto updated by hardware. Duty mode(CR96 bit0=1): This byte is reserved byte. A3h R/W 8’h01 RPM mode(CR96 bit0=0): FAN1 expect speed count value (LSB) or expect PWM duty, in auto FAN_PROG_SEL R/W Reserved - 70 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 fan mode this register is auto updated by hardware and read only. Duty mode(CR96 bit0=1): The Value programming in this byte is duty value. In auto fan mode (CR96 bit1 Ex: 5 255 0) this register is updated by hardware. 5*100/255 % 100% FAN1 full speed count reading (MSB). At the moment of reading this A4h R/W 8’h03 register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. A5h R/W 8’hff FAN1 full speed count reading (LSB). 6.6.46 VT1 BOUNDARY 1 TEMPERATURE – Index A6h Bit Name R/W Default Description The first boundary temperature for VT1 in temperature mode. When VT1 temperature exceeds this boundary, expected FAN1 value 7-0 BOUND1TMP1 R/W 3Ch will be loaded from segment 1 register (index AAh). (60oC) When VT1 temperature is under this boundary – hysteresis, expected FAN1 value will be loaded from segment 2 register (index ABh). This byte is a 2’s complement value ranged from -128’C ~ 127’C. 6.6.47 VT1 BOUNDARY 2 TEMPERATURE – Index A9h Bit Name R/W Default Description The second boundary temperature for VT1 in temperature mode. When VT1 temperature exceeds this boundary, FAN1 expect value 7-0 BOUND2TMP1 R/W 1Eh will load from segment 2 register (index ABh). (30oC) When VT1 temperature is under this boundary – hysteresis, FAN1 expect value will load from segment 3 register (index AEh). This byte is a 2’s complement value ranging from -128’C ~ 127’C. 6.6.48 FAN1 SEGMENT 1 SPEED COUNT – Index AAh Bit Name R/W Default Description 71 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 The meaning of this register is depending on the FAN1_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 7-0 SEC1SPEED1 Ex: FFh 100%:full speed: User must set this register to 0. R/W (100%) 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is duty-cycle in this temperature section. 6.6.49 FAN1 SEGMENT 2 SPEED COUNT – Index ABh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 7-0 SEC2SPEED1 R/W 2’b00: The value that set in this byte is the relative expect fan speed D9h % of the full speed in this temperature section. (85%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 6.6.50 FAN1 SEGMENT 3 SPEED COUNT – Index AEh Bit Name R/W Default Description The meaning of this register is depending on the FAN1_MODE(CR96) 7-0 SEC3SPEED1 R/W 80h 2’b00: The value that set in this byte is the relative expect fan speed (50%) % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 6.6.51 FAN1 Temperature Mapping Select – Index AFh Bit 7 Name FAN1_TEMP _SEL_DIG FAN1_PWM _FREQ_SEL FAN1_UP_T_EN FAN1_ INTERPOLATION_EN R/W Default R/W 0 source for controlling FAN1. Set this bit to select FAN2 PWM output frequency. R/W 0 0: 23.5 kHz 1: 220 Hz R/W R/W 0 1 Set 1 to force FAN1 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. Description This bit companies with FAN1_TEMP_SEL select the temperature (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM 6 5 4 72 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 This register controls the FAN1 duty movement when temperature over highest boundary. 3 FAN1_JUMP _HIGH_EN 0: The FAN1 duty will increases with the slope selected by R/W 1 FAN1_RATE_SEL register. 1: The FAN1 duty will directly jumps to the value of SEC1SPEED1 register. This bit only activates in duty mode. This register controls the FAN1 duty movement when temperature under (highest boundary – hysteresis). 2 FAN1_JUMP _LOW_EN 0: The FAN1 duty will decreases with the slope selected by R/W 1 FAN1_RATE_SEL register. 1: The FAN1 duty will directly jumps to the value of SEC2SPEED1 register. This bit only activates in duty mode. This registers company with FAN1_TEMP_SEL_DIG select the temperature source for controlling FAN1. The following value is comprised by {FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL} 000: fan1 follows PECI temperature (CR7Eh) 001: fan1 follows temperature 1 (CR72h). 1-0 FAN1_TEMP_SEL R/W 01 010: fan1 follows temperature 2 (CR74h). 011: fan1 follows temperature 3 (CR76h). 100: fan1 follows IBX/TSI CPU temperature (CR7Ah) 101: fan1 follows IBX PCH temperature (CR7Bh). 110: fan1 follows IBX MCH temperature (CR7Ch). 111: fan1 follows IBX maximum temperature (CR7Dh). Others are reserved. 6.6.52 FAN2 Index B0h~BFh Address Attribute Default Value Description FAN2 count reading (MSB). At the moment of reading this register, B0h RO 8’h0f the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. B1h B2h RO R/W 8’hff 8’h00 FAN2 count reading (LSB). RPM mode(CR96 bit2=0): FAN2 expect speed count value (MSB), in auto fan mode(CR96 73 2009 V1.1 Fintek bit3 Feature Integration Technology Inc. F71869 0) this register is auto updated by hardware. Duty mode(CR96 bit2=1): This byte is reserved byte. RPM mode(CR96 bit2=0): FAN2 expect speed count value (LSB) or expect PWM duty , in auto fan mode this register is auto updated by hardware and read only. B3h R/W 8’h01 Duty mode(CR96 bit2=1): The Value programming in this byte is duty value. In auto fan mode(CR96 bit3 Ex: 5 255 100% 0) this register is updated by hardware. 5*100/255 % FAN2 full speed count reading (MSB). At the moment of reading this B4h R/W 8’h03 register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. B5h R/W 8’hff FAN2 full speed count reading (LSB). 6.6.53 VT2 BOUNDARY 1 TEMPERATURE – Index B6h Bit Name R/W Default Description The first boundary temperature for VT2 in temperature mode. When VT2 temperature exceeds this boundary, FAN2 expect value 7-0 BOUND1TMP2 will load from segment 1 register (index Bah). 3Ch R/W When VT2 temperature is under this boundary – hysteresis, FAN2 (60oC) expect value will load from segment 2 register (index BAh). This byte is a 2’s complement value ranging from -128’C ~ 127’C. Bit 7 will always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”. 6.6.54 VT2 BOUNDARY 2 TEMPERATURE – Index B7h Bit Name R/W Default Description 74 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 The second boundary temperature for VT2 in temperature mode. When VT2 temperature exceeds this boundary, FAN2 expect value 7-0 BOUND2TMP2 will load from segment 2 register (index BB)h. 1Eh R/W When VT2 temperature is under this boundary – hysteresis, FAN2 (30oC) expect value will load from segment 3 register (index BBh). This byte is a 2’s complement value ranging from -128’C ~ 127’C. Bit 7 will always be “0” (always positive) if FAN_NEG_TEMP_EN is “0”. 6.6.55 FAN2 SEGMENT 1 SPEED COUNT – Index BAh Bit Name R/W Default Description The meaning of this register is depending on the FAN2_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 7-0 SEC1SPEED2 Ex: FFh 100%:full speed: User must set this register to 0. R/W (100%) 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is duty-cycle in this temperature section. 6.6.56 FAN2 SEGMENT 2 SPEED COUNT – Index BBh Bit Name R/W Default Description The meaning of this register is depending on the FAN2_MODE(CR96) 7-0 SEC2SPEED2 R/W 2’b00: The value that set in this byte is the relative expect fan speed D9h % of the full speed in this temperature section. (85%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 6.6.57 FAN2 SEGMENT 3 SPEED COUNT – Index BEh Bit Name R/W Default Description The meaning of this register is depending on the FAN2_MODE(CR96) 7-0 SEC3SPEED2 R/W 80h 2’b00: The value that set in this byte is the relative expect fan speed (50%) % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM 75 2009 V1.1 Fintek 6.6.58 FAN2 Temperature Mapping Select – Index BFh Bit 7 Name FAN2_TEMP_ SEL_DIG FAN2_PWM_ FREQ_SEL FAN2_UP_T_EN FAN2_ INTERPOLATION_EN R/W Default R/W 0 Feature Integration Technology Inc. F71869 Description This bit companies with FAN2_TEMP_SEL to select the temperature source for controlling FAN2. Set this bit to select FAN2 PWM output frequency. R/W 0 0: 23.5 kHz 1: 220 Hz R/W R/W 0 1 Set 1 to force FAN2 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. This register controls the FAN2 duty movement when temperature over highest boundary. 3 FAN2_JUMP_ HIGH_EN 0: The FAN2 duty will increases with the slope selected by R/W 1 FAN2_RATE_SEL register. 1: The FAN2 duty will directly jumps to the value of SEC1SPEED2 register. This bit only activates in duty mode. This register controls the FAN2 duty movement when temperature under (highest boundary – hysteresis). 2 FAN2_JUMP_ LOW_EN 0: The FAN2 duty will decreases with the slope selected by R/W 1 FAN2_RATE_SEL register. 1: The FAN2 duty will directly jumps to the value of SEC2SPEED2 register. This bit only activates in duty mode. This registers companying with FAN2_TEMP_SEL_DIG select the temperature source for controlling FAN2. The following value is comprised by {FAN2_TEMP_SEL_DIG, FAN2_TEMP_SEL} 000: fan1 follows PECI temperature (CR7Eh) 001: fan1 follows temperature 1 (CR72h). 1-0 FAN2_TEMP_SEL R/W 10 010: fan1 follows temperature 2 (CR74h). 011: fan1 follows temperature 3 (CR76h). 100: fan1 follows IBEX/TSI CPU temperature (CR7Ah) 101: fan1 follows IBEX PCH temperature (CR7Bh). 110: fan1 follows IBEX MCH temperature (CR7Ch). 111: fan1 follows IBEX maximum temperature (CR7Dh). Otherwise: reserved. 6 5 4 76 2009 V1.1 Fintek 6.6.59 FAN3 Index C0h- CFh Address Attribute Default Value Feature Integration Technology Inc. F71869 Description FAN3 count reading (MSB). At the moment of reading this register, C0h RO 8’h0F the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. C1h RO 8’hff FAN3 count reading (LSB). RPM mode(CR96 bit4=0): FAN3 expect speed count value (MSB), in auto fan mode(CR96 C2h R/W 8’h00 bit5 0) this register is auto updated by hardware. Duty mode(CR96 bit4=1): This byte is reserved byte. RPM mode(CR96 bit4=0): FAN3 expect speed count value (LSB) or expect PWM duty , in auto fan mode this register is auto updated by hardware and read only. C3h R/W 8’h01 Duty mode(CR96 bit4=1): The Value programming in this byte is duty value. In auto fan mode(CR96 bit5 Ex: 5 255 100% 0) this register is updated by hardware. 5*100/255 % FAN3 full speed count reading (MSB). At the moment of reading this C4h R/W 8’h03 register, the LSB will be latched. This will prevent from data updating when reading. To read the fan count correctly, read MSB first and followed read the LSB. C5h R/W 8’hff FAN3 full speed count reading (LSB). 6.6.60 VT3 BOUNDARY 1 TEMPERATURE – Index C6h Bit Name R/W Default Description The first boundary temperature for VT3 in temperature mode. When VT3 temperature exceeds this boundary, FAN3 expect value 7-0 BOUND1TMP3 R/W 3Ch will load from segment 1 register (index CA)h. (60oC) When VT3 temperature is under this boundary – hysteresis, FAN3 expect value will load from segment 2 register (index CAh). This byte is a 2’s complement value ranging from -128’C ~ 127’C. 77 2009 V1.1 Fintek 6.6.61 VT3 BOUNDARY 2 TEMPERATURE – Index C9h Bit Name R/W Default Feature Integration Technology Inc. F71869 Description The second boundary temperature for VT3 in temperature mode. When VT3 temperature exceeds this boundary, FAN3 expect value 7-0 BOUND2TMP3 R/W 1Eh will load from segment 2 register (index CB)h. (30oC) When VT3 temperature is under this boundary – hysteresis, FAN3 expect value will load from segment 3 register (index CBh). This byte is a 2’s complement value ranging from -128’C ~ 127’C. 6.6.62 FAN3 SEGMENT 1 SPEED COUNT – Index CAh Bit Name R/W Default Description The meaning of this register is depending on the FAN3_MODE(CR96) 2’b00: The value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 7-0 SEC1SPEED3 Ex: FFh 100%:full speed: User must set this register to 0. R/W (100%) 60% full speed: (100-60)*32/60, so user must program 21 to this reg. X% full speed: The value programming in this byte is duty-cycle in this temperature section. 6.6.63 FAN3 SEGMENT 2 SPEED COUNT – Index CBh Bit Name R/W Default Description The meaning of this register is depending on the FAN3_MODE(CR96) 7-0 SEC2SPEED3 R/W 2’b00: The value that set in this byte is the relative expect fan speed D9h % of the full speed in this temperature section. (85%) 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. 6.6.64 FAN3 SEGMENT 3 SPEED COUNT – Index CEh Bit Name R/W Default Description The meaning of this register is depending on the FAN3_MODE(CR96) 7-0 SEC3SPEED3 R/W 80h 2’b00: The value that set in this byte is the relative expect fan speed (50%) % of the full speed in this temperature section. 2’b01: The value that set in this byte is mean the expect PWM duty-cycle in this temperature section. (100-X)*32/X 2’b01: The value that set in this byte is mean the expect PWM 78 2009 V1.1 Fintek 6.6.65 FAN3 Temperature Mapping Select – Index CFh Bit 7 Name FAN3_TEMP_ SEL_DIG FAN3_PWM_ FREQ_SEL FAN3_UP_T_EN FAN3_ INTERPOLATION_EN R/W Default R/W 0 Feature Integration Technology Inc. F71869 Description This bit companies with FAN3_TEMP_SEL select the temperature source for controlling FAN3. Set this bit to select FAN3 PWM output frequency. R/W 0 0: 23.5 kHz 1: 220 Hz R/W R/W 0 1 Set 1 to force FAN3 to full speed if any temperature over its high limit. Set 1 will enable the interpolation of the fan expect table. This register controls the FAN3 duty movement when temperature over highest boundary. 3 FAN3_JUMP_ HIGH_EN 0: The FAN3 duty will increases with the slope selected by R/W 1 FAN3_RATE_SEL register. 1: The FAN3 duty will directly jumps to the value of SEC1SPEED3 register. This bit only activates in duty mode. This register controls the FAN3 duty movement when temperature under (highest boundary – hysteresis). 2 FAN3_JUMP_ LOW_EN 0: The FAN3 duty will decreases with the slope selected by R/W 1 FAN3_RATE_SEL register. 1: The FAN3 duty will directly jumps to the value of SEC2SPEED3 register. This bit only activates in duty mode. This registers companying with FAN3_TEMP_SEL_DIG select the temperature source for controlling FAN3. The following value is comprised by {FAN3_TEMP_SEL_DIG, FAN3_TEMP_SEL} 000: fan1 follows PECI temperature (CR7Eh) 001: fan1 follows temperature 1 (CR72h). 1-0 FAN3_TEMP_SEL R/W 11 010: fan1 follows temperature 2 (CR74h). 011: fan1 follows temperature 3 (CR76h). 100: fan1 follows IBEX/TSI CPU temperature (CR7Ah) 101: fan1 follows IBEX PCH temperature (CR7Bh). 110: fan1 follows IBEX MCH temperature (CR7Ch). 111: fan1 follows IBEX maximum temperature (CR7Dh). Otherwise: reserved. 6 5 4 79 2009 V1.1 Fintek 6.6.66 TSI Temperature 0 – Index E0h Bit Name R/W Default Feature Integration Technology Inc. F71869 Description This is the AMD TSI reading if AMD TSI enable. TSI_TEMP0 R/W And will be highest temperature among CPU, MCH and PCH if Intel temperature interface enable. The range is 0~255’C. To access this byte, MCH_BANK_SEL must set to “0”. This byte is used as multi-purpose: 7-0 6. The received data of receive protocol. 7. The first received byte of read word protocol. SMB_DATA0 R/W 8’h00 8. The 10th received byte of read block protocol. 9. The sent data for send byte protocol and write byte protocol. 10. The first send byte for write word protocol. 11. The first send byte for write block protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.67 TSI Temperature 1 – Index E1h Bit Name TSI_TEMP1 R/W Default R range is 0~255’C. To access this byte, MCH_BANK_SEL should be set to “0”. This byte is used as multi-purpose: 7-0 SMB_DATA1 R/W 8’h00 1. The second received byte of read word protocol. 2. The 11th received byte of read block protocol. 3. The second send byte for write word protocol. 4. The second send byte for write block protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.68 TSI Temperature 2 Low Byte – Index E2h Bit Name R/W Default Description This is the low byte of Intel temperature interface CPU reading. The reading is the fraction part of CPU temperature. Bit 0 indicates the 7-0 TSI_TEMP2_LO R error status. 0: No error. 1: Error code. To access this byte, MCH_BANK_SEL should be set to “0”. Description This is the high byte of Intel temperature interface PCH reading. The 80 2009 V1.1 Fintek th Feature Integration Technology Inc. F71869 This is the 12 byte of the block read protocol. SMB_DATA2 R/W 8’h00 This byte is also used as the 3rd byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.69 TSI Temperature 2 High Byte – Index E3h Bit Name TSI_TEMP2_HI 7-0 SMB_DATA3 R/W R/W Default R Description This is the high byte of Intel temperature interface CPU reading. The reading is the decimal part of CPU temperature. To access this byte, MCH_BANK_SEL should be set to “0”. This is the 13th byte of the block read protocol. 8’h00 This byte is also used as the 4th byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.70 TSI Temperature 3 – Index E4h Bit Name TSI_TEMP3 7-0 SMB_DATA4 R/W R/W Default R range is 0~255’C. To access this byte, MCH_BANK_SEL should be set to “0”. This is the 14th byte of the block read protocol. 8’h00 This byte is also used as the 5th byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.71 TSI Temperature 4 – Index E5h Bit Name TSI_TEMP4 7-0 SMB_DATA5 R/W R/W Default R The range is 0~255’C. To access this byte, MCH_BANK_SEL should be set to “0”. This is the 15th byte of the block read protocol. 8’h00 This byte is also used as the 6th byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.72 TSI Temperature 5 – Index E6h Bit 7-0 Name TSI_TEMP5 R/W Default R The range is 0~255’C. To access this byte, MCH_BANK_SEL should be set to “0”. Description This is the high byte of Intel temperature interface DIMM1 reading. Description This is the high byte of Intel temperature interface DIMM0 reading. Description This is the high byte of Intel temperature interface MCH reading. The 81 2009 V1.1 Fintek th Feature Integration Technology Inc. F71869 This is the 16 byte of the block read protocol. SMB_DATA6 R/W 8’h00 This byte is also used as the 7th byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.73 TSI Temperature 6 – Index E7h Bit Name TSI_TEMP6 7-0 SMB_DATA7 R/W R/W Default R The range is 0~255’C. To access this byte, MCH_BANK_SEL should be set to “0”. This is the 17th byte of the block read protocol. 8’h00 This byte is also used as the 8th byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.74 TSI Temperature 7 – Index E8h Bit Name TSI_TEMP7 7-0 SMB_DATA8 R/W R/W Default R Description This is the high byte of Intel temperature interface DIMM3 reading. The range is 0~255’C. The above 9 bytes could also be used as the read data of block read protocol if the TSI is disable or pending. This is the 18th byte of the block read protocol. 8’h00 This byte is also used as the 9th byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. 6.6.75 SMB Data Buffer 9 – Index E9h Bit 7-0 Name SMB_DATA9 R/W Default th Description This is the high byte of Intel temperature interface DIMM2 reading. Description This is the 18 byte of the block read protocol. This byte is also used as the 9th byte of block write protocol. To access this byte, MCH_BANK_SEL should be set to “1”. R/W FFh 6.6.76 Block Write Count Register – Index ECh Bit 7 6 5-0 Name MCH_BANK_SEL Reserved BLOCK_WR_CNT R/W Default R/W R/W 0 0 0 Description This bit is used to select the register in index E0h to E9h. Set “0” to read the temperature bank and “1” to access the data bank. Reserved Use the register to specify the byte count of block write protocol. Support up to 10 bytes. 82 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 6.6.77 SMB Command Byte/TSI Command Byte – Index EDh Bit Name R/W Default Description There are actual two bytes for this index. TSI_CMD_PROG select which byte to be programmed: 0: SMB_CMD, which is the command code for write byte/word, read 7-0 SMB_CMD/TSI_CMD R/W 0/1 byte/word, block write/read and process call protocol. 1: TSI_CMD, which is the command code for Intel temperature interface block read protocol and the data byte for AMD TSI send byte protocol. 6.6.78 SMB Status – Index EEh Bit Name R/W Default Description Set 1 to pending auto TSI accessing. (In AMD model, auto accessing will issue a send-byte followed a receive-byte; In Intel model, auto 7 TSI_PENDING R/W 0 accessing will issue a block read). To use the TSI_SCL/TSI_SDA as a SMBus master, set this bit to “1” first. 6 5 TSI_CMD_PROG PROC_KILL R/W R/W 0 0 Set 1 to program TSI_CMD. Kill the current SMBus transfer and return the state machine to idle. It will set an fail status if the current transfer is not completed. This is set when PROC_KI LL kill a un-completed transfer. It will be auto cleared by next SMBus transfer. This is the arbitration lost status if a SMBus command is issued. Auto cleared by next SMBus command. This is the timeout status if a SMBus command is issued. Auto cleared by next SMBus command. This is the NACK error status if a SMBus command is issued. Auto cleared by next SMBus command. 0: a SMBus transfer is in process. 1: Ready for next SMBus command. 4 FAIL_STS R 0 3 SMB_ABT_ERR R 0 2 SMB_TO_ERR R 0 1 SMB_NAC_ERR R 0 0 SMB_READY R 1 6.6.79 SMB Protocol Select – Index EFh Bit 7 6-4 Name SMB_START Reserved R/W Default W 0 SMB_PROTOCOL. Reserved. Description Write “1” to trigger a SMBus transfer with the protocol specified by 83 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Select what protocol if a SMBus transfer is triggered. 0001b: send byte. 0010b: write byte. 0011b: write word. 0100b: Reserved. 0101b: block write. 3-0 SMB_PROTOCOL R/W 0 0111b: quick command (write). 1001b: receive byte. 1010b: read byte. 1011b: Reserved 1101b: block read. 1111b: Reserved Otherwise: reserved. 6.7 KBC Registers (CR05) 6.7.1 Bit 7-1 0 6.7.2 Bit 7-0 6.7.3 Bit 7-0 6.7.4 Bit 7-4 3-0 6.7.5 KBC Device Enable Register ⎯ Index 30h Name Reserved KBC_EN R/W Default R/W 1 Reserved 0: disable KBC. 1: enable KBC. Description Base Address High Register ⎯ Index 60h Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of KBC command port address. The address of data port is command port address + 4; Base Address Low Register ⎯ Index 61h Name R/W Default 60h Description The LSB of KBC command port address. The address of data port is command port address + 4. BASE_ADDR_LO R/W KBC IRQ Channel Select Register ⎯ Index 70h Name Reserved SELKIRQ R/W Default R/W 1h Reserved. Select the IRQ channel for keyboard interrupt. Description Mouse IRQ Channel Select Register ⎯ Index 72h 84 2009 V1.1 Fintek Bit Name R/W Default R/W Ch Reserved. Feature Integration Technology Inc. F71869 Description 7-4 Reserved 3-0 SELMIRQ 6.7.6 Bit 7 6-5 Select the IRQ channel for PS/2 mouse interrupt. Auto Swap Register ⎯ Index FEh (Powered by VBAT) Name AUTO_DET_EN Reserved R/W Default R/W 1b Description 0: disable auto detect keyboard/mouse swap. 1: enable auto detect keyboard/mouse swap. Reserved. 0: Keyboard/mouse not swap. 4 KB_MO_SWAP R/W 0b 1: Keyboard/mouse swap. This bit is set/clear by hardware if AUTO_DET_EN is set to “1”. Users could also program this bit manually. 3-0 Reserved - 1h Reserved 6.8 GPIO Registers (CR06) 6.8.1 GPIO Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved GPIO_EN R/W Default R/W 0 Reserved 0: disable GPIO I/O Port. 1: enable GPIO I/O Port. Description 6.8.2 Base Address High Register ⎯ Index 60h Bit 7-0 Name BASE_ADDR_HI R/W Default R/W 00h Description The MSB of GPIO index/data port address. The index port is BASE_ADDR[15:2] + 5 and the data port is BASE_ADDR[15:2] + 6. 6.8.3 Base Address Low Register ⎯ Index 61h Bit 7-0 Name R/W Default 00h Description The LSB of GPIO index/data port address. The index port is BASE_ADDR[15:2] + 5 and the data port is BASE_ADDR[15:2] + 6. BASE_ADDR_LO R/W 85 2009 V1.1 Fintek 6.8.4 GPIRQ Channel Select Register ⎯ Index 70h Bit 7-4 3-0 Name Reserved SELGPIRQ R/W Default R/W 0h Feature Integration Technology Inc. F71869 Description Reserved. Select the IRQ channel for GPIO interrupt. 6.8.5 GPIO0 Output Enable Register ⎯ Index F0h Bit 7-6 5 4 3 2 1 0 Name Reserved GPIO05_OE GPIO04_OE GPIO03_OE GPIO02_OE GPIO01_OE GPIO00_OE R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Reserved. 0: GPIO05 is in input mode. 1: GPIO05 is in output mode. 0: GPIO04 is in input mode. 1: GPIO04 is in output mode. 0: GPIO03 is in input mode. 1: GPIO03 is in output mode. 0: GPIO02 is in input mode. 1: GPIO02 is in output mode. 0: GPIO01 is in input mode. 1: GPIO01 is in output mode. 0: GPIO00 is in input mode. 1: GPIO00 is in output mode. Description 6.8.6 GPIO0 Output Data Register ⎯ Index F1h Bit 7-6 5 4 3 2 1 0 Name Reserved GPIO05_VAL GPIO04_VAL GPIO03_VAL GPIO02_VAL GPIO01_VAL GPIO00_VAL R/W Default R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Reserved. 0: GPIO05 outputs 0 when in output mode. 1: GPIO05 outputs 1 when in output mode. 0: GPIO04 outputs 0 when in output mode. 1: GPIO04 outputs 1 when in output mode. 0: GPIO03 outputs 0 when in output mode. 1: GPIO03 outputs 1 when in output mode. 0: GPIO02 outputs 0 when in output mode. 1: GPIO02 outputs 1 when in output mode. 0: GPIO01 outputs 0 when in output mode. 1: GPIO01 outputs 1 when in output mode. 0: GPIO00 outputs 0 when in output mode. 1: GPIO00 outputs 1 when in output mode. Description 6.8.7 GPIO Pin Status Register ⎯ Index F2h Bit 7-6 Name Reserved R/W Default Reserved. Description 86 2009 V1.1 Fintek 5 4 3 2 1 0 GPIO05_IN GPIO04_IN GPIO03_IN GPIO02_IN GPIO01_IN GPIO00_IN R R R R R R - Feature Integration Technology Inc. F71869 The pin status of 3VSBSW/GPIO05 The pin status of SLOTOCC#/GPIO04 The pin status of TIMING1/GPIO03 The pin status of TIMING2/GPIO02 The pin status of TIMING4/GPIO01 The pin status of TIMING3/GPIO00 6.8.8 GPIO Drive Enable Register ⎯ Index F3h Bit 7 5 4 3 2 1 0 Name Reserved R/W Default 0 0 0 0 0 0 Reserved. 0: GPIO05 is open drain in output mode. 1: GPIO05 is push pull in output mode. 0: GPIO04 is open drain in output mode. 1: GPIO04 is push pull in output mode. 0: GPIO03 is open drain in output mode. 1: GPIO03 is push pull in output mode. 0: GPIO02 is open drain in output mode. 1: GPIO02 is push pull in output mode. 0: GPIO01 is open drain in output mode. 1: GPIO01 is push pull in output mode. 0: GPIO00 is open drain in output mode. 1: GPIO00 is push pull in output mode. Description GPIO05_DRV_EN R/W GPIO04_DRV_EN R/W GPIO03_DRV_EN R/W GPIO02_DRV_EN R/W GPIO01_DRV_EN R/W GPIO00_DRV_EN R/W 6.8.9 GPIO1 Output Enable Register ⎯ Index E0h Bit 7 6 5 4 3 2 1 0 Name GPIO17_OE GPIO16_OE GPIO15_OE GPIO14_OE GPIO13_OE GPIO12_OE GPIO11_OE GPIO10_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: GPIO17 is in input mode. 1: GPIO17 is in output mode. 0: GPIO16 is in input mode. 1: GPIO16 is in output mode. 0: GPIO15 is in input mode. 1: GPIO15 is in output mode. 0: GPIO14 is in input mode. 1: GPIO14 is in output mode. 0: GPIO13 is in input mode. 1: GPIO13 is in output mode. 0: GPIO12 is in input mode. 1: GPIO12 is in output mode. 0: GPIO11 is in input mode. 1: GPIO11 is in output mode. 0: GPIO10 is in input mode. 1: GPIO10 is in output mode. 87 2009 V1.1 Fintek 6.8.10 GPIO1 Output Data Register ⎯ Index E1h Bit 7 6 5 4 3 2 1 0 Name GPIO17_VAL GPIO16_VAL GPIO15_VAL GPIO14_VAL GPIO13_VAL GPIO12_VAL GPIO11_VAL GPIO10_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Feature Integration Technology Inc. F71869 Description 0: GPIO17 outputs 0 when in output mode. 1: GPIO17 outputs1 when in output mode. 0: GPIO16 outputs 0 when in output mode. 1: GPIO16 outputs1 when in output mode. 0: GPIO15 outputs 0 when in output mode. 1: GPIO15 outputs 1 when in output mode. 0: GPIO14 outputs 0 when in output mode. 1: GPIO14 outputs 1 when in output mode. 0: GPIO13 outputs 0 when in output mode. 1: GPIO13 outputs 1 when in output mode. 0: GPIO12 outputs 0 when in output mode. 1: GPIO12 outputs 1 when in output mode. 0: GPIO11 outputs 0 when in output mode. 1: GPIO11 outputs 1 when in output mode. 0: GPIO10 outputs 0 when in output mode. 1: GPIO10 outputs 1 when in output mode. 6.8.11 GPIO1 Pin Status Register ⎯ Index E2h Bit 7 6 5 4 3 2 1 0 Name GPIO17_IN GPIO16_IN GPIO15_IN GPIO14_IN GPIO13_IN GPIO12_IN GPIO11_IN GPIO10_IN R/W Default Description R R R R R R R R The pin status of CPU_PWRGD/GPIO17. The pin status of LED_VCC/GPIO16. The pin status of LED_VSB/ALERT#/GPIO15. The pin status of WDTRST#/GPIO14. The pin status of BEEP/GPIO13. The pin status of RSTCON#/GPIO12. The pin status of PCI_RST5#/GPIO11. The pin status of PCI_RST4#/GPIO10. 6.8.12 GPIO1 Drive Enable Register ⎯ Index E3h Bit 7 6 5 4 3 Name R/W Default 0 0 0 0 0 Description 0: GPIO17 is open drain in output mode. 1: GPIO17 is push pull in output mode. 0: GPIO16 is open drain in output mode. 1: GPIO16 is push pull in output mode. 0: GPIO15 is open drain in output mode. 1: GPIO15 is push pull in output mode. 0: GPIO14 is open drain in output mode. 1: GPIO14 is push pull in output mode. 0: GPIO13 is open drain in output mode. 1: GPIO13 is push pull in output mode. GPIO17_DRV_EN R/W GPIO16_DRV_EN R/W GPIO15_DRV_EN R/W GPIO14_DRV_EN R/W GPIO13_DRV_EN R/W 88 2009 V1.1 Fintek 2 1 0 GPIO12_DRV_EN R/W GPIO11_DRV_EN R/W GPIO10_DRV_EN R/W 0 0 0 Feature Integration Technology Inc. F71869 0: GPIO12 is open drain in output mode. 1: GPIO12 is push pull in output mode. 0: GPIO11 is open drain in output mode. 1: GPIO11 is push pull in output mode. 0: GPIO10 is open drain in output mode. 1: GPIO10 is push pull in output mode. 6.8.13 GPIO1 PME Enable Register ⎯ Index E4h Bit 7 6 5 4 3 2 1 0 Name R/W Default 0 0 0 0 0 0 0 0 Description When GPIO17_EVENT_STS is 1 and GPIO17_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO16_EVENT_STS is 1 and GPIO16_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO15_EVENT_STS is 1 and GPIO15_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO14_EVENT_STS is 1 and GPIO14_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO13_EVENT_STS is 1 and GPIO13_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO12_EVENT_STS is 1 and GPIO12_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO11_EVENT_STS is 1 and GPIO11_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO10_EVENT_STS is 1 and GPIO10_PME_EN is set to 1, a GPIO PME event will be generated. GPIO17_PME_EN R/W GPIO16_PME_EN R/W GPIO15_PME_EN R/W GPIO14_PME_EN R/W GPIO13_PME_EN R/W GPIO12_PME_EN R/W GPIO11_PME_EN R/W GPIO10_PME_EN R/W 6.8.14 GPIO1 Input Detection Select Register ⎯ Index E5h Bit 7 Name R/W Default 0 Description When GPIO17 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO16 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO15 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO14 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge GPIO17_DET_SEL R/W 6 GPIO16_DET_SEL R/W 0 5 GPIO15_DET_SEL R/W 0 4 GPIO14_DET_SEL R/W 0 89 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 3 GPIO13_DET_SEL R/W 0 When GPIO13 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO12 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO11 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO10 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 2 GPIO12_DET_SEL R/W 0 1 GPIO11_DET_SEL R/W 0 0 GPIO10_DET_SEL R/W 0 6.8.15 GPIO1 Event Status Register ⎯ Index E6h Bit 7 Name GPIO17_ EVENT_STS GPIO16_ EVENT_STS GPIO15_ EVENT_STS GPIO14_ EVENT_STS GPIO13_ EVENT_STS GPIO12_ EVENT_STS GPIO11_ EVENT_STS GPIO10_ EVENT_STS R/W Default R/W 0 Description When GPIO17 is in input mode and a GPIO17 input is detected according to CRE5[7], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO16 is in input mode and a GPIO16 input is detected according to CRE5[6], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO15 is in input mode and a GPIO15 input is detected according to CRE5[5], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO14 is in input mode and a GPIO14 input is detected according to CRE5[4], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO13 is in input mode and a GPIO13 input is detected according to CRE5[3], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO12 is in input mode and a GPIO12 input is detected according to CRE5[2], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO11 is in input mode and a GPIO11 input is detected according to CRE5[1], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO10 is in input mode and a GPIO10 input is detected according to CRE5[0], this bit will be set to 1. Write a 1 to this bit will clear it to 0. 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 6.8.16 GPIO2 Output Enable Register ⎯ Index D0h Bit Name R/W Default Description 90 2009 V1.1 Fintek 7 6 5 4 3 2 1 0 GPIO27_OE GPIO26_OE GPIO25_OE GPIO24_OE GPIO23_OE GPIO22_OE GPIO21_OE GPIO20_OE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Feature Integration Technology Inc. F71869 0: GPIO27 is in input mode. 1: GPIO27 is in output mode. 0: GPIO26 is in input mode. 1: GPIO25 is in output mode. 0: GPIO25 is in input mode. 1: GPIO25 is in output mode. 0: GPIO24 is in input mode. 1: GPIO24 is in output mode. 0: GPIO23 is in input mode. 1: GPIO23 is in output mode. 0: GPIO22 is in input mode. 1: GPIO22 is in output mode. 0: GPIO21 is in input mode. 1: GPIO21 is in output mode. 0: GPIO20 is in input mode. 1: GPIO20 is in output mode. 6.8.17 GPIO2 Output Data Register ⎯ Index D1h Bit 7 6 5 4 3 2 1 0 Name GPIO27_VAL GPIO26_VAL GPIO25_VAL GPIO24_VAL GPIO23_VAL GPIO22_VAL GPIO21_VAL GPIO20_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description 0: GPIO27 outputs 0 when in output mode. 1: GPIO27 outputs 1 when in output mode. 0: GPIO26 outputs 0 when in output mode. 1: GPIO26 outputs 1 when in output mode. 0: GPIO25 outputs 0 when in output mode. 1: GPIO25 outputs 1 when in output mode. 0: GPIO24 outputs 0 when in output mode. 1: GPIO24 outputs 1 when in output mode. 0: GPIO23 outputs 0 when in output mode. 1: GPIO23 outputs 1 when in output mode. 0: GPIO22 outputs 0 when in output mode. 1: GPIO22 outputs 1 when in output mode. 0: GPIO21 outputs 0 when in output mode. 1: GPIO21 outputs 1 when in output mode. 0: GPIO20 outputs 0 when in output mode. 1: GPIO20 outputs 1 when in output mode. 6.8.18 GPIO2 Pin Status Register ⎯ Index D2h Bit 7 6 5 4 3 Name GPIO27_IN GPIO26_IN GPIO25_IN GPIO24_IN GPIO23_IN R/W Default R R R R R Description The pin status of SIN2/GPIO27. The pin status of SOUT2/GPIO26. The pin status of DSR2#/GPIO25. The pin status of RTS2#/GPIO24. The pin status of DTR2#/GPIO23. 91 2009 V1.1 Fintek 2 1 0 GPIO22_IN GPIO21_IN GPIO20_IN R R R - Feature Integration Technology Inc. F71869 The pin status of CTS2#/GPIO22. The pin status of RI2#/GPIO21. The pin status of DCD2#/GPIO20. 6.8.19 GPIO2 Drive Enable Register ⎯ Index D3h Bit 7 6 5 4 3 2 1 0 Name R/W Default 0 0 0 0 0 0 0 0 Description 0: GPIO27 is open drain in output mode. 1: GPIO27 is push pull in output mode. 0: GPIO26 is open drain in output mode. 1: GPIO26 is push pull in output mode. 0: GPIO25 is open drain in output mode. 1: GPIO25 is push pull in output mode. 0: GPIO24 is open drain in output mode. 1: GPIO24 is push pull in output mode. 0: GPIO23 is open drain in output mode. 1: GPIO23 is push pull in output mode. 0: GPIO22 is open drain in output mode. 1: GPIO22 is push pull in output mode. 0: GPIO21 is open drain in output mode. 1: GPIO21 is push pull in output mode. 0: GPIO20 is open drain in output mode. 1: GPIO20 is push pull in output mode. GPIO27_DRV_EN R/W GPIO26_DRV_EN R/W GPIO25_DRV_EN R/W GPIO24_DRV_EN R/W GPIO23_DRV_EN R/W GPIO22_DRV_EN R/W GPIO21_DRV_EN R/W GPIO20_DRV_EN R/W 6.8.20 GPIO3 Output Enable Register ⎯ Index C0h Bit 7 6 5 4 3 2 1 0 Name GPIO37_OE GPIO36_OE GPIO35_OE GPIO34_OE GPIO33_OE GPIO32_OE GPIO31_OE GPIO30_OE R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Description 0: GPIO37 is in input mode. 1: GPIO37 is in output mode. (Open-drain). 0: GPIO36 is in input mode. 1: GPIO35 is in output mode. (Open-drain). 0: GPIO35 is in input mode. 1: GPIO35 is in output mode. (Open-drain). 0: GPIO34 is in input mode. 1: GPIO34 is in output mode. (Open-drain). 0: GPIO33 is in input mode. 1: GPIO33 is in output mode. (Open-drain). 0: GPIO32 is in input mode. 1: GPIO32 is in output mode. (Open-drain). 0: GPIO31 is in input mode. 1: GPIO31 is in output mode. (Open-drain). 0: GPIO30 is in input mode. 1: GPIO30 is in output mode. (Open-drain). 92 2009 V1.1 Fintek 6.8.21 GPIO3 Output Data Register ⎯ Index C1h Bit 7 6 5 4 3 2 1 0 Name GPIO37_VAL GPIO36_VAL GPIO35_VAL GPIO34_VAL GPIO33_VAL GPIO32_VAL GPIO31_VAL GPIO30_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Feature Integration Technology Inc. F71869 Description 0: GPIO37 outputs 0 when in output mode. 1: GPIO37 outputs 1 when in output mode. 0: GPIO36 outputs 0 when in output mode. 1: GPIO36 outputs 1 when in output mode. 0: GPIO35 outputs 0 when in output mode. 1: GPIO35 outputs 1 when in output mode. 0: GPIO34 outputs 0 when in output mode. 1: GPIO34 outputs 1 when in output mode. 0: GPIO33 outputs 0 when in output mode. 1: GPIO33 outputs 1 when in output mode. 0: GPIO32 outputs 0 when in output mode. 1: GPIO32 outputs 1 when in output mode. 0: GPIO31 outputs 0 when in output mode. 1: GPIO31 outputs 1 when in output mode. 0: GPIO30 outputs 0 when in output mode. 1: GPIO30 outputs 1 when in output mode. 6.8.22 GPIO3 Pin Status Register ⎯ Index C2h Bit 7 6 5 4 3 2 1 0 Name GPIO37_IN GPIO36_IN GPIO35_IN GPIO34_IN GPIO33_IN GPIO32_IN GPIO31_IN GPIO30_IN R/W Default R R R R R R R R Description The pin status of WGATE#/GPIO37. The pin status of HDSEL#/GPIO36. The pin status of STEP#/GPIO35. The pin status of DIR#/GPIO34. The pin status of WDATA#/GPIO3. The pin status of DRVA#/GPIO32. The pin status of MOA#/GPIO31. The pin status of DENSEL#/GPIO30. 6.8.23 GPIO4 Output Enable Register ⎯ Index B0h Bit 7 6 5 4 3 Name GPIO47_OE GPIO46_OE GPIO45_OE GPIO44_OE GPIO43_OE R/W Default Description R/W R/W R/W R/W R/W 0 0 0 0 0 0: GPIO47 is in input mode. 1: GPIO47 is in output mode. 0: GPIO46 is in input mode. 1: GPIO46 is in output mode. 0: GPIO45 is in input mode. 1: GPIO45 is in output mode. 0: GPIO44 is in input mode. 1: GPIO44 is in output mode. 0: GPIO43 is in input mode. 1: GPIO43 is in output mode. 93 2009 V1.1 Fintek 2 1 0 GPIO42_OE GPIO41_OE GPIO40_OE R/W R/W R/W 0 0 0 Feature Integration Technology Inc. F71869 0: GPIO42 is in input mode. 1: GPIO42 is in output mode. 0: GPIO41 is in input mode. 1: GPIO41 is in output mode. 0: GPIO40 is in input mode. 1: GPIO40 is in output mode. 6.8.24 GPIO4 Output Data Register ⎯ Index B1h Bit 7 6 5 4 3 2 1 0 Name GPIO47_VAL GPIO46_VAL GPIO45_VAL GPIO44_VAL GPIO43_VAL GPIO42_VAL GPIO41_VAL GPIO40_VAL R/W Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Description 0: GPIO47 outputs 0 when in output mode. 1: GPIO47 outputs 1 when in output mode. 0: GPIO46 outputs 0 when in output mode. 1: GPIO46 outputs 1 when in output mode. 0: GPIO45 outputs 0 when in output mode. 1: GPIO45 outputs 1 when in output mode. 0: GPIO44 outputs 0 when in output mode. 1: GPIO44 outputs 1 when in output mode. 0: GPIO43 outputs 0 when in output mode. 1: GPIO43 outputs 1 when in output mode. 0: GPIO42 outputs 0 when in output mode. 1: GPIO42 outputs 1 when in output mode. 0: GPIO41 outputs 0 when in output mode. 1: GPIO41 outputs 1 when in output mode. 0: GPIO40 outputs 0 when in output mode. 1: GPIO40 outputs 1 when in output mode. 6.8.25 GPIO4 Pin Status Register ⎯ Index B2h Bit 7 6 5 4 3 2 1 0 Name GPIO47_IN GPIO46_IN GPIO45_IN GPIO44_IN GPIO43_IN GPIO42_IN GPIO41_IN GPIO40_IN R/W Default R R R R R R R R Description The pin status of PS_ON#/GPIO47. The pin status of PWSOUT#/GPIO46 The pin status of PWSIN#/GPIO45 The pin status of ATXPG_IN/GPIO44 The pin status of IRRX/GPIO43. The pin status of IRTX/GPIO42. The pin status of FANCTL3/GPIO41. The pin status of FANIN3/GPIO40. 6.8.26 GPIO4 Drive Enable Register ⎯ Index B3h Bit 7-4 Name Reserved R/W Default Reserved Description 94 2009 V1.1 Fintek 3 2 1 0 GPIO43_DRV_EN R/W GPIO42_DRV_EN R/W GPIO41_DRV_EN R/W GPIO40_DRV_EN R/W 0 0 0 0 Feature Integration Technology Inc. F71869 0: GPIO43 is open drain in output mode. 1: GPIO43 is push pull in output mode. 0: GPIO42 is open drain in output mode. 1: GPIO42 is push pull in output mode. 0: GPIO41 is open drain in output mode. 1: GPIO41 is push pull in output mode. 0: GPIO40 is open drain in output mode. 1: GPIO40 is push pull in output mode. 6.8.27 GPIO4 PME Enable Register ⎯ Index B4h Bit 7-4 3 2 1 0 Name Reserved R/W Default 0 0 0 0 Reserved When GPIO43_EVENT_STS is 1 and GPIO43_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO42_EVENT_STS is 1 and GPIO42_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO41_EVENT_STS is 1 and GPIO41_PME_EN is set to 1, a GPIO PME event will be generated. When GPIO40_EVENT_STS is 1 and GPIO40_PME_EN is set to 1, a GPIO PME event will be generated. Description GPIO43_PME_EN R/W GPIO42_PME_EN R/W GPIO41_PME_EN R/W GPIO40_PME_EN R/W 6.8.28 GPIO4 Input Detection Select Register ⎯ Index B5h Bit 7-4 Name Reserved R/W Default Reserved When GPIO43 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO42 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO41 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge When GPIO40 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge Description 3 GPIO43_DET_SEL R/W 0 2 GPIO42_DET_SEL R/W 0 1 GPIO41_DET_SEL R/W 0 0 GPIO40_DET_SEL R/W 0 6.8.29 GPIO4 Event Status Register ⎯ Index B6h Bit Name R/W Default Description 95 2009 V1.1 Fintek 7-4 3 Reserved GPIO43_ EVENT_STS GPIO42_ EVENT_STS GPIO41_ EVENT_STS GPIO40_ EVENT_STS R/W Reserved Feature Integration Technology Inc. F71869 When GPIO43 is in input mode and a GPIO43 input is detected according to CRB5[3], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO42 is in input mode and a GPIO42 input is detected according to CRB5[2], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO41 is in input mode and a GPIO41 input is detected according to CRB5[1], this bit will be set to 1. Write a 1 to this bit will clear it to 0. When GPIO40 is in input mode and a GPIO40 input is detected according to CRB5[0], this bit will be set to 1. Write a 1 to this bit will clear it to 0. 2 R/W - 1 R/W - 0 R/W - 6.8.30 GPIO5 Output Enable Register ⎯ Index A0h Bit 7-5 4 3 2 1 0 Name Reserved GPIO54_OE GPIO53_OE GPIO52_OE GPIO51_OE GPIO50_OE R/W Default R/W R/W R/W R/W R/W 0 0 0 0 0 Reserved. 0: GPIO54 is in input mode. 1: GPIO54 is in output mode. 0: GPIO53 is in input mode. 1: GPIO53 is in output mode. 0: GPIO52 is in input mode. 1: GPIO52 is in output mode. 0: GPIO51 is in input mode. 1: GPIO51 is in output mode. 0: GPIO50 is in input mode. 1: GPIO50 is in output mode. Description 6.8.31 GPIO5 Output Data Register ⎯ Index A1h Bit 7-5 4 3 2 1 0 Name Reserved GPIO54_VAL GPIO53_VAL GPIO52_VAL GPIO51_VAL GPIO50_VAL R/W Default R/W R/W R/W R/W R/W 1 1 1 1 1 Reserved. 0: GPIO54 outputs 0 when in output mode. 1: GPIO54 outputs 1 when in output mode. 0: GPIO53 outputs 0 when in output mode. 1: GPIO53 outputs 1 when in output mode. 0: GPIO52 outputs 0 when in output mode. 1: GPIO52 outputs 1 when in output mode. 0: GPIO51 outputs 0 when in output mode. 1: GPIO51 outputs 1 when in output mode. 0: GPIO50 outputs 0 when in output mode. 1: GPIO50 outputs 1 when in output mode. Description 96 2009 V1.1 Fintek 6.8.32 GPIO5 Pin Status Register ⎯ Index A2h Bit 7-5 4 3 2 1 0 Name Reserved GPIO54_IN GPIO53_IN GPIO52_IN GPIO51_IN GPIO50_IN R/W Default R R R R R Reserved. Feature Integration Technology Inc. F71869 Description The pin status of DSKCHG#/GPIO54. The pin status of WPT#/GPIO53. The pin status of INDEX#/GPIO52. The pin status of TRK0#/GPIO51. The pin status of RDDATA#/GPIO50. 6.8.33 GPIO5 Drive Enable Register ⎯ Index A3h Bit 7-5 4 3 2 1 0 Name Reserved R/W Default 0 0 0 0 0 Reserved. 0: GPIO54 is open drain in output mode. 1: GPIO54 is push pull in output mode. 0: GPIO53 is open drain in output mode. 1: GPIO53 is push pull in output mode. 0: GPIO52 is open drain in output mode. 1: GPIO52 is push pull in output mode. 0: GPIO51 is open drain in output mode. 1: GPIO51 is push pull in output mode. 0: GPIO50 is open drain in output mode. 1: GPIO50 is push pull in output mode. Description GPIO54_DRV_EN R/W GPIO53_DRV_EN R/W GPIO52_DRV_EN R/W GPIO51_DRV_EN R/W GPIO50_DRV_EN R/W 6.8.34 GPIO6 Output Enable Register ⎯ Index 90h Bit 7-6 5 4 3 2 1 0 Name Reserved GPIO65_OE GPIO64_OE GPIO63_OE GPIO62_OE GPIO61_OE GPIO60_OE R/W Default R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Reserved. 0: GPIO65 is in input mode. 1: GPIO65 is in output mode. 0: GPIO64 is in input mode. 1: GPIO64 is in output mode. 0: GPIO63 is in input mode. 1: GPIO63 is in output mode. 0: GPIO62 is in input mode. 1: GPIO62 is in output mode. 0: GPIO61 is in input mode. 1: GPIO61 is in output mode. 0: GPIO60 is in input mode. 1: GPIO60 is in output mode. Description 6.8.35 GPIO6 Output Data Register ⎯ Index 91h Bit Name R/W Default Description 97 2009 V1.1 Fintek 7-6 5 4 3 2 1 0 Reserved GPIO65_VAL GPIO64_VAL GPIO63_VAL GPIO62_VAL GPIO61_VAL GPIO60_VAL R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Reserved. Feature Integration Technology Inc. F71869 0: GPIO65 outputs 0 when in output mode. 1: GPIO65 outputs 1 when in output mode. 0: GPIO64 outputs 0 when in output mode. 1: GPIO64 outputs 1 when in output mode. 0: GPIO63 outputs 0 when in output mode. 1: GPIO63 outputs 1 when in output mode. 0: GPIO62 outputs 0 when in output mode. 1: GPIO62 outputs 1 when in output mode. 0: GPIO61 outputs 0 when in output mode. 1: GPIO61 outputs 1 when in output mode. 0: GPIO60 outputs 0 when in output mode. 1: GPIO60 outputs 1 when in output mode. 6.8.36 GPIO6 Pin Status Register ⎯ Index 92h Bit 7-6 5 4 3 2 1 0 Name Reserved GPIO65_IN GPIO64_IN GPIO63_IN GPIO62_IN GPIO61_IN GPIO60_IN R/W Default R R R R R R Reserved. The pin status of BIT_SEL_OUT3/GPIO65. The pin status of BIT_SEL_OUT2/GPIO64. The pin status of BIT_SEL_OUT1/GPIO63. The pin status of BIT_SEL_IN3/GPIO62. The pin status of BIT_SEL_IN2/GPIO61. The pin status of BIT_SEL_IN1/GPIO60. Description 6.8.37 GPIO6 Drive Enable Register ⎯ Index 93h Bit 7-6 5 4 3 2 1 0 Name Reserved R/W Default 0 0 0 0 0 0 Reserved. 0: GPIO65 is open drain in output mode. 1: GPIO65 is push pull in output mode. 0: GPIO64 is open drain in output mode. 1: GPIO64 is push pull in output mode. 0: GPIO63 is open drain in output mode. 1: GPIO63 is push pull in output mode. 0: GPIO62 is open drain in output mode. 1: GPIO62 is push pull in output mode. 0: GPIO61 is open drain in output mode. 1: GPIO61 is push pull in output mode. 0: GPIO60 is open drain in output mode. 1: GPIO60 is push pull in output mode. Description GPIO65_DRV_EN R/W GPIO64_DRV_EN R/W GPIO63_DRV_EN R/W GPIO62_DRV_EN R/W GPIO61_DRV_EN R/W GPIO60_DRV_EN R/W 98 2009 V1.1 Fintek 6.9 BIT SELECT Registers (CR07) 6.9.1 VID Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved BSEL_EN R/W Default R/W 0 0 Reserved Feature Integration Technology Inc. F71869 Description 0: disable BSEL I/O port. 1: enable BSEL I/O port. 6.9.2 Base Address High Register ⎯ Index 60h Bit Name R/W Default R/W 00h Description The MSB of VID base address. 7-0 BASE_ADDR_HI 6.9.3 Base Address Low Register ⎯ Index 61h Bit Name R/W Default R/W 00h Description The LSB of VID base address. 7-0 BASE_ADDR_LO 6.9.4 Configuration Register ⎯ Index F0h (Offset 00h) (* Cleared by Slotocc# and watch dog timeout) Bit 7 Name WDOUT_EN R/W Default Description This bit is decided by RTS1# power-on trapping. R/W If this bit is set to 1 and watchdog timeout event occurs, WDTRST# output is enabled. 6-1 0 Reserved WD_RST_EN R/W 1 Reserved 0: Disable WDT to reset the VID register marked with *. 1: Enable WDT to reset the VID register marked with *. 6.9.5 BUS Manual Register ⎯ Index F2h (Offset 02h) Bit Name BSEL_MANUAL_ MODE R/W Default Description 0: BUSIN2-0 is bypassed to BUSOUT2-0. 7* R/W 1 1: BUSOUT2-0 is controlled by BSEL_MANUAL. This bit is reset by SLOTOCC# falling edge or WDT(with WD_RT_EN set). 6 5-3 2-0 KEY_OK Reserved BSEL_MANUAL R R/W R/W 1 2h This bit is 1 represents that the serial key is entered correctly. Reserved The output value for BUSOUT2-0 if BSEL_MANUAL_MODE is set. 6.9.6 Serial Key Data Register ⎯ Index F3h (Offset 03h) Bit Name R/W Default Description 99 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Write serial data to this register correctly, the KEY_OK bit will be 7-0 KEY_DATA R/W F3h set to 1. Hence, users are able to write key protected registers. The sequence to enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When KEY_OK is set, write this register 0x35 will clear KEY_OK. 6.9.7 BUSIN Status Register ⎯ Index F4h (Offset 04h) Bit 7-3 2:0 Name Reserved BSELIN_ST R/W Default R R 0 Reserved This is the pin status of BSEL_IN[2:0]. Description 6.9.8 Watchdog Timer Configuration Register 1⎯ Index F5h (Offset 05h) Bit Name R/W Default Description Select the WDT clock source. 0: The clock source is from CLKIN. (powered by VDD and is 7 WDT_CLK_SEL R 0 accurate)\ 1: The clock source is from internal 500KHz (powered by VSB3V and 20% tolerance). 6 WDTMOUT_STS R/W 0 If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this bit will clear it to 0. This bit is decided by RTS1# power-on trapping. If this bit is set to 1, the counting of watchdog time is enabled. Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit. Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. Select output polarity of RSTOUT# (1: high active, 0: low active) by setting this bit. Select output pulse width of RSTOUT# 1:0 WD_PSWIDTH R/W 0 0: 1 ms 2: 125 ms 1: 25 ms 3: 5 sec 5 WD_EN R/W - 4 WD_PULSE R/W 0 3 WD_UNIT R/W 0 2 WD_HACTIVE R/W 0 6.9.9 Watchdog Timer Configuration Register 2 ⎯ Index F6h (Offset 06h) Bit 7:0 Name WD_TIME R/W Default R/W 0A Time of watchdog timer Description 6.9.10 WDT PME Register ⎯ Index F7h (Offset 07h) Bit Name R/W Default Description 100 2009 V1.1 Fintek 7 6 WDT_PME WDT_PME_EN R R/W 0 0 Feature Integration Technology Inc. F71869 WDT PME real time status. 0: Disable WDT PME. 1: Enable WDT PME. 0: No WDT PME occurred. 6 WDT_PME_ST R/W 0 1: WDT PME occurred. The WDT PME is occurred one unit before WDT timeout. 4-1 Reserved R R/W C 0 Reserved This bit will be set at SLOTOCC# rising edge. Internal 1us de-bounce circuit is implemented. Write “1” to this bit will clear the status.(This bit is powered by VBAT.) 0 CPU_CHANGE 6.10 PME and ACPI Registers (CR0A) 6.10.1 Device Enable Register ⎯ Index 30h Bit 7-1 0 Name Reserved PME_EN R/W Default R/W 0 Reserved 0: disable PME. 1: enable PME. Description 6.10.2 PME Event Enable Register 1⎯ Index F0h Bit 7 Name WDT_PME_EN R/W Default R/W 0 WDT PME event enable. 0: disable WDT PME event. 1: enable WDT PME event. Mouse PME event enable. 0: disable mouse PME event. 1: enable mouse PME event. Keyboard PME event enable. 0: disable keyboard PME event. 1: enable keyboard PME event. Hardware monitor PME event enable. 0: disable hardware monitor PME event. 1: enable hardware monitor PME event. Parallel port PME event enable. 0: disable parallel port PME event. 1: enable parallel port PME event. UART 2 PME event enable. 0: disable UART 2 PME event. 1: enable UART 2 PME event. Description 6 MO_PME_EN R/W 0 5 KB_PME_EN R/W 0 4 HM_PME_EN R/W 0 3 PRT_PME_EN R/W 0 2 UR2_PME_EN R/W 0 101 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 1 UR1_PME_EN R/W 0 UART 1 PME event enable. 0: disable UART 1 PME event. 1: enable UART 1 PME event. FDC PME event enable. 0: disable FDC PME event. 1: enable FDC PME event. 0 FDC_PME_EN R/W 0 6.10.3 PME Event Status Register ⎯ Index F1h Bit 7 Name WDT_PME_ST R/W Default R/W Description WDT PME event status. 0: WDT has no PME event. 1: WDT has a PME event to assert. Write 1 to clear to be ready for next PME event. Mouse PME event status. 0: Mouse has no PME event. 1: Mouse has a PME event to assert. Write 1 to clear to be ready for next PME event. Keyboard PME event status. 0: Keyboard has no PME event. 1: Keyboard has a PME event to assert. Write 1 to clear to be ready for next PME event. Hardware monitor PME event status. 0: Hardware monitor has no PME event. 1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready for next PME event. Parallel port PME event status. 0: Parallel port has no PME event. 1: Parallel port has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 2 PME event status. 0: UART 2 has no PME event. 1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next PME event. UART 1 PME event status. 0: UART 1 has no PME event. 1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next PME event. FDC PME event status. 0: FDC has no PME event. 1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME event. 6 MO_PME_ST R/W - 5 KB_PME_ST R/W - 4 HM_PME_ST R/W - 3 PRT_PME_ST R/W - 2 UR2_PME_ST R/W - 1 UR1_PME_ST R/W - 0 FDC_PME_ST R/W - 6.10.4 PME Event Enable Register 2 ⎯ Index F2h Bit 7-3 Name Reserved R/W Default Reserved Description 102 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 2 RI2_PME_EN R/W 0 RI2# PME event enable. 0: disable RI2# PME event. 1: enable RI2# PME event. RI1# PME event enable. 0: disable RI1# PME event. 1: enable RI1# PME event. GPIO PME event enable. 0: disable GPIO PME event. 1: enable GPIO PME event. 1 RI1_PME_EN R/W 0 0 GP_PME_EN R/W 0 6.10.5 PME Event Status Register ⎯ Index F3h Bit 7-3 2 Name Reserved RI2_PME_ST R/W Default R/W Reserved RI2# PME event status. 0: RI2# has no PME event. 1: RI2# has a PME event to assert. Write 1 to clear to be ready for next PME event. RI1# PME event status. 0: RI1# has no PME event. 1: RI1# has a PME event to assert. Write 1 to clear to be ready for next PME event. WDT PME event status. 0: WDT has no PME event. 1: WDT has a PME event to assert. Write 1 to clear to be ready for next PME event. Description 1 RI1_PME_ST R/W - 0 WDT_PME_ST R/W - 6.10.6 Keep Last State Select Register ⎯ Index F4h Bit 7 6-5 4 3 Name Reserved Reserved EN_KBWAKEUP R/W Default Description R/W 0 0 0 0 Reserved Reserved Set one to enable keyboard wakeup event asserted via PWSOUT#. Set one to enable mouse wakeup event asserted via PWSOUT#. The ACPI Control the PSON_N to always on or always off or keep last state 00 : Keep last state 10 : Always on 01 : Bypass mode. 11: Always off When VSB 3V comes, it will set to 1, and write 1 to clear it EN_MOWAKEUP R/W 2-1 PWRCTRL R/W 11 0 VSB_PWR_LOSS R/W 0 6.10.7 VDDOK Delay Register ⎯ Index F5h Bit Name R/W Default Description 103 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 7-6 PWROK_DELAY R/W 0 The additional PWROK delay. 00: no delay 01: 100ms. 10: 200ms 11: 400ms. 0: RSTCON# will assert via PWROK. 1: RSTCON# will assert via PCIRST4# and PCIRST5#. The PWROK delay timing from VDD3VOK by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms Enable the PCIRSTIN_N and ATXPWGD de-bounce. Enable the LRESET_N de-bounce. Reserved 5 RSTCON_EN R/W 0 4-3 VDD_DELAY R/W 11 2 1 0 VINDB_EN PCIRST_DB_EN Reserved R/W R/W R/W 1 0 0 6.10.8 PCIRST Control Register ⎯ Index F6h Bit 7 Name S3_SEL R/W Default R/W 0 Description Select the KBC S3 state. 0: Enter S3 state when internal VDD3VOK signal de-asserted. 1: Enter S3 state when S3# is low or the TS3 register is set to 1. 0: PSON# is the inverted of S3# signal. 1: PSON# will sink low only if the time after the last turn-off elapse at least 4 seconds. Reserved Write “0” to this bit will force PCIRST5# to sink low. Write “0” to this bit will force PCIRST4# to sink low. Write “0” to this bit will force PCIRST3# to sink low. Write “0” to this bit will force PCIRST2# to sink low. Write “0” to this bit will force PCIRST1# to sink low. 6 5 4 3 2 1 0 PSON_DEL_EN Reserved PCIRST5_GATE PCIRST4_GATE PCIRST3_GATE PCIRST2_GATE PCIRST1_GATE R/W R/W R/W R/W R/W R/W 0 1 1 1 1 1 6.10.9 Power Sequence Control Register ⎯ Index F7h Bit 7 6 5 4 3 2 Name VDIMM_S3_ON VDDA_S3_ON VCORE_S3_ON VLDT_S3_ON R/W Default R/W R/W R/W R/W 1 0 0 0 0 1 Description 0: TIMING_1 will low during S3 state. 1: TIMING_1 will be tri-state during S3 state. 0: TIMING_2 will low during S3 state. 1: TIMING_2 will be tri-state during S3 state. 0: TIMING_3 will low during S3 state. 1: TIMING_3 will be tri-state during S3 state. 0: TIMING_4 will low during S3 state. 1: TIMING_4 will be tri-state during S3 state. Set “1” to enable WDTRST# assert from PWROK pin. 0: ATXPGSW# will sink low in S5 state. 1: ATXPGSW# will be tri-state in S5 state. WDT_PWROK_EN R/W ATXPG_SW_TRI R/W 104 2009 V1.1 Fintek 1 0 PWR_ST2_TRI Reserved R/W R/W 1 0 Feature Integration Technology Inc. F71869 0: ST2 will sink low in S5 state. 1: ST2 will be tri-state in S5 state. Reserved 6.10.10 LED VCC Mode Select Register ⎯ Index F8h Bit 7-6 Name Reserved LED_VCC_ S5_MODE R/W Default Reserved Select LED_VCC mode in S5 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VCC mode in S3 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VCC mode in S0 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Description 5-4 R/W 0 3-2 LED_VCC_ S3_MODE R/W 0 1-0 LED_VCC_ S0_MODE R/W 0 6.10.11 LED VSB Mode Select Register ⎯ Index F9h Bit 7-6 Name Reserved LED_VSB_ S5_MODE R/W Default Reserved Select LED_VSB mode in S5 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VSB mode in S3 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Select LED_VSB mode in S0 state. 00: Sink low. 01: Tri-state. 10: 0.5Hz clock. 11: 1Hz clock. Description 5-4 R/W 0 3-2 LED_VSB_ S3_MODE R/W 0 1-0 LED_VSB_ S0_MODE R/W 0 6.10.12 Bit RI De-bounce Select Register ⎯ Index FEh Name R/W Default Description 105 2009 V1.1 Fintek 7-2 Reserved Reserved Feature Integration Technology Inc. F71869 Select RI de-bounce time. 00: reserved. 01: 200us. 10: 2ms. 11: 20ms. 1-0 RI_DB_SEL R/W 0 106 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 7. Electrical Characteristic 7.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature reliability of the device RATING -0.5 to 5.5 -0.5 to VDD+0.5 0 to +70 -55 to 150 UNIT V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and 7.2 DC Characteristics (Ta = 0° C to 70° C, VCC = 3.3V ± 10%, VSS = 0V) PARAMETER Operating Voltage Battery Voltage Operating Current Idle State Current Battery Current SYM. VDD VBAT ICC ISTY IBAT MIN. 3.0 2.4 TYP. 3.3 3.3 35 5 4 MAX. 3.6 3.6 UNIT V V mA uA uA CONDITIONS VCC=3.3V VBAT=3.3V VCC=3.3V VBAT=3.3V VCC=3.3V VBAT=3.3V I/OD12st5v - TTL level and schmitt trigger bi-directional pin with 12 mA source-sink capability 5V tolerance Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Hysteresis 0.5 V Output Low Current IOL +12 mA VOL = 0.4V Input High Leakage ILIH -1 +1 μA Input Low Leakage ILIL -1 +1 μA I/O12 – Output pin with12mA source-sink capability ,5V tolerance Input Low Voltage VIL 0.8 V VDD = 3.3 V Input High Voltage VIH 2.0 V VDD = 3.3 V Hysteresis 0.5 V Output High Current IOH 12 mA VOH = 2.0 V Input High Leakage ILIH -1 +1 μA Input Low Leakage ILIL -1 +1 μA INts_5v – TTL level input pin and schmitt trigger, 5V tolerance Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Hysteresis 0.5 V Input High Leakage ILIH +1 μA Input Low Leakage ILIL -1 μA 107 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 8. Ordering Information Part Number F71869F Package Type 128-PQFP (Green Package) Production Flow Commercial, 0°C to +70°C 9. Package Dimensions (128-PQFP) Figure 20 128 Pin PQFP Package Diagram Feature Integration Technology Inc. Headquarters 3F-7, No 36, Tai Yuan St., Chupei City, Hsinchu, Taiwan 302, R.O.C. TEL : 886-3-5600168 FAX : 886-3-5600166 www: http://www.fintek.com.tw Taipei Office Bldg. K4, 7F, No.700, Chung Cheng Rd., Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037 108 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner 109 2009 V1.1 Fintek 10. Application Circuit (GND close to IC) VSB3V VBAT VSB3V RSMRST# COPEN# DD3+ D2+ D1+ VREF VIN6 VIN5 VDIMM(VIN4) VDDA(VIN3) VLDT(VIN2) VCORE(VIN1) SLCT PE BUSY 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Feature Integration Technology Inc. F71869 VCC5V PWOK PSON# S3# PWSOUT# PWSIN# PME# ATXPG_IN S5# PCIRST3# PCIRST2# PCIRST1# MCLK MDAT KCLK KDAT OVT# CPU_PWRGD LED_VCC R3 R4 R1 R2 R5 VSB3V VCC3V 1K 1K 1K 1K 1K WPT# INDEX# TRK0# RDATA# DSKCHG# S3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 D ENSEL# INDEX# MOA# DRVA# DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# HDSEL# DSKCHG# ATXPG_IN R6 4.7k RSMRST# PWOK R7 4.7k HEADER 17X2 FLOPPY CONN. TIMING GPIO BITSEL GPIO DTR1# SOUT1# FANCTL1 FANCTL2 FANCTL3 R8 1K R9 1K R10 1K R11 1K R12 1K R13 1K R14 1K ACK# SLIN# INIT# ERR# AFD# STB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 DCD1# RI1# CTS1# DTR1# RTS1# DSR1# SOUT1 SIN1 DCD2# RI2# CTS2# GPIO23/DTR2# GPIO24/RTS2# GPIO25/DSR2# VCC GPIO26/SOUT2 GPIO27/SIN2 GPIO30/DENSEL# GPIO31/MOA# GPIO32/DRVA# GPIO33/WDATA# GPIO34/DIR# GPIO35/STEP# GPIO36/HDSEL# GPIO37/WGATE# GPIO50/RDATA# GPIO51/TRK0# GPIO52/INDEX# GPIO53/WPT# GPIO54/DSKCHG# GND FANIN1 FANCTL1 FANIN2 FANCTL2 GPIO40/FANIN3 GPIO41/FANCTL3 GPIO42/IRTX GPIO43/IRRX LRESET# LDRQ# SERIRQ LFRAM# LAD0 LAD1 LAD2 LAD3 VCC PCICLK 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 BUSY PE SLCT VSB VIN1(VCORE) VIN2(VLDT) VIN3(VDDA) VIN4(VDIMM) VIN5 VIN6 VREF D+(CPU) D2+ D3+(SYSTEM) AGND(D-) COPEN# VBAT RSMRST# PWOK PS_ON#/GPIO73 S3# PWSOUT#/GPIO72 PWSIN#/GPIO71 PME# ATXPG_IN/GPIO70 S5# PCIRST3# PCIRST2# PCIRST1# GND MCLK MDATA KCLK KDATA VSB OVT# CPU_PWRGD/GPIO17 GPIO16/LED_VCC RSMRST# and PWROK pull-up 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 WDTRST# LED_VSB WDTRST# ATX_PWRGDSW RSTCON# IBX_DAT IBX_CLK PECI PECI_REQ# ST1 ST2 TIMING_1 TIMING_2 TIMING_GPIO BITSEL_OUT3 BITSEL_OUT2 BITSEL_OUT1 TIMING_4 TIMING_3 BITSEL_GPIO BITSEL_IN3 BITSEL_IN2 BITSEL_IN1 GA20 KBRST# CLK_24/48M ACK# SLIN# INIT# ERR# AFD# STB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GND DCD1# RI1# CTS1# DTR1#/FAN40_100 RTS1#/WDTRST# DSR1# SOUT/CONFIG4E_2E SIN1 GPIO20/DCD2# GPIO21/RI2# GPIO22/CTS2# F71869 GPIO15/LED_VSB/ALERT# WDTRST#/GPIO14 ATX_PWRGDSW/GPIO13/BEEP GPIO12/RSTCON#/FANCTL_1 GPIO11/PCIRST5#/IBX_SDA GPIO10/PCIRST4#/IBX_SCL PECI/TSI_DAT/IBX_SDA PECI_REQ#/TSI_CLK/IBX_SCL ST1/GPIO05/WDTRST# ST2/SLOTOCC#/GPIO04 TIMING_1/GPIO03 TIMING_2/GPIO02 TIMING_GPIO BITSEL_OUT3/GPIO65 BITSEL_OUT2/GPIO64 BITSEL_OUT1/GPIO63 GND TIMING_4/GPIO01 TIMING_3/GPIO00 BITSEL_GPIO BITSEL_IN3/GPIO62 BITSEL_IN2/GPIO61 BITSEL_IN1/GPIO60 GA20 KBRST# CLKIN TIMING_GPIO POWER-ON TRIP PIN Function NET Name HI LO BITSEL_GPIO 26 24 22 121 VSB3V 124 45 R15 4.7k R16 4.7k 52 FANCTL3 FANCTL2 FANCTL1 DTR1# SOUT1# BITSEL/GPIO TIMING/GPIO FANCTL3 FANCTL2 FANCTL1 Config 4E/2E FAN40_100 BITSEL/GPIO TIMING/GPIO PWM FAN PWM FAN PWM FAN 4E LINEAR FAN LINEAR FAN LINEAR FAN 2E FAN SPEED DUTY:100% GPIO GPIO GA20 KBRST# CLK_24/48M FAN SPEED DUTY:40% BITSEL TIMING F71869 DTR2# RTS2# DSR2# SOUT2 SIN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 1 1 1 1 VCC3V C1 0.1U C2 0.1U C3 0.1UF C4 2 2 2 2 2 VCC3V 0.1U 1 DENSEL# MOA# DRVA# WDATA# DIR# STEP# HDSEL# WGATE# RDATA# TRK0# INDEX# WPT# DSKCHG# PCICLK LAD3 LAD2 LAD1 LAD0 LFRAME# SERIRQ LDRQ# LRESET# IRRX IRTX FANCTL3 FANIN3 FANCTL2 FANIN2 FANCTL1 FANIN1 ST1 ST2 ST1 & ST2 Pull-up VCC3V VCC3V VCC3V VSB3V VBAT C5 0.1U Title Size B Date: Feature Integration Technology Inc. Document Number F71869F&FDD Tuesday , May 05, 2009 Sheet 1 of 6 Rev 0.11 (Place capacitor close to IC) 110 2009 V1.1 Fintek 2 D1 1 2 4 6 8 2 4 6 8 2 4 6 8 2 4 6 8 1N5819 FOR LEKAGE TO POWER Feature Integration Technology Inc. VCC5V 20 VCC5V RI1# CTS1# DSR1# RTS1# DTR1# SIN1 SOUT1 DCD1# 19 18 17 16 15 14 13 12 11 U1 VCC RY 1 RY 2 RY 3 DA1 DA2 RY 4 DA3 RY 5 GND +12V RA1 RA2 RA3 DY 1 DY 2 RA4 DY 3 RA9 -12V 1 2 3 4 5 6 7 8 9 10 +12V RIN1 CTSN1 DSRN1 RTSN1 DTRN1 SINN1 SOUTN1 DCDN1 -12V F71869 GND RIN1 DTRN1 CTSN1 SOUTN1 RTSN1 SINN1 DSRN1 DCDN1 VCC3V P1 RN1 RN2 RN3 RN4 2.7K-8P4R 2.7K-8P4R 2.7K-8P4R 2.7K-8P4R 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7 R23 2.7K 5 9 4 8 3 7 2 6 1 R18 4.7K DCD1# RI1# CTS1# DSR1# SIN1 R19 4.7K R20 4.7K R21 4.7K R22 4.7K RN5 STB# AFD# INIT# SLIN# 1 3 5 7 33-8P4R RN6 PD0 PD1 PD2 PD3 1 3 5 7 33-8P4R RN7 PD4 PD5 PD6 PD7 1 3 5 7 33-8P4R ERR# ACK# BUSY PE SLCT 2 4 6 8 2 4 6 8 2 4 6 8 UART DB9 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J2 UART 1 PORT INTERFACE If you do not use the UART port 1, please pull-up these pin to VCC3V. VCC3V VCC5V RI2# CTS2# DSR2# RTS2# DTR2# SIN2 SOUT2 DCD2# 20 19 18 17 16 15 14 13 12 11 U2 VCC RY 1 RY 2 RY 3 DA1 DA2 RY 4 DA3 RY 5 GND +12V RA1 RA2 RA3 DY 1 DY 2 RA4 DY 3 RA9 -12V 1 2 3 4 5 6 7 8 9 10 +12V RIN2 CTSN2 DSRN2 RTSN2 DTRN2 SINN2 SOUTN2 DCDN2 -12V GND RIN2 DTRN2 CTSN2 SOUTN2 RTSN2 SINN2 DSRN2 DCDN2 5 9 4 8 3 7 2 6 1 P2 R24 4.7K DCD2# RI2# CTS2# DSR2# SIN2 R25 4.7K R26 4.7K R27 4.7K R28 4.7K UART DB9 DB25 (FEMALE) C13 180pC15 180p C6 180p C16 180p C7 180p C17 180p C8 180p C18 180p C9 180p C19 180p C10 180p C20 180p C11 180p C21 180p C12 180p C14 C22 180p 180p UART 2 PORT INTERFACE supported by F71869. If you do not use the UART port 2, please pull-up these pin to VCC3V. RING-IN Wake-up is PARALLEL PORT INTERFACE VSB5V J3 1 2 3 CON3 VCC5V R29 4.7K If you do not use the KBC, please pull-up these pin to VSB5V. F1 FUSE M-DIN_6-R JS1 1 2 3 6 5 4 R31 4.7K R32 4.7K F2 FUSE M-DIN_6-R JS2 1 2 3 6 5 4 IRTX IRRX C23 C29 0.1U 0.1U Title Size B Date: VCC5V/3V JP1 1 2 3 4 5 HEADER 5 R30 4.7K L1 MDAT FB L3 MCLK C24 100P C25 100P FB C26 0.1U KCLK C27 100P C28 100P KDAT L2 FB L4 FB Feature Integration Technology Inc. Document Number Printer &UART Tuesday , May 05, 2009 Sheet 2 of 6 Rev 0.11 PS2 MOUSE INTERFACE PS2 KEYBOARD INTERFACE IR INTERFACE 111 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 D1+ C30 DR34 VCORE R35 VLDT 1K_1% 1K_1% VCORE(VIN1) VLDT(VIN2) DR36 VDDA R37 10K_1% VDIMM(VIN4) 10K_1% VDDA(VIN3) D3+ C32 R38 VDIMM R39 10K_1% VREF R38 R39 D1+ VREF D2+ VREF D3+ R46 10K 1% R42 10K 1% R40 10K 1% RT1 10K 1% VBAT (for system) RT2 10K 1% R43 2M (for system) RT3 10K 1% COPEN# C33 1000P 2 SW1 1 4.7K D3300P D2+ C31 3300P 3300P THERMDC from CPU R33 4.7K THERMDA VCC3V Q1 PNP 3906 for SYSTEM Q2 PNP 3906 for SYSTEM OVT# OVT Pull-up DIODE SENSING CIRCUIT THERMISTOR DDR2(1.8V) 12K_1% 15K_1% THERMISTOR DDR3 (1.5V) 6k 12k THERMISTOR (for system) VDIMM Input Level Must > 1V T T T THERMISTOR SENSING CIRCUIT R41 VCC1.5V R44 200K_1% R45 20K_1% 10K_1% VIN5 CASE OPEN CIRCUIT Temperature Sensing +12V VIN6 *VIN1 VIN2 VIN3 VIN4 internal pull-down 225K ohm VOLTAGE SENSING. VSB5V VSB3V R49 4.7K LED_VCC R47 4.7K PLED Q3 LED_VSB VSB3V R50 4.7K VSB5V R48 4.7K SUSLED Q4 Title Size B Date: Feature Integration Technology Inc Document Number Hardware Monitor Tuesday , May 05, 2009 Sheet 3 of 6 Rev 0.13 112 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 12V +12V 8 U3A 1 LM358 JP3 R59 10K C35 47u 3 2 1 CON3 C36 R51 4.7K D2 1N4148 C34 + FANCTL1 R57 100 47U 4 HEADER 4 3 2 1 JP2 R55 27K R58 10K C37 0.1U R61 3.9K FANIN1 3 R53 4.7K FANCTL1 2 + 4 PMOS Q5 D3 1N4148 R54 4.7K R56 27K 0.1u R60 10K FANIN1 VCC5V R52 10K (4 PIN FAN Control) DC FAN Control with OP 1 PWM FAN 1 SPEED CONTROL 12V +12V R62 R64 4.7K 8 4.7K Q7 PNP D4 1N4148 JP4 3 2 1 HEADER 3 5 R66 4.7K R70 27K R71 10K C41 0.1U R74 3.9K FANCTL2 6 U3B 7 LM358 JP5 R72 10K C39 47u 3 2 1 CON3 C40 + 4 R63 4.7K PMOS Q6 D5 1N4148 R67 4.7K R68 27K 0.1u R73 10K FANIN2 VCC3V R65 4.7K R69 330 F ANCTL2 Q8 + MOSFET N 2N7002 47U C38 FANIN2 PWM FAN 2 SPEED CONTROL +12V DC FAN Control with OP 2 12V R76 4.7K R75 R77 4.7K 4.7K Q10 PNP 8 D6 1N4148 JP6 3 2 1 HEADER 3 U4A 1 VCC3V R78 4.7K R81 330 R79 4.7K R82 27K R83 10K C45 0.1U 3 FANCTL3 FANIN3 2 PMOS Q9 D7 1N4148 R80 4.7K JP7 C43 47u 3 2 1 CON3 R84 27K C44 0.1u R86 10K FANIN3 + 4 FANCTL3 C42 Q11 + MOSFET N 2N7002 47U LM358 R85 10K R87 3.9K PWM FAN 3 SPEED CONTROL DC FAN Control with OP 3 FAN CONTROL FOR PWM OR DC 113 2009 V1.1 Fintek Feature Integration Technology Inc. F71869 VDDIO R69 300 R70 300 PECI PECI_REQ# SIC SID PECI R71 100K (avoid pre-bios floating) PECI_Client Client AMD_TSI Client INTEL PECI VSB3V R72 4.7K TIMING1 TIMING2 TIMING3 TIMING4 VCC3V R73 4.7K VCC3V R74 4.7K VCC3V R75 4.7K 2.5V R76 4.7K CPU_PWRGD CPU_PWRGD Pull-Up Power Sequence Pull-up Title Size A Date: Feature Integration Technology Inc. Document Number AMDSI/PECI Wednesday , May 06, 2009 Sheet 4 of 5 Rev 0.11 114 2009 V1.1 Fintek CPU Feature Integration Technology Inc. VCC3 F71869 1 3 2 1K-8P4R 4 1K-8P4R NORTH BRIDGE IDE ATA 133 PCIRST1# PCIRST1# PCIRST2# VSB3 FRONT PANEL VSB3 SATA*2 SOUTH BRIDGE 1 2 R97 4.7K R99 1 33 Front Panel 2 7 RESET PSW8 R98 12 2 C46 0.1UF 5 RSTGND PSW+ 6 -PWR_BTN 1 2 R96 4.7K 1 RSTCON# PCIRST2# LRESET# F71869 PCI S3# PWSOUT# RSMRST# PCIRST3# VSB5 1 R101 4.7K -12V 2 ATX1 3V3 3V3 -12V 3V3 GND GND PS-ON 5V GND GND GND 5V GND GND -5V PW-OK 5V 5VSB 5V 12V VSB5 VCC3 VCC5 2 1 1 3 1 1K 2 4.7K 4 4.7K 2 VSB3 VCC3 PCLK_1,2,3(33MHz) PWSIN# ATXPG_IN PSON# VCC5 1 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 R102 4.7K Title +12V VSB5 TC1 22uF Size A Date: Feature Integration Technology Inc. Document Number Example_ACPI Tuesday , May 05, 2009 Sheet 6 of 6 Rev 0.10 ATX CONNECTOR ATX CONNECTOR Figure 21 F71869F Application Circuit 2 115 2009 V1.1