33287

Freescale Semiconductor Technical Data Document Number: MC33287 Rev. 5.0, 2/2007 Contact Monitoring and Dual Low-Side Protected Driver The 33287 interfaces between switch contacts and a microcontroller. Eight switch-to-battery (or switch-to-ground) sense monitor switch status. Additionally, two internal low-side switches are available to control inductive or capacitive loads. The 33287 has eight sense inputs (rated at 40 V) with thresholds ratiometric to VBAT. One sense input has a dedicated output for direct interfacing to the MCU and the remaining seven inputs are multiplexed interfaced to the MCU. The two low-side switch outputs are current limited to 535 mA and internally clamped to 50 V. Outputs also have independent overtemperature shutdown and diagnostic reporting. Features • • • • Eight High-Voltage Sense Inputs Direct Interfacing to Microcontroller Two Current Limited Low-Side Drivers Drivers Internally Overvoltage Clamped and Thermally Protected • 55 µA Standby Current • Pb-Free Packaging Designated by Suffix Code EG 33287 AUTOMOTIVE CONTACT MONITORING AND DUAL LOW-SIDE PROTECTED DRIVER DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42343B 20-PIN SOICW ORDERING INFORMATION Device MC33287DW/R2 -40 to 125°C MCZ33287EG/R2 20 SOICW Temperature Range (TA) Package GND Sense 5.0 V 33287 VBAT VDD1 IN0 IN1 AD0 AD1 AD2 OUT1 OUT7 CD1 OUTD1 CD2 OUTD2 GND MCU VDD2 VDD 8 Sense to GND or VBAT Inputs IN2 IN3 IN4 IN5 IN6 IN7 VBAT Sense Figure 1. Simplified Application Design Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM IN0 Internal Supply IN1 IN2 IN3 IN4 IN5 IN6 IN7 VDD2 VDD1 AD2 Multiplexer 8 to 1 and Diagnostic Logic DIAGD1 DIAGD2 OUT7 AD1 OUT1 AD0 Fault Detector OUTD1 Overtemperature Fault Detector Overtemperature OUTD2 Detection Control Current Limitation VDD2 Detection Control Current Limitation GND CD1 CD2 Figure 2. 33287 Simplified Internal Block Diagram 33287 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS VDD1 IN3 IN2 IN1 IN0 AD0 AD1 AD2 OUTD1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD2 IN4 IN5 IN6 IN7 OUT7 OUT1 CD1 CD2 OUTD2 Figure 3. 33287 Pin Connections Table 1. 33287 Pin Definitions Pin Number Pin Name 1, 20 5, 4, 3, 2, 19, 18, 17, 16 6, 7, 8 9, 11 10 12, 13 14 15 VDD1, VDD2 IN0 – IN7 Formal Name Voltage Power Input 0 – 7 Definition These are high-voltage power supply 5.0 V pins (VBAT). These are high-voltage input pins. AD0 – AD2 OUTD1, OUTD2 GND CD1, CD2 OUT1 OUT7 Address Output Drain Ground Command Driver Output 1 Output 7 These pins are the addresses for mode and input selection. These two are output driver pins (drain). This pin in the ground for the logic and analog circuitry of the device. These are the two driver command pins. This is the output (multiplexed Output 1 = 0 to 6.0 V for IN0 to IN6 and DIAGD1 or DIAGD2) and DIAGD2 pins. This is the direct output from IN7 pin. 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Power Supply Voltage Normal Operation (Steady-State) Load Dump Conditions Logic Supply Voltage (Continuous) Input Pin Voltage (1) ESD Voltage (2) Human Body Model Machine Model Operating Ambient Temperature Storage Temperature Power Dissipation (TA = 85°C) Peak Package Reflow Temperature During Reflow Thermal Resistance Junction-to-Ambient (3) (4) Symbol VDD1 Value Unit V 24 40 VDD2 VIN VESD1 VESD2 TA TSTG PD , TPPRT RθJ-A 7.0 40 V V V ±2000 ±200 -40 to 125°C -65 to 150 0.7 Note 4. 100 °C °C W °C °C/W Notes 1 With Serial Resistor ≥ 25 kΩ 2 ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 3. 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33287 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 7.0 V ≤ VDD1 ≤ 18 V, 4.75 V ≤ VDD2 ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Extended limit is 5.0 V ≤ VDD1 ≤ 7.0 V and other parameters are full specification in this mode. Inputs IN1–IN7 and lowside drivers are still functional with down-graded characteristics. Characteristic SUPPLY VOLTAGE (VDD1 AND VDD2 PINS) Operational Supply Voltage Full Specification Extend Limit Operational Supply Voltage (Full Specification) Supply Current Standby Mode VDD1 ≤ 14 V VCD1 = VDD2, VCD2 = 0 V Supply Current in Drivers on Configuration (Full Specification) VCD1 = 0 V VCD2 = VDD2 OUTPUT DRIVERS CHARACTERISTICS (OUTD1 AND OUTD2 PINS) Output Resistance (Full Specification and TJ ≤ 130°C) Output Resistance (Extent Limit and TJ ≤ 130°C) Leakage Current (Internal Current Source) PROTECTION AND LEVEL DETECTION (OUTD1 AND OUTD2 PINS) Positive Output Clamp Output Current Limitation (130°C ≥ TJ) Output Fault Detector Level Overtemperature Detection (at 25°C by Function Simulation) INPUTS (CD1 AND CD2 PINS) Input Voltage Low Input Voltage High Hysteresis Input Current on Pin CD1 (Internal Pull-Up and CD1 Connected to Ground) Leakage Current on Pin CD1 (Internal Pull-Up Connected to VDD2) Input Current on Pin CD2 (Internal Pull Down CD2 Connected to VDD2) Leakage Current on Pin CD2 (Internal Pull-Up CD1 Connected to Ground) Notes 5 All INn and ADn inputs are connected to ground. VIL VIH VHST ICD1 ILEAK ICD2 ILEAK — 8.0 x VDD2 500 -100 -5.0 10 -5.0 — — 800 -30 — 30 — 4.0 x VDD2 — — -10 5.0 100 5.0 V V mV µA µA µA µA VCLAMP ILIM VFAULT TDETEC 40 300 2.0 145 50 535 2.75 160 60 750 3.5 175 V mA V °C RDS(ON) RDS(ON) ILEAK — — 1.0 1.40 — — 3.20 5.0 13 Ω Ω µs (5) (5) Symbol Min Typ Max Unit VDD1 V 7.0 5.0 12 — — 18 7.0 — V µA VDD2 4.75 IVDD1-0 — — 55 — 110 10 µA IVDD2-0 IVDD1-1 — — 250 650 1500 1500 IVDD2-1 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 7.0 V ≤ VDD1 ≤ 18 V, 4.75 V ≤ VDD2 ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Extended limit is 5.0 V ≤ VDD1 ≤ 7.0 V and other parameters are full specification in this mode. Inputs IN1–IN7 and lowside drivers are still functional with down-graded characteristics. Characteristic INPUTS (IN0 TO IN7 PINS) Input Voltage Low (Full Specification) Input Voltage Low (Extended Limit) Input Voltage High (Full Specification and Extended Limit) Hysteresis (5.0 V < VDD1 < 16 V) Input Current (VIN < 16 V) Input Voltage Clamp (I = 100 µA) INPUTS (AD0, AD1, AND AD2 PINS) Input Voltage Low Input Voltage High Hysteresis Input Current OUTPUTS (OUT1 AND OUT7 PINS) Output Voltage Low (ILOAD = 2.0 mA) Output Voltage High (ILOAD = -2.0 mA) VOL VOH — 8.0 x VDD2 — — 2.0 x VDD2 — V V VIL VIH VHYS ILEAK — 8.0 x VDD2 500 -5.0 — — 750 — 4.0 x VDD2 — — 5.0 V V mV µA VIL VIL VIH VHYS ILEAK VINCLAMP — — 7.0 x VDD1 5.0 5.0 17 — — — 1.0 — 20 4.0 x VDD1 3.0 x VDD1 — — 5.0 23 V V V V µA V Symbol Min Typ Max Unit 33287 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic OUTPUT DRIVERS CHARACTERISTICS (OUTD1 AND OUTD2 PINS) Turn ON Delay Time Turn OFF Delay Time Output Rising Edge Output Falling Edge Difference Between Command Duration and Bit Duration tON tOFF tRISE tFALL ∆BIT — — — — -5.0 1.3 2.1 2.8 1.0 — 10 10 10 10 5.0 µs µs µs µs µs Symbol Min Typ Max Unit 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CD2 t tCOMMAND OUTD2 80% 50% ∆Bit = tCOMMAND- tBIT 80% tBIT 50% 20% tOFF tFALL Figure 4. Timing Characteristics VBAT 20% tON tRISE t R1 = 500 Ω C1 = 2.0 nF C2 = 250 pF CD1 OUTD1 R2 = 47 kΩ VBAT R1 = 500 Ω CD2 f = 5.0 kHz C1 = 2.0 nF C2 = 250 pF OUTD2 R2 = 47 kΩ Figure 5. Timing Test Configuration 33287 8 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 5. Drivers Function Table CD1 (6) High Level for Logic Signals Low Level for Logic Signals High Level for Logic Signals Low Level for Logic Signals CD2 (7) OUTD1 High Level for Drivers Outputs Low Level for Drivers Outputs Low Level for Drivers Outputs High Level for Drivers Outputs OUTD2 High Level for Drivers Outputs Low Level for Drivers Outputs Low Level for Drivers Outputs High Level for Drivers Outputs DIAGD1 (8) High Level for Logic Signals High Level for Logic Signals Low Level for Logic Signals Low Level for Logic Signals DIAGD2 High Level for Logic Signals High Level for Logic Signals Low Level for Logic Signals Low Level for Logic Signals Status Driver 1 Normally OFF Driver 1 Normally ON Driver 1 Shorted to GND or Open Load Driver 1 Overloaded Status Driver 2 Normally OFF Driver 2 Normally ON Driver 2 Shorted to GND or Open Load Driver 2 Overloaded Low Level for Logic Signals High Level for Logic Signals Low Level for Logic Signals High Level for Logic Signals Notes 6 CD1 is active on low level (driver 1 is on when CD1 is low). 7 CD2 is active on high level (driver 2 is on when CD2 is high. 8 DIAGD1 output is neither latched nor filtered. Table 6. Eight-to-One Data Multiplexer Function Inputs OUT1 AD2 High Impedance Low Level Low Level Low Level Low Level High Level High Level High Level High Level AD1 High Impedance Low Level Low Level High Level High Level Low Level Low Level High Level High Level AD0 High Impedance Low Level High Level Low Level High Level Low Level High Level Low Level High Level Unknown IN0(9) IN1 IN2 IN3 IN4 IN5 IN6 DIAGD1 or DIAGD2(10) Notes 9 IN0 to IN6 are the normalized values. 10 DIAGD1 or DIAGD2 are the values of the selected internal fault detector. See Table 7. 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 7. Fault Detector Selection Inputs OUT1 AD2 Unknown Unknown High Level Unknown Unknown High Level AD1 Unknown Low Level High Level Unknown High Level High Level AD0 Unknown High Level High Level Unknown Low Level High Level Unknown Unknown DIAGD1 Unknown Unknown DIAGD2 33287 10 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS TYPICAL APPLICATIONS 8 contacts to Vbat or GND 5V Regulator VDD Vbat 1 VDD1 IN3 IN2 IN1 IN0 AD0 AD1 AD2 D1 GND VDD2 IN4 IN5 IN6 IN7 OUT7 OUTi CD1 CD2 D2 20 I/O PORT 470nF 2 19 3 18 4 17 5 16 6 15 MICROCONTROLLER 7 14 Relay 8 13 Relay (65Ω) Lamp (1,2W) Resistor 9 12 10 11 Lamp Figure 6. Typical Application Configuration VBAT 47 kΩ 500 Ω VBAT 500 Ω 10 nF 10 nF 47 kΩ Contact to VBAT Figure 7. Contact Configuration Contact to GND 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS IN0 VALIM IN1 IN2 IN3 IN4 IN5 IN6 IN7 AD2 OUT7 AD1 8 TO 1 LOGIC MULTIPLEXER OUTi AD0 VDD2 All the symbols represented without supply pin are connected to VDD2 DIAGD1 NQ Q VDD1 R S VDD2 DIAGD2 VALIM VALIM GND OUTD2 CD2 S R Q VALIM + - VDD2 OUTD2 Driver CD1 OUTD1 OUTD1 Driver NOTE: The only difference between the low side driver 1 and 2 is the polarity of the command. Also, there is an integral pull-up at pin CD1, and an internal pull-down at pin CD2. Figure 8. Electrical Schematic 33287 12 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGE PACKAGE DIMENSIONS PACKAGE PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DW SUFFIX EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42343B REV. J 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 13 REVISION HISTORY REVISION HISTORY REVISION 4.0 DATE 11/2006 DESCRIPTION OF CHANGES • • • • • Converted to Freescale format with the current form and style Implemented Revision History page Updated Package Drawing 98ASB42343B to Rev. J Added EG Pb-FREE suffix Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com. Corrected Internal Block Diagram on page 2 Restated Definition for OUT1 in 33287 Pin Definitions on page 3 Corrected value for Storage Temperature on page 4 Corrected unit for Output Resistance (Extent Limit and TJ ≤ 130°C) on page 5 Corrected Electrical Schematic on page 12 Restated note 4 in Maximum Ratings on page 4. 5.0 2/2007 • • • • • • 33287 14 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. MC33287 Rev. 5.0 2/2007