33892

Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Document order number: MC33892 Rev 1.0, 03/2004 Preliminary Information Quad Intelligent High-Side Switch (Dual 10 mΩ and Dual 35 mΩ) The 33892 is one in a family of devices designed for low-voltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (two 10 mΩ, two 35 mΩ) can control the high sides of four separate resistive or inductive loads or serve as high-side switches for a pair of DC motors. 33892 QUAD INTELLIGENT HIGH-SIDE SWITCH Freescale Semiconductor, Inc... Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for PWM control if desired. The 33892 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33892 is packaged in a power-enhanced 10 x 10 nonleaded Power QFN package with exposed tabs. Features • Dual 10 mΩ and Dual 35 mΩ High-Side Switches • Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA • SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting • SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Terminal Status, and Program Status • Analog Current Feedback with Selectable Ratio • Enhanced 16 V Reverse Polarity VPWR Protection Simplified Application Diagram VPWR VDD VDD VDD VPWR PNC SUFFIX CASE 1558-02 24-TERMINAL PQFN ORDERING INFORMATION Device PC33892PNC/R2 Temperature Range (TA) -40°C to 125°C Package 24 PQFN 33892 Simplified Application Diagram 33892 VDD WAKE SO SCLK CS SI MCU I/O I/O I/O I/O I/O I/O A/D GND SI SCLK CS SO RST FS IN0 IN1 IN2 IN3 CSNS FSI GND HS3 LOAD 3 HS2 LOAD 2 HS1 LOAD 1 VPWR HS0 LOAD 0 This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. VDD VPWR Internal Regulator Over/Undervoltage Protection Selectable Slew Rate Gate Drive Freescale Semiconductor, Inc... CS SCLK SO SI RST WAKE FS IN0 IN1 IN2 IN3 SPI 3.0 MHz Selectable Current Limit HS[0:1]: 100 A or 70 A HS[2:3]: 50 A or 35 A Logic Selectable Current Detection Time 0.15 ms–620 ms Open Load Detection Overtemperature Detection Selectable Overcurrent Detection HS[0:1]: 4.8 A–18.2 A HS[2:3]: 2.4 A–9.1 A HS0 HS0 HS1 Programmable Watchdog 310 ms–2500 ms HS1 HS2 HS2 FSI HS3 Selectable Output Current Recopy (Analog MUX) HS[0:1]: 1/13000 or 1/40000 HS[2:3]: 1/6500 or 1/20000 HS3 GND CSNS Figure 1. 33892 Simplified Internal Block Diagram 33892 2 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. RST IN3 3 IN2 VDD SO GND 11 12 13 10 9 8 7 65 4 21 IN1 CS FS SI Transparent Top View of Package WAKE SCLK GND 24 23 22 IN0 CSNS FSI GND 14 HS3 15 21 HS2 16 Freescale Semiconductor, Inc... VPWR HS1 17 18 HS1 19 HS0 20 HS0 TERMINAL FUNCTION DESCRIPTION Terminal 1 2 3 24 4 Terminal Name IN1 IN2 IN3 IN0 Formal Name Serial Inputs Definition The IN0–IN3 high-side input terminals are used to directly control HS0–HS3 high-side output terminals, respectively. An SPI register determines if each input is activated or if the input logic state is ORed or ANDed with the SPI instruction. These terminals are to be driven with 5.0 V CMOS levels, and they have an internal active pull-down current source. This terminal is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is detected, this terminal is active LOW. Specific device diagnostic faults are reported via the SPI SO terminal. This terminal is an input that controls the device mode and watchdog timeout feature if enabled. An internal clamp protects this terminal from high damaging voltages when the output is current limited with an external resistor. This input has an internal passive pull-down. These terminals are the ground for the logic and analog circuitry of the device. This terminal is an input used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. The terminal also starts the watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not be allowed to be logic [1] until VDD is in regulation. This terminal has an internal passive pull-down. This terminal is an input terminal connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS terminal of the selected device logic LOW, thereby enabling SPI communication with the device. Other unselected devices on the serial link having their CS terminals pulled up logic HIGH disregard the SPI communication data sent. This terminal has an internal active pull-up current source and requires CMOS logic levels. This terminal is an input terminal connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS level serial clock signal is idle between command transfers. The signal is used to shift data into and out-of the device. This terminal has an internal active pull-down. FS Fault Status (Active Low) 5 WAKE Wake 6, 13, 15 7 GND RST Ground Reset 8 CS Chip Select (Active Low) 9 SCLK Serial Clock MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 3 Freescale Semiconductor, Inc. TERMINAL FUNCTION DESCRIPTION (continued) Terminal 10 Terminal Name SI Formal Name Serial Input Definition This terminal is a command data input terminal connected to the SPI Serial Data Output of the MCU or to the SO terminal of the previous device of a daisy chain of devices. The input requires CMOS logic level signals and incorporates an internal active pull-down. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register. This terminal has an internal active pull-down. This terminal is an external voltage input terminal used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. This terminal is an output terminal connected to the SPI Serial Data Input terminal of the MCU or to the SI terminal of the next device of a daisy chain of devices. This output will remain tri-stated (high-impedance OFF condition) so long as the CS terminal of the device is logic HIGH. SO is only active when the CS terminal of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. This terminal connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. Protected 35 mΩ high-side power output terminals to the load. Protected 10 mΩ high-side power output terminals to the load. The value of the resistance connected between this terminal and ground determines the state of the outputs after a Watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF or the output HSO only is ON. If the FSI terminal is left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the Fail-Safe state. When the FSI terminal is connected to GND, the Watchdog circuit and Fail-Safe operation are disabled. This terminal incorporates an active internal pullup. The Current Sense terminal sources a current proportional to the designated HS0– HS3 output. That current is fed into a ground referenced resistor and its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This terminal can be tri-stated through SPI. 11 VDD Digital Drain Voltage (Power) 12 SO Serial Output Freescale Semiconductor, Inc... 16 VPWR Positive Power Supply 14 21 17, 18 19, 20 22 HS3 HS2 HS1 (Note 1) HS0 (Note 2) FSI High-Side Outputs High-Side Outputs Fail-Safe Input 23 CSNS Output Current Monitoring Notes 1. HS1 output (17 and 18) must be connected externally on the PCB as close as possible to the terminals. 2. HS0 output (19 and 20) must be connected externally on the PCB as close as possible to the terminals. 33892 4 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Operating Voltage Range Steady-State VDD Supply Voltage Input/Output Voltage (Note 3) VDD VIN[0:3], RST, FSI, CSNS, SI, SCLK, CS, FS VSO ICL(WAKE) ICL(CSNS) IHS0, IHS1 IHS2, IHS3 ECL0, ECL1 ECL2, ECL3 TSTG TA TJ RθJC RθJA VESD1 VESD2 TSOLDER Symbol VPWR(SS) -16 to 41 0 to 5.5 -0.3 to 7.0 V V Value Unit V SO Output Voltage (Note 3) WAKE Input Clamp Current -0.3 to VDD +0.3 2.5 10 25 12 TBD TBD -55 to 150 -40 to 125 -40 to 150 V mA mA A A J J Freescale Semiconductor, Inc... CSNS Input Clamp Current Output Current (Note 4) Output Current (Note 4) Output Clamp Energy (Note 5) Output Clamp Energy (Note 5) Storage Temperature Operating Ambient Temperature Operating Junction Temperature Thermal Resistance Junction to Case Junction to Ambient ESD Voltage Human Body Model (Note 6) Machine Model (Note 7) Terminal Soldering Temperature (Note 8) °C °C °C °C/W 0.01 µF connected from high-side outputs to GND. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 5 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER INPUT Battery Supply Voltage Range Fully Operational VPWR Operating Supply Current Outputs ON, IHS[0:3] = 0 A VPWR Supply Current IPWR(sby) – IPWR(sleep) – – VDD(on) IDD(on) – – IDD(sleep) VPWR(OV) VPWR(OVHYS) VPWR(UV) VPWR(UVHYS) VPWR(UVPOR) – 28 0.2 4.75 – – – – – 32 0.8 5.24 0.25 – 1.0 5.0 5.0 36 1.5 5.75 – 5.0 µA V V V V V 4.5 – – 5.0 10 50 5.5 V mA – 5.0 µA IPWR(on) – – 20 mA VPWR 6.0 – 27 mA V Freescale Semiconductor, Inc... Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) TJ = 25°C TJ = 85°C VDD Supply Voltage VDD Supply Current No SPI Communication 3.0 MHz SPI Communication VDD Sleep State Current Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage Shutdown Threshold (Note 9) Undervoltage Hysteresis (Note 10) Undervoltage Power-ON Reset Notes 9. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 10. This applies when the undervoltage fault is not latched (IN = 0). 33892 6 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS0 AND HS1 Output Drain-to-Source ON Resistance (IHS[0:1] = 10 A, TJ = 25°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Drain-to-Source ON Resistance (IHS[0:1] = 10 A, TJ = 150°C) VPWR = 6.0 V RDS(ON)150 – – – RSD(ON) – 10 20 A IOCH0 IOCH1 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 CSR0 CSR1 CSR0_ACC -20 -14 -13 -12 -13 -13 – – – – – – 20 14 13 12 13 13 80 56 100 70 120 84 A 14.6 13.0 11.5 10.0 8.4 6.9 5.4 3.8 18.2 16.3 14.4 12.5 10.5 8.6 6.7 4.8 22.8 20.4 18 15.7 13.2 10.8 8.4 6.0 – – – 1/13000 1/40000 – – % – – – 26 17 17 mΩ RDS(ON)25 – – – – – – 15 10 10 mΩ mΩ Freescale Semiconductor, Inc... VPWR = 10 V VPWR = 13 V Output Source-to-Drain ON Resistance (Note 11) IHS = 15 A, TJ = 25°C, VPWR = -12 V Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V) 000 001 010 011 100 101 110 111 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR0) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A Notes 11. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 7 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS0 AND HS1 (continued) Current Sense Ratio (CSR1) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A Maximum Current Sense Clamp Voltage ICSNS = 15 mA Open Load Detection Current (Note 12) Output Fault Detection Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5 A < = IHS < = 2.0 A, Output OFF Overtemperature Shutdown (Note 13) TA = 125°C, Output OFF Overtemperature Shutdown Hysteresis (Note 13) TSD(HYS) TSD 150 5.0 175 – 190 20 VCL -20 – – IOLDC VOFD(THRES) 2.0 3.0 4.0 V VCL(MAXCSNS) 4.5 30 6.0 – 7.0 100 µA V -25 -19 -18 -17 -18 -18 – – – – – – 25 19 18 17 18 18 V CSR1_ACC % Freescale Semiconductor, Inc... °C °C OUTPUTS HS2 AND HS3 Output Drain-to-Source ON Resistance (IHS[2:3] = 5.0 A, TJ = 25°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Drain-to-Source ON Resistance (IHS[2:3] = 5.0 A, TJ = 150°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Source-to-Drain ON Resistance (Note 14) IHS = 15 A, TJ = 25°C, VPWR = -12 V Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 IOCH0 IOCH1 40 28 50 35 62 43 RDS(ON) – 35 70 A RDS(ON)150 – – – – – – 94 60 60 mΩ RDS(ON)25 – – – – – – 55 35 35 mΩ mΩ Notes 12. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 13. Guaranteed by process monitoring. Not production tested. 14. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. 33892 8 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS2 AND HS3 (continued) Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V) 000 001 010 011 100 101 110 111 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR2) Accuracy Output Current 2.0 A 5.0 A 10 A 12.5 A 15 A 20 A Current Sense Ratio (CSR3) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A Maximum Current Sense Clamp Voltage ICSNS = 15 mA Open Load Detection Current (Note 15) Output Fault Detection Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5 A < = IHS < = 2.0 A, Output OFF Overtemperature Shutdown (Note 16) TA = 125°C, Output OFF Overtemperature Shutdown Hysteresis (Note 16) TSD(HYS) TSD 150 5.0 175 – 190 20 VCL -20 – – IOLDC VOFD(THRES) 2.0 3.0 4.0 V VCL(MAXCSNS) 4.5 30 6.0 – 7.0 100 µA V -25 -19 -18 -17 -18 -18 – – – – – – 25 19 18 17 18 18 V CSR3_ACC -20 -14 -13 -12 -13 -13 – – – – – – 20 14 13 12 13 13 % CSR2 CSR3 CSR2_ACC – – 1/6500 1/20000 – – % IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 7.2 6.5 5.7 5.0 4.2 3.4 2.6 1.9 9.1 8.15 7.2 6.25 5.25 4.3 3.35 2.4 11 9.8 8.7 7.5 6.3 5.2 4.1 2.9 – A Freescale Semiconductor, Inc... °C °C Notes 15. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 16. Guaranteed by process monitoring. Not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 9 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CONTROL INTERFACE Input Logic High Voltage (Note 17) Input Logic Low Voltage (Note 17) Input Logic Voltage Hysteresis (Note 17) Input Logic Pull-Down Current (SCLK, IN, SI, IN[0:3]) RST Input Voltage Range VIH VIL VIN(HYS) IDWN VRST CSO IDWN CIN VCL(WAKE) 0.7VDD – 100 5.0 4.5 – 100 – – – 350 – 5.0 – 200 4.0 – 0.2VDD 750 20 5.5 20 400 12 V V mV µA V pF kΩ pF V Freescale Semiconductor, Inc... SO, FS Tri-State Capacitance (Note 18) Input Logic Pull-Down Resistor (RST) and WAKE Input Capacitance (Note 19) Wake Input Clamp Voltage (Note 20) ICL(WAKE) < 2.5 mA Wake Input Forward Voltage ICL(WAKE) = -2.5 mA SO High-State Output Voltage IOH = 1.0 mA FS, SO Low-State Output Voltage 7.0 VF(WAKE) -2.0 VSOH 0.8VDD VSOL – ISO(LEAK) -5.0 IUP 5.0 RFS RFSdis RFSoffoff RFSonoff RFSonon – 6.0 15 30 – 14 V – -0.3 V – – V IOL = -1.6 mA SO Tri-State Leakage Current CS > 0.7 VDD 0.2 0.4 µA 0 5.0 µA Input Logic Pull-Up Current (Note 21) CS, VIN > 0.7 VDD – 20 kΩ FSI Input terminal External Pull-Down Resistance (Note 22) FSI Disabled, HS[0:3] Indeterminate FSI Enabled, all HS OFF FSI Enabled, HS0 ON, HS[1:3] OFF FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF 0 6.5 17 Infinite 1.0 7.0 19 – Notes 17. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 18. 19. 20. 21. 22. Parameter is guaranteed by process monitoring but is not production tested. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0 V. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance value will always be within the desired (specified) range. 33892 10 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING HS0, HS1, HS2, AND HS3 Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 23) 9.0 V < VPWR < 16 V Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 24) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 23) 9.0 V < VPWR < 16 V SRRA_FAST 0.2 SRRB_FAST 0.015 SRFA_SLOW 0.1 SRFB_SLOW 0.015 SRFA_FAST 0.4 SRFB_FAST 0.05 tDLY(ON) 2.0 tDLY_SLOW(OFF) 40 tDLY_FAST(OFF) 20 fPWM – 120 – 400 300 Hz ms 460 1000 µs 30 200 µs 0.175 0.6 µs 1.0 2.0 V/µs 0.05 0.15 V/µs 0.3 0.5 V/µs 0.05 0.5 V/µs 0.5 1.5 V/µs SRRB_SLOW 0.015 0.05 0.15 V/µs SRRA_SLOW 0.1 0.3 0.5 V/µs V/µs Freescale Semiconductor, Inc... Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 24) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 23) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 24) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 23) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 24) 9.0 V < VPWR < 16 V Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 25) DICR = 0, DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 26) DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 26) DICR = 1 Direct Input Switching Frequency (DICR D3 = 0) Overcurrent Low Detection Blanking Time (OCLT[1:0]) 00 01 10 11 tOCL0 tOCL1 tOCL2 tOCL3 108 434 55 0.08 155 620 75 0.15 202 806 95 0.25 Notes 23. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V (see Figure 2, page 14). These parameters are guaranteed by process monitoring. 24. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V (see Figure 2). These parameters are guaranteed by process monitoring. 25. Turn-ON delay time measured from rising edge of any signal (IN[0:3], SCLK, CS) that would turn the output ON to VHS = 0.5 V with RL = 5.0 Ω resistive load. 26. Turn-OFF delay time measured from falling edge of any signal (IN[0:3], SCLK, CS) that would turn the output OFF to VHS = VPWR -0.5 V with RL = 5.0 Ω resistive load. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 11 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING HS0, HS1, HS2, AND HS3 (continued) Overcurrent High Detection Blanking Time CS to CSNS Valid Time (Note 27) tOCH CNSVAL tWDTO0 tWDTO1 tWDTO2 tWDTO3 1.0 – 10 – 20 10 µs µs ms Watchdog Timeout (WD[1:0]) (Note 28) 00 01 10 11 496 248 2000 1000 620 310 2500 1250 806 403 3250 1625 Freescale Semiconductor, Inc... Notes 27. Time necessary for the CSNS to be with ±5% of the targeted value. 28. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. 33892 12 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit SPI INTERFACE CHARACTERISTICS Maximum Frequency of SPI Operation Required Low State Duration for RST (Note 29) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 30) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 30) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 30) fSPI tWRST tCS tENBL tLEAD tWSCLKh tWSCLKl tLAG tSI(SU) tSI(HOLD) tRSO – – – – – – – – – – – 50 – – 50 – – 50 25 25 3.0 350 300 5.0 167 167 167 167 83 83 MHz ns ns µs ns ns ns ns ns ns ns Freescale Semiconductor, Inc... Required High State Duration of SCLK (Required Setup Time) (Note 30) Required Low State Duration of SCLK (Required Setup Time) (Note 30) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 30) SI to Falling Edge of SCLK (Required Setup Time) (Note 31) Falling Edge of SCLK to SI (Required Setup Time) (Note 31) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (Note 31) SI, CS, SCLK, Incoming Signal Fall Time (Note 31) Time from Falling Edge of CS to SO Low Impedance (Note 32) Time from Rising Edge of CS to SO High Impedance (Note 33) Time from Rising Edge of SCLK to SO Data Valid (Note 34) 0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF Notes 29. 30. 31. 32. 33. 34. – 25 50 ns tFSO – 25 – – – 65 50 50 50 145 145 tRSI tFSI tSO(EN) tSO(DIS) tVALID – – – – ns ns ns ns ns – 65 105 RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33892 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS. Time required to obtain valid data out from SO following the rise of SCLK. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 13 Freescale Semiconductor, Inc. Timing Diagrams CS VPWR VPWR VPWR - 0.5V VPWR -0.5 V VPWR - 3V VPWR -3.5 V SRRB SRrB SRFB SRfB SRFA SRfA SRRA SRrA 0.5V 0.5 V tDLY(OFF) Tdly(off) Freescale Semiconductor, Inc... t dly(on) TDLY(ON) Figure 2. Output Slew Rate and Time Delays IOCHx ILOAD2 Load Current ILOAD1 tOCH IOCLx tOCLx Time Figure 3. Overcurrent Shutdown 33892 14 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. IOCH0 IOCH1 IOCL0 IOCL1 Load Current IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 Freescale Semiconductor, Inc... Time tOCH tOCL3 tOCL2 tOCL1 tOCL0 Figure 4. Overcurrent Low and High Detection VIH V IH RSTB RST 0.2 VDD 0.2 VDD TwRSTB VIL TCSB t CS VIL tWRST tENBL TENBL 0.7 VDD 0.7VDD CS CSB 0.7 VDD 0.7VDD tTlead LEAD tWSCLKh TwSCLKh tRSI TrSI VIH V IH VIL V IL SCLK SCLK 0.7 VDD 0.7VDD 0.2 VDD 0.2VDD tLAG Tlag VIH VIH VIL V tSI(SU) TSIsu tWSCLKl TwSCLKl IL tSI(HOLD) TSI(hold) tTfSI FSI VIH V Valid Don’t Care IH SI SI Don’t Care 0.7 VDD 0.7 VDD 0.2VDD 0.2 VDD Valid Don’t Care VIH VIL Figure 5. Input Timing Switching Characteristics MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 15 Freescale Semiconductor, Inc. tRSI tFSI TrSI 3.5 3.5V V TfSI VOH VOH 50% 1.0V 1.0 V VOL VOL SCLK SCLK tSO(EN) TdlyLH SO SO 0.7 VDD 0.7 VDD VOH VOH VOL VOL 0.2 VDD 0.2 VDD TrSO tRSO TVALID tVALID Freescale Semiconductor, Inc... Low-to-High Low to High SO SO 0.7 VDD High to Low High-to-Low 0.7 VDD TfSO tFSO VVOH OH TdlyHL tSO(DIS) 0.2VDD 0.2 VDD VVOL OL Figure 6. SCLK Waveform and Valid SO Data Delay Time 33892 16 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33892 is one in a family of devices designed for lowvoltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (two 10 mΩ, two 35 mΩ) can control the high sides of four separate resistive or inductive loads or serve as high-side switches for a pair of DC motors. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for PWM control if desired. The 33892 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33892 is packaged in a power-enhanced 10 x 10 PQFN package with exposed tabs. FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... SPI Protocol Description The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). The SI/SO terminals of the 33892 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions: Serial Input (SI) This is a serial interface (SI) command data input terminal. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI terminal, starting with D15 to D0. The internal registers of the 33892 are configured and controlled using a 5-bit addressing scheme described in Table 1, page 18. Register addressing and configuration are described in Table 2, page 19. The SI input has an internal pulldown, IDWN. Serial Output (SO) The SO data terminal is a tri-stateable output from the shift register. The SO terminal remains in a high-impedance state until the CS terminal is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO terminal changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and input status descriptions are provided in Table 9, page 22. Serial Clock (SCLK) The SCLK terminal clocks the internal shift registers of the 33892 device. The serial input (SI) terminal accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) terminal shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK terminal be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK terminal be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an internal pull-down. When CS is logic [1], signals at the SCLK and SI terminals are ignored and SO is tri-stated (high impedance) (see Figure 7, page 18). Chip Select (CS) The CS terminal enables communication with the master microcontroller (MCU). When this terminal is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33892 latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The 33892 transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an internal pull-up, IUP. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 17 Freescale Semiconductor, Inc. CSB CS CS SCLK SI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SO OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Freescale Semiconductor, Inc... NOTES: 1. 2. 3. Notes 1. RST is a logic [1] state during the above operation. RSTB is in a logic H state during the 2. D15–D0 relate to the mostabove operation. entry of data into the device. recent ordered device. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC 3. OD15–OD0 relate to the first 16 bits of ordered fault and status data out of the device. device. OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC Figure 7. Single 16-Bit Word SPI Communication Serial Input Communication SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 1). Each incoming command message on the SI terminal can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit. In some cases, output channel selection is done with bits D12–D11. The next three bits, D10–D8, are used to select the command register. The remaining five bits, D4–D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 33892 has defined registers, which are used to configure the device and to control the state of the outputs. Table 2, page 19, summarizes the SI registers. LSB Table 1. SI Message Bit Assignment Bit Sig SI Msg Bit Message Bit Description MSB D15 D14–D15 D12–D11 D10–D8 D7–D5 D4–D1 Watchdog in: toggled to satisfy watchdog requirements. Not used. Register address bits used in some cases for output channel selection. Register address bits. Not used. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content. D0 33892 18 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. Table 2. Serial Input Address and Configuration Bit Map SI Register SI Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 STATR OCR0 OCR1 SOCHLR_s CDTOLR_s DICR_s UOVR WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN x x x x x x x x x x x x x x x x x x x x x x x A1 A1 A1 x x x x x 0 1 A0 A0 A0 0 1 x x 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x SOA4 x x x x x x x x x SOA3 IN_SPI3 CSNS EN3 SOCH_s OL_DIS_s SOA2 IN_SPI2 CSNS EN2 SOCL2_s OCL_DIS_s SOA1 IN_SPI1 SOA0 IN_SPI0 CSNS EN1 CSNS EN0 SOCL1_s OCLT1_s SOCL0_s OCLT0_s A/O_s OV_DIS WD0 FAST_SR_s CSNS_high_s DIR_DIS_s x x x x UV_DIS WD1 Freescale Semiconductor, Inc... WDR NAR TEST No Action (Allow Toggling of D15–WDIN) Motorola Internal Use (Test) x =Don’t care. s=Output selection with the bits A1A0 as defined in Table 3. Device Register Addressing The following section describes the possible register addresses and their impact on device operation. Address xx000—Status Register (STATR) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device status, this feature provides the ability to read the content of the OCR0, OCR1, SOCHLR, CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 21.) Address x0001—Output Control Register (OCR0) The OCR0 register allows the MCU to control the ON/OFF state of four outputs through the SPI. Incoming message bit D[3:0] reflects the desired states of the four high-side outputs (IN_SPI), respectively. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF. Address x1001—Output Control Register (OCR1) Incoming message bit D[3:0] reflects the desired channel that will be mirrored on the Current Sense (CSNS) terminal. A logic [1] on message bit D[3:0] enables the CSNS terminal for the outputs HS3–HS0, respectively. In the event that the current sense is enabled for multiple outputs, the current will be summed. In the event that all bits D[3:0] are logic [0], the output CSNS will then tri-stated. This is useful when several CSNS terminals of several devices share the same A/D converter. Address A1A0010 — Select Overcurrent High and Low Register (SOCHLR_s) The SOCHLR_s register allows the MCU to configure the output overcurrent low and high detection levels, respectively. Each output “s” is independently selected for configuration based on the state of the D12–D11 bits (Table 3). Table 3. Channel Selection A1 (D12) A0 (D11) HS_s 0 0 1 1 0 1 0 1 HS0 HS1 HS2 HS3 Each output can be configured to different levels. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements matching system characteristics. Bits D2–D0 set the overcurrent low detection level to one of eight possible levels, as shown in Table 4, page 20. Bit D3 sets the overcurrent high detection level to one of two levels, as outlined in Table 5, page 20. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 19 Freescale Semiconductor, Inc. Table 4. Overcurrent Low Detection Levels SOCL2_s* (D2) SOCL1_s* (D1) SOCL0_s* (D0) Overcurrent Low Detection (Amperes) HS0 or HS1 HS2 or HS3 A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent low detection feature. When disabled, there is no timeout for the selected output and the overcurrent low detection feature is disabled. A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL) detection feature for the channel corresponding to the state of bits D12–D11. Address A1A0100—Direct Input Control Register (DICR) The DICR register is used by the MCU to enable, disable, or configure the direct IN terminal control of each output. Each output is independently selected for configuration based on the state bits D12–D11 (refer to Table 3, page 19). For the selected output, a logic [0] on bit D1 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the Input was enabled for direct control, a logic [1] for the D0 (A/O_s) bit will result in a Boolean AND of the IN terminal with its corresponding IN_SPI D[4:0] message bit when addressing OCR0. Similarly, a logic [0] on the D0 terminal results in a Boolean OR of the IN terminal to the corresponding message bits when addressing the OCR0. This register is especially useful if several loads are required to be independently PWM controlled. For example, the IN terminals of several devices can be configured to operate all of the outputs with one PWM output from the MCU. If each output is then configured to be Boolean ANDed to its respective IN terminal, each output can be individually turned OFF by SPI while controlling all of the outputs, commanded on with the single PWM output. A logic [1] on bit D2 (CSNS_high_s) is used to select the high ratio on the CSNS terminal for the selected output. The default value [0] is used to select the low ratio (Table 7). Table 7. Current Sense Ratio CSNS_high_s* (D2) Current Sense Ratio HS0 or HS1 HS2 or HS3 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 18.2 16.3 14.4 12.5 10.5 8.6 6.7 4.8 9.1 8.15 7.2 6.25 5.25 4.3 3.35 2.4 Freescale Semiconductor, Inc... 1 * “_s” refers to the channel, which is selected through bits D12–D11; refer to Table 3, page 19. Table 5. Overcurrent High Detection Levels SOCH_s* (D3) Overcurrent High Detection (Amperes) HS0 or HS1 HS2 or HS3 0 1 100 70 50 35 * “_s” refers to the channel, which is selected through bits D12–D11; refer to Table 3, page 19. Address A1A0011—Current Detection Time and Open Load Register (CDTOLR) The CDTOLR register is used by the MCU to determine the amount of time the 33892 will allow an overcurrent low condition before an output latches OFF. Each output is independently selected for configuration based on A1A0 , which are the state of the D12–D11 bits (refer to Table 3, page 19). Bits D1–D0 (OCLT[1:0]_s) allow the MCU to select one of four overcurrent fault blanking times defined in Table 6. Note that these timeouts apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 µs. Table 6. Overcurrent Low Detection Blanking Time OCLT[1:0]_s* Timing 0 1 1/13000 1/40000 1/6500 1/20000 * “_s” refers to the channel, which is selected through bits D12–D11; refer to Table 3, page 19. A logic [1] on bit D3 (FAST_SR_s) is used to select the high speed slew rate for the selected output, the default value [0] corresponds to the low speed slew rate Address x0101 — Undervoltage/Overvoltage Register (UOVR) The UOVR register disables the undervoltage (D1) and/or overvoltage (D0) protection. When these two bits are [0], the under- and overvoltage are active (default value). 00 01 10 11 155 ms 620 ms 75 ms 150 µs * “_s” refers to the channel, which is selected through bits D12–D11; refer to Table 3, page 19. 33892 20 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. Address x1101 — Watchdog Register (WDR) The WDR register is used by the MCU to configure the Watchdog timeout. The Watchdog timeout is configured using bits D1 and D0. When D1 and D0 bits are programmed for the desired watchdog timeout period (Table 8), the WDSPI bit should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence. Table 8. Watchdog Timeout WD[1:0] (D1, D0) Timing (ms) SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers which are output specific; viz., Fault, SOCHLR, CDTOLR, and DICR registers. Note that the SO data will continue to reflect the information for each output (depending on the previous OD4, OD3 state) that was selected during the most recent STATR write until changed with an updated STATR write. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exceptions: • The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. • Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored. • The RST terminal transition from a logic [0] to [1] while the WAKE terminal is at logic [0] may result in incorrect data loaded into the Status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. 00 01 10 620 310 2500 1250 Freescale Semiconductor, Inc... 11 Address xx110—No Action Register (NAR) The NAR register can be used to no-operation fill SPI data packets in a daisy-chain SPI configuration. This would allow devices to be unaffected by commands being clocked over a daisy-chained SPI configuration. By toggling the WD bit (D15) the watchdog circuitry would continue to be reset while no programming or data read back functions are being requested from the device. Address xx111—TEST The TEST register is reserved for test and is not accessible with SPI during normal operation. Serial Output Bit Assignment Serial Output Communication (Device Status Return Data) When the CS terminal is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message data is clocked into the SI terminal. The first sixteen bits of data clocking out of the SO, and following a CS transition, is dependent upon the previously written SPI word. Any bits clocked out of the Serial Output (SO) terminal after the first 16 bits will be representative of the initial message bits clocked into the SI terminal since the CS terminal first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO terminal is tri-stated and the fault status register is now able to accept new fault status information. The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 9, page 22, summarizes SO returned data for bits OD15 through OD0. • Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. • Bit OD14 remains logic [0] except when an undervoltage condition occurred. • Bit OD13 remains logic [0] except when an overvoltage condition occurred. • Bits OD[12:8] reflect the state of the bits SOA[4:0] from the previously clocked in message. • Bits OD[7:4] give the fault status flag of the outputs HS3, HS2, HS1, and HS0, respectively. • The contents of bits OD[3:0] depend on bits D[4:0] from the most recent STATR command SOA[4:0] as explained in the paragraphs following the table. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 21 Freescale Semiconductor, Inc. Table 9. Serial Output Bit Map Description Previous STATR SO SO SO SO SO A4 A3 A2 A1 A0 A1 A0 x x 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 SO Returned Data OD 15 WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN OD 14 UVF UVF UVF UVF UVF UVF UVF UVF UVF UVF OD 13 OVF OVF OVF OVF OVF OVF OVF OVF OVF OVF OD 12 SOA4 SOA4 SOA4 SOA4 SOA4 SOA4 SOA4 SOA4 SOA4 SOA4 OD 11 SOA3 SOA3 SOA3 SOA3 SOA3 SOA3 SOA3 SOA3 SOA3 SOA3 OD OD9 OD8 OD7 OD6 OD5 OD4 10 SOA2 SOA2 SOA2 SOA2 SOA2 SOA2 SOA2 SOA2 SOA2 SOA2 SOA1 SOA1 SOA1 SOA1 SOA1 SOA1 SOA1 SOA1 SOA1 SOA1 SOA0 SOA0 SOA0 SOA0 SOA0 SOA0 SOA0 SOA0 SOA0 SOA0 ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST0 ST0 ST0 ST0 ST0 ST0 ST0 ST0 ST0 ST0 OD3 OTF_s IN_SPI3 CSNS EN3 SOCH_s OL_DIS_s Fast_SR_s – – HS2_failsaf IN3 OD2 OCHF_s IN_SPI2 CSNS EN2 SOCL2_s OCL_DIS_s CSNS_high_s – WDTO HS0_failsaf IN2 OD1 OCLF_s IN_SPI1 CSNS EN1 SOCL1_s OCLT1_s DIR_DIS_s UV_DIS WD1 WD_en IN1 OD0 OLF_s IN_SPI0 CSNS EN0 SOCL0_s OCLT0_s A/O_s OV_DIS WD0 WAKE IN0 A1 A0 A1 A0 A1 A0 x 0 1 0 1 Freescale Semiconductor, Inc... x x x x=Don’t care. s=Output selection with the bits A1A0 as defined in Table 3, page 19. Previous Address SOA[4:0]=A1A0000 The bits OD[3:0] will reflect the current state of the Fault Register (FLTR) corresponding to the output previously selected with the bits A1A0 (Table 10). Table 10. Channel-Specific Fault Register OD3 OD2 OD1 OD0 Previous Address SOA[4:0]=A1A0011 The returned data contains the programmed values in the CDTOLR register for the output selected with A1A0. Previous Address SOA[4:0]=A1A0100 The returned data contains the programmed values in the DICR register for the output selected with A1A0. Previous Address SOA[4:0]=A1A0101 The returned data contains the programmed values in the UOVR register. Previous Address SOA[4:0]=x1101 The returned data contains the programmed values in the WDR register. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is [1], the watchdog has timed out and the 33892 is in Fail-Safe mode. IF WDTO is [0], the device is in Normal mode (assuming the device is powered and not in the Sleep mode), with the watchdog either enabled or disabled. Previous Address SOA[4:0]=x0110 The returned data OD3 and OD2 contain the state of the outputs HS2 and HS0, respectively, in case of Fail-Safe state. This information is stated with the external resistance placed at the FSI terminal. OD1 indicates if the watchdog is enabled or not. OD0 returns the state of the WAKE terminal. Previous Address SOA[4:0]=x1110 The returned data OD[3:0] reflects the state of the direct terminals IN3 to IN0, respectively. OTF_s OCHF_s OCLF_s OLF_s s=Selection of the output. Note The FS terminal reports all faults. For latched faults, this terminal is reset by a new Switch ON command (via SPI or direct input IN). Previous Address SOA[4:0]=x0001 Data in bits OD[3:0] contains IN_SPI[3:0]-programmed bits for channel from HS3 to HS0, respectively. Previous Address SOA[4:0]=x1001 Data in bits OD[3:0] contains the programmed CSNS EN[3:0] bits for channels HS3 to HS0, respectively. Previous Address SOA[4:0]=A1A0010 Data returned in bits OD[3:0] are programmed current values for the overcurrent high detection level (refer to Table 5, page 20) and the overcurrent low detection level (refer to Table 4, page 20), corresponding to the output previously selected with A1A0. 33892 22 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. MODES OF OPERATION The 33892 has four operating modes. They are Sleep, Normal, Fault, and Fail-Safe. Table 11 summarizes details contained in succeeding paragraphs. Table 11. Fail-Safe Operation and Transitions to Other 33892 Modes Mode FS Wake RST WDTO Comments Fail-Safe Mode Fail-Safe Mode and Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input terminal transitions from logic [0] to [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The Watchdog timeout is a multiple of an internal oscillator and is specified in the Table 8, page 21. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR, the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 12). Table 12. Output State During Fail-Safe Mode RFS (kΩ) High-Side State Sleep Normal x 1 0 0 x 1 1 x 0 1 1 0 1 1 0 1 1 1 0 x No Device is in Sleep mode. All outputs are OFF Normal mode. Watchdog is active if enabled. Device is currently in fault mode. The faulted output(s) is (are) OFF. Watchdog has timed out and the device is in Fail-Safe Mode. The outputs are as configured with the RFS resistor connected to FSI. RST and WAKE must be transitioned to logic [0] simultaneously to bring the device out of the Fail-safe mode or momentarily tied the FSI pin to ground. Freescale Semiconductor, Inc... Fault 0 0 1 1 1 No FailSafe Yes x = Don’t care. 0 6.0 Fail-Safe Mode Disabled All HS OFF HS0 ON HS[1:3] OFF HS0 and HS2 ON HS1 and HS3 OFF Sleep Mode The Default mode of the 33892 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the device are as if set to logic [0]. The device will transition to the Normal or Fail-Safe operating modes based on the WAKE and RST inputs as defined in Table 11. 15 30 In the Fail-Safe mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCTL). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational. The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is logic [1] when the device is in Fail-Safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or forcing the FSI pin to logic [0]. Table 11 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog Fail-Safe operation is disabled. Normal Mode The 33892 is in Normal mode when: • VPWR is within the normal voltage range. • RST terminal is logic [1]. • No fault has occurred. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 23 Freescale Semiconductor, Inc. Loss of VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The outputs can still be driven by the direct inputs IN[0:3]. The 33892 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values. level then returns above 5.75 V, the 33892 can be returned to the state that it was in prior to the low VPWR excursion. Once the output latches OFF, the outputs must be turned OFF and ON again to re-enable them. In the case IN[1:0]=0, this fault is nonlatched. The undervoltage protection can be disabled through SPI (bit UV_DIS). When disabled, the returned SO bit OD14 still reflects any undervoltage condition (undervoltage warning). Open Load Fault (Non-Latching) Fault Mode The 33892 indicates the faults below as they occur by driving the FS terminal to [0]: Freescale Semiconductor, Inc... • • • • Overtemperature fault Overvoltage and Undervoltage fault Open load fault Overcurrent fault (high and low) The 33892 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled trough SPI (bit OL_DIS). Overcurrent Fault (Latching) The 33892 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 4, page 15. The eight different overcurrent low detection levels (IOCL0, IOCL1, IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, and IOCL7) are illustrated in Figure 4. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF. If, at any time, the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCLx driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again. The FS terminal will automatically return to [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO terminal during the first valid SPI communication (refer to Table 10, page 22). Overtemperature Fault (Non-Latching) The 33892 incorporates overtemperature detection and shutdown circuitry in the output structure. Overtemperature detection is enabled when the output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device. Overvoltage Fault (Non-Latching) The 33892 shuts down the output during an overvoltage fault (OVF) condition on the VPWR terminal. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit D1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection can be disabled through SPI (bit OV_DIS). When disabled, the returned SO bit OD13 still reflects any overvoltage condition (overvoltage warning). Undervoltage Shutdown (Latching or Non-Latching) The output latches OFF at some battery voltage between 4.75 V and 5.75 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. This ensures that when the battery Reverse Battery The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output’s gate is enhanced to keep the junction temperature less than 150°C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required. Ground Disconnect Protection In the event the 33892 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection. 33892 24 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. PACKAGE DIMENSIONS PNC SUFFIX 24-TERMINAL POWER QFN NON-LEADED PACKAGE CASE 1558-02 ISSUE A SHEET 1 OF 2 10 A DETAIL G 5 10 11 2 1 24 2X M 0.1 C Freescale Semiconductor, Inc... 13 22 5 14 21 10 PIN 1 INDEX AREA 17 18 19 20 M PIN NUMBER REF. ONLY B 2X 0.1 C PIN NUMBER REF. ONLY 5.85 4.95 4.65 0.1 C A B 1 24 2 10 11 2X VIEW A 0.65 3.0 2.7 0.1 C A B 22 15 13 2.525 21 14 3.2 1.375 4.45 4.05 0.1 C A B 2.45 2.05 16 (0.25) 2X 1.43 0.93 20 2X 1.3 19 18 2X 2.3 1.8 (0.75) (0.25) (0.25) 2.2 1.8 0.8 (0.25) (0.1) (1.25) 0.5 17 (0.25) NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. 5. METAL PADS CONNECTED TO THE GND. 6. MINIMUM METAL GAP SHOULD BE 0.25MM. 2X 0.1 C A B 7.2 6.8 0.1 C A B 2X 1.65 1.35 0.1 C A B 9.70 9.30 0.1 C A B VIEW M M MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 25 Freescale Semiconductor, Inc. PNC SUFFIX 24-TERMINAL POWER QFN NON-LEADED PACKAGE CASE 1558-02 ISSUE A SHEET 2 OF 2 0.1 C 2.2 2.0 2.20 1.95 4 0.05 C Freescale Semiconductor, Inc... 0.05 0.00 (0.65) (0.4) DETAIL G VIEW ROTATED 90˚ CW C SEATING PLANE 3.5 2X 9X 0.65 16X 0.325 0.47 0.33 0.1 M C A B 0.05 M C 10 1.20 0.95 6X 1.20 0.95 (0.05) (0.2) 8X 0.90 0.65 11 3.025 0.3±0.2 5 X0.3±0.2 0.1 C A B 2 PLACES 2.5 1.8 1.3 0.25±0.2 5 X0.25±0.2 0.1 C A B 2 PLACES 1.0 0.6 2.0 1.6 (0.25) 2.8 2.6 VIEW A 0.6 0.2 2 PLACES 33892 26 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. NOTES Freescale Semiconductor, Inc... MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33892 27 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Motorola reserves the right to make changes without further notice to any products herein. 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MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 For More Information On This Product, Go to: www.freescale.com MC33892