68HC05E1

Freescale Semiconductor, Inc. HC05E1GRS/D REV. 2.0 Freescale Semiconductor, Inc... General Release Specification For More Information On This Product, Go to: www.freescale.com NON-DISCLOSURE AGREEMENT 68HC05E1 REQUIRED Freescale Semiconductor, Inc. General Release Specification REQUIRED Freescale Semiconductor, Inc... AGREEMENT NON-DISCLOSURE Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. General Release Specification For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Rev. 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Freescale Semiconductor, Inc... 1.2 1.3 1.4 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.2 IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . . .16 1.5.3 OSC1, OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.5 PA0-PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.6 PB0-PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.7 PC0-PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.8 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.9 VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Section 2. Operating Modes 2.1 2.2 2.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4.1 Timer Test Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.4.2 ROM Checksum Subroutine. . . . . . . . . . . . . . . . . . . . . . . . .24 MC68HC05E1 — Revision 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Table of Contents 2.4.3 2.4.3.1 2.4.3.2 2.4.3.3 Additional Self-Check Routines . . . . . . . . . . . . . . . . . . . . . .25 Self-Check PLL Disabled . . . . . . . . . . . . . . . . . . . . . . . . .26 Jump to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Load RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Section 3. CPU Core 3.1 3.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Freescale Semiconductor, Inc... 3.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.2 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.1 Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.2 Interrupt (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.3 Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.4 Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.3.5 Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .32 3.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .33 3.4.3 Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .35 3.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.1 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.2 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.3 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.4 Re;atove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.8 Bit Set/Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Table of Contents 3.5.9 3.5.10 Bit Test and Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.2 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.3 Computer Operating Properly (COP) Reset . . . . . . . . . . . . .40 3.6.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7.1 Hardware Controlled Interrupt Sequence. . . . . . . . . . . . . . .42 3.7.2 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.7.3 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.4 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.5 Custom Peirodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . .45 3.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.2 WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.3 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Freescale Semiconductor, Inc... Section 4. Input/Output Ports 4.1 4.2 4.3 4.4 4.5 4.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Input/Output Programmingf . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Section 5. Memory 5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 MC68HC05E1 — Revision 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Table of Contents Section 6. Timer, Phase-Locked Loop, and Custom Periodic Interrupt 6.1 6.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Freescale Semiconductor, Inc... 6.3 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.3.1 Timer Control and Status Register (TCSR) $08 . . . . . . . . . .60 6.3.2 Computer Operating Properly (COP) Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.3.3 Timer Control Register (TCR) $09 . . . . . . . . . . . . . . . . . . . .63 6.4 Phase-Locked Loop Synthesizer . . . . . . . . . . . . . . . . . . . . . . .64 6.4.1 Phase-Locked Loop Control Register (PLLCR) $07 . . . . . .66 6.4.2 Operation During STOP Mode . . . . . . . . . . . . . . . . . . . . . . .68 6.4.3 Noise Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5 Custom Periodic Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5.1 Custom Periodic Interrupt Control and Status Register (CPICSR) $12. . . . . . . . . . . . . . . . .70 6.6 6.7 Operation During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . .70 Operation During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . .71 Section 7. Electrical Specifications 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .76 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .77 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Table of Contents Section 8. Mechanical Specifications 8.1 8.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Mechnical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 8.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 8.3.1 P Suffix, Plastic DIP, Case # 710-02 . . . . . . . . . . . . . . . . . .82 8.3.2 DW Suffix, SOIC, Case # 751F-02. . . . . . . . . . . . . . . . . . . .83 Freescale Semiconductor, Inc... MC68HC05E1 — Revision 2.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 List of Figures Figure 1-1 1-2 2-1 2-2 2-3 3-1 3-2 3-3 4-1 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 Title Page Freescale Semiconductor, Inc... Block Diagram of the MC68HC05E1 . . . . . . . . . . . . . . . . . .15 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Single-Chip Mode Pinout of the MC68HC05E1 . . . . . . . . . .22 Self-Check Circuit Schematic Diagram . . . . . . . . . . . . . . . .23 Self-Check Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . .25 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .43 STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Port I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Port I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 The 8 Kbyte Memory Map of the MC68HC05E1 . . . . . . . . .54 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . .55 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Timer Control and Status Register (TCSR) . . . . . . . . . . . . .60 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Phase-Locked Loop Control Register . . . . . . . . . . . . . . . . .66 Custom Periodic Interrupt Control and Status Register (CPICSR) . . . . . . . . . . . . . . . . . . . .70 External Interrupt Mode Diagram . . . . . . . . . . . . . . . . . . . . .79 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .79 Power-On Reset and RESET. . . . . . . . . . . . . . . . . . . . . . . .80 7-1 7-2 7-3 MC68HC05E1 — Revision 2.0 List of Figures For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... General Release Specification List of Figures For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 List of Tables Table 2-1 2-2 3-1 4-1 6-1 6-2 6-3 6-4 Title Page Freescale Semiconductor, Inc... Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .21 Self-Check Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . .42 I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 RTI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 COP Reset Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Loop Filter Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . .67 PS1 and PS0 Speed Selects with 32.768 kHz Crystal . . . . . .68 MC68HC05E1 — Revision 2.0 List of Tables For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. List of Tables Freescale Semiconductor, Inc... General Release Specification List of Tables For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Freescale Semiconductor, Inc... 1.3 1.4 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.2 IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . . .16 1.5.3 OSC1, OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.3.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.5 PA0-PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.6 PB0-PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.7 PC0-PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.8 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.9 VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 Introduction The MC68HC05E1 is a low-cost introduction to the M68HC05 Family of microcontrollers (MCUs). The HC05 CPU core has been enhanced with a 15-stage multi-functional timer and programmable phase-locked loop. The MCU is available in a 28-pin package, and has two 8-bit I/O ports and one 4-bit I/O port. The 8 Kbyte memory map includes 368 bytes of RAM and 4096 bytes of user ROM. MC68HC05E1 — Revision 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. General Description 1.3 Features Features of the MC68HC05E1 include: • • • • Low cost HC05 Core 28-pin package On-Chip Oscillator (Crystal or Ceramic Resonator) Phase-Locked Loop (PLL) Synthesizer with Programmable Speed 4112 Bytes of User ROM (including 16 Bytes of User Vectors) 368 Bytes of On-Chip RAM 15-Stage Multi-functional Timer with Programmable Input Real Time Interrupt Circuit COP Watchdog Timer Mask Option Custom Periodic Interrupt Circuit 20 Bidirectional I/O Lines Single-Chip Mode Self-Check Mode Power Saving STOP and WAIT Modes Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger Mask Option STOP Instruction Disable Mask Option Illegal Address Reset Freescale Semiconductor, Inc... • • • • • • • • • • • • • • General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Description Features OSC2 OSC1 OSCILLATOR OSCOUT CUSTOM PERIODIC INTERRUPT TPLL COP SYSTEM TIMER SYSTEM INTERNAL PROCESSOR CLOCK VDDSYN XFC PLL SYNTH. CLOCK SELECT ÷2 VDD VSS PA0 DATA DIRECTION REGISTER Freescale Semiconductor, Inc... PA1 PA2 PORT A PA3 PA4 PA5 PA6 PA7 PB0 RESET IRQ CPU CONTROL M68HC05 CPU CPU REGISTERS ALU ACCUMULATOR INDEX REGISTER DATA DIRECTION REGISTER STACK POINTER PROGRAM COUNTER PB1 PB2 PORT B PB3 PB4 PB5 PB6 PB7 CONDITION CODE REG. SRAM — 368 BYTES ROM — 4112 BYTES DATA DIR REG PC0 PORT C PC1 PC2 PC3 SELF-CHECK ROM — 240 BYTES Figure 1-1. Block Diagram of the MC68HC05E1 MC68HC05E1 — Revision 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. General Description 1.4 Mask Options There are four mask options on the MC68HC05E1: STOP instruction (enable/disable), IRQ (Edge-sensitive only or Edge- and level-sensitive), COP Watchdog Timer (enable/disable), and CPI Rate (1 second, 0.5 second, or 0.25 second). NOTE: A line over a signal name indicates an active low signal. For example, RESET is active low. Freescale Semiconductor, Inc... 1.5 Functional Pin Description 1.5.1 VDD and VSS Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground. 1.5.2 IRQ (Maskable Interrupt Request) This pin has a programmable option that provides two different choices of interrupt triggering sensitivity. The options are: 1. negative edge-sensitive triggering only, or 2. both negative edge-sensitive and level-sensitive triggering. The MCU completes the current instruction before it responds to the interrupt request. When IRQ goes low for at least one tILIH, a logic one is latched internally to signify an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch contains a logic one, and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then begins the interrupt sequence. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to VDD for “wire-OR” operation. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to 3.7 Interrupts for more detail. General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Description Functional Pin Description NOTE: The voltage on this pin affects the mode of operation. See Section 2. Operating Modes. 1.5.3 OSC1, OSC2 These pins provide control input for an on-chip clock oscillator circuit which can optionally drive a Phase-Locked Loop clock. A crystal, a ceramic resonator, or an external signal connects to these pins providing a system clock. The oscillator frequency is two times the internal bus rate if the PLL is not used. 1.5.3.1 Crystal Figure 1-2 shows the recommended circuit for using a crystal. The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and start-up stabilization time. 1.5.3.2 Ceramic Resonator A ceramic resonator may be used in place of the crystal in cost-sensitive applications. Figure 1-2 shows the recommended circuit for using a ceramic resonator. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information. 1.5.3.3 External Clock An external clock should be applied to the OSC1 input with the OSC2 pin not connected. See Figure 1-2. This setup can be used if the user does not wish to run the CPU with a 32.768 KHz crystal or the PLL frequencies are not suitable for the application. Freescale Semiconductor, Inc... MC68HC05E1 — Revision 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. General Description MCU OSC1 OSC2 330 kΩ OSC1 MCU OSC2 20 MΩ Unconnected < External Clock 10 PF 32.768 kHz 33 pF Freescale Semiconductor, Inc... (a) Crystal/Ceramic Resonator Oscillator Connections (b) External Clock Source Connections Figure 1-2. Oscillator Connections 1.5.4 RESET This active low pin is used to reset the MCU to a known start-up state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See 3.6 Resets. 1.5.5 PA0-PA7 These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as input during power-on or reset. See 4.6 Input/Output Programmingf. 1.5.6 PB0-PB7 These eight I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as input during power-on or reset. See 4.6 Input/Output Programmingf. General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Description Functional Pin Description 1.5.7 PC0-PC3 These four I/O lines comprise port C. The state of any pin is software programmable and all port C lines are configured as input during power-on or reset. See 4.6 Input/Output Programmingf. 1.5.8 XFC This pin provides a means for connecting an external filter capacitor to the synthesizer phase-locked loop filter. See 6.4 Phase-Locked Loop Synthesizer for additional information concerning this capacitor. Freescale Semiconductor, Inc... 1.5.9 VDDSYN This pin provides a separate power connection to the PLL synthesizer which should be at the same potential as VDD. NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC05E1 do not require termination, it is recommended to reduce the possibility of static damage. MC68HC05E1 — Revision 2.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. General Description Freescale Semiconductor, Inc... General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 2. Operating Modes 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Freescale Semiconductor, Inc... 2.3 2.4 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4.1 Timer Test Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.4.2 ROM Checksum Subroutine. . . . . . . . . . . . . . . . . . . . . . . . .24 2.4.3 Additional Self-Check Routines . . . . . . . . . . . . . . . . . . . . . .25 2.4.3.1 Self-Check PLL Disabled . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4.3.2 Jump to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4.3.3 Load RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.2 Introduction The MCU has 3 modes of operation: Single-chip mode, Self-Check Mode, and Test Mode. Table 2-1 shows the conditions required to go into each mode. Table 2-1. Operating Mode Conditions RESET IRQ VSS–VDD VTST VTST VTST = 2 x VDD PB1 VSS–VDD VDD VSS Mode Single Chip Self Check Factory Test MC68HC05E1 — Revision 2.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Operating Modes 2.3 Single-Chip Mode In single-chip mode, the address and data buses are not available externally, but there are two 8-bit I/O ports and one 4-bit I/O port. This mode allows the MCU to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. All address and data activity occurs within the MCU. Single-Chip Mode is entered on the rising edge of RESET if the IRQ pin is within normal operating range. Freescale Semiconductor, Inc... IRQ RESET OSC1 OSC2 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XFC VDDSYN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0 PC1 PC2 PC3 Figure 2-1. Single-Chip Mode Pinout of the MC68HC05E1 2.4 Self-Check Mode The Self-Check Mode provides an internal check to determine if the device is functional. See Figure 2-2. General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Operating Modes Self-Check Mode VTST VTST = 2 X VDD VDD 10 KΩ 1 1 µf 2 3 IRQ RESET OSC1 OSC2 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VDD VSS XFC VDDSYN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0 PC1 PC2 PC3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.1 µf VDDSYN 4.7 kΩ 2N3904 Freescale Semiconductor, Inc... 32.768 kHz 330 kΩ 20 MΩ 10 pf 4 5 6 10 pf 7 8 9 10 11 10 kΩ VDD 1 kΩ 0.1 µf 12 13 14 10 kΩ Figure 2-2. Self-Check Circuit Schematic Diagram The Self-Check Mode is entered on the rising edge of RESET if the IRQ pin is at VTST, and the PB1 pin is at logic one. RESET must be held low for 4064 cycles after POR, or for a time tRL for any other reset. After reset, the PLL is turned on (fop = 1.049 MHz) and the following tests are performed automatically: 1. I/O – Functionally exercises ports A, B, and C 2. RAM – Counter test for each page zero RAM byte 3. Timer/CPI – Tracks counter register and checks TOF and RTIF flags 4. ROM – Exclusive OR with odd ones parity result 5. Interrupts –Tests external interrupts, RTI and CPI MC68HC05E1 — Revision 2.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Operating Modes Self-check results (using the LEDs as monitors) are shown in Table 2-2. The Self-Check program resides at ROM location $1F00 to $1FEF. The following subroutines are available to user programs and do not require any external hardware. 2.4.1 Timer Test Subroutine This subroutine returns with the Z bit cleared if any error is detected; otherwise, the Z bit is set. Freescale Semiconductor, Inc... This subroutine is called at location $1F9B. Because the timer is free running and has only a divide-by-four prescaler, each timer count cannot be tested. The test sets RTIE and CPIE and reads the timer once every 3 counts (12 cycles) to check for correct counting. The test tracks the counter until the timer wraps around, setting the TOF bit in the Timer Control and Status register. The routine then waits for RTIF=1 and CPIF = 1 before returning with the RTI and the CPI pending. RAM location $0095 is overwritten. Upon return to the user’s program, A=0 if the test passed. 2.4.2 ROM Checksum Subroutine This subroutine returns with the Z bit cleared if any error is detected; otherwise, the Z bit is set. This subroutine is called at location $1FD1. A short routine is set up and executed in RAM to compute a checksum of the entire ROM pattern. The checksum byte is computed by Motorola and is located in the Self-Check ROM. Upon return to the user’s program, X=0. If the test passed, A=0. RAM locations $0090 through $0093 are overwritten. General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Operating Modes Self-Check Mode Table 2-2. Self-Check Results PA3 1 1 1 1 1 PA2 0 0 0 1 1 Flashing All Others 0 indicates LED is on; 1 indicates LED is off. PA1 0 1 1 0 0 PA0 1 0 1 0 1 Bad I/O Bad RAM Bad Timer Bad ROM Remarks Bad Interrupts or IRQ request Good Device Bad Device Freescale Semiconductor, Inc... 2.4.3 Additional Self-Check Routines The Self-Check ROM contains additional programs to facilitate testing and characterization of the device. Figure 2-3 shows the program flow in the Self-Check ROM. These programs are used in Self-Check Mode (PB1=1). On power-up, the device goes into Self-Check Mode on the rising edge of RESET if the IRQ pin is at VTST, and the PB1 pin is at logic one. The values of PB0:PB3 after power-up determine which routine is executed from the Self-Check ROM. Only the Self-Check routine is intended for customer use. POWER-UP IRQ = VTST PB1=1 PB2=1? YES NO PB0=1? YES NO SELF-CHECK LOAD RAM & EXECUTE JUMP TO RAM PLL ENABLED YES PB3=1? NO PLL DISABLED Figure 2-3. Self-Check Mode Flowchart MC68HC05E1 — Revision 2.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Operating Modes 2.4.3.1 Self-Check PLL Disabled If PB2=1 and PB3=0, the self-check routine is run without turning on the PLL. This allows the self-check program to run at any frequency, as determined by the value of the crystal oscillator in the self-check circuit. 2.4.3.2 Jump to RAM This routine is executed if PB2=0, PB1=1, and PB0=0. Freescale Semiconductor, Inc... This routine jumps to the starting address of the RAM. This is used after a program has been placed in the RAM. This feature is useful for production testing where single-chip timing or port functionality is needed. 2.4.3.3 Load RAM This routine is entered if PB2=0, PB1=1, and PB0=1. The ldram routine does a parallel download of a program into port A using IRQ (data ready) and PC0 (data acknowledge) to synchronize the download with the host system. When IRQ (data ready) goes low, PC0 (data acknowledge) is deasserted and a byte of data is loaded from port A to RAM starting at location $100. After the byte is stored in RAM, PC0 is asserted as an active low data acknowledge signal to the host. The first byte downloaded must contain the total number of bytes to be downloaded (program length +1). When the download is complete, the program in RAM is executed. General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 3. CPU Core 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Freescale Semiconductor, Inc... 3.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.2 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.1 Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.2 Interrupt (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.3 Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.3.4 Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.3.5 Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .32 3.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .33 3.4.3 Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .35 3.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.1 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.2 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.3 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.5.4 Re;atove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.5.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.8 Bit Set/Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.9 Bit Test and Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.5.10 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core 3.6 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.2 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.6.3 Computer Operating Properly (COP) Reset . . . . . . . . . . . . .40 3.6.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.7.1 Hardware Controlled Interrupt Sequence. . . . . . . . . . . . . . .42 3.7.2 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.7.3 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.4 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.7.5 Custom Peirodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . .45 3.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.2 WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.8.3 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Freescale Semiconductor, Inc... 3.2 Introduction This section describes the CPU core. 3.3 Registers The MCU contains the registers described in the following paragraphs. 3.3.1 Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 7 A 0 General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Registers 3.3.2 Index Register (X) The index register is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area. 7 X 0 Freescale Semiconductor, Inc... 3.3.3 Condition Code Register (CCR) The CCR is a 5-bit register in which the H, N, Z, and C bits are used to indicate the results of the instruction just executed, and the I bit is used to enable interrupts. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. CCR H I N Z C 3.3.3.1 Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. 3.3.3.2 Interrupt (I) When this bit is set, the timer and external interrupt is masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared. 3.3.3.3 Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core 3.3.3.4 Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. 3.3.3.5 Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. Freescale Semiconductor, Inc... 3.3.4 Stack Pointer (SP) The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits are permanently set to 0000011. These seven bits are appended to the six least significant register bits to produce and address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 12 0 0 0 0 0 7 1 0 1 SP General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Instruction Set 3.3.5 Program Counter (PC) The program counter is a 13-bit register that contains the address of the next byte to be fetched. NOTE: The HC05 CPU core is capable of addressing 16-bit locations. For this implementation, however, the addressing registers are limited to an 8K byte memory map. 12 PC 0 Freescale Semiconductor, Inc... 3.4 Instruction Set The MCU has a set of 62 basic instructions. They can be divided into five different types: register/memory, read-modify-write, branch, bit manipulation, and control. The following paragraphs briefly explain each type. For more information on the instruction set, refer to the M6805 Family User’s Manual (M6805UM/AD2) or the MC68HC05C4 Data Sheet (MC68HC05C4/D). MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core 3.4.1 Register/Memory Instructions Most of these instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to the following instruction list. Function Mnemonic LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR MUL Freescale Semiconductor, Inc... Load A from Memory Load X from Memory Store A in Memory Store X in Memory Add Memory to A Add Memory and Carry to A Subtract Memory Subtract Memory from A with Borrow AND Memory to A OR Memory with A Exclusive OR Memory with A Arithmetic compare A with Memory Arithmetic Compare X with Memory Bit Test Memory with A (Logical Compare) Jump Unconditional Jump to Subroutine Multiply General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Instruction Set 3.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to the read-modify-write sequence since it does not modify the value. Do not use these read-modify-write instructions on write-only locations. Refer to the following list of instructions. Freescale Semiconductor, Inc... Function Increment Decrement Clear Complement Negate (Twos Complement) Rotate Left Thru Carry Rotate Right Thru Carry Logical Shift Left Logical Shift Right Arithmetic Shift Right Test for Negative or Zero Mnemonic INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core 3.4.3 Branch Instructions This set of instruction branches if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to the following list for branch instructions. Function Branch Always Branch Never Mnemonic BRA BRN BHI BLS BCC BHS BCS BLO BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR Freescale Semiconductor, Inc... Branch if Higher Branch if Lower or Same Branch if Carry Clear Branch if Higher or Same Branch if Carry Set Branch if Lower Branch if Not Equal Branch if Equal Branch if Half Carry Clear Branch if Half Carry Set Branch if Plus Branch if Minus Branch if Interrupt Mask Bit is Clear Branch if Interrupt Mask Bit is Set Branch if Interrupt Line is Low Branch if Interrupt Line is High Branch to Subroutine General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Instruction Set 3.4.4 Bit Manipulation Instructions The MCU is capable of setting or clearing any writable bit which resides in the first 256 bytes of the memory space where all port registers, port DDRs, timer, timer control, and on-chip RAM reside. An additional feature allows the software to test and branch on the state of any bit within these 256 locations. The bit set, bit clear and bit test, and branch functions are all implemented with a single instruction. For test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. These instructions are also read-modify-write instructions. Do not bit manipulate write-only locations. Refer to the following list for bit manipulation instructions. Freescale Semiconductor, Inc... Function Branch if Bit n is Set Branch if bit n is Clear Set Bit n Clear Bit n Mnemonic BRSET n (n = 0. . .7) BRCLR n (n = 0. . .7) BSET n (n = 0. . .7) BCLR n (n = 0. . .7) MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core 3.4.5 Control Instructions These instructions are register reference instructions and are used to control processor operation during program execution. Refer to the following list for control instructions. Function Transfer A to X Transfer X to A Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT Freescale Semiconductor, Inc... Set Carry Bit Clear Carry Bit Set Interrupt Mask Bit Clear Interrupt Mask Bit Software Interrupt Return from Subroutine Return from Interrupt Reset Stack Pointer No-Operation Stop Wait General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Addressing Modes 3.5 Addressing Modes The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) permit accessing tables throughout memory. Short and long absolute addressing is also included. One- or two-byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory. The term “effective address” (EA) is used in describing the various addressing modes. Effective address is defined as the address from which the argument for an instruction is fetched or stored. Freescale Semiconductor, Inc... 3.5.1 Immediate In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g., a constant used to initialize a loop counter). 3.5.2 Direct In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. 3.5.3 Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core uses direct or extended addressing. The assembler automatically selects the shortest form of the instruction. 3.5.4 Re;atove The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed offset byte (which is the last byte of the instruction) is added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -128 to +127 from the address of the next opcode. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. Freescale Semiconductor, Inc... 3.5.5 Indexed, No Offset In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. 3.5.6 Indexed, 8-Bit Offset In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. The addressing mode is useful for selecting the Kth element in an n element table. With this two-byte instruction, K would typically be in X with the address of the beginning of the table in the instruction. As such, tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510. $1FE is the last location which can be accessed in this way. General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Addressing Modes 3.5.7 Indexed, 16-Bit Offset In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Freescale Semiconductor, Inc... 3.5.8 Bit Set/Clear In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode specifies the direct address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. 3.5.9 Bit Test and Branch The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit that is to be tested and its condition (set or clear), is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte. The signed relative 8-bit offset in the third byte is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branching is from -128 to +127 from the address of the next opcode. The state of the tested bit is also transferred to the carry bit of the condition code register. MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core 3.5.10 Inherent In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register and/or accumulator as well as the control instructions with no other arguments are included in this mode. These instructions are one byte long. 3.6 Resets Freescale Semiconductor, Inc... The MCU can be reset three ways: by the initial power-on reset function, by an active low input to the RESET pin, by a COP watchdog-timer reset, and by the ILADR bit being set in the test register. 3.6.1 Power-On Reset (POR) An internal reset is generated on power-up to allow the internal clock generator to stabilize. The power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a 4064 internal processor clock cycle (tcyc) oscillator stabilization delay after the oscillator becomes active. If the RESET pin is low at the end of this 4064 cycle delay, the MCU will remain in the reset condition until RESET goes high. 3.6.2 RESET Pin The MCU is reset when a logic zero is applied to the RESET input for a period of one and one-half machine cycles (tcyc). RESET is an input-only pin and will not indicate when an internal reset has occurred. 3.6.3 Computer Operating Properly (COP) Reset The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU. Because the internal reset signal is used, the MCU General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Interrupts comes out of a COP reset in the same operating mode it was in when the COP time-out was generated. The COP reset function is enabled or disabled by a mask option. Refer to 6.3.2 Computer Operating Properly (COP) Watchdog Reset, for more information on the COP Watchdog timer. 3.6.4 Illegal Address Reset Freescale Semiconductor, Inc... When an opcode fetch occurs from an address which is not implemented in the RAM ($0090–$01FF) or ROM ($0F00–$1FFF), the part is automatically reset. 3.7 Interrupts The MCU can be interrupted four different ways: the three maskable hardware interrupts (IRQ, timer, and CPI) and the nonmaskable software interrupt instruction (SWI). Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. NOTE: The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. Table 3-1. Vector Address for Interrupts and Reset Register N/A Flag Name N/A N/A N/A TOF RTIF CPICSR CPIF Reset Software External Interrupt Timer Overflow Real Time Interrupt Custom Periodic Interrupt Interrupts CPU Interrupt RESET SWI RQ TIMER IMER CPI Vector Address $1FFE–$1FFF $1FFC–$1FFD $1FFA–$1FFB $1FF8–$1FF9 $1FF8–$1FF9 $1FF6–$1FF7 Freescale Semiconductor, Inc... N/A N/A TCSR 3.7.1 Hardware Controlled Interrupt Sequence The following three functions (RESET, STOP, and WAIT) are not in the strictest sense an interrupt; however, they are acted upon in a similar manner. See Figure 3-1 and Figure 3-2. A discussion is provided below. 1. RESET - A low input on the RESET input pin causes the program to vector to its starting address which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition code register is also set. Much of the MCU is configured to a known state during this type of reset as previously described in 3.6 Resets. 2. STOP - The STOP instruction causes the oscillator to be turned off and the processor to “sleep” until an external interrupt (IRQ) or reset occurs. 3. WAIT - The WAIT instruction causes all processor clocks to stop, but leaves the timer clock running. This “rest” state of the processor can be cleared by reset, an external interrupt (IRQ), or Timer interrupt. There are no special wait vectors for these individual interrupts. General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Interrupts From RESET Y Is I Bit Set N IRQ External Interrupt N Timer Internal Interrupt N CPI Internal Interrupt N Clear IRQ Request Latch Freescale Semiconductor, Inc... Y Y Stack PC, X, A, CC Y Set I Bit Fetch Next Instruction N SWI Instruction ? N RTI Instruction ? N Execute Instruction Load PC From: SWI: $1FFC, $1FFD IRQ: $1FFA-$1FFB Timer: $1FF8-$1FF9 CPI: $1FF6, $1FF7 Y Y Restore Resisters from stack CC, A, X, PC Figure 3-1. Interrupt Processing Flowchart MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core STOP WAIT Stop Oscillator And All Clocks Clear I Bit Oscillator Active Timer Clock Active Processor Clocks Stopped Freescale Semiconductor, Inc... N Reset Reset N N External Interrupt (IRQ) Y Y Y External Interrupt (IRQ) Y N Timer Internal Y Interrupt Y N Turn On Oscillator Wait for Time Delay to Stabilize Restart Processor Clock CPI Internal Interrupt Y N 1. Fetch Reset Vector or 2. Service Interrupt a. Stack b. Set I Bit c. Vector to Interrupt Routine 1. Fetch Reset Vector or 2. Service Interrupt a. Stack b. Set I Bit c. Vector to Interrupt Routine Figure 3-2. STOP/WAIT Flowcharts 3.7.2 Software Interrupt (SWI) The SWI is an executable instruction and a non-maskable interrupt: it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Interrupts 3.7.3 External Interrupt If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of IRQ. It is then synchronized internally and serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger is available as a mask option. Freescale Semiconductor, Inc... NOTE: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I bit is cleared. 3.7.4 Timer Interrupt There are two different timer interrupt flags that cause a timer interrupt whenever they are set and enabled. The interrupt flags and enable bits are located in the Timer Control and Status Register (TCSR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1FF8 and $1FF9. See 6.3.1 Timer Control and Status Register (TCSR) $08. 3.7.5 Custom Peirodic Interrupt (CPI) The CPI flag and enable bits are located in the CPI Control and Status Register (CPICSR). A CPI interrupt will vector to the interrupt service routine located at the address specified by the contents of memory location $1FF6 and $1FF7. See 6.5 Custom Periodic Interrupt. MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core 3.8 Low-Power Modes 3.8.1 STOP The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off, halting all internal processing, including timer (and COP Watchdog timer) operation. Freescale Semiconductor, Inc... The I bit in the CCR is cleared to enable external interrupts. All other registers, including the remaining bits in the TCSR, and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an external interrupt or RESET. The STOP instruction can be disabled by a mask option. When disabled, the STOP instruction is executed as a NOP. See 6.6 Operation During STOP Mode. 3.8.2 WAIT The WAIT instruction places the MCU in a low-power consumption mode, but the WAIT mode consumes more power than the STOP mode. All CPU action is suspended, but the timer remains active. An interrupt from the timer can cause the MCU to exit the WAIT mode. During the WAIT mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timer may be enabled to allow a periodic exit from the WAIT mode. See 6.7 Operation During WAIT Mode. General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. CPU Core Low-Power Modes 3.8.3 Data-Retention Mode The contents of RAM and CPU registers are retained at supply voltages as low as 2.0Vdc. This is called the data-retention mode where the data is held, but the device is not guaranteed to operate. RESET must be held low during data-retention mode. Freescale Semiconductor, Inc... Data Direction Register Bit Internal HC05 Connections Latched Output Data Bit Output I/O Pin Input Register Bit Input I/O Figure 3-3. Port I/O Circuitry MC68HC05E1 — Revision 2.0 CPU Core For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. CPU Core Freescale Semiconductor, Inc... General Release Specification CPU Core For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 4. Input/Output Ports 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Input/Output Programmingf . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Freescale Semiconductor, Inc... 4.3 4.4 4.5 4.6 4.2 Introduction In single-chip mode there will be 20 lines arranged as two 8-bit I/O port and one 4-bit I/O port. These ports are programmable as either inputs or outputs under software control of the data direction registers. To avoid a glitch on the output pins, write data to the I/O Port Data Register before writing a one to the corresponding Data Direction Register. 4.3 Port A Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. MC68HC05E1 — Revision 2.0 Input/Output Ports For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Input/Output Ports 4.4 Port B Port B is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The address of the port B data register is $0001 and the data direction register (DDR) is at address $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Freescale Semiconductor, Inc... 4.5 Port C Port C is a 4-bit bidirectional port which does not share any of its pins with other subsystems. The port C data register is at $0002 and the data direction register (DDR) is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. 4.6 Input/Output Programmingf Ports A, B and C may be programmed as an input or an output under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any port A, port B or port C pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or reset, all DDRs are cleared, which configures all port A, B, and C pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. See Table 4-1 and Figure 4-1. General Release Specification Input/Output Ports For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Input/Output Ports Input/Output Programmingf Table 4-1. I/O Pin Functions R/W* 0 0 1 1 DDR 0 1 0 1 I/O Pin Function The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output of the I/O pin. The state of the I/O pin is read. The I/O pin is in an output jmode. The output data latch is read. Freescale Semiconductor, Inc... *R/W is an internal signal. Data Direction Register Bit Internal HC05 Connections Latched Output Data Bit Output I/O Pin Input Register Bit Input I/O Figure 4-1. Port I/O Circuitry MC68HC05E1 — Revision 2.0 Input/Output Ports For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Input/Output Ports Freescale Semiconductor, Inc... General Release Specification Input/Output Ports For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 5. Memory 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Freescale Semiconductor, Inc... 5.3 5.4 5.2 Introduction The MC68HC05E1 has an 8K byte memory map, consisting of user ROM, user RAM, Self-Check ROM, Control Registers, and I/O. See Figure 5-1 and Figure 5-2. 5.3 ROM 4096 bytes of user ROM are located from $0F00 to $1EFF, with 16 additional bytes of user vectors from $1FF0 to $1FFF. The Self-Check ROM and vectors are located from $1F00 to $1FEF. 5.4 RAM The user RAM consists of 368 bytes from location $0090 to $01FF including the stack area. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM from $00FF to $00C0. Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. MC68HC05E1 — Revision 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Memory $0000 $001F $0020 $008F $0090 $00BF $00C0 $00FF $0100 $01FF $0200 I/O 32 Bytes Unused 112 Bytes RAM 112 Bytes Stack 64 Bytes RAM 256 Bytes Unused 3328 Bytes 0000 0031 0032 0143 0144 0191 0192 0255 0256 0511 0512 Port A Data Register Port B Data Register Port C Data Register Unused Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register PLL Control Register Timer Control & Status Register Timer Counter Register Unused $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A Freescale Semiconductor, Inc... $0EFF $0F00 User ROM 4096 Bytes $1EFF $1F00 Self-Check ROM & Vectors 240 Bytes User Vectors 16 Bytes 3839 3840 Unused CPI Control & Status Register 7935 7936 Unused ... ... $11 $12 $13 $1FEF $1FF0 $1FFF 8175 8176 8191 Unused Test Register $1E $1F Unused ... $1FF0 Unused CPI Vector (High Byte) CPI Vector (Low Byte) Timer Vector (High Byte) Timer Vector (Low Byte) IRQ Vector (High Byte) IRQ Vector (Low Byte) SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte) $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF Figure 5-1. The 8 Kbyte Memory Map of the MC68HC05E1 General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Memory RAM ADDRESS $00 TO $001F $00 PORT A DATA $01 PORT B DATA $02 PORT C DATA $03 UNUSED $04 PORT A DDR $05 PORT B DDR DATA 7 6 5 4 3 2 1 0 0 — 0 — 0 — 0 — — — — — Freescale Semiconductor, Inc... $06 PORT C DDR $07 PLL CONTROL REG $08 TIMER CONTROL & STATUS REG $09 TIMER COUNTER REG $0A UNUSED $0B UNUSED $0C UNUSED $0D UNUSED $0E UNUSED $0F UNUSED $10 UNUSED $11 UNUSED $12 CPI CONTROL &STATUS REG $13 UNUSED $14 UNUSED $15 UNUSED $16 UNUSED $17 UNUSED $18 UNUSED $19 UNUSED $1A UNUSED $1B UNUSED $1C UNUSED $1D UNUSED $1E UNUSED $1F UNUSED — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CPIF — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CPIE — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0 TOF BCS RTIF AUTO TOFE BWC RTIE PLLON 0 VCOTST 0 PS1 RT1 PS0 RT0 Figure 5-2. Input/Output (I/O) Registers MC68HC05E1 — Revision 2.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Memory Freescale Semiconductor, Inc... General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 6. Timer, Phase-Locked Loop, and Custom Periodic Interrupt 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Freescale Semiconductor, Inc... 6.3 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.3.1 Timer Control and Status Register (TCSR) $08 . . . . . . . . . .60 6.3.2 Computer Operating Properly (COP) Watchdog Reset . . . .62 6.3.3 Timer Control Register (TCR) $09 . . . . . . . . . . . . . . . . . . . .63 6.4 Phase-Locked Loop Synthesizer . . . . . . . . . . . . . . . . . . . . . . .64 6.4.1 Phase-Locked Loop Control Register (PLLCR) $07 . . . . . .66 6.4.2 Operation During STOP Mode . . . . . . . . . . . . . . . . . . . . . . .68 6.4.3 Noise Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5 Custom Periodic Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.5.1 Custom Periodic Interrupt Control and Status Register (CPICSR) $12. . . . . . . . . . . . . . . . .70 6.6 6.7 Operation During STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . .70 Operation During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . .71 6.2 Introduction This section describes the timer, phase-locked loop (PLL), and custom periodic interrupt (CPI). MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic 6.3 Timer The Timer for this device is a 15-stage multi-functional ripple counter. The features include Timer Over Flow, Power-On Reset (POR), Real Time Interrupt, and COP Watchdog Timer. As seen in Figure 6-1, the Timer is driven by the output of the clock select circuit (as determined by the value of BCS in the PLLCR) then a fixed divide by four prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the Timer Counter Register (TCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of fop/1024. Two additional stages produce the POR function at fop/4064. The Timer Counter Bypass circuitry (available only in Test Mode) is at this point in the timer chain. This circuit is followed by two more stages, with the resulting clock (fop/16384) driving the Real Time Interrupt circuit. The RTI circuit consists of three divider stages with a 1 of 4 selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP Watchdog Timer circuit. The RTI rate selector bits, and the RTI and TOF enable bits and flags are located in the Timer Control and Status Register at location $08. Freescale Semiconductor, Inc... General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Interrupt Timer MC68HC05E1 Internal Bus 8 8 Internal Processor Clock COP Clear $09 TCR Timer Counter Register (TCR) fop fop/22 TCR fop/210 ÷4 Freescale Semiconductor, Inc... 7-bit counter POR TCBP RTI Select Circuit Overflow Detect Circuit fop/214 TO fop/217 $08 TCSR Timer Control & Status Register TCSR TOF RTIF TOFE RTIE — — RT1 RT0 Interrupt Circuit COP Watchdog Timer (÷8) To Interrupt Logic To Reset Logic Figure 6-1. Timer Block Diagram MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic 6.3.1 Timer Control and Status Register (TCSR) $08 The TCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. Figure 6-2 shows the value of each bit in the TCSR when coming out of reset. $08 RESET: TOF 0 RTIF 0 TOFE 0 RTIE 0 0 0 0 0 RT1 1 RT0 1 Freescale Semiconductor, Inc... Figure 6-2. Timer Control and Status Register (TCSR) TOF — Timer Over Flow TOF is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $FF to $00. A CPU interrupt request will be generated if TOFE is set. Clearing the TOF is done by writing a ’0’ to it. Writing a ’1’ to TOF has no effect on the bit’s value. Reset clears TOF. RTIF — Real Time Interrupt Flag The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4 selector. The clock frequency that drives the RTI circuit is fop/213 (or fop/8192) with three additional divider stages giving a maximum interrupt period of 4 seconds at a crystal frequency of 32.768 kHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. A CPU interrupt request will be generated if RTIE is set. Clearing the RTIF is done by writing a ’0’ to it. Writing a ’1’ to RTIF has no effect on this bit. Reset clears RTIF. TOFE — Timer Over Flow Enable When this bit is set, a CPU interrupt request is generated when the TOF bit is set. Reset clears this bit. General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Interrupt Timer RTIE — Real Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit. RT1:RT0 — Real Time Interrupt Rate Select These two bits select one of four taps from the Real Time Interrupt circuit.Table 6-1 shows the available interrupt rates with several fop values. Reset sets these RT0 and RT1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps. Table 6-1. RTI Rates RTI RATES AT fOP FREQUENCY SPECIFIED: RT1:RT0 16.384 kHz 00 01 10 11 1s 2s 4s 8s 524 kHz 31.3 ms 62.5 ms 125 ms 250 ms 1.049 MHz 15.6 ms 31.3 ms 62.5 ms 125.1 ms 2.097 MHz 7.8 ms 15.6 ms 31.3 ms 62.5 ms 4.194 MHz 3.9 ms 7.8 ms 15.6 ms 31.3 ms fOP 214 op f 215 f op 216 f op 217 f op Freescale Semiconductor, Inc... NOTE: In rare instances, clearing any of the timer control and status register (TCSR) flag or enable bits could result in vectoring to the reset vector rather than the timer interrupt vector if the correct precautions are not followed. Do not clear any of the timer flags or enable bits (i.e., TOF, TOFE, RTI, and RTIF) with bit manipulation instructions. MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Example: CLEARING TIMER OVERFLOW FLAG (TOF) BIT SEI SEI NOT REQUIRED IF USED WITHIN TIMER INTERRUPT ROUTINE. LDA AND OR STA CLI #$73 $TCSR #$40 $TCSR DO NOT USE CLI IF THIS CODE SEGMENT IF USED WITHIN TIMER INTERRUPT ROUTINE MASK RTIF BIT Freescale Semiconductor, Inc... CLEARING TIMER OVERFLOW ENABLE (TOFE) BIT SEI LDA AND OR STA CLI #$D3 $TCSR #$C0 $TCSR DO NOT USE CLI IF THIS CODE SEGMENT IF USED WITHIN TIMER INTERRUPT ROUTINE MASK RTIF & TOF 6.3.2 Computer Operating Properly (COP) Watchdog Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 6-2. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP time-out is done by writing a ’0’ to bit 0 of address $1FF0. When the COP is cleared, only the final divide by eight stage (output of the RTI) is cleared. This function is a mask option. General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Interrupt Timer Table 6-2. COP Reset Times RTI RATES AT fOP FREQUENCY SPECIFIED: RT1:RT0 16.384 kHz 00 01 10 11 7s 14 s 28 s 56 s 524 kHz 218.8 ms 437.5 ms 875.0 ms 1.75 s 1.049 MHz 109.4 ms 218.8 ms 437.5 ms 875.0 ms 2.097 MHz 54.7 ms 109.4 ms 218.8 ms 437.5 ms 4.194 MHz 27.3 ms 54.7 ms 109.4 ms 218.8 ms fOP 7 x (RTI Rate) 7 x (RTI Rate) 7 x (RTI Rate) 7 x (RTI Rate) Freescale Semiconductor, Inc... 6.3.3 Timer Control Register (TCR) $09 The Timer Counter Register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fop divided by 4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. $09 Figure 6-3. Timer Counter Register The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin. When RESET is asserted anytime during operation (other than POR), the counter chain will be cleared. MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic 6.4 Phase-Locked Loop Synthesizer The phase-locked loop (PLL) consists of a variable bandwidth loop filter, a voltage controlled oscillator (VCO), a feedback frequency divider, and a digital phase detector. The PLL requires an external loop filter capacitor (typically 0.1 uf) connected between XFC and VDDSYN. This capacitor should be located as close to the chip as possible to minimize noise. VDDSYN is the supply source for the PLL and should be bypassed to minimize noise. The VDDSYN bypass cap should be as close as possible to the chip. Freescale Semiconductor, Inc... V 0.1 µF tREF OSC1 Crystal Oscillator PCOMP 0.1 µF DDSYN XFC PLLOUT Phase Detect loop filter VCO and ÷2 Clock Select BCS To clock generation circuitry tFB Frequency Divider PS1 PS0 Figure 6-4. PLL Circuit The phase detector compares the frequency and phase of the feedback frequency (tFB) and the crystal oscillator reference frequency (tREF) and generates the output, PCOMP, as shown in Figure 6-4. The output wave-form is then integrated and amplified. The resultant dc voltage is applied to the voltage controlled oscillator. The output of the VCO is divided by a variable frequency divider of 256, 128, 64, or 32 to provide the feedback frequency for the phase detector. General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Interrupt Phase-Locked Loop Synthesizer To change PLL frequencies, follow the procedure outlined below: 1. Clear BCS to enable the low frequency bus rate, 2. Clear PLLON to disable the PLL and select manual high bandwidth, 3. Select the speed using PS1 and PS0, 4. Set PLLON to enable the PLL, 5. Wait a time of 90% tPLLS for the PLL frequency to stabilize and select manual low bandwidth, wait another 10% tPLLS, 6. Set BCS to switch to the high frequency bus rate. The user should not switch among the high speeds with the BCS bit set. Following the procedure above will prevent possible bursts of high frequency operation during the re-configuration of the PLL. The PLL loop filter has two bandwidths which are automatically selected by the PLL if AUTO=1. Whenever the PLL is first enabled, the wide bandwidth mode is used. This enables the PLL frequency to ramp up quickly. When the output frequency is near the desired frequency, the filter is switched to the narrow bandwidth mode to make the final frequency more stable. The use of automatic bandwidth is not recommended at this time. Manual bandwidth control can be done by clearing AUTO in the PLLCR and setting the appropriate value for BWC. Freescale Semiconductor, Inc... MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic 6.4.1 Phase-Locked Loop Control Register (PLLCR) $07 This read/write register contains the control bits select the PLL frequency and enable/disable the synthesizer. $07 RESET: 0 0 BCS 0 AUTO 1 BWC 0 PLLON VCOTST 1 1 PS1 0 PS0 1 Freescale Semiconductor, Inc... Figure 6-5. Phase-Locked Loop Control Register BCS — Bus Clock Select When this bit is set, the output of the PLL is used to generate the internal processor clock. When clear, the internal bus clock is driven by the crystal (OSC1÷2). Once BCS has been changed, it may take up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition. During the transition, the clock select output will be held low and all CPU and timer activity will cease until the transition is complete. Before setting BCS, allow at least a time of tPLLS after PLLON is set. Reset clears this bit. AUTO When set, this bit selects the automatic bandwidth circuitry in the Phase detect block. When clear, manual bandwidth control is selected. Reset sets this bit. NOTE: The use of automatic bandwidth is not recommended at this time. BWC — Bandwidth Control This bit selects high bandwidth control when set, and low bandwidth control when clear. The low bandwidth driver is always enabled, so this bit determines whether the high bandwidth driver is on or off. Bandwidth control is under manual control only when the AUTO bit is clear. When the AUTO bit is set, BWC acts as a read-only status bit to indicate which mode has been selected by the internal circuit. On PLL start-up in automatic mode (AUTO=1), the high bandwidth driver is enabled (BWC=1) by internal circuitry until the PLL has locked onto General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Interrupt Phase-Locked Loop Synthesizer the specified frequency. The high bandwidth driver is then disabled and BWC is cleared by internal circuitry. Reset clears this bit. Table 6-3 Table 6-3. Loop Filter Bandwidth Control AUTO 0 0 BWC 0 0 1 1 X VCOTST 0 1 0 1 1 HIGH BANDWIDTH OFF OFF ON ON AUTO LOW BANDWIDTH OFF ON OFF ON ON Freescale Semiconductor, Inc... 0 0 1 PLLON — PLL On This bit activates the synthesizer circuit without connecting it to the control circuit. This allows the synthesizer to stabilize before it can drive the CPU clocks. When this bit is cleared, the PLL is shut off. Reset sets this bit. NOTE: PLLON should not be cleared while using the PLL to drive the internal processor clock, i.e. when BCS is high. If the internal processor clock is driven by the PLL, clearing the PLLON bit would cause the internal processor clock to stop. Exercise caution when using these bits. VCOTST — VCO Test This bit is used to isolate the loop filter from the VCO in order to facilitate testing. When clear, the low bandwidth mode of the PLL filter is disabled. When set, the loop filter operates as indicated by the values of AUTO and BWC. This bit is always set when AUTO=1 as security when running in automatic mode. Reset sets this bit. NOTE: This bit is intended for use by Motorola to test and characterize the PLL. The user should always have this bit set to 1. MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic PS1:PS0 — PLL Synthesizer Speed Select These two bits select one of four taps from the PLL to drive the CPU clocks. These bits are used in conjunction with PLLON and BCS bits in the PLL Control Register. These bits should not be written if BCS in the PLLCR is at a logic high. Reset clears PS1 and sets PS0, choosing a bus clock frequency of 1.049 MHz. Table 6-4. PS1 and PS0 Speed Selects with 32.768 kHz Crystal Freescale Semiconductor, Inc... PA1:PS0 CPU BUS CLOCK FREQUENCY (fOP) 524 kHz 1.049 MHz 2.097 MHz 4.194 MHz Reset Condition See Note below See Note below 00 01 10 11 NOTE: For the standard MC68HC05E1, the 4.194 MHz bus clock frequency should never be selected, and the 2.097 MHz bus clock frequency should not be selected when running the part below VDD = 4.5 V. For the high speed MC68HSC05E1, the 4.194 MHz bus clock frequency should not be selected when running the part below VDD = 4.5 V. 6.4.2 Operation During STOP Mode The PLL is switched to low frequency bus rate and is temporarily turned off when STOP is executed. Coming out of STOP mode with an external IRQ, the PLL is turned on with the same configuration it had before going into STOP with the exception of BCS which is reset. Otherwise, the PLL control register is in the reset condition. General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Interrupt Custom Periodic Interrupt 6.4.3 Noise Immunity The MCU should be insulated as much as possible from noise in the system. We recommend the following steps be taken to help prevent problems due to noise injection. 1. The application environment should be designed so that the MCU is not near signal traces which switch often, such as a clock signal, 2. The oscillator circuit for the MCU should be placed as close as possible to the OSC1 and OSC2 pins on the MCU, and Freescale Semiconductor, Inc... 3. All power pins should be filtered (to minimize noise on these signals) by using bypass capacitors placed as close as possible to the MCU. See the Application Note Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers, available through the Motorola Literature Distribution Center, document number AN1050/D. 6.5 Custom Periodic Interrupt The custom periodic interrupt is mask programmable to a 0.25 second, 0.5 second, or 1 second interrupt. The interrupt is generated from the 32 kHz OSC1 input by a 15-bit counter. This interrupt is under the control of the Custom Periodic Interrupt Control and Status Register located at $12. MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic 6.5.1 Custom Periodic Interrupt Control and Status Register (CPICSR) $12 The CPICSR contains the CPI flag and enable bits. Figure 6-6 shows the location of these bits and their values after reset. $12 RESET: 0 0 CPIF 0 0 0 CPIE 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Figure 6-6. Custom Periodic Interrupt Control and Status Register (CPICSR) CPIF — Custom Periodic Interrupt Flag CPIF is a clearable, read-only status bit and is set when the 15-bit counter changes from $7FFF to $0000. A CPU interrupt request will be generated if CPIE is set. Clearing the CPIF is done by writing a ’0’ to it. Writing a ’1’ to CPIF has no effect on the bit’s value. Reset clears CPIF. CPIE — Custom Periodic Interrupt Enable When this bit is cleared, the counter is cleared and CPI interrupts are disabled. When this bit is set, the counter starts from $0000 and a CPU interrupt request is generated when the CPIF bit is set. Reset clears this bit. 6.6 Operation During STOP Mode The timer system is cleared and the CPI counter is halted when going into STOP mode. When STOP is exited by an external interrupt or an external RESET, the internal oscillator will resume, followed by a 4064 internal processor oscillator stabilization delay. The timer system counter is then cleared and operation resumes. The CPI will continue counting once the oscillator resumes and does not wait for the oscillator to stabilize. General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Interrupt Operation During WAIT Mode 6.7 Operation During WAIT Mode The CPU clock halts during the WAIT mode, but the timer and CPI remain active. If interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the processor to exit the WAIT mode. Freescale Semiconductor, Inc... MC68HC05E1 — Revision 2.0 General Release Specification Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer, Phase-Locked Loop, and Custom Periodic Freescale Semiconductor, Inc... General Release Specification MC68HC05E1 — Revision 2.0 Timer, Phase-Locked Loop, and Custom Periodic Interrupt For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 7. Electrical Specifications 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .76 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .77 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Freescale Semiconductor, Inc... 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.2 Introduction This section provides parametric information for the MC68HC05E1. MC68HC05E1 — Revision 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Electrical Specifications 7.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD Freescale Semiconductor, Inc... Rating Supply Voltage Input Voltage Self-Check Mode (IRQ Pin Only) Current Drain per Pin Excluding VDD and VSS Storage Temperature Range Symbol VDD VIN VIN I Tstg Value –0.3 to + 7.0 VSS –0.3 to VDD +0.3 VSS –0.3 to 2 x VDD +0.3 25 –65 to + 150 Unit V V V mA °C NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 7.6 5.0-Volt DC Electrical Characteristics and 7.7 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions. General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Electrical Specifications Operating Range 7.4 Operating Range Characteristic Operating Temperature Range MC68HC05E1P (Standard) MC68HC05E1CP (Extended) MC68HC05E1MP (Automotive) Symbol Value TL to TH 0 to +70 –40 to +85 –40 to +125 Unit TA °C Freescale Semiconductor, Inc... 7.5 Thermal Characteristics Characteristic Thermal Resistance Plastic DIP SOIC Symbol θJA Value 60 60 Unit °C/W MC68HC05E1 — Revision 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Electrical Specifications 7.6 5.0-Volt DC Electrical Characteristics Characteristic Output Voltage ILoad = 10.0 µA ILoad = –10.0 µA Output High Voltage (ILoad = –0.8 mA) PA0–PA7, PB0–PB7, PC0–PC3 Output Low Voltage (ILoad = 1.6 mA) PA0–PA7, PB0–PB7, PC0–PC3 Input High Voltage PA0–PA7, PB0–PB7, PD0–PD3, IRQ, RESET, OSC1 Input Low Voltage PA0–PA7, PB0–PB7, PD0–PD3, IRQ, RESET, OSC1 XFC Wide Bandwidth Source Sink XFC Narrow Bandwidth Source Sink Supply Current (see Notes) Run fosc = 32.768 kHz, fOP =16.384 kHz fosc = 4.2 MHz, fOP = 2.1 MHz Wait fosc = 32.768 kHz, fOP =16.384 kHz fosc = 4.2 MHz, fOP = 2.1 MHz Stop (PLL off) 25 °C –40 °C to +85 °C (Extended) I/O Ports Hi-Z Leakage Current PB0–PB7, PC0–PC3, PA0–PA7 Input Current RESET, IRQ, OSC1 Capacitance Ports (As Input or Output) RESET, IRQ Symbol VOL VOH VOH VOL VIH VIL Min — VDD –0.1 VDD –0.8 — 0.7 x VDD VSS Typ — — — — — — Max 0.1 — — 0.40 VDD 0.3 x VDD Unit V V V V V Freescale Semiconductor, Inc... IOH IOL IOH IOL –50 50 –1 1 –100 100 –2 2 — — — — µA µA — — IDD — — — — IOZ IIN — — 100 3.5 60 0.8 2 — — — 160 5.0 100 1.2 50 180 10 1 µA mA µA mA µA µA µA µA COUT CIN — — — — 12 8 pF NOTES: 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to 70 °C, unless otherwise noted 2. All values shown reflect average measurements at midpoint of voltage range at 25 °C. 3. Wait IDD: Only timer and CPI systems active 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source, all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc. 6. Stop IDD is measured with OSC1 = VSS. 7. Standard temperature range is 0 °C to 70 °C. Extended temperature range (–40 °C to 85 °C) is available. 8. Wait IDD is affected linearly by the OSC2 capacitance. General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Electrical Specifications 3.3-Volt DC Electrical Characteristics 7.7 3.3-Volt DC Electrical Characteristics Characteristic Output Voltage ILoad = 10.0 µA ILoad = –10.0 µA Output High Voltage (ILoad = –0.2 mA) PA0–PA7, PB0–PB7, PC0–PC3 Output Low Voltage (ILoad = 0.4 mA) PA0–PA7, PB0–PB7, PC0–PC3 Input High Voltage PA0–PA7, PB0–PB7, PD0–PD3, IRQ, RESET, OSC1 Input Low Voltage PA0–PA7, PB0–PB7, PD0–PD3, IRQ, RESET, OSC1 XFC Wide Bandwidth Source Sink XFC Narrow Bandwidth Source Sink Supply Current (see Notes) Run fosc = 32.768 kHz, fOP =16.384 kHz fosc = 2.1 MHz, fOP = 1.0 MHz Wait fosc = 32.768 kHz, fOP =16.384 kHz fosc = 2.1 MHz, fOP = 1.0 MHz Stop (PLL off) 25 °C –40 °C to +85 °C (Extended) I/O Ports Hi-Z Leakage Current PB0–PB7, PC0–PC3, PA0–PA7 Input Current RESET, IRQ, OSC1 Capacitance Ports (As Input or Output) RESET, IRQ Symbol VOL VOH VOH VOL VIH VIL Min — VDD –0.1 VDD –0.3 — 0.7 x VDD VSS Typ — — — — — — Max 0.1 — — 0.30 VDD 0.3 x VDD Unit V V V V V Freescale Semiconductor, Inc... IOH IOL IOH IOL –25 25 –-0.5 0.5 –50 50 –1 1 — — — — µA µA — — IDD — — — — IOZ IIN — — 60 1.5 30 0.3 1 — — — 90 2.0 50 0.3 30 120 10 1 µA mA µA mA µA µA µA µA COUT CIN — — — — 12 8 pF NOTES: 1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to 70 °C, unless otherwise noted 2. All values shown reflect average measurements at midpoint of voltage range at 25 °C. 3. Wait IDD: Only timer and CPI systems active 4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source, all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc. 6. Stop IDD is measured with OSC1 = VSS. 7. Standard temperature range is 0 °C to 70 °C. Extended temperature range (–40 °C to 85 °C) is available. 8. Wait IDD is affected linearly by the OSC2 capacitance. MC68HC05E1 — Revision 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Electrical Specifications 7.8 5.0-Volt Control Timing Characteristic Frequency of Operation Crystal Oscillator Option External Clock Option Internal Operating Frequency Crystal Oscillator (fOSC ÷ 2) External Clock (fOSC ÷ 2) Cycle Time RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) (see Figure 7-1) Interrupt Pulse Period (see Figure 7-1) OSC1 Pulse Width PLL Startup Stabilization Time Symbol fosc Min — DC — DC 480 1.5 125 Note 2 90 50 Max 32.768 4.2 16.384 2.1 — — — — — — Unit kHz MHz kHz MHz ns tcyc ns tcyc ns ms fop tcyc tRL tILIH tILIL tOH, tOL tPLLS Freescale Semiconductor, Inc... NOTES: 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to 70 °C, unless otherwise note 2. The minimum period, tILIL, should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc. 7.9 3.3-Volt Control Timing Characteristic Frequency of Operation Crystal Oscillator Option External Clock Option Internal Operating Frequency Crystal Oscillator (fOSC ÷ 2) External Clock (fOSC ÷ 2) Cycle Time RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) (see Figure 7-1) Interrupt Pulse Period (see Figure 7-1) OSC1 Pulse Width PLL Startup Stabilization Time Symbol fosc Min — DC — DC 1000 1.5 250 Note 2 200 100 Max 32.768 2.1 16.384 1.0 — — — — — — Unit kHz MHz kHz MHz ns tcyc ns tcyc ns ms fop tcyc tRL tILIH tILIL tOH, tOL tPLLS NOTES: 1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to 70 °C, unless otherwise note 2. The minimum period, tILIL, should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc. General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Electrical Specifications 3.3-Volt Control Timing IRQ tILIH tILIL IRQ1 tILIH . . . IRQn NORMALLY USED WITH WIRE-ORED CONNECTION Freescale Semiconductor, Inc... IRQ (MCU) Figure 7-1. External Interrupt Mode Diagram OSC11 tRL RESET tILIH IRQ2 4064 tcyc IRQ3 Internal Clock Internal Address Bus 1FFE 1FFE 1FFE 1FFE 1FFF4 NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option. 3. IRQ pin level and edge-sensitive mask option. 4. RESET vector address shown for timing example. RESET or Interrupt Vector Fetch Figure 7-2. Stop Recovery Timing Diagram MC68HC05E1 — Revision 2.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc... tVDDR V DD VDD Threshold (1-2 V Typical) Electrical Specifications General Release Specification 4064 tcyc tcyc 1FFE 1FFF NEW PC NEW PC 1FFE 1FFE 1FFE 1FFE 1FFF NEW PC NEW PC NEW PCH NEW PCL OP CODE tRL 3 PCH PCL OP CODE 2 OSC1 INTERNAL PROCESSOR CLOCK 1 INTERNAL ADDRESS BUS 1 INTERNAL DATA BUS 1 Freescale Semiconductor, Inc. Electrical Specifications For More Information On This Product, Go to: www.freescale.com RESET NOTES: 1. Internal timing signal and bus information not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. MC68HC05E1 — Revision 2.0 Figure 7-3. Power-On Reset and RESET Freescale Semiconductor, Inc. General Release Specification — MC68HC05E1 Section 8. Mechanical Specifications 8.1 Contents 8.2 Mechnical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Freescale Semiconductor, Inc... 8.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 8.3.1 P Suffix, Plastic DIP, Case # 710-02 . . . . . . . . . . . . . . . . . .82 8.3.2 DW Suffix, SOIC, Case # 751F-02. . . . . . . . . . . . . . . . . . . .83 8.2 Mechnical Data IRQ RESET OSC1 OSC2 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XFC VDDSYN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0 PC1 PC2 PC3 MC68HC05E1 — Revision 2.0 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Mechanical Specifications 8.3 Package Dimensions 8.3.1 P Suffix, Plastic DIP, Case # 710-02 -A28 15 B 1 14 Freescale Semiconductor, Inc... C L -TSEATING PLANE H G F D 20 PL N K 0.25(0.010) J 20 PL M M TB M 0.25(0.010) M TA M DIM NOTES 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION "B" DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 36.45 37.21 13.72 14.2 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0° 15° 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0° 15° 0.020 0.040 A B C D F G H J K L M N General Release Specification Mechanical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Mechanical Specifications Package Dimensions 8.3.2 DW Suffix, SOIC, Case # 751F-02 -A- 28 15 -B- P 0.25(0.010) 14 PL M B M 1 14 Freescale Semiconductor, Inc... G R X 45° J -TSEATING PLANE D 20 PL K C M F NOTES 1. DIMENSIONS "A" AND "B" ARE DATUMS AND "T" IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. CONTROLLING DIM; MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 6. 751F-01 OBSOLETE, NEW STANDARD 751F-02. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.701 0.710 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050BSC 0010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 MC68HC05E1 — Revision 2.0 Mechanical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification Freescale Semiconductor, Inc. Mechanical Specifications Freescale Semiconductor, Inc... General Release Specification Mechanical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E1 — Revision 2.0 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. For More Information On This Product, Go to: www.freescale.com