68HC08PT48

Order this document by MC68HC08PT48/D Rev. 2.0 68HC08PT48 68HC908PT48 Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice. NON-DISCLOSURE AGREEMENT HC08 REQUIRED Advance Information REQUIRED AGREEMENT NON-DISCLOSURE Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Advance Information 2 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . 27 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 37 Section 3. Central Processing Unit (CPU). . . . . . . . . . . . 53 Section 4. Clock Generator Module (CGMB) . . . . . . . . 69 Section 5. Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . 103 Section 6. Keyboard Interrupt (KBI) Module . . . . . . . . 109 Section 7. System Integration Module (SIM) . . . . . . . . 117 Section 8. Random-Access Memory (RAM) . . . . . . . . 141 Section 9. 2-Kbyte FLASH Memory. . . . . . . . . . . . . . . . 143 Section 10. 48-Kbyte FLASH Memory. . . . . . . . . . . . . . 153 Section 11. Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . 165 Section 12. Serial Communications Interface (SCI) Module. . . . . . . . . . . . . . . . . . . . 197 Section 13. Analog-to-Digital Converter (ADC) Module. . . . . . . . . . . . . . . . . . 233 Section 14. Configuration Register (CONFIG) . . . . . . . 243 Section 15. Timer Interface Module (TIM) . . . . . . . . . . 247 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA List of Sections Advance Information 3 NON-DISCLOSURE AGREEMENT REQUIRED List of Sections REQUIRED Section 16. Timebase Module (TIMTBX). . . . . . . . . . . . 275 Section 17. Input/Output (I/O) Ports . . . . . . . . . . . . . . 281 Section 18. Monitor ROM (MON) . . . . . . . . . . . . . . . . . 299 Section 19. Break Module. . . . . . . . . . . . . . . . . . . . . . . 309 Section 20. External Interrupt Module (IRQ) . . . . . . . . 315 Section 21. Alert Output Generator (ALR) . . . . . . . . . . 325 Section 22. Electrical Specifications . . . . . . . . . . . . . . 331 Section 23. Mechanical Data. . . . . . . . . . . . . . . . . . . . 345 Section 24. Ordering Information . . . . . . . . . . . . . . . . . 347 NON-DISCLOSURE Advance Information 4 List of Sections AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 1.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Advance Information 5 NON-DISCLOSURE 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.6.1 Power Supply Pins (VDD, VSS, EVDD1-4, EVSS1-4,VDDA1,2,VSSA1,2). . . . . . . . . . . . . . . . . . . . . . . .32 1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .33 1.6.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.6.4 External Interrupt Pin (IRQ1). . . . . . . . . . . . . . . . . . . . . . . .34 1.6.5 External Interrupt Pin (IRQ2). . . . . . . . . . . . . . . . . . . . . . . .34 1.6.6 External Filter Capacitor Pins (PLLXFC). . . . . . . . . . . . . . .34 1.6.7 Port A I/O Pins (PTA7–PTA0) . . . . . . . . . . . . . . . . . . . . . . .34 1.6.8 Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . .34 1.6.9 Port C I/O Pins (PTC7–PTC0). . . . . . . . . . . . . . . . . . . . . . .34 1.6.10 Port D I/O Pins (PTD7–PTD0). . . . . . . . . . . . . . . . . . . . . . .34 1.6.11 Port E I/O Pins (PTE7/AD3–PTE4/AD0 and PTE3/MISO-PTE0/SS) . . . . . . . . . . . . . . . . . . . . . .35 1.6.12 Port F I/O Pins (PTF7/KBD7–PTF0/KBD0) . . . . . . . . . . . . .35 1.6.13 Port G I/O Pins (PTG7/TCH3–PTG3/TCLK, PTG2/TxD, PTG1/RxD, and PTG0) . . . . . . . . . . . . . . . . . . . . . . . . .35 1.6.14 Alert Generator Output (ALERT) . . . . . . . . . . . . . . . . . . . . .35 1.6.15 ADC Voltage Reference Pin (VRH) . . . . . . . . . . . . . . . . . . .35 AGREEMENT REQUIRED Table of Contents REQUIRED Section 2. Memory Map 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .38 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 User FLASH/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 FLASH PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 AGREEMENT Section 3. Central Processing Unit (CPU) 3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 NON-DISCLOSURE 3.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.4.4 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.5 3.6 3.7 3.8 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .60 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .60 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Section 4. Clock Generator Module (CGMB) 4.1 4.2 4.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Advance Information 6 Table of Contents MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents 4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . .73 4.4.2.1 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . .75 4.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . . .75 4.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . . .80 4.4.3 Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . .80 4.4.4 CGMB External Connections . . . . . . . . . . . . . . . . . . . . . . .81 4.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 4.5.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . .82 4.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .82 4.5.3 External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . .83 4.5.4 PLL Analog Power Pin (VDDA1) . . . . . . . . . . . . . . . . . . . . . .83 4.5.5 PLL Analog Ground Pin (VSSA1) . . . . . . . . . . . . . . . . . . . . .83 4.5.6 Buffered Crystal Clock Output (CGMVOUT) . . . . . . . . . . . .83 4.5.7 CGMVSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.5.8 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . .84 4.5.9 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . .84 4.5.10 CGMB Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . .84 4.5.11 CGMB CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .84 4.6 CGMB Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . .90 4.6.3 PLL Multiplier Select Register High. . . . . . . . . . . . . . . . . . .92 4.6.4 PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . . .93 4.6.5 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .94 4.6.6 PLL Reference Divider Select Register. . . . . . . . . . . . . . . .95 4.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 4.9 CGMB During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .97 4.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . .98 4.10.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . .98 4.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .99 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Advance Information 7 NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents REQUIRED 4.10.3 4.10.4 Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . .100 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . .101 Section 5. Computer Operating Properly (COP) Module 5.1 5.2 5.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 AGREEMENT 5.4 I/O Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.1 CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.6 Reset Vetor Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.7 COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5.5 5.6 5.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 NON-DISCLOSURE 5.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 5.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 5.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .107 Section 6. Keyboard Interrupt (KBI) Module 6.1 6.2 6.3 6.4 6.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Advance Information 8 Table of Contents MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.7 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.8.1 Keyboard Status and Control Register . . . . . . . . . . . . . . .114 6.8.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . .116 7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .121 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 7.3.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . .121 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . .122 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .122 7.4.1 External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .124 7.4.2.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .126 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .126 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .126 7.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .127 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .127 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . .128 7.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . .128 7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 7.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 7.6.3 Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 7.6.4 Status Flag Protection in Break Mode. . . . . . . . . . . . . . . .132 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Advance Information 9 NON-DISCLOSURE AGREEMENT Section 7. System Integration Module (SIM) REQUIRED Table of Contents REQUIRED 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 7.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . .136 7.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .138 7.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . .139 AGREEMENT Section 8. Random-Access Memory (RAM) 8.1 8.2 8.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Section 9. 2-Kbyte FLASH Memory 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 FLASH 3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .145 FLASH 3 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .147 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . . .148 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 FLASH Program and Margin Read Operation . . . . . . . . . . . .150 NON-DISCLOSURE Section 10. 48-Kbyte FLASH Memory 10.1 10.2 10.3 10.4 10.5 Advance Information 10 Table of Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 FLASH 1Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 FLASH 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .155 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents 10.6 10.7 10.8 10.9 FLASH 1 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .158 FLASH 2 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .159 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . . .161 10.10 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 10.11 FLASH Program and Margin Read Operation . . . . . . . . . . . .162 11.1 11.2 11.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.5 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.6.1 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . .171 11.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .171 11.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .173 11.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .174 11.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .176 11.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 11.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 11.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 11.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 11.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 11.11 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 11.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .185 11.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 11.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .186 11.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .186 11.13.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 11.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Advance Information 11 NON-DISCLOSURE AGREEMENT Section 11. Serial Peripheral Interface (SPI) Module REQUIRED Table of Contents REQUIRED 11.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 11.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 11.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . .192 11.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 Section 12. Serial Communications Interface (SCI) Module 12.1 12.2 12.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 AGREEMENT NON-DISCLOSURE 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 12.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 12.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 12.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 12.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . .203 12.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 12.4.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.4.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .205 12.4.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12.4.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 12.4.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 12.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 12.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.6 SCI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .215 Advance Information 12 Table of Contents MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents 12.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 12.7.1 PTG2/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .216 12.7.2 PTG1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .216 12.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 12.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .217 12.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .220 12.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .222 12.8.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.8.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 12.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 12.8.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .229 Section 13. Analog-to-Digital Converter (ADC) Module 13.1 13.2 13.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 13.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.7.1 ADC Analog Power Pin (VDDA2) . . . . . . . . . . . . . . . . . . . .237 13.7.2 ADC Analog Ground Pin (VSSA2) . . . . . . . . . . . . . . . . . . .238 13.7.3 ADC Voltage Reference Pin (VRH) . . . . . . . . . . . . . . . . . .238 13.7.4 ADC Voltage In (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . .238 13.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 13.8.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . .238 13.8.2 ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 13.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Advance Information 13 NON-DISCLOSURE 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 13.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 13.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 13.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 13.4.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 13.4.5 Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .236 AGREEMENT REQUIRED Table of Contents REQUIRED Section 14. Configuration Register (CONFIG) 14.1 14.2 14.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Section 15. Timer Interface Module (TIM) 15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 15.2 15.3 AGREEMENT NON-DISCLOSURE 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 15.4.1 Timer Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . .252 15.4.2 Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 15.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 15.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .252 15.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .253 15.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .254 15.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .255 15.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .256 15.4.4.3 PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 15.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 15.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .260 15.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 15.8.1 TIM Clock Pin (PTG3/TCLK) . . . . . . . . . . . . . . . . . . . . . . .261 15.8.2 Timer Channel I/O Pins (PTG4/TCH0–PTG7/TCH3) . . . .261 15.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 15.9.1 Timer Status and Control Register . . . . . . . . . . . . . . . . . .262 15.9.2 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .264 15.9.3 Timer Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . .265 15.9.4 Timer Channel Status and Control Registers . . . . . . . . . .266 15.9.5 Timer Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . .271 Advance Information 14 Table of Contents MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Section 16. Timebase Module (TIMTBX) 16.1 16.2 16.3 16.4 16.5 16.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 Timebase Control Register Description . . . . . . . . . . . . . . . . .277 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Section 17. Input/Output (I/O) Ports 17.1 17.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 17.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 17.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 17.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .284 17.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 17.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 17.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .286 17.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 17.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 17.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .288 17.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 17.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 17.6.2 Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .290 17.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 17.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 17.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .292 17.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 17.8.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 17.8.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . .294 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Advance Information 15 NON-DISCLOSURE AGREEMENT 16.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 16.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 16.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 REQUIRED Table of Contents REQUIRED 17.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 17.9.1 Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 17.9.2 Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . .296 Section 18. Monitor ROM (MON) 18.1 18.2 18.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 AGREEMENT 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .300 18.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 18.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 18.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 18.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 Section 19. Break Module 19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 19.2 19.3 NON-DISCLOSURE 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310 19.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . .312 19.4.2 CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .312 19.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .312 19.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .312 19.4.5 COP During Break. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 19.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 19.5.1 Break Status and Control Register . . . . . . . . . . . . . . . . . .313 19.5.2 Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . .314 19.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 Advance Information 16 Table of Contents MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Section 20. External Interrupt Module (IRQ) 20.1 20.2 20.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 20.4.1 20.4.2 IRQ2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 20.5 20.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .321 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .321 Section 21. Alert Output Generator (ALR) 21.1 21.2 21.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 21.4.1 Alert Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 21.4.2 Sound Pressure Level Circuit . . . . . . . . . . . . . . . . . . . . . .328 21.4.3 Alert Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 Section 22. Electrical Specifications 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .332 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .333 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 3.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .334 2.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .335 RAM Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 3.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 22.10 2.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Table of Contents Advance Information 17 NON-DISCLOSURE AGREEMENT REQUIRED Table of Contents REQUIRED 22.11 3.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .337 22.12 2.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .338 22.13 PLL2P12M Electrical Specifications . . . . . . . . . . . . . . . . . . . .341 22.14 PLL2P12M Component Specifications . . . . . . . . . . . . . . . . . .341 22.15 Bus Clock PLL Acquisition/Lock Time Specifications . . . . . . .342 22.16 2-K FLASH Memory Electrical Characteristics . . . . . . . . . . . .343 22.17 48-K FLASH Memory Electrical Characteristics . . . . . . . . . . .343 22.18 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 AGREEMENT Section 23. Mechanical Data 23.1 23.2 23.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 80-Pin LQFP (Case 917-01) . . . . . . . . . . . . . . . . . . . . . . . . . .346 Section 24. Ordering Information 24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .348 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .349 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .350 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 24.2 24.3 24.4 24.5 24.6 NON-DISCLOSURE Advance Information 18 MC68HC(9)08PT48 — Rev. 2.0 Table of Contents MOTOROLA Advance Information — MC68HC(9)08PT48 List of Figures Figure 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 Title Page Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 MC68HC(9)08PT48 Register Map . . . . . . . . . . . . . . . . . . . .40 Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . .40 Vector Addresses in FLASH/ROM . . . . . . . . . . . . . . . . . . . .50 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .58 CGMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 CGMB External Connections . . . . . . . . . . . . . . . . . . . . . . . .82 CGMB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .86 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . .87 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . .90 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . .92 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . .93 PLL VCO Range Select Register (PVRS) . . . . . . . . . . . . . .94 PLL Reference Divider Select Register (PRDS) . . . . . . . . .95 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .106 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA List of Figures Advance Information 19 NON-DISCLOSURE AGREEMENT MC68HC(9)08PT48 Block Diagram . . . . . . . . . . . . . . . . . . .30 MC68HC(9)08PT48 Pinout (Top View) . . . . . . . . . . . . . . . .31 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 REQUIRED List of Figures REQUIRED Figure 6-1 6-2 6-3 6-4 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 9-1 9-2 9-3 10-1 10-2 10-3 10-4 10-5 Title Page KBI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 KBI Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Keyboard Status and Control Register (KBSCR) . . . . . . . .115 Keyboard Interrupt Enable Register (KBER) . . . . . . . . . . .116 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 SIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .120 CGM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . .124 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . .131 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . .134 Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . .134 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .135 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . .136 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . .136 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . .138 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .139 FLASH 3 Control Register (FL3CR) . . . . . . . . . . . . . . . . . .145 FLASH 3 Block Protect Register (FL3BPR) . . . . . . . . . . . .147 Page Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .151 FLASH 1 Control Register (FL1CR) . . . . . . . . . . . . . . . . . .155 FLASH 2 Control Register (FL2CR) . . . . . . . . . . . . . . . . . .155 FLASH 1 Block Protect Register (FL1BPR) . . . . . . . . . . . .158 FLASH 2 Block Protect Register (FL2BPR) . . . . . . . . . . . .159 Page Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .164 NON-DISCLOSURE Advance Information 20 AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 List of Figures MOTOROLA List of Figures Figure 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 13-1 13-2 13-3 13-4 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA List of Figures Title Page ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 ADC Status and Control Register (ADSCR). . . . . . . . . . . .238 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .241 ADC Clock Register (ADCLKR) . . . . . . . . . . . . . . . . . . . . .241 Advance Information 21 NON-DISCLOSURE SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .200 SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .201 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .207 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .208 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . .217 SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . .220 SCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . .223 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . .225 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .228 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .229 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . .229 AGREEMENT SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .167 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .168 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .169 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .172 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .174 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . .175 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .176 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . .178 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . .179 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .183 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .190 SPI Status and Control Register (SPSCR). . . . . . . . . . . . .192 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .195 REQUIRED List of Figures REQUIRED Figure 14-1 14-2 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 16-1 16-2 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 Advance Information 22 List of Figures Title Page Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . .244 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . .244 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Timer I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .250 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .255 Timer Status and Control Register (TSC) . . . . . . . . . . . . .262 Timer Counter Register High (TCNTH) . . . . . . . . . . . . . . .264 Timer Counter Register Low (TCNTL) . . . . . . . . . . . . . . . .264 Timer Modulo Register High (TMODH) . . . . . . . . . . . . . . .265 Timer Modulo Register Low (TMODL) . . . . . . . . . . . . . . . .265 Timer Channel 0 Status and Control Register (TSC0) . . . .266 Timer Channel 1 Status and Control Register (TSC1) . . . .266 Timer Channel 2 Status and Control Register (TSC2) . . . .267 Timer Channel 3 Status and Control Register (TSC3) . . . .267 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 Timer Channel 0 Register High (TCH0H). . . . . . . . . . . . . .271 Timer Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . .271 Timer Channel 1 Register High (TCH1H). . . . . . . . . . . . . .272 Timer Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . .272 Timer Channel 2 Register High (TCH2H). . . . . . . . . . . . . .272 Timer Channel 2 Register Low (TCH2L) . . . . . . . . . . . . . .272 Timer Channel 3 Register High (TCH3H). . . . . . . . . . . . . .273 Timer Channel 3 Register Low (TCH3L) . . . . . . . . . . . . . .273 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .276 Timebase Control Register (TBXCR) . . . . . . . . . . . . . . . . .277 I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .284 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .284 Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .286 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .286 Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .288 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA NON-DISCLOSURE AGREEMENT List of Figures Figure 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20 17-21 17-22 18-1 18-2 18-3 18-4 18-5 19-1 19-2 19-3 19-4 19-5 20-1 20-2 20-3 21-1 21-2 21-3 Title Page Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . .303 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . .311 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .311 Break Status and Control Register (BRKSCR) . . . . . . . . .313 Break Address Register High (BRKH) . . . . . . . . . . . . . . . .314 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . .314 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .317 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .318 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . .322 Alert Control Register (ALCR) . . . . . . . . . . . . . . . . . . . . . .327 Block Diagram of SPL Reduction Circuit . . . . . . . . . . . . . .328 Alert Data Register (ALDR) . . . . . . . . . . . . . . . . . . . . . . . .329 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA List of Figures Advance Information 23 NON-DISCLOSURE AGREEMENT Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . .288 Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .290 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . .290 Port D I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . .292 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . .292 Port E I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . .294 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . .294 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . .296 Data Direction Register G (DDRG) . . . . . . . . . . . . . . . . . .296 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 REQUIRED List of Figures REQUIRED Figure 22-1 22-2 Title Page SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 NON-DISCLOSURE Advance Information 24 List of Figures AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 List of Tables Table 3-1 3-2 4-1 4-2 4-3 7-1 7-2 7-3 9-1 9-2 10-1 10-2 10-3 11-1 11-2 11-3 12-1 12-2 12-3 12-4 12-5 12-6 12-7 Title Page Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 PRE1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . .89 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .89 Signal Name Convention . . . . . . . . . . . . . . . . . . . . . . . . . . .120 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Erase Block Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . .149 32-Kbyte Erase Block Sizes . . . . . . . . . . . . . . . . . . . . . . . . .156 16-Kbyte Erase Block Sizes . . . . . . . . . . . . . . . . . . . . . . . . .156 Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . .161 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . .194 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . .219 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . .230 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .230 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . .232 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA List of Tables Advance Information 25 NON-DISCLOSURE AGREEMENT Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 REQUIRED List of Tables REQUIRED Table 13-1 13-2 15-1 15-2 16-1 16-2 17-1 17-2 17-3 17-4 17-5 17-6 17-7 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 21-1 21-2 21-3 24-1 Title Page Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . .269 Timebase Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .277 Input Crystal Frequency Selection . . . . . . . . . . . . . . . . . . . .278 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 Port G Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . .305 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . .305 READ (Indexed Read) Command . . . . . . . . . . . . . . . . . . . .306 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . .306 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . .307 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . .307 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .308 Audio Alert Tone Generator divider Ratios. . . . . . . . . . . . . .326 Clock Divider and Modulator Selections . . . . . . . . . . . . . . .329 Duty Cycle Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 NON-DISCLOSURE Advance Information 26 AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 List of Tables MOTOROLA Advance Information — MC68HC(9)08PT48 Section 1. General Description 1.1 Contents 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA General Description Advance Information 27 NON-DISCLOSURE 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.6.1 Power Supply Pins (VDD, VSS, EVDD1-4, EVSS1-4,VDDA1,2,VSSA1,2). . . . . . . . . . . . . . . . . . . . . . . .32 1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .33 1.6.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.6.4 External Interrupt Pin (IRQ1). . . . . . . . . . . . . . . . . . . . . . . .34 1.6.5 External Interrupt Pin (IRQ2). . . . . . . . . . . . . . . . . . . . . . . .34 1.6.6 External Filter Capacitor Pins (PLLXFC). . . . . . . . . . . . . . .34 1.6.7 Port A I/O Pins (PTA7–PTA0) . . . . . . . . . . . . . . . . . . . . . . .34 1.6.8 Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . .34 1.6.9 Port C I/O Pins (PTC7–PTC0). . . . . . . . . . . . . . . . . . . . . . .34 1.6.10 Port D I/O Pins (PTD7–PTD0). . . . . . . . . . . . . . . . . . . . . . .34 1.6.11 Port E I/O Pins (PTE7/AD3–PTE4/AD0 and PTE3/MISO-PTE0/SS) . . . . . . . . . . . . . . . . . . . . . .35 1.6.12 Port F I/O Pins (PTF7/KBD7–PTF0/KBD0) . . . . . . . . . . . . .35 1.6.13 Port G I/O Pins (PTG7/TCH3–PTG3/TCLK, PTG2/TxD, PTG1/RxD, and PTG0) . . . . . . . . . . . . . . . .35 1.6.14 Alert Generator Output (ALERT) . . . . . . . . . . . . . . . . . . . . .35 1.6.15 ADC Voltage Reference Pin (VRH) . . . . . . . . . . . . . . . . . . .35 AGREEMENT REQUIRED General Description REQUIRED 1.2 Introduction The MC68HC(9)08PT48 is a member of the low-cost, low-power, highperformance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. AGREEMENT 1.3 Features Features of the MC68HC(9)08PT48 include: • • • • • • • • • • • • • • High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 Families On-chip FLASH/ROM of 48 Kbytes On-chip FLASH of 2 Kbytes separate from program ROM/FLASH ROM data security1 option (no security option for MC68HC908PT48) Configuration register (CONFIG) 2.5 Kbytes of on-chip MCU random-access memory (RAM) 56 general-purpose input/output (I/O) pins Programmable phase locked loop (PLL) for bus clock generation Serial peripheral interface module (SPI) Serial communications interface module (SCI) Timebase module (TBM) with software selection of crystal clock source Two external interrupt request pins ALERT generator module (ALR) NON-DISCLOSURE 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Advance Information 28 General Description MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA General Description MCU Block Diagram • • • • 16-bit, 4-channel timer interface module (TIM) Computer operating properly (COP) reset 8-bit, 4-channel analog-to-digital converter (ADC) System protection features: – Illegal opcode detect reset – Illegal address detect reset Packaged in an 80-pin quad flat pack (LQFP) Low-power design (fully static with stop and wait modes) Master reset pin and power-on reset (POR) • • • Features of the CPU08 include: • • • • • • • • • Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Fast 8 x 8 multiply instruction Fast 16 ÷ 8 divide instruction Optimization for controller applications High-level language (C language) support 1.4 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC(9)08PT48. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA General Description Advance Information 29 NON-DISCLOSURE Binary coded decimal (BCD) instructions AGREEMENT REQUIRED General Description REQUIRED DATA & ADDRESS BUS CPU CONTROL 7 15 15 15 7 V 87 ARITHMETIC/ LOGIC UNIT (ALU) 0 A 0 H:X 0 SP 0 PC 0 H I N Z C CCR PTBDDR ANALOG TO DIGITAL CONVERTOR PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTE7/AD3 PTE6/AD2 PTE5/AD1 PTE4/AD0 PTE3/MISO PTE2/MOSI PTE1/SPSCK PTE0/SS PTF7/KBD7 PTF6/KBD6 PTF5/KBD5 PTF4/KBD4 PTF3/KBD3 PTF2/KBD2 PTF1/KBD1 PTF0/KBD0 PTG7/TCH3 PTG6/TCH2 PTG5/TCH1 PTG4/TCH0 PTG3/TCLK PTG2/TxD PTG1/RxD PTG0 ALERT PTADDR PTCDDR PTDDDR PTEDDR PTFDDR PTGDDR AGREEMENT CONTROL/STATUS REGISTERS 80 BYTES SYSTEM MANAGEMENT MODULE RAM — 2.5 KBYTES TIME BASE MODULE FLASH PROM — 2 KBYTES USER FLASH/ROM — 48,640 BYTES TIMER MODULE MONITOR ROM — 240 BYTES SCI MODULE USER FLASH/ROM VECTORS 44 BYTES NON-DISCLOSURE OSC1 OSC2 PLLXFC CLOCK GENERATION MODULES SERIAL PERIPHERAL INTERFACE MODULE RST IRQ1 IRQ2 EVSS EVDD VSSA VDDA VSS VDD 4 4 2 2 2 2 POWER ALERT GENERATOR MODULE KEYBOARD INTERRUPT MODULE Figure 1-1. MC68HC(9)08PT48 Block Diagram Advance Information 30 General Description MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA PTG PTF SYSTEM INTEGRATION MODULE COMPUTER OPERATING PROPERLY MODULE PTE PTD PTC PTB PTA VRH General Description Pin Assignments 1.5 Pin Assignments Pin assignments for the MC68HC(9)08PT48 are shown in Figure 1-2. 80 79 78 77 72 71 70 69 68 67 76 75 74 73 66 65 64 63 62 61 OSC1 OSC2 EVDD4 VDD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PTA7 EVDD4 EVSS4 PB0 PB1 PB2 PB3 PB4 PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 23 26 27 28 29 32 33 36 37 22 24 25 30 31 34 35 38 39 20 21 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 60 PF4/KBD4 PF3/KBD3 PF2/KBD2 PF1/KBD1 PF0/KBD0 VSS VDD EVDD2 VDDA2 VRH PE7/AD3 PE6/AD2 PE5/AD1 PE4/AD0 EVSS2 PE3/MISO PE2/MOSI PE1/SPCLK 41 PE0/SS Figure 1-2. MC68HC(9)08PT48 Pinout (Top View) 1.6 Pin Functions Descriptions of the pin functions are provided here. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA General Description Advance Information 31 NON-DISCLOSURE VSSA2 EVDD3 EVSS3 PD7 40 PC0 PC3 PC4 PC5 PC6 PD0 PD4 PD1 PD2 PD3 PD5 PD6 PB6 PB7 PC1 PC2 PC7 AGREEMENT REQUIRED PG7/TCH3 PG6/TCH2 PG5/TCH1 PG4/TCH0 PG3/TCLK PF7/KBD7 PF6/KBD6 PF5/KBD5 EVSS1 IRQ2 IRQ1 RST PG1/RxD PG2/TxD PLLXFC ALERT EVDD1 VDDA1 VSSA1 PG0 General Description REQUIRED 1.6.1 Power Supply Pins (VDD, VSS, EVDD1-4, EVSS1-4, VDDA1,2, VSSA1,2) VDD and VSS are power supply and ground pins for the digital sections of the MCU. The MCU operates from a single power supply ranging from 2 V ± 10% to 3 V ± 10%. The EVDD and EVSS pins are power supply and ground pins for the I/O section of the MCU. VDDA1 and VSSA1 are used for the analog portion of the bus clock PLL to reduce noise injected to the clocks. Very fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide good power supply bypassing at the MCU as shown in Figure 1-3. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. EVSS2 pin is also the ground return pin for the serial clock in the serial peripheral interface module (SPI). It enables the user to implement a coplanar transmission line for the SPI clock on printed circuit boards (PCBs) with no ground plane. VSS can help reduce radiated radio frequency (RF) emissions by controlling trace impedance and minimizing radiating loop area. NON-DISCLOSURE AGREEMENT MCU VDD VSS C1 0.1 µF + C2 VDD Figure 1-3. Power Supply Bypassing NOTE: Advance Information 32 Component values shown represent typical applications. MC68HC(9)08PT48 — Rev. 2.0 General Description MOTOROLA General Description Pin Functions 1.6.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the crystal connections for the on-chip oscillator. Figure 1-4 shows a typical crystal oscillator circuit for a parallel resonant crystal. Follow the crystal supplier’s recommendations, as the crystal parameters determine the external component values required to provide reliable start up and maximum stability. NOTE: The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. To minimize output distortion and RF emissions, mount the crystal and capacitors as close as possible to the pins. MCU OSC1 OSC2 C1 XTAL C2 Figure 1-4. Crystal Connections NOTE: Follow the crystal manufacturer’s recommendations for component sizes. 1.6.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. See Section 7. System Integration Module (SIM) for more information. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA General Description Advance Information 33 NON-DISCLOSURE AGREEMENT REQUIRED General Description REQUIRED 1.6.4 External Interrupt Pin (IRQ1) IRQ1 is an asynchronous external interrupt pin. See Section 20. External Interrupt Module (IRQ) for more information. 1.6.5 External Interrupt Pin (IRQ2) IRQ2 is an asynchronous external interrupt pin. See Section 20. External Interrupt Module (IRQ) for more information. AGREEMENT 1.6.6 External Filter Capacitor Pins (PLLXFC) PLLXFC is the external filter capacitor connections for the PLL. See Section 17. Input/Output (I/O) Ports for more information. 1.6.7 Port A I/O Pins (PTA7–PTA0) PTA7–PTA0 are general-purpose bidirectional I/O port pins. See Section 17. Input/Output (I/O) Ports for more information. NON-DISCLOSURE 1.6.8 Port B I/O Pins (PTB7–PTB0) PTB7–PTB0 are general-purpose bidirectional I/O port pins.See Section 17. Input/Output (I/O) Ports for more information. 1.6.9 Port C I/O Pins (PTC7–PTC0) PTC7–PTC0 are general-purpose bidirectional I/O port pins. See Section 17. Input/Output (I/O) Ports for more information. 1.6.10 Port D I/O Pins (PTD7–PTD0) PTD7–PTD0 are general-purpose bidirectional I/O port pins. See Section 17. Input/Output (I/O) Ports for more information. Advance Information 34 General Description MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA General Description Pin Functions 1.6.11 Port E I/O Pins (PTE7/AD3–PTE4/AD0 and PTE3/MISO–PTE0/SS) Port E is an 8-bit special function port that shares four of its pins with the ADC and the other four pins with SPI. 1.6.12 Port F I/O Pins (PTF7/KBD7–PTF0/KBD0) Port F is an 8-bit special function port that shares with the keyboard interrupts. 1.6.13 Port G I/O Pins (PTG7/TCH3–PTG3/TCLK, PTG2/TxD, PTG1/RxD, and PTG0) Port G is an 8-bit special function port that shares five of its pins with the timer and two of its pins with SCI. 1.6.14 Alert Generator Output (ALERT) ALERT is the output from the ALR. See 21.1 Contents for more information. VRH is the power supply for setting the reference voltage VRH. Connect the VRH pin to a voltage potential ← VDDA2, not less than 1.5 V. It supplies the resistor legs. Ideally, route this to its own pad. It can be routed to VDDA. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA General Description Advance Information 35 NON-DISCLOSURE 1.6.15 ADC Voltage Reference Pin (VRH) AGREEMENT REQUIRED General Description REQUIRED NON-DISCLOSURE Advance Information 36 General Description AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 2. Memory Map 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .38 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 User FLASH/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 FLASH PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • • • • • 48 Kbytes of low-voltage FLASH/ROM 2.5 Kbytes of RAM 2 Kbytes of low-voltage FLASH separate from ROM/emulation FLASH 44 bytes of user-defined vectors 240 bytes of monitor ROM MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 37 NON-DISCLOSURE AGREEMENT REQUIRED Memory Map REQUIRED 2.3 I/O Section Addresses $0000–$004F, shown in Figure 2-1, contain most of the control, status, and data registers. Additional input/output (I/O) registers located in upper page memory are shown in Figure 2-2. 2.4 Random-Access Memory (RAM) The 2.5 Kbyte addresses from $0050–$0A4F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in RAM, allowing all page zero locations to be used for I/O control and user data or code. Within page zero there are 176 bytes of RAM. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM therefore provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NON-DISCLOSURE AGREEMENT NOTE: Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking. 2.5 Memory Map See Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4. Advance Information 38 Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Memory Map Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register $0000 Port B Data Direction Register I/O 80 Bytes Port C Data Direction Register Port D Data Direction Register Port E Data Register Page 0 User RAM 176 Bytes Port F Data Register Port G Data Register Unused Port E Data Direction Register Port F Data Direction Register Port G Data Direction Register SPI Control Register SPI Status Register SPI Data Register Unused Unused SCI Control Register 1 SCI Control Register 2 SCI Control Register 3 User FLASH/ROM 48,640 Bytes $FDFF $FE00 $FE10 $FEFF $FF00 $FFDB $FFDC $FFFF SCI Status Register 1 SCI Status Register 2 SCI Data Register SIM Registers 16 Bytes Monitor ROM 240 Bytes Unused 220 Bytes User Vectors 36 Bytes SCI Baud Rate Register Unused Unused IRQ Status/Control Register 2-K FLASH Block Protect Register *32-K FLASH Block Protect Register TIM Status and Control Register Unused TIM Counter Register High TIM Counter Register Low TIM Counter Modulo Register High TIM Counter Modulo Register Low *MC68HC908PT48 only TIM Channel 0 Status/Control Register TIM Channel 0 Register High $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 TIM Channel 0 Register Low TIM Channel 1 Status/Control Register TIM Channel 1 Register High TIM Channel 1 Register Low TIM Channel 2 Status/Control Register TIM Channel 2 Register High TIM Channel 2 Register Low TIM Channel 3 Status/Control Register TIM Channel 3 Register High TIM Channel 3 Register Low Unused Keyboard Status/Control Register Keyboard Interrupt Enable Register Unused Alert Control Register Alert Data Register Timebase Control Register Unused Unused Unused Unused Unused Unused Configuration Register Unused Unused Unused Unused Unused Unused PLL Control Register PLL Bandwidth Control Register PLL Multiplier Select High Register PLL Multiplier Select Low Register PLL VCO Range Select Register PLL Reference Divider Select Register A/D Status/Control Register A/D Data Register A/D Clock Register *16-K FLASH Block Protect Register $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $004F $0050 $00FF $0100 $0A4F $0A50 $17FF $1800 $1FFF $2000 Stack 64 Bytes User RAM 2560 Bytes (Total) Unused 3504 Bytes FLASH 2048 Bytes Unused 8192 Bytes $3FFF $4000 $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F Figure 2-1. Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 39 NON-DISCLOSURE $3F AGREEMENT REQUIRED Memory Map REQUIRED SIM Break Status Register SIM Reset Status Register Reserved SIM Break Flag Control Register Reserved Reserved Reserved $FE00 $FE0F SIM Registers 16 Bytes Reserved for -K FLASH Test 2-K FLASH Control Register Reserved for 16-K FLASH 1 Test 16-K FLASH 2 Control Register Reserved for 32-K FLASH 2 Test 32-K FLASH 1 Control Register Break Address Register (High) Break Address Register (Low) Break Status and Control Register $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F AGREEMENT Figure 2-2. MC68HC(9)08PT48 Register Map Addr. Register Name Bit 7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0 NON-DISCLOSURE $0000 Read: PTA7 Port A Data Register Write: (PTA) Reset: Read: PTB7 Port B Data Register Write: (PTB) Reset: Read: PTC7 Port C Data Register Write: (PTC) Reset: Read: PTD7 Port D Data Register Write: (PTD) Reset: Unaffected by reset PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001 Unaffected by reset PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 $0002 Unaffected by reset PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 $0003 Unaffected by reset = Unimplemented U = Undetermined X = Indeterminate Figure 2-3. Control, Status, and Data Registers (Sheet 1 of 10) Advance Information 40 Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Memory Map Addr. Register Name Bit 7 6 DDRA6 0 DDRB6 0 5 DDRA5 0 DDRB5 0 DDRC5 0 DDRD5 0 PTE5 4 DDRA4 0 DDRB4 0 DDRC4 0 DDRD4 0 PTE4 3 DDRA3 0 DDRB3 0 DDRC3 0 DDRD3 0 PTE3 2 DDRA2 0 DDRB2 0 DDRC2 0 DDRD2 0 PTE2 1 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 PTE1 Bit 0 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 PTE0 Read: DDRA7 Port A Data Direction Register $0004 Write: (DDRA) Reset: 0 Read: DDRB7 Port B Data Direction Register $0005 Write: (DDRB) Reset: 0 Read: DDRD7 DDRD6 Port D Data Direction Register $0007 Write: (DDRD) Reset: 0 0 Read: PTE7 Port E Data Register Write: (PTE) Reset: Read: PTF7 Port F Data Register Write: (PTF) Reset: Read: PTG7 Port G Data Register Write: (PTG) Reset: PTE6 $0008 Unaffected by reset PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 $0009 Unaffected by reset PTG6 PTG5 PTG4 PTG3 PTG2 PTG1 PTG0 $000A Unaffected by reset Unimplemented $000B Read: DDRE7 Port E Data Direction Register $000C Write: (DDRE) Reset: 0 Read: DDRF7 Port F Data Direction Register $000D Write: (DDRF) Reset: 0 DDRE6 0 DDRF6 0 DDRE5 0 DDRF5 0 DDRE4 0 DDRF4 0 DDRE3 0 DDRF3 0 DDRE2 0 DDRF2 0 DDRE1 0 DDRF1 0 DDRE0 0 DDRF0 0 = Unimplemented U = Undetermined X = Indeterminate Figure 2-3. Control, Status, and Data Registers (Sheet 2 of 10) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 41 NON-DISCLOSURE AGREEMENT Read: DDRC7 DDRC6 Port C Data Direction Register $0006 Write: (DDRC) Reset: 0 0 REQUIRED Memory Map REQUIRED Addr. Register Name Bit 7 6 5 DDRG5 0 SPMSTR 1 OVRF 4 DDRG4 0 CPOL 0 MODF 3 DDRG3 0 CPHA 1 SPTE 2 DDRG2 0 SPWOM 0 MODFEN 0 R2 T2 1 Bit 0 Read: DDRG7 DDRG6 Port G Data Direction Register $000E Write: (DDRG) Reset: 0 0 Read: SPRIE SPI Control Register Write: (SPCR) Reset: 0 Read: SPRF SPI Status and Control Write: Register (SPSCR) Reset: 0 Read: SPI Data Register Write: (SPDR) Reset: R7 T7 DMAS 0 ERRIE 0 R6 T6 DDRG1 DDRG0 0 SPE 0 SPR1 0 R1 T1 0 SPTIE 0 SPR0 0 R0 T0 $000F AGREEMENT $0010 0 R5 T5 0 R4 T4 1 R3 T3 $0011 Indeterminate after reset Unimplemented $0012 $0013 Read: LOOPS SCI Control Register 1 Write: (SCC1) Reset: 0 Read: SCTIE SCI Control Register 2 Write: (SCC2) Reset: 0 Read: SCI Control Register 3 Write: (SCC3) Reset: R8 Unimplemented NON-DISCLOSURE $0014 ENSCI 0 TCIE 0 T8 U TC TXINV 0 SCRIE 0 DMARE 0 SCRF M 0 ILIE 0 DMATE 0 IDLE WAKE 0 TE 0 ORIE 0 OR ILTY 0 RE 0 NEIE 0 NF PEN 0 RWU 0 FEIE 0 FE PTY 0 SBK 0 PEIE 0 PE $0015 $0016 U $0017 Read: SCTE SCI Status Register 1 Write: (SCS1) Reset: 1 1 0 0 0 0 X = Indeterminate 0 0 = Unimplemented U = Undetermined Figure 2-3. Control, Status, and Data Registers (Sheet 3 of 10) Advance Information 42 Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Memory Map Addr. Register Name Read: SCI Status Register 2 Write: (SCS2) Reset: Read: SCI Data Register Write: (SCDR) Reset: Read: SCI Baud Rate Register Write: (SCBR) Reset: Bit 7 6 5 4 3 2 1 BKF Bit 0 RPF $0018 0 R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 $0019 Unaffected by reset SCP1 0 0 0 SCP0 0 0 SCR2 0 SCR1 0 SCR0 0 $001B Unimplemented $001C Read: IRQF2 IRQ Status and Control Write: Register (ISCR) Reset: 0 Read: FLASH 3 Block Protect Write: Register (FL3BPR) Reset: Read: FLASH 1 Block Protect Write: Register (FL1BPR) Reset: Read: Timer Status and Control Write: Register (TSC) Reset: 0 ACK2 0 Unimplemented IRQF1 0 ACK1 0 0 $001D IMASK2 0 MODE2 0 IMASK1 MODE1 0 0 $001E BPR3 X X X X 1 BPR2 1 BPR1 1 BPR0 1 $001F F1BPR3 X TOF 0 0 X TOIE 0 X TSTOP 1 X 0 TRST 0 0 1 0 F1BPR2 F1BPR1 F1BPR0 1 PS2 0 1 PS1 0 1 PS0 0 $0020 $0021 Read: Bit 15 Timer Counter Register High Write: (TCNTH) Reset: 0 Bit 14 Bit 13 Unimplemented Bit 12 Bit 11 Bit 10 Bit 9 Bit 0 $0022 0 0 0 0 0 X = Indeterminate 0 0 = Unimplemented U = Undetermined Figure 2-3. Control, Status, and Data Registers (Sheet 4 of 10) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 43 NON-DISCLOSURE AGREEMENT $001A REQUIRED Memory Map REQUIRED Addr. Register Name Read: Timer Counter Register Low Write: (TCNTL) Reset: Bit 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 $0023 0 0 Bit 14 1 Bit 6 1 CH0IE 0 Bit 14 0 Bit 13 1 Bit 5 1 MS0B 0 Bit 13 0 Bit 12 1 Bit 4 1 MS0A 0 Bit 12 0 Bit 11 1 Bit 3 1 ELS0B 0 Bit 11 0 Bit 10 1 Bit 2 1 ELS0A 0 Bit 10 0 Bit 9 1 Bit 1 1 TOV0 0 Bit 9 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 $0024 Read: Bit 15 Timer Modulo Register High Write: (TMODH) Reset: 1 Read: Timer Modulo Register Low Write: (TMODL) Reset: Bit 7 1 AGREEMENT $0025 $0026 Read: CH0F Timer Channel 0 Status and Write: 0 Control Register (TSC0) Reset: 0 Read: Bit 15 Timer Channel 0 Register High $0027 Write: (TCH0H) Reset: Read: Timer Channel 0 Register Low Write: $0028 (TCH0L) Reset: Bit 7 Indeterminate after reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset CH1IE 0 Bit 14 0 MS1A 0 Bit 12 ELS1B 0 Bit 11 ELS1A 0 Bit 10 TOV1 0 Bit 9 CH1MAX 0 Bit 8 NON-DISCLOSURE $0029 Read: CH1F Timer Channel 1 Status and Write: 0 Control Register (TSC1) Reset: 0 0 Bit 13 Read: Bit 15 Timer Channel 1 Register High $002A Write: (TCH1H) Reset: Read: Timer Channel 1 Register Low $002B Write: (TCH1L) Reset: Bit 7 Indeterminate after reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unaffected by reset CH2IE 0 MS2B 0 MS2A 0 ELS2B 0 ELS2A 0 X = Indeterminate TOV2 0 CH2MAX 0 $002C Read: CH2F Timer Channel 2 Status and Write: 0 Control Register (TSC2) Reset: 0 = Unimplemented U = Undetermined Figure 2-3. Control, Status, and Data Registers (Sheet 5 of 10) Advance Information 44 Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Memory Map Addr. Register Name Bit 7 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 Read: Bit 15 Timer Channel 2 Register High $002D Write: (TCH2H) Reset: Read: Timer Channel 2 Register Low $002E Write: (TCH2L) Reset: Bit 7 Unaffected by reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unaffected by reset CH3IE 0 Bit 14 0 MS3A 0 Bit 12 ELS3B 0 Bit 11 ELS3A 0 Bit 10 TOV3 0 Bit 9 CH3MAX 0 Bit 8 0 Bit 13 Read: Bit 15 Timer Channel 3 Register High $0030 Write: (TCH3H) Reset: Read: Timer Channel 3 Register Low $0031 Write: (TCH3L) Reset: $0032 Read: Keyboard Status and Control Write: Register (KBSCR) Reset: 0 Bit 7 Unaffected by reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unaffected by reset Unimplemented 0 0 0 KEYF 0 ACKK 0 0 KBIE6 0 0 KBIE5 0 0 KBIE4 0 0 KBIE3 0 0 KBIE2 0 0 KBIE1 0 0 KBIE0 0 $0034 Read: KBIE7 Keyboard Interrupt Enable Write: Register (KBIER) Reset: 0 $0035 Read: Alert Control Register Write: (ALCR) Reset: 0 0 0 Unimplemented 0 $0036 AL3 0 AL2 0 AL1 0 AL0 0 0 0 0 0 = Unimplemented U = Undetermined X = Indeterminate Figure 2-3. Control, Status, and Data Registers (Sheet 6 of 10) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 45 NON-DISCLOSURE $0033 IMASKK MODEK AGREEMENT $002F Read: CH3F Timer Channel 3 Status and Write: 0 Control Register (TSC3) Reset: 0 REQUIRED Memory Map REQUIRED Addr. Register Name Bit 7 6 SPL6 0 TBXIE 0 5 SPL5 0 TBXR1 0 4 SPL4 0 TBXR0 0 3 SPL3 0 0 TACK 0 2 SPL2 0 TBXON 0 1 SPL1 0 Bit 0 SPL0 0 $0037 Read: SPL7 Alert Data Register Write: (ALDR) Reset: 0 Read: TBXIF Timebase Control Register Write: (TBXCR) Reset: 0 $0038 XTALR1 XTALR0 0 0 AGREEMENT $0039 Unimplemented $003A Unimplemented $003B Unimplemented $003C Unimplemented $003D Unimplemented NON-DISCLOSURE $003E Read: MC68HC908PT48 Configuration Register Write: (CONFIG) Reset: Read: MC68HC08PT48 Mask Option Register Write: (MOR) Reset: 0 0 0 Unimplemented 0 $003F SSREC SCIBDSRC 0 1 STOP 0 STOP COPD 0 COPD 0 0 0 0 0 0 0 SEC SSREC SCIBDSRC $003F 0 0 0 X X X X X $0040 Unimplemented $0041 Unimplemented = Unimplemented U = Undetermined X = Indeterminate Figure 2-3. Control, Status, and Data Registers (Sheet 7 of 10) Advance Information 46 Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Memory Map Addr. $0042 Register Name Bit 7 6 5 4 3 2 1 Bit 0 Unimplemented $0043 Unimplemented $0044 Unimplemented $0045 Read: PLLIE PLL Control Register Write: (PCTL) Reset: 0 Read: AUTO PLL Bandwidth Control Write: Register (PBWC) Reset: 0 Read: PLL Multiplier Select Register Write: High (PMSH) Reset: 0 PLLF Unimplemented $0046 PLLON 1 ACQ 0 0 BCS 0 0 PRE1 1 0 PRE0 1 0 VPR1 1 0 VPR0 1 COE 0 MUL8 0 MUL0 0 VRS0 0 RDS0 1 ADCH0 1 0 LOCK $0047 0 0 0 0 0 MUL11 0 MUL3 0 VRS3 0 RDS3 0 ADCH3 1 0 MUL10 0 MUL2 0 VRS2 0 RDS2 0 ADCH2 1 X = Indeterminate 0 MUL9 0 MUL1 0 VRS1 0 RDS1 0 ADCH1 1 $0048 0 0 MUL6 0 VRS6 1 0 0 MUL5 0 VRS5 0 0 0 MUL4 0 VRS4 0 0 $004A Read: VRS7 PLL VCO Range Select Write: Register (PVRS) Reset: 0 Read: PLL Reference Divider Select Write: Register (PRDS) Reset: 0 $004B 0 0 AIEN 0 0 ADCO 0 0 ADCH4 1 $004C Read: COCO/ Analog-to-Digital Status and Write: IDMAS Control Register (ADSCR) Reset: 0 = Unimplemented U = Undetermined Figure 2-3. Control, Status, and Data Registers (Sheet 8 of 10) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 47 NON-DISCLOSURE $0049 Read: MUL7 PLL Multiplier Select Register Write: Low (PMSL) Reset: 0 AGREEMENT REQUIRED Memory Map REQUIRED Addr. Register Name Read: Analog-to-Digital Data Write: Register (ADR) Reset: Bit 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0 $004D 0 0 ADIV1 0 0 ADIV0 0 0 ADICLK 0 0 0 0 0 0 0 0 0 $004E Read: ADIV2 Analog-to-Digital Clock Write: Register (ADCLKR) Reset: 0 Read: MC68HC908PT48 16 K-FLASH 2 Block Protect Write: Register (FL2BPR) Reset: 0 0 0 0 AGREEMENT $004F ↓ F2BPR3 X X X X 1 F2BPR2 F2BPR1 F2BPR0 1 1 1 $FE00 Read: SIM Break Status Register Write: (SBSR) Reset: R R R R R R SBSW Note 1 0 R Note 1. Writing a logic 0 clears SBSW. Read: SIM Reset Status Register Write: (SRSR) Reset: POR PIN COP ILOP ILAD 0 LVI 0 $FE01 1 0 0 0 Reserved 0 0 0 0 NON-DISCLOSURE $FE02 Read: BCFE SIM Break Flag Control Write: Register (SBFCR) Reset: 0 $FE03 R R R R R R R $FE04 Reserved $FE05 Reserved $FE06 Reserved = Unimplemented U = Undetermined X = Indeterminate Figure 2-3. Control, Status, and Data Registers (Sheet 9 of 10) Advance Information 48 Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Memory Map Addr. $FE07 Register Name Bit 7 6 5 4 Reserved 3 2 1 Bit 0 $FE08 Read: F3DIV1 FLASH 3 Control Register Write: (FL3CR) Reset: 0 F3DIV0 0 F3BLK1 0 F3BLK0 0 HVEN 0 MARG 0 ERASE 0 PGM 0 $FE09 Read: F2DIV1 FLASH2 Control Register Write: (FL2CR) Reset: 0 Reserved $FE0A 0 0 0 Reserved 0 0 0 0 $FE0B Read: F1DIV1 FLASH 1 Control Register Write: (FL1CR) Reset: 0 Read: Bit 15 Break Address Register High Write: (BRKH) Reset: 0 Read: Break Address Register Low Write: (BRKL) Reset: Bit 7 0 $FE0C F1DIV0 0 Bit 14 0 Bit 6 0 BRKA 0 F1BLK1 0 Bit 13 0 Bit 5 0 F1BLK0 0 Bit 12 0 Bit 4 0 HVEN 0 Bit 11 0 Bit 3 0 MARG 0 Bit 10 0 Bit 2 0 ERASE 0 Bit 9 0 Bit 1 0 PGM 0 Bit 8 0 Bit 0 0 $FE0D $FE0E Read: BRKE Break Status/Control Register $FE0F Write: (BRKSCR) Reset: 0 ↓ Read: COP Control Register Write: (COPCTL) Reset: 0 0 0 0 0 0 Low Byte of Reset Vector Clear COP Counter Unaffected by reset = Unimplemented U = Undetermined X = Indeterminate $FFFF Figure 2-3. Control, Status, and Data Registers (Sheet 10 of 10) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 49 NON-DISCLOSURE AGREEMENT F2DIV0 F2BLK1 F2BLK0 HVEN MARG ERASE PGM REQUIRED Memory Map REQUIRED Lowest Priority $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 Keyboard Vector (High) Keyboard Vector (Low) A/D Vector (High) A/D Vector (Low) PLL Vector (High) PLL Vector (Low) SPI Transmit Vector (High) SPI Transmit Vector (Low) SPI Receive Vector (High) SPI Receive Vector (Low) SCI Transmit Vector (High) SCI Transmit Vector (Low) SCI Receive Vector (High) SCI Receive Vector (Low) SCI Error Vector (High) SCI Error Vector (Low) Timebase Vector (High) Timebase Vector(Low) TIM OverflowVector (High) TIM Overflow Vector (Low) TIM Channel 3 Vector (High) TIM Channel 3 Vector (Low) TIM Channel 2 Vector (High) TIM Channel 2 Vector (Low) TIM Channel 1 Vector (High) TIM Channel 1 Vector (Low) TIM Channel 0 Vector (High) TIM Channel 0 Vector (Low) External IRQ2 Vector (High) External IRQ2 Vector (Low) IRQ1 Vector (High) IRQ1 Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low) AGREEMENT $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 NON-DISCLOSURE $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE Highest Priority $FFFF Figure 2-4. Vector Addresses in FLASH/ROM Advance Information 50 Memory Map MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map User FLASH/ROM 2.6 User FLASH/ROM The MCU has 48 Kbytes of FLASH (MC68HC908PT48) or mask programmable ROM (MC68HC08PT48). These addresses are user FLASH/ROM locations: • • $4000–$FDFF $FFDC–$FFFF; reserved for user-defined interrupt and reset vectors) 2.7 FLASH PROM The MCU has 2 Kbytes of FLASH separate from the main array. These addresses are FLASH locations: • $1800–$1FFF 2.8 Monitor ROM The 240 bytes at addresses $FE10–$FEFF are reserved ROM addresses that contain the instructions for the monitor functions. For more information, see Section 18. Monitor ROM (MON). MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Memory Map Advance Information 51 NON-DISCLOSURE AGREEMENT REQUIRED Memory Map REQUIRED NON-DISCLOSURE Advance Information 52 Memory Map AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 3. Central Processor Unit (CPU) 3.1 Contents 3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.4.4 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.5 3.6 3.7 3.8 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .60 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .60 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.2 Introduction This section describes the central processor unit (CPU8, Version A). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 53 NON-DISCLOSURE AGREEMENT REQUIRED Central Processor Unit (CPU) REQUIRED 3.3 Features Features of the CPU include: • • • • • • • • • • Full upward, object-code compatibility with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with X-register manipulation instructions 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes AGREEMENT 3.4 CPU Registers Figure 3-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) NON-DISCLOSURE CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWOS COMPLEMENT OVERFLOW FLAG Figure 3-1. CPU Registers Advance Information 54 Central Processor Unit (CPU) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) CPU Registers 3.4.1 Accumulator The accumulator (A) is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: 6 5 4 3 2 1 Bit 0 Figure 3-2. Accumulator (A) 3.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X Bit 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X = Indeterminate Figure 3-3. Index Register (H:X) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 55 NON-DISCLOSURE AGREEMENT Reset: Unaffected by reset REQUIRED Central Processor Unit (CPU) REQUIRED 3.4.3 Stack Pointer The stack pointer (SP) is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte (LSB) to $FF and does not affect the most significant byte (MSB). The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 0 AGREEMENT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 3-4. Stack Pointer (SP) NON-DISCLOSURE NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point to RAM locations only. Advance Information 56 Central Processor Unit (CPU) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) CPU Registers 3.4.4 Program Counter The program counter (PC) is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF Bit 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 3-5. Program Counter (PC) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 57 NON-DISCLOSURE AGREEMENT REQUIRED Central Processor Unit (CPU) REQUIRED 3.4.5 Condition Code Register The 8-bit condition code register (CCR) contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Bit 7 Read: 6 5 4 3 2 1 Bit 0 AGREEMENT V Write: Reset: X 1 1 1 1 H X I 1 N X Z X C X X = Indeterminate Figure 3-6. Condition Code Register (CCR) V — Overflow Flag The CPU sets the overflow flag when a twos complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADC (add with carry) or ADD (add without carry) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA (decimal adjust A) instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 NON-DISCLOSURE Advance Information 58 MC68HC(9)08PT48 — Rev. 2.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) CPU Registers I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N — Negative Flag Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 59 NON-DISCLOSURE The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result AGREEMENT To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. REQUIRED Central Processor Unit (CPU) REQUIRED C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 AGREEMENT 3.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture. 3.6 CPU During Break Interrupts If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. (See Section 19. Break Module.) The program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode). A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. NON-DISCLOSURE Advance Information 60 MC68HC(9)08PT48 — Rev. 2.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set Summary 3.7 Instruction Set Summary Table 3-1. Instruction Set Summary Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel Operation Description VH I NZC Add with Carry A ← (A) + (M) + (C) Add without Carry A ← (A) + (M) IMM DIR EXT ¤ ¤ – ¤ ¤ ¤ IX2 IX1 IX SP1 SP2 – – – – – – IMM – – – – – – IMM IMM DIR EXT 0 – – ¤ ¤ – IX2 IX1 IX SP1 SP2 DIR INH ¤ – – ¤ ¤ ¤ INH IX1 IX SP1 DIR INH ¤ – – ¤ ¤ ¤ INH IX1 IX SP1 – – – – – – REL DIR (b0) DIR (b1) DIR (b2) – – – – – – DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) – – – – – – REL – – – – – – REL – – – – – – REL AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 3 3 3 Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X SP ← (SP) + (16 « M) H:X ← (H:X) + (16 « M) Logical AND A ← (A) & (M) Arithmetic Shift Left (Same as LSL) C b7 b0 0 Arithmetic Shift Right b7 b0 C 37 dd 47 57 67 ff 77 9E67 ff 24 11 13 15 17 19 1B 1D 1F 25 27 90 rr dd dd dd dd dd dd dd dd rr rr rr Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 BCLR n, opr Clear Bit n in M Mn ← 0 BCS rel BEQ rel BGE opr Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) PC ← (PC) + 2 + rel ? (C) = 1 PC ← (PC) + 2 + rel ? (Z) = 1 PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 61 NON-DISCLOSURE 38 dd 48 58 68 ff 78 9E68 ff AGREEMENT IMM DIR EXT ¤ ¤ – ¤ ¤ ¤ IX2 IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff ff ee ff Cycles 2 3 4 4 3 2 4 5 Effect on CCR REQUIRED Operand Address Mode Central Processor Unit (CPU) REQUIRED Table 3-1. Instruction Set Summary (Continued) Opcode Source Form BGT opr BHCC rel BHCS rel BHI rel Operation Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low Description VH I NZC PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL PC ← (PC) + 2 + rel ? (H) = 0 PC ← (PC) + 2 + rel ? (H) = 1 PC ← (PC) + 2 + rel ? (C) | (Z) = 0 PC ← (PC) + 2 + rel ? (C) = 0 PC ← (PC) + 2 + rel ? IRQ = 1 PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL IMM DIR EXT 0 – – ¤ ¤ – IX2 IX1 IX SP1 SP2 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 AGREEMENT BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr Bit Test (A) & (M) Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL PC ← (PC) + 2 + rel ? (C) = 1 PC ← (PC) + 2 + rel ? (C) | (Z) = 1 PC ← (PC) + 2 + rel ? (N ⊕ V) =1 PC ← (PC) + 2 + rel ? (I) = 0 PC ← (PC) + 2 + rel ? (N) = 1 PC ← (PC) + 2 + rel ? (I) = 1 PC ← (PC) + 2 + rel ? (Z) = 0 PC ← (PC) + 2 + rel ? (N) = 0 PC ← (PC) + 2 + rel – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL – – – – – – REL DIR (b0) DIR (b1) DIR (b2) – – – – – ¤ DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) – – – – – – REL DIR (b0) DIR (b1) DIR (b2) – – – – – ¤ DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) NON-DISCLOSURE BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 BRN rel Branch Never PC ← (PC) + 2 BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 Advance Information 62 Central Processor Unit (CPU) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Cycles 3 3 Effect on CCR Operand Address Mode Central Processor Unit (CPU) Instruction Set Summary Table 3-1. Instruction Set Summary (Continued) Opcode Source Form Operation Description Cycles 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 Effect on CCR VH I NZC BSET n,opr Set Bit n in M Mn ← 1 DIR (b0) DIR (b1) DIR (b2) – – – – – – DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Clear Carry Bit Clear Interrupt Mask PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (X) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 2 + rel ? (A) – (M) = $00 PC ← (PC) + 4 + rel ? (A) – (M) = $00 C←0 I←0 M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 DIR IMM – – – – – – IMM IX1+ IX+ SP1 – – – – – 0 INH – – 0 – – – INH DIR INH INH 0 – – 0 1 – INH IX1 IX SP1 IMM DIR EXT ¤ – – ¤ ¤ ¤ IX2 IX1 IX SP1 SP2 DIR INH 0 – – ¤ ¤ 1 INH IX1 IX SP1 ¤ – – ¤ ¤ ¤ IMM DIR IMM DIR EXT ¤ – – ¤ ¤ ¤ IX2 IX1 IX SP1 SP2 U – – ¤ ¤ ¤ INH 31 41 51 61 71 9E61 98 9A dd rr ii rr ii rr ff rr rr ff rr Clear 3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff Compare A with M (A) – (M) Complement (One’s Complement) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – (M:M + 1) 33 dd 43 53 63 ff 73 9E63 ff 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 ii ii+1 dd ii dd hh ll ee ff ff ff ee ff Compare H:X with M Compare X with M (X) – (M) Decimal Adjust A (A)10 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 63 NON-DISCLOSURE AGREEMENT BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel – – – – – – REL AD rr REQUIRED Operand Address Mode Central Processor Unit (CPU) REQUIRED Table 3-1. Instruction Set Summary (Continued) Opcode Source Form Operation Description Cycles 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 Effect on CCR VH I NZC DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1 PC ← (PC) + 3 + rel ? (result) ≠ 0 DIR PC ← (PC) + 2 + rel ? (result) ≠ 0 INH PC ← (PC) + 2 + rel ? (result) ≠ 0 – – – – – – INH PC ← (PC) + 3 + rel ? (result) ≠ 0 IX1 PC ← (PC) + 2 + rel ? (result) ≠ 0 IX PC ← (PC) + 4 + rel ? (result) ≠ 0 SP1 M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1 A ← (H:A)/(X) H ← Remainder DIR INH ¤ – – ¤ ¤ – INH IX1 IX SP1 – – – – ¤ ¤ INH IMM DIR EXT 0 – – ¤ ¤ – IX2 IX1 IX SP1 SP2 DIR INH ¤ – – ¤ ¤ – INH IX1 IX SP1 DIR EXT – – – – – – IX2 IX1 IX DIR EXT – – – – – – IX2 IX1 IX IMM DIR EXT 0 – – ¤ ¤ – IX2 IX1 IX SP1 SP2 0 – – ¤ ¤ – IMM DIR IMM DIR EXT 0 – – ¤ ¤ – IX2 IX1 IX SP1 SP2 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr AGREEMENT Decrement 3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 Divide Exclusive OR M with A A ← (A ⊕ M) Increment M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1 3C dd 4C 5C 6C ff 7C 9E6C ff BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff NON-DISCLOSURE Jump PC ← Jump Address Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address Load A from M A ← (M) Load H:X from M H:X ← (M:M + 1) Load X from M X ← (M) Advance Information 64 Central Processor Unit (CPU) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Operand Address Mode Central Processor Unit (CPU) Instruction Set Summary Table 3-1. Instruction Set Summary (Continued) Opcode Source Form LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP Operation Description VH I NZC Logical Shift Left (Same as ASL) C b7 b0 0 DIR INH ¤ – – ¤ ¤ ¤ INH IX1 IX SP1 DIR INH ¤ – – 0 ¤ ¤ INH IX1 IX SP1 DD 0 – – ¤ ¤ – DIX+ IMD IX+D – 0 – – – 0 INH DIR INH ¤ – – ¤ ¤ ¤ INH IX1 IX SP1 – – – – – – INH – – – – – – INH IMM DIR EXT 0 – – ¤ ¤ – IX2 IX1 IX SP1 SP2 – – – – – – INH – – – – – – INH – – – – – – INH – – – – – – INH – – – – – – INH – – – – – – INH DIR INH ¤ – – ¤ ¤ ¤ INH IX1 IX SP1 DIR INH ¤ – – ¤ ¤ ¤ INH IX1 IX SP1 38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd Logical Shift Right 0 b7 b0 C Cycles 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3 2 3 4 4 3 2 4 5 2 2 2 2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 Effect on CCR Move (M)Destination ← (M)Source H:X ← (H:X) + 1 (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) None A ← (A[3:0]:A[7:4]) Unsigned multiply Negate (Two’s Complement) No Operation Nibble Swap A Inclusive OR A and M Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack Push (A); SP ← (SP) – 1 Push (H); SP ← (SP) – 1 Push (X); SP ← (SP) – 1 SP ← (SP + 1); Pull (A) SP ← (SP + 1); Pull (H) SP ← (SP + 1); Pull (X) Rotate Left through Carry C b7 b0 Rotate Right through Carry b7 b0 C MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 65 NON-DISCLOSURE A ← (A) | (M) AGREEMENT REQUIRED Operand Address Mode Central Processor Unit (CPU) REQUIRED Table 3-1. Instruction Set Summary (Continued) Opcode Source Form RSP Operation Reset Stack Pointer Description SP ← $FF SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL) VH I NZC – – – – – – INH 9C RTI Return from Interrupt ¤ ¤ ¤ ¤ ¤ ¤ INH 80 RTS Return from Subroutine – – – – – – INH IMM DIR EXT IX2 ¤ – – ¤ ¤ ¤ IX1 IX SP1 SP2 – – – – – 1 INH – – 1 – – – INH DIR EXT IX2 0 – – ¤ ¤ – IX1 IX SP1 SP2 0 – – ¤ ¤ – DIR – – 0 – – – INH DIR EXT IX2 0 – – ¤ ¤ – IX1 IX SP1 SP2 IMM DIR EXT ¤ – – ¤ ¤ ¤ IX2 IX1 IX SP1 SP2 81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff AGREEMENT SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr Subtract with Carry A ← (A) – (M) – (C) Set Carry Bit Set Interrupt Mask C←1 I←1 Store A in M M ← (A) Store H:X in M Enable IRQ Pin; Stop Oscillator (M:M + 1) ← (H:X) I ← 0; Stop Oscillator NON-DISCLOSURE STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Store X in M M ← (X) Subtract A ← (A) – (M) SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte CCR ← (A) X ← (A) A ← (CCR) – – 1 – – – INH 83 TAP TAX TPA Transfer A to CCR Transfer A to X Transfer CCR to A ¤ ¤ ¤ ¤ ¤ ¤ INH – – – – – – INH – – – – – – INH 84 97 85 Advance Information 66 Central Processor Unit (CPU) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Cycles 1 7 4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 9 2 1 1 Effect on CCR Operand Address Mode Central Processor Unit (CPU) Opcode Map Table 3-1. Instruction Set Summary (Continued) Opcode Source Form TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Operation Description VH I NZC Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 DIR INH 0 – – ¤ ¤ – INH IX1 IX SP1 – – – – – – INH – – – – – – INH – – – – – – INH 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94 Transfer SP to H:X Transfer X to A Transfer H:X to SP H:X ← (SP) + 1 A ← (X) (SP) ← (H:X) – 1 Cycles 3 1 1 3 2 4 2 1 2 Effect on CCR () –( ) # ← ? : ¤ — « 3.8 Opcode Map See Table 3-2. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Central Processor Unit (CPU) Advance Information 67 NON-DISCLOSURE Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & | ⊕ Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (twos complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected AGREEMENT REQUIRED Operand Address Mode NON-DISCLOSURE 68 Central Processor Unit (CPU) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information AGREEMENT REQUIRED Central Processor Unit (CPU) Table 3-2. Opcode Map Bit Manipulation DIR DIR MSB LSB Branch REL 2 3 BRA REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL 2 DIR 3 INH 4 Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 2 SP1 9E6 IX 7 Control INH INH 8 9 IMM A 2 SUB IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM 2 DIR B 3 SUB DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 JSR 2 DIR 3 LDX 2 DIR 3 STX 2 DIR 2 MSB LSB EXT C 4 SUB EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT 3 Register/Memory IX2 SP2 D 4 SUB IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 3 9ED 5 SUB SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 4 IX1 E 3 SUB IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 3 LDX 2 IX1 3 STX 2 IX1 2 SP1 9EE 4 SUB SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 3 IX F 2 SUB IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 2 LDX 1 IX 2 STX 1 IX 1 0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 0 1 2 3 4 5 6 7 8 9 A B C D E F 4 1 NEG NEGA DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH 2 5 3 NEG NEG SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX 3 7 3 RTI BGE INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH 1 2 4 BSR REL 2 LDX 2 IMM 2 AIX 2 IMM 5 LDX 4 SP2 5 STX 4 SP2 4 LDX 3 SP1 4 STX 3 SP1 INH Inherent REL Relative IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD Direct-Direct IMD Immediate-Direct IX+D Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment 0 High Byte of Opcode in Hexadecimal Low Byte of Opcode in Hexadecimal 0 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode Advance Information — MC68HC(9)08PT48 Section 4. Clock Generator Module (CGMB) 4.1 Contents 4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . .73 4.4.2.1 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . .75 4.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . . .75 4.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . . .80 4.4.3 Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . .80 4.4.4 CGMB External Connections . . . . . . . . . . . . . . . . . . . . . . .81 4.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 4.5.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . .82 4.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .82 4.5.3 External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . .83 4.5.4 PLL Analog Power Pin (VDDA1) . . . . . . . . . . . . . . . . . . . . . .83 4.5.5 PLL Analog Ground Pin (VSSA1) . . . . . . . . . . . . . . . . . . . . .83 4.5.6 Buffered Crystal Clock Output (CGMVOUT) . . . . . . . . . . . .83 4.5.7 CGMVSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.5.8 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . .84 4.5.9 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . .84 4.5.10 CGMB Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . .84 4.5.11 CGMB CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .84 4.6 CGMB Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . .90 4.6.3 PLL Multiplier Select Register High. . . . . . . . . . . . . . . . . . .92 4.6.4 PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . . .93 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 69 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED 4.6.5 4.6.6 4.7 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .94 PLL Reference Divider Select Register. . . . . . . . . . . . . . . .95 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 4.9 CGMB During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .97 4.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . .98 4.10.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . .98 4.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .99 4.10.3 Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . .100 4.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . .101 AGREEMENT 4.2 Introduction This section describes the clock generator module (CGM, version B). The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system integration module (SIM) derives the system clocks. CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a fully functional frequency generator designed for use with crystals or ceramic resonators. The PLL can generate a 4-MHz bus frequency without using a 16-MHz crystal. NON-DISCLOSURE Advance Information 70 MC68HC(9)08PT48 — Rev. 2.0 Clock Generator Module (CGMB) MOTOROLA Clock Generator Module (CGMB) Features 4.3 Features Features of the CGMB include: • • • • • • • • • Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low -requency crystal operation with low-power operation and high-output frequency resolution Programmable reference divider for even greater resolution Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation Automatic bandwidth control mode for low-jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition Fast stop recovery mode for exiting stop mode even without a stable crystal The CGMB consists of three major submodules: 1. Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK. 2. Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock CGMVCLK. 3. Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from CGMOUT. Figure 4-1 shows the structure of the CGM. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 71 NON-DISCLOSURE 4.4 Functional Description AGREEMENT Programmable prescaler for power-of-two increases in frequency REQUIRED Clock Generator Module (CGMB) REQUIRED CRYSTAL OSCILLATOR OSC2 CGMXCLK OSC1 BCS CLOCK SELECT CIRCUIT ÷2 CGMOUT SIMOSCEN CGMRDV REFERENCE DIVIDER CGMRCLK AGREEMENT RDS[3:0] VDDA1 PLLXFC VSSA1 VRS[7:0] VPR[1:0] PHASE DETECTOR LOOP FILTER VOLTAGE CONTROLLED OSCILLATOR PLL ANALOG NON-DISCLOSURE LOCK DETECTOR AUTOMATIC MODE CONTROL INTERRUPT CONTROL CGMINT LOCK MUL[11:0] AUTO ACQ PLLIE PRE[1:0] PLLF CGMVDV FREQUENCY DIVIDER FREQUENCY DIVIDER CGMVCLK Figure 4-1. CGMB Block Diagram Advance Information 72 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Functional Description 4.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock. CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float. 4.4.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 4.4.2.1 PLL Circuits The PLL consists of these circuits: • • • • • • • MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Voltage-controlled oscillator (VCO) Reference divider Frequency prescaler Modulo VCO frequency divider Phase detector Loop filter Lock detector Advance Information 73 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or (L × 2E)fNOM. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a programmable modulo reference divider, which divides fRCLK by a factor R. This feature allows frequency steps of higher resolution. The divider’s output is the final reference clock, CGMRDV, running at a frequency fRDV = fRCLK/R. The VCO’s output clock, CGMVCLK, running at a frequency fVCLK, is fed back through a programmable prescale divider and a programmable modulo divider. The prescaler divides the VCO clock by a power-of-two factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output is the VCO feedback clock, CGMVDV, running at a frequency, fVDV = fVCLK/(N × 2P). (See 4.4.2.4 Programming the PLL for more information.) The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 4.4.2.2 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. NON-DISCLOSURE Advance Information 74 AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 Clock Generator Module (CGMB) MOTOROLA Clock Generator Module (CGMB) Functional Description 4.4.2.2 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 4.6.2 PLL Bandwidth Control Register.) Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. (See 4.4.3 Base Clock Selector Circuit.) The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set. • 4.4.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 4.6.2 PLL Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. (See 4.4.3 Base Clock Selector Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. (See 4.7 Interrupts for information and precautions on using interrupts.) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 75 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED The following conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit (see 4.6.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the filter. (See 4.4.2.2 Acquisition and Tracking Modes.) The ACQ bit is set when the VCO frequency is within a certain tolerance, ∆TRK, and is cleared when the VCO frequency is out of a certain tolerance, ∆UNT. (See 4.10 Acquisition/Lock Time Specifications for more information.) The LOCK bit is a read-only indicator of the locked state of the PLL. The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆LOCK, and is cleared when the VCO frequency is out of a certain tolerance, ∆UNL. (See 4.10 Acquisition/Lock Time Specifications for more information.) CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. (See 4.6.1 PLL Control Register.) • AGREEMENT • • • NON-DISCLOSURE The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fBUSMAX and require fast startup. The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (see 4.10 Acquisition/Lock Time Specifications), after turning on the PLL by setting PLLON in the PLL control register (PCTL). Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). The LOCK bit is disabled. CPU interrupts from the CGMB are disabled. MC68HC(9)08PT48 — Rev. 2.0 Clock Generator Module (CGMB) MOTOROLA • • • • Advance Information 76 Clock Generator Module (CGMB) Functional Description 4.4.2.4 Programming the PLL The following procedure shows how to program the PLL. NOTE: The round function in the following equations means that the real number should be rounded to the nearest integer number. 1. Choose the desired bus frequency, fBUSDES. 2. Calculate the desired VCO frequency (four times the desired bus frequency). f VCLKDES = 4 × f BUSDES 3. Choose a practical PLL reference frequency, fRCLK. 4. Select the prescaler power-of-two multiplier, P. × f VCLKDES 2 log  ----------------------------------------------- f VCLKMAX   P = integer ------------------------------------------------------------- + 1 log ( 2 ) PMAX  f VCLKDES     f VCLKDES  R = round R MAX ×   --------------------------  – integer  --------------------------   P  2 P × f RCLK    2 × f RCLK Select a VCO frequency multiplier, N.  R × f VCLKDES N = round  ----------------------------------  2 P × f RCLK  MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 77 NON-DISCLOSURE 5. Select the reference divider based on the resolution desired. For maximum resolution, use this formula. However, higher degrees of resolution slow down the final reference frequency, which may cause acquisition time to increase and may affect the value of the external capacitor. For more information, see 4.10 Acquisition/Lock Time Specifications. AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED 6. For fastest acquisition time, reduce N/R until R is the smallest value possible. For example, if N = 6 and R = 4, N reduces to 3 and R reduces to 2. 7. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. f VCLK = N × f RCLK f VCLK = ( 2 × N ⁄ R ) × f RCLK f BUS = ( f VCLK ) ⁄ 4 8. Select the VCO’s power-of-two range multiplier E. Higher values of E should be used at higher frequencies. × f VCLK 2 log  -------------------------------------  f VRSMAX  E = integer --------------------------------------------------- + 1 log ( 2 ) EMAX P AGREEMENT NON-DISCLOSURE Select a VCO linear range multiplier, L, where fNOM = 38.4 KHz  f VCLK  L = round  -------------------------  2 E × f NOM 9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency fVRS. fVRS = (L × 2E)fNOM 10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper operation, fVCLK must be within the application’s tolerance of fVCLKDES, and fVRS must be as close as possible to fVCLK. NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. Advance Information 78 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Functional Description Table 4-1 provides a numeric example with numbers in hexadecimal notation. Table 4-1. Numeric Example Bus Frequency 307,200 Hz 614,400 Hz 652,800 Hz 691,200 Hz 729,600 Hz 768,000 Hz 806,400 Hz 998,400 Hz E 1 1 2 2 2 2 2 2 P 1 1 2 2 2 2 2 2 N 10 20 11 12 13 14 15 1a L 10 20 11 12 13 14 15 1a R 1 1 1 1 1 1 1 1 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 79 NON-DISCLOSURE AGREEMENT 11. Program the PLL registers accordingly: a. In the PRE bits of the PLL Control Register, program the binary equivalent of P. b. In the VPR bits of the PLL Control Register, program the binary equivalent of E. c. In the PLL Multiplier Select Register Low and the PLL Multiplier Select Register High, program the binary equivalent of N. d. In the PLL VCO Range Select Register, program the binary coded equivalent of L. e. In the PLL Reference Divider Select Register, program the binary coded equivalent of R. REQUIRED Clock Generator Module (CGMB) REQUIRED 4.4.2.5 Special Programming Exceptions The programming method described in 4.4.2.4 Programming the PLL does not account for three possible exceptions. A value of zero for R, N, or L is meaningless when used in the equations given. To account for these exceptions: • A 0 value for R or N is interpreted exactly the same as a value of 1. at the minimum frequency and the VCO range power-of-two bits.This mode is currently disabled in MT2. A 0 value for L disables the PLL and prevents its selection as the source for the base clock. (See 4.4.3 Base Clock Selector Circuit.) AGREEMENT • 4.4.3 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. NON-DISCLOSURE Advance Information 80 MC68HC(9)08PT48 — Rev. 2.0 Clock Generator Module (CGMB) MOTOROLA Clock Generator Module (CGMB) Functional Description 4.4.4 CGMB External Connections In its typical configuration, the CGMB requires seven external components. Five of these are for the crystal oscillator and two are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-2. Figure 4-2 shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: • • • • • Crystal, X1 Fixed capacitor, C1 Tuning capacitor, C2; can also be a fixed capacitor Feedback resistor, RB Series resistor, RS; optional Figure 4-2 also shows the external components for the PLL: • • Bypass capacitor, CBYP Filter capacitor, CF Routing should be done with great care to minimize signal cross talk and noise. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 81 NON-DISCLOSURE The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED SIMOSCEN CGMXCLK OSC1 OSC2 VSS CGMXFC CF VDDA1 VDD CBYP RS* RB X1 AGREEMENT C1 C2 *Rs can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. Figure 4-2. CGMB External Connections 4.5 I/O Signals The following paragraphs describe the CGMB I/O (input/output) signals. The CGM may also have up to four additional inputs, if enabled in MT2. NON-DISCLOSURE 4.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. Advance Information 82 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) I/O Signals 4.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin. NOTE: To prevent noise problems, CF should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the CF connection. VDDA1 is a power pin used by the analog portions of the PLL. Connect the VDDA1 pin to the same voltage potential as the VDD pin. NOTE: Route VDDA1 carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 4.5.5 PLL Analog Ground Pin (VSSA1) VSSA1 is a ground pin used by the analog portions of the PLL. Connect the VSSA1 pin to the same voltage potential as the VSS pin. NOTE: 4.5.6 Buffered Crystal Clock Output (CGMVOUT) CGMVOUT buffers the OSC1 clock for external use. 4.5.7 CGMVSEL CGMVSEL must be tied low or floated. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 83 NON-DISCLOSURE Route VSSA1 carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. AGREEMENT 4.5.4 PLL Analog Power Pin (VDD1) REQUIRED Clock Generator Module (CGMB) REQUIRED 4.5.8 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. 4.5.9 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup. AGREEMENT 4.5.10 CGMB Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGMB. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. NON-DISCLOSURE 4.5.11 CGMB CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. Advance Information 84 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) CGMB Registers 4.6 CGMB Registers The following registers control and monitor operation of the CGMB: • • • • • • PLL control register (PCTL) See 4.6.1 PLL Control Register. PLL bandwidth control register (PBWC) See 4.6.2 PLL Bandwidth Control Register. PLL multiplier select register high (PMSH) See 4.6.3 PLL Multiplier Select Register High. PLL multiplier select register low (PMSL) See 4.6.4 PLL Multiplier Select Register Low. PLL VCO range select register See 4.6.5 PLL VCO Range Select Register. PLL reference divider select register (PRDS) See 4.6.6 PLL Reference Divider Select Register. Figure 4-3 is a summary of the CGMB registers. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 85 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED Addr. Register Name Bit 7 6 PLLF 5 PLLON 4 BCS 0 0 3 PRE1 1 0 2 PRE0 1 0 1 VPR1 1 0 Bit 0 VPR0 1 COE $0046 Read: PLLIE PLL Control Register Write: (PCTL) Reset: 0 Read: AUTO PLL Bandwidth Control Write: Register (PBWC) Reset: 0 Read: PLL Multiplier Select Register Write: High (PMSH) Reset: 0 0 LOCK 1 ACQ $0047 0 0 0 0 0 0 0 MUL11 0 MUL10 0 MUL2 0 VRS2 0 RDS2 0 0 MUL9 0 MUL1 0 VRS1 0 RDS1 0 0 MUL8 0 MUL0 0 VRS0 0 RDS0 1 AGREEMENT $0048 0 0 MUL6 0 VRS6 1 0 0 MUL5 0 VRS5 0 0 0 MUL4 0 VRS4 0 0 0 MUL3 0 VRS3 0 RDS3 $0049 Read: MUL7 PLL Multiplier Select Register Write: Low (PMSL) Reset: 0 Read: VRS7 PLL VCO Range Select Write: Register (PVRS) Reset: 0 Read: PLL Reference Divider Select Write: Register (PRDS) Reset: 0 $004A NON-DISCLOSURE $004B 0 0 0 0 0 = Unimplemented Notes: 1. When AUTO = 0, PLLIE is forced clear and is read only. 2. When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read only. 5. When PLLON = 1, the PLL programming register is read only. 6. When BCS = 1, PLLON is forced set and is read only. Figure 4-3. CGMB I/O Register Summary Advance Information 86 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) CGMB Registers 4.6.1 PLL Control Register The PLL control register contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0046 Bit 7 Read: PLLIE Write: Reset: 0 0 1 0 1 1 1 1 6 PLLF 5 PLLON 4 BCS 3 PRE1 2 PRE0 1 VPR1 Bit 0 VPR0 = Unimplemented Figure 4-4. PLL Control Register (PCTL) PLLIE — PLL Interrupt Enable Bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF — PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 87 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 4.4.3 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS — Base Clock Select Bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See 4.4.3 Base Clock Selector Circuit.) Reset clear the BCS bit. 1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT AGREEMENT NOTE: NON-DISCLOSURE PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 4.4.3 Base Clock Selector Circuit.) PRE1 and PRE0 — Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier P. (See 4.4.2.1 PLL Circuits and 4.4.2.4 Programming the PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set. Reset clears these bits. (See Table 4-2.) Advance Information 88 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) CGMB Registers Table 4-2. PRE1 and PRE0 Programming PRE1 and PRE0 00 01 10 11 P 0 1 2 3 Prescaler Multiplier 1 2 4 8 These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L (See 4.4.2.1 PLL Circuits, 4.4.2.4 Programming the PLL, and 4.6.5 PLL VCO Range Select Register.) controls the hardware center-of-range frequency fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears these bits. (See Table 4-3.) Table 4-3. VPR1 and VPR0 Programming VPR1 and VPR0 00 01 10 11 E 0 1 2 3 VCO Power-of-Two Range Multiplier 1 2 4 8 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 89 NON-DISCLOSURE AGREEMENT VPR1 and VPR0 — VCO Power-of-Two Range Select Bits REQUIRED Clock Generator Module (CGMB) REQUIRED 4.6.2 PLL Bandwidth Control Register The PLL bandwidth control register: • • • • Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking mode $0047 Bit 7 Read: AUTO Write: Reset: 0 0 0 0 0 0 0 0 6 LOCK ACQ 5 4 0 3 0 2 0 1 0 COE Bit 0 AGREEMENT Address: = Unimplemented Figure 4-5. PLL Bandwidth Control Register (PBWC) AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. The write function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked Advance Information 90 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA NON-DISCLOSURE Clock Generator Module (CGMB) CGMB Registers ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode COE— Clock Out Enable When the COE bit is cleared, a buffered version of OSC1 is present on the CGMVOUT pin. When the COE bit is set, the CGMVOUT pin will be driven low. 1 = CGMVOUT driven low 0 = CGMVOUT is buffered OSC1 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 91 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED 4.6.3 PLL Multiplier Select Register High The PLL multiplier select register high contains the programming information for the high byte of the modulo feedback divider. Address: $0048 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 MUL11 MUL10 MUL9 MUL8 3 2 1 Bit 0 AGREEMENT = Unimplemented Figure 4-6. PLL Multiplier Select Register High (PMSH) MUL[11:8] — Multiplier Select Bits These read/write bits control the high byte of the modulo feedback divider that selects the VCO frequency multiplier N. (See 4.4.2.1 PLL Circuits and 4.4.2.4 Programming the PLL.) A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64. NON-DISCLOSURE NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). Advance Information 92 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) CGMB Registers 4.6.4 PLL Multiplier Select Register Low The PLL multiplier select register low contains the programming information for the low byte of the modulo feedback divider. Address: $0049 Bit 7 Read: MUL7 Write: Reset: 0 0 0 0 0 0 0 0 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 6 5 4 3 2 1 Bit 0 Figure 4-7. PLL Multiplier Select Register Low (PMSL) MUL[7:0] — Multiplier Select Bits These read/write bits control the low byte of the modulo feedback divider that selects the VCO frequency multiplier, N. (See 4.4.2.1 PLL Circuits and 4.4.2.4 Programming the PLL.) MUL[7:0] cannot be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to $40 for a default multiply value of 64. NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 93 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED 4.6.5 PLL VCO Range Select Register The PLL VCO range select register contains the programming information required for the hardware configuration of the VCO. Address: $004A Bit 7 Read: VRS7 VRS6 1 VRS5 0 VRS4 0 VRS3 0 VRS2 0 VRS1 0 VRS0 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 AGREEMENT Figure 4-8. PLL VCO Range Select Register (PVRS) VRS[7:0] — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (see 4.4.2.1 PLL Circuits, 4.4.2.4 Programming the PLL, and 4.6.1 PLL Control Register), controls the hardware center-of-range frequency, fVRS. VRS[7:0] cannot be written when the PLLON bit in the PCTL is set. (See 4.4.2.5 Special Programming Exceptions. ) A value of $00 in the VCO Range Select Register disables the PLL and clears the BCS bit in the PLL Control Register. (See 4.4.3 Base Clock Selector Circuit and 4.4.2.5 Special Programming Exceptions.) Reset initializes the register to $40 for a default range multiply value of 64. NON-DISCLOSURE NOTE: The VCO range select bits have built in protection such that they cannot be written when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock. Advance Information 94 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) CGMB Registers 4.6.6 PLL Reference Divider Select Register The PLL reference divider select register contains the programming information for the modulo reference divider. Address: $004B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 1 0 6 0 5 0 4 0 RDS3 RDS2 RDS1 RDS0 3 2 1 Bit 0 = Unimplemented Figure 4-9. PLL Reference Divider Select Register (PRDS) RDS[3:0] — Reference Divider Select Bits These read/write bits control the modulo reference divider that selects the reference division factor R. (See 4.4.2.1 PLL Circuits and 4.4.2.4 Programming the PLL.) RDS[7:0] cannot be written when the PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference divider the same as a value of $01. (See 4.4.2.5 Special Programming Exceptions.) Reset initializes the register to $01 for a default divide value of 1. NOTE: The reference divider select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PRDS[7:4] — Unimplemented Bits These bits have no function and always read as logic 0s. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 95 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED 4.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt and appropriate precautions should be taken. If the application is not frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. AGREEMENT NOTE: NON-DISCLOSURE Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. 4.8 Special Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby mode. 4.8.1 Wait Mode The WAIT instruction does not affect the CGMB. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. Advance Information 96 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) CGMB During Break Interrupts 4.8.2 Stop Mode The STOP instruction disables the CGMB and holds low all CGMB outputs (CGMXCLK, CGMOUT, and CGMINT). If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear. 4.9 CGMB During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 7.8.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. If this mode is desired during reset, the reset conditions of BCS and PLLON must be set. If this mode is desired for use in applications where no crystal is used, the BCS and PLLON bits must not be clearable. During a large frequency change, the software must allow a stabilization time. The CGMXCLK signal will always reflect the crystal clock, so the value of CGMXCLK upon removing the crystal will reflect the value of the OSC1 pin. If OSC1 is floating, the module could consume significant power and the output of the CGMXCLK signal would be indeterminate. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 97 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED 4.10 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 4.10.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the 100-kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are: • Acquisition time, tACQ, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆TRK. MC68HC(9)08PT48 — Rev. 2.0 Clock Generator Module (CGMB) MOTOROLA NON-DISCLOSURE Advance Information 98 AGREEMENT Clock Generator Module (CGMB) Acquisition/Lock Time Specifications Acquisition time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100 percent. In automatic bandwidth control mode (see 4.4.2.3 Manual and Automatic PLL Bandwidth Modes), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register (PBWC). • Lock time, tLOCK, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, ∆LOCK. Lock time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100 percent. In automatic bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). (See 4.4.2.3 Manual and Automatic PLL Bandwidth Modes.) Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 4.10.2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency fXCLK and the R value programmed in the reference divider. (See 4.4.2.1 PLL Circuits, 4.4.2.4 Programming the PLL, and 4.6.6 PLL Reference Divider Select Register). Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 99 NON-DISCLOSURE AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED given frequency error (thus change in charge) is proportional to the capacitor size. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. (See 4.10.3 Choosing a Filter Capacitor.) Also important is the operating voltage potential applied to VDDA1. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. NON-DISCLOSURE AGREEMENT 4.10.3 Choosing a Filter Capacitor As described in 4.10.2 Parametric Influences on Reaction Time, the external filter capacitor, CF, is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. For proper operation, the external filter capacitor must be chosen according to this equation: V DDA C F = C FACT  ------------   f RDV  For acceptable values of CFACT, see 4.10 Acquisition/Lock Time Specifications. For the value of VDDA1, choose the voltage potential at which the MCU is operating. If the power supply is variable, choose a value near the middle of the range of possible supply values. Advance Information 100 Clock Generator Module (CGMB) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Acquisition/Lock Time Specifications This equation does not always yield a commonly available capacitor size, so round to the nearest available size. If the value is between two different sizes, choose the higher value for better stability. Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become unstable. Also, always choose a capacitor with a tight tolerance (±20 percent or better) and low dissipation. 4.10.4 Reaction Time Calculation The actual acquisition and lock times can be calculated using the equations in this section. These equations yield nominal values under the following conditions: • • • • Correct selection of filter capacitor, CF (See 4.10.3 Choosing a Filter Capacitor.) Room temperature operation Negligible external leakage on CGMXFC Negligible noise V DDA 8 t ACQ =  -------------   -------------  -   f RDV K ACQ V DDA 4 t AL =  -------------  ------------   f RDV-  K TRK t LOCK = t ACQ + t AL NOTE:T he inverse proportionality between the lock time and the reference frequency. In automatic bandwidth control mode the acquisition and lock times are quantized into units based on the reference frequency. (See 4.4.2.3 Manual and Automatic PLL Bandwidth Modes.) A certain number of MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Clock Generator Module (CGMB) Advance Information 101 NON-DISCLOSURE The K factor in the equations is derived from internal PLL parameters. KACQ is the K factor when the PLL is configured in acquisition mode, and KTRK is the K factor when the PLL is configured in tracking mode. (See 4.4.2.2 Acquisition and Tracking Modes.) AGREEMENT REQUIRED Clock Generator Module (CGMB) REQUIRED clock cycles, nACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆TRK, before exiting acquisition mode. A certain number of clock cycles, nTRK, is required to ascertain that the PLL is within the lock mode entry tolerance, ∆LOCK. Therefore, the acquisition time, tACQ, is an integer multiple of nACQ/fRDV, and the acquisition to lock time, tAL, is an integer multiple of nTRK/fRDV. Also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than tLOCK as calculated earlier. In manual mode, it is usually necessary to wait considerably longer than tLOCK before selecting the PLL clock (see 4.4.3 Base Clock Selector Circuit) because the factors described in 4.10.2 Parametric Influences on Reaction Time may slow the lock time considerably. NON-DISCLOSURE Advance Information 102 Clock Generator Module (CGMB) AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 5. Computer Operating Properly (COP) Module 5.1 Contents 5.2 5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 5.4 I/O Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.1 CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.6 Reset Vetor Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.4.7 COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5.5 5.6 5.7 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 5.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 5.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .107 5.2 Introduction This section describes the computer operating properly module (COP, version B10), a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Computer Operating Properly (COP) Module Advance Information 103 NON-DISCLOSURE AGREEMENT REQUIRED Computer Operating Properly (COP) Module REQUIRED 5.3 Functional Description SIM CGMXCLK 12-BIT SIM COUNTER SIM RESET CIRCUIT SIM RESET STATUS REGISTER STOP INSTRUCTION INTERNAL RESET RESET VECTOR FETCH COPCTL WRITE AGREEMENT COP COPEN (FROM SIM) COPD (FROM MOR) RESET COPCTL WRITE 6-BIT COP COUNTER Figure 5-1. COP Block Diagram The COP counter uses a free-running 6-bit counter preceded by the 13bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218–24 CGMXCLK cycles. With a 38.4-kHz crystal, the COP timeout period is 6.83 seconds. Writing any value to location $FFFF before overflow occurs clears the COP counter and prevents reset. A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status register (SRSR). Clear the COP immediately before entering or after exiting stop mode to assure a full COP timeout period after entering or exiting stop mode. A CPU interrupt routine or a DMA service routine can be used to clear the COP. NON-DISCLOSURE NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. MC68HC(9)08PT48 — Rev. 2.0 Computer Operating Properly (COP) Module MOTOROLA Advance Information 104 Computer Operating Properly (COP) Module I/O Signals 5.4 I/O Signals This section describes the signals shown in Figure 5-1. 5.4.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency. 5.4.2 STOP Instruction The STOP instruction clears the SIM counter. 5.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) clears the COP counter and clears bits 12 through 4 of the SIM counter. Reading the COP control register returns the reset vector. 5.4.4 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 CGMXCLK cycles after power-up. 5.4.5 Internal Reset An internal reset clears the SIM counter and the COP counter. 5.4.6 Reset Vetor Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Computer Operating Properly (COP) Module Advance Information 105 NON-DISCLOSURE AGREEMENT REQUIRED Computer Operating Properly (COP) Module REQUIRED 5.4.7 COPD The COPD (COP disable) signal refects the state of the COP disable bit (COPD) in the mask option register (MOR). 5.5 COP Control Register The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 AGREEMENT Low Byte of Reset Vector Clear COP Counter Unaffected by reset Figure 5-2. COP Control Register (COPCTL) NON-DISCLOSURE 5.6 Interrupts The COP does not generate CPU interrupt requests or DMA service requests. 5.7 Monitor Mode The COP is disabled in monitor mode when VDD +VHI is present on the IRQ1/VPP pin or on the RST pin. 5.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. Advance Information 106 Computer Operating Properly (COP) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Computer Operating Properly (COP) Module COP Module During Break Interrupts 5.8.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine or a DMA service routine. 5.8.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the mask option register (MOR) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by programming the STOP bits to logic 0. 5.9 COP Module During Break Interrupts The COP is disabled during a break interrupt when VDD = VHI is present on the RST pin. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Computer Operating Properly (COP) Module Advance Information 107 NON-DISCLOSURE AGREEMENT REQUIRED Computer Operating Properly (COP) Module REQUIRED NON-DISCLOSURE Advance Information 108 Computer Operating Properly (COP) Module AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 6. Keyboard Interrupt (KBI) Module 6.1 Contents 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.7 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.8.1 Keyboard Status and Control Register . . . . . . . . . . . . . . .114 6.8.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . .116 6.2 Introduction The keyboard interrupt (KBI) module provides eight independently maskable external interrupt pins. 6.3 Features The KBI features include: • • • • • MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Keyboard Interrupt (KBI) Module Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Hysteresis buffers Programmable edge-only or edge- and level-interrupt sensitivity Automatic interrupt acknowledge Exit from low-power modes Advance Information 109 NON-DISCLOSURE AGREEMENT REQUIRED Keyboard Interrupt (KBI) Module REQUIRED INTERNAL BUS KBD0 VDD TO PULLUP ENABLE KB0IE . . . D CLR Q ACKK RESET VECTOR FETCH DECODER KEYF SYNCHRONIZER KEYBOARD INTERRUPT REQUEST CK AGREEMENT KBD7 KEYBOARD INTERRUPT FF IMASKK TO PULLUP ENABLE KB7IE MODEK Figure 6-1. KBI Block Diagram Addr. Register Name Read: Keyboard Status and Control Write: Register (KBSCR) Reset: Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 1 Bit 0 IMASKK MODEK ACKK 0 0 KBIE6 0 0 KBIE5 0 0 KBIE4 0 0 KBIE3 0 0 KBIE2 0 X = Indeterminate 0 KBIE1 0 0 KBIE0 0 $0033 NON-DISCLOSURE $0034 Read: KBIE7 Keyboard Interrupt Enable Write: Register (KBICR) Reset: 0 = Unimplemented U = Undetermined Figure 6-2. KBI Register Summary Advance Information 110 Keyboard Interrupt (KBI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Keyboard Interrupt (KBI) Module Functional Description 6.4 Functional Description Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port F pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt request is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering sensitivity of the keyboard interrupt pins. • If the keyboard interrupt pins are edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt pins are falling edge- and low levelsensitive, an interrupt request is present as long as any keyboard pin is low. • • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software can generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit in an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFDC and $FFDD. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Keyboard Interrupt (KBI) Module Advance Information 111 NON-DISCLOSURE If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: AGREEMENT REQUIRED Keyboard Interrupt (KBI) Module REQUIRED • Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt request remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. AGREEMENT NOTE: NON-DISCLOSURE Setting a keyboard interrupt enable bit (KBxIE) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 6.5 Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. Advance Information 112 Keyboard Interrupt (KBI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Keyboard Interrupt (KBI) Module Low-Power Modes 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRF bits. 2. Write logic 1s to the appropriate port F data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 6.6.1 Wait Mode The keyboard interrupt module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 6.6.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Keyboard Interrupt (KBI) Module Advance Information 113 NON-DISCLOSURE AGREEMENT REQUIRED Keyboard Interrupt (KBI) Module REQUIRED 6.7 KBI During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 7.8.3 SIM Break Flag Control Register.) To allow software to clear the KEYF bit during a break interrupt, write a logic 1 to the BCFE bit. If KEYF is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the KEYF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0, writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. (See 6.8.1 Keyboard Status and Control Register.) AGREEMENT 6.8 I/O Registers These control and monitor operation of the keyboard interrupt module: • • Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER) NON-DISCLOSURE 6.8.1 Keyboard Status and Control Register The keyboard status and control register: • • • • Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity Advance Information 114 Keyboard Interrupt (KBI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Keyboard Interrupt (KBI) Module I/O Registers Address: $0033 Bit 7 6 0 5 0 4 0 3 KEYF 2 0 IMASKK MODEK 0 ACKK 0 0 0 0 0 0 0 1 Bit 0 Read: Write: Reset: 0 = Unimplemented Figure 6-3. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used These read-only bits always read as logic 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Keyboard Interrupt (KBI) Module Advance Information 115 NON-DISCLOSURE AGREEMENT REQUIRED Keyboard Interrupt (KBI) Module REQUIRED 6.8.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port F pin to operate as a keyboard interrupt pin. Address: $0034 Bit 7 Read: KBIE7 KBIE6 0 KBIE5 0 KBIE4 0 KBIE3 0 KBIE2 0 KBIE1 0 KBIE0 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 AGREEMENT Figure 6-4. Keyboard Interrupt Enable Register (KBIER) KBIE7–KBIE0 — Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PFx pin enabled as keyboard interrupt pin 0 = PFx pin not enabled as keyboard interrupt pin NON-DISCLOSURE Advance Information 116 Keyboard Interrupt (KBI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 7. System Integration Module (SIM) 7.1 Contents 7.1 7.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .121 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 7.3.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . .121 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . .122 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .122 7.4.1 External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .124 7.4.2.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .126 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .126 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .126 7.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .127 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .127 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . .128 7.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . .128 7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 7.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 7.6.3 Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 7.6.4 Status Flag Protection in Break Mode. . . . . . . . . . . . . . . .132 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 117 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 7.8.1 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . .136 7.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .138 7.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . .139 7.2 Introduction This section describes the system integration module (SIM24, version E), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: • • Controlling mode selection Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control Master reset control, including power-on reset (POR) and COP timeout Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation CPU clock control with DMA transfer and low-power modes Slow memory read/write timing CPU enable/disable timing Modular architecture expandable to 128 interrupt sources AGREEMENT NON-DISCLOSURE • • • • • • NOTE: All references to LVI and DMA operation in this section should be ignored. Table 7-1 shows the internal signal names used in this section. Advance Information 118 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Introduction MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS RESET PIN LOGIC POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET INTERRUPT CONTROL AND PRIORITY DECODE INTERRUPT SOURCES CPU INTERFACE Figure 7-1. SIM Block Diagram MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 119 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED Addr. Register Name Read: SIM Break Status Register Write: (SBSR) Reset: Bit 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW Bit 0 R $FE00 Note 1 0 Note 1. Writing a logic 0 clears SBSW. Read: $FE01 SIM Reset Status Register Write: (SRSR) Reset: Read: $FE03 BCFE SIM Break Flag Control Write: Register (SBFCR) Reset: 0 R R R R R R R R POR PIN COP ILOP ILAD 0 LVI 0 AGREEMENT 1 0 0 0 0 0 0 0 = Reserved = Unimplemented Figure 7-2. SIM I/O Register Summary Table 7-1. Signal Name Conventions NON-DISCLOSURE Signal Name CGMXCLK CGMVCLK CGMOUT IAB IDB PORRST IRST R/W Description Buffered version of OSC1 from clock generator module (CGM) PLL output PLL-based or OSC1-based clock output from CGM module (bus clock = CGMOUT divided by two) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal Advance Information 120 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) SIM Bus Clock Control and Generation 7.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can come from either an external oscillator or from the on-chip PLL. For additional information, refer to Section 4. Clock Generator Module (CGMB). OSC1 CLOCK SELECT CIRCUIT SIM COUNTER CGMVCLK ÷2 A CGMOUT B S* *When S = 1, CGMOUT = B ÷2 BUS CLOCK GENERATORS PLL BCS PTC3 MONITOR MODE USER MODE SIM CGM Figure 7-3. CGM Clock Signals 7.3.1 Bus Timing In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. For additional information, refer to Section 4. Clock Generator Module (CGMB). 7.3.2 Clock Startup from POR or LVI Reset When the power-on reset (POR) module or the low-voltage inhibit (LVI) module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 121 NON-DISCLOSURE AGREEMENT CGMXCLK REQUIRED System Integration Module (SIM) REQUIRED 7.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode (by an interrupt, break, or reset), the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 7.7.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. AGREEMENT 7.4 Reset and System Initialization The MCU has the following reset sources: • • • • Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address NON-DISCLOSURE • • All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 7.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 7.8 SIM Registers.) Advance Information 122 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Reset and System Initialization 7.4.1 External Pin Reset Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 7-2 for details. Figure 7-4 shows the relative timing. Table 7-2. PIN Bit Set Timing Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3) CGMOUT RST IAB PC VECT H VECT L Figure 7-4. External Reset Timing MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 123 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED 7.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. (See Figure 7-5.) An internal reset can be caused by an illegal address, illegal opcode, COP timeout, module reset, LVI, or POR. (See Figure 7-6.) NOTE: AGREEMENT For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 7-5. IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 7-5. Internal Reset Timing NON-DISCLOSURE The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET Figure 7-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. Advance Information 124 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Reset and System Initialization 7.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: • • • • • • A POR pulse is generated. The internal reset signal is asserted. The SIM enables CGMOUT. Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. PORRST 4096 CYCLES CGMXCLK 32 CYCLES 32 CYCLES CGMOUT RST IAB $FFFE $FFFF Figure 7-7. POR Recovery MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 125 NON-DISCLOSURE OSC1 AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED 7.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 4 of the SIM counter. The SIM counter output, which occurs at least every 213 – 24 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ1/VPP pin is held at VDD + VHI while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ1/VPP pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VDD + VHI on the RST pin disables the COP module. 7.4.2.3 Illegal Opcode Reset NON-DISCLOSURE AGREEMENT The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 7.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. Advance Information 126 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) SIM Counter 7.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set and the external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 7.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. Reset recovery control logic and real time interrupt models also use taps from the SIM counter. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK. 7.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 127 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED 7.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared (grounded). AGREEMENT 7.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 7.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 7.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.) 7.6 Exception Control Normal, sequential program execution can be changed in three different ways: • Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts NON-DISCLOSURE • • Advance Information 128 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Exception Control 7.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 7-8 shows interrupt entry timing. Figure 7-9 shows interrupt recovery timing. Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt may take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See Figure 7-10.) MODULE INTERRUPT I BIT IAB DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR IDB DUMMY PC – 1[7:0] PC–1[15:8] X A CCR V DATA H V DATA L OPCODE R/W Figure 7-8. Interrupt Entry MODULE INTERRUPT I BIT IAB SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1 IDB CCR A X PC – 1[7:0] PC–1[15:8] OPCODE OPERAND R/W Figure 7-9. Interrupt Recovery MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 129 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED FROM RESET BREAK INTERRUPT? I BIT SET? NO YES YES AGREEMENT I BIT SET? NO IRQ0 INTERRUPT? NO YES IRQ1 INTERRUPT? NO YES STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR AS MANY INTERRUPTS AS EXIST ON CHIP NON-DISCLOSURE FETCH NEXT INSTRUCTION SWI INSTRUCTION? NO YES RTI INSTRUCTION? NO YES UNSTACK CPU REGISTERS EXECUTE INSTRUCTION Figure 7-10. Interrupt Processing Advance Information 130 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Exception Control 7.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. CLI LDA #$FF BACKGROUND ROUTINE INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 7-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine Advance Information System Integration Module (SIM) 131 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 7.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. AGREEMENT NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 7.6.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 7.6.3 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See Section 19. Break Module.) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. NON-DISCLOSURE 7.6.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Advance Information 132 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Low-Power Modes Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 7.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in the subsections that follow. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 7.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 7-12 shows the timing for wait mode entry. IAB WAIT ADDR WAIT ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 7-12. Wait Mode Entry Timing A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 133 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 7-13 and Figure 7-14 show the timing for WAIT recovery. AGREEMENT IAB $6E0B $6E0C $00FF $00FE $00FD $00FC IDB $A6 $A6 $A6 $01 $0B $6E EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 7-13. Wait Recovery from Interrupt or Break NON-DISCLOSURE 32 Cycles IAB $6E0B 32 Cycles RSTVCTH RSTVCTL IDB $A6 $A6 $A6 RST CGMXCLK Figure 7-14. Wait Recovery from Internal Reset Advance Information 134 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Low-Power Modes 7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register (MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-15 shows stop mode entry timing and Figure 7-16 shows stop mode recovery timing from interrupt or break. CPUSTOP IAB STOP ADDR STOP ADDR + 1 SAME SAME IDB PREVIOUS DATA NEXT OPCODE SAME SAME R/W Note: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 7-15. Stop Mode Entry Timing MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 135 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED STOP RECOVERY PERIOD CGMXCLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 7-16. Stop Mode Recovery from Interrupt or Break AGREEMENT 7.8 SIM Registers The SIM has three memory mapped registers. Table 7-3 shows the mapping of these registers. Table 7-3. SIM Registers Address $FE00 $FE01 $FE03 Register SBSR SRSR SBFCR Access Mode User User User NON-DISCLOSURE 7.8.1 SIM Break Status Register The SIM break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: $FE00 Bit 7 Read: R Write: Reset: R = Reserved Note 1. Writing a logic 0 clears SBSW. R R R R R Note 1 0 6 5 4 3 2 1 SBSW R Bit 0 Figure 7-17. SIM Break Status Register (SBSR) Advance Information 136 System Integration Module (SIM) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) SIM Registers SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing 0 to the SBSW bit clears it. ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE LOBYTE ; EQU EQU 5 6 If not SBSW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI SBSW,SBSR, RETURN ; See if wait mode or stop mode was exited ; by break. LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; If RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 137 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED 7.8.2 SIM Reset Status Register This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: $FE01 Bit 7 Read: POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 0 1 LVI Bit 0 0 AGREEMENT Write: Reset: 1 0 0 0 0 0 0 0 = Unimplemented Figure 7-18. SIM Reset Status Register (SRSR) POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MOD — Module Reset Bit 1 = Last reset caused by one of the internal modules 0 = POR or read of SRSR NON-DISCLOSURE Advance Information 138 MC68HC(9)08PT48 — Rev. 2.0 System Integration Module (SIM) MOTOROLA System Integration Module (SIM) SIM Registers LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR 7.8.3 SIM Break Flag Control Register The SIM break control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 Read: BCFE Write: Reset:: 0 R = Reserved R R R R R R R 6 5 4 3 2 1 Bit 0 Figure 7-19. SIM Break Flag Control Register (SBFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA System Integration Module (SIM) Advance Information 139 NON-DISCLOSURE AGREEMENT REQUIRED System Integration Module (SIM) REQUIRED NON-DISCLOSURE Advance Information 140 System Integration Module (SIM) AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 8. Random-Access Memory (RAM) 8.1 Contents 8.2 8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 8.2 Introduction This section describes the 2.5 Kbytes of RAM. 8.3 Functional Description Addresses $0050 through $0A4F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Within page zero are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O (input/output) control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses 5 bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Random-Access Memory (RAM) Advance Information 141 NON-DISCLOSURE AGREEMENT REQUIRED Random-Access Memory (RAM) REQUIRED During a subroutine call, the CPU uses 2 bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. NON-DISCLOSURE Advance Information 142 Random-Access Memory (RAM) AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 9. 2-Kbyte FLASH Memory 9.1 Contents 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 FLASH 3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .145 FLASH 3 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .147 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . . .148 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 FLASH Program and Margin Read Operation . . . . . . . . . . . .150 9.2 Introduction This section describes the operation of the embedded 2-Kbyte FLASH memory. This is non-volatile memory which can be read, programmed, and erased from a single external supply. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 2-Kbyte FLASH Memory Advance Information 143 NON-DISCLOSURE AGREEMENT REQUIRED 2-Kbyte FLASH Memory REQUIRED 9.3 Functional Description This FLASH memory array contains 2,048 bytes. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH array is organized into pages and rows. There are eight pages of memory per row and for this array, 1 byte per page. The minimum erase block size is a single row, eight bytes. Programming is performed on a per page basis, or for this array, one byte at a time. The address ranges for the 2-Kbyte FLASH memory are: • $1800–$1FFF; general-purpose FLASH array AGREEMENT When programming the FLASH, just enough program time must be utilized via an iterative programming algorithm. Too much program time can result in a disturb condition in which an erased bit becomes programmed. This can be prevented as long as no more than eight program operations are performed per row before again performing an erase operation. Each programmed page is read in margin mode to ensure that the bits are programmed enough for data retention over device lifetime. The row architecture for this array is: • • • • • $1800–$1807; row 0 $1808–$180F; row 1 $1810–$1817; row 2 ---------------------------$1FF8–$1FFF; row 255 NON-DISCLOSURE Advance Information 144 MC68HC(9)08PT48 — Rev. 2.0 2-Kbyte FLASH Memory MOTOROLA 2-Kbyte FLASH Memory FLASH 3 Control Register 9.4 FLASH 3 Control Register The FLASH control register (FL3CR) controls FLASH program, erase, and margin operations. Address: $FE08 Bit 7 Read: F3DIV1 Write: Reset: 0 F3DIV0 0 F3BLK1 0 F3BLK0 0 HVEN 0 MARG 0 ERASE 0 PGM 0 6 5 4 3 2 1 Bit 0 Figure 9-1. FLASH 3 Control Register (FL3CR) NOTE: Devices with more than one FLASH have multiple control registers (FLCRs). Only one FLASH control register should be accessed at a time, so while accessing one control register, ensure that any others are cleared. F3DIV0 — Frequency Divide Control Bit This bit selects the factor by which CGMVCLK is divided to derive the charge pump frequency. See Table 9-2. Note that F3DIV1 has no effect. F3BLK1 and F3BLK0 — Block Erase Control Bits These bits control erasing of blocks of varying size. Table 9-1 shows the various block sizes which can be erased in one erase operation. Table 9-1. Erase Block Sizes BLK1 0 0 BLK0 0 1 Block Size Full array: 2 Kbytes One-half array: 1 Kbyte Row Boundaries 0–255($1800–$1FFF) 0–127($1800–$1BFF) 128–255($1C00–$1FFF 0–7($1800–$183F) 8–15($1840–$187F) 16–23($1880–$18BF) --248–255($1FC0–$1FFF) 0($1800–$1807) 1($1808–$180F) ---255($1FF8–$1FFF) Advance Information 2-Kbyte FLASH Memory 145 1 0 Eight rows: 64 bytes 1 1 Single row: 8 bytes MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA NON-DISCLOSURE AGREEMENT REQUIRED 2-Kbyte FLASH Memory REQUIRED In step 4 of the erase operation in section 9.8 FLASH Erase Operation, the upper addresses are latched and used to determine the location of the block to be erased. For the full array, the only requirement is that the target address points to any byte in this array. Writing to any address in the array will enable the erase. HVEN — High-Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM or ERASE is set. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MARG — Program Margin Control Bit This read/write bit configures the memory for a program margin operation. It cannot be set if the HVEN bit is set, and if it is set when HVEN is set, it will automatically return to 0. 1 = Margin operation selected 0 = Margin operation unselected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. It is interlocked with the PGM bit such that both bits cannot be set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. It is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected NON-DISCLOSURE Advance Information 146 AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 2-Kbyte FLASH Memory MOTOROLA 2-Kbyte FLASH Memory FLASH 3 Block Protect Register 9.5 FLASH 3 Block Protect Register The block protect register (FL3BPR) is implemented as an input/output (I/O) register. Each bit, when programmed, protects a range of addresses in the FLASH. Address: $001E Bit 7 Read: Write: Reset: X X X X BPR3 1 BPR2 1 BPR1 1 BPR0 1 6 5 4 3 2 1 Bit 0 = Unimplemented X = Indeterminate Figure 9-2. FLASH 3 Block Protect Register (FL3BPR) BPR3 — Block Protect Register Bit 3 This bit protects the memory contents in the address range $1C00 to $1FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR2 — Block Protect Register Bit 2 BPR1 — Block Protect Register Bit 1 This bit protects the memory contents in the address range $1900 to $1FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR0 — Block Protect Register Bit 0 This bit protects the memory contents in the address range $1800 to $1FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 2-Kbyte FLASH Memory Advance Information 147 NON-DISCLOSURE This bit protects the memory contents in the address range $1A00 to $1FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program AGREEMENT REQUIRED 2-Kbyte FLASH Memory REQUIRED By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both BPR3 and BPR2 are set, for instance, the address range $1A00 through $1FFF is locked. If all bits are cleared, then all of the memory is available for erase and program. 9.6 Block Protection AGREEMENT Because of the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations. This protection is done by reserving a location in the I/O space for block protect information. If the address range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is allowed in the array. When the block protect register is cleared, the entire memory is accessible for program and erase. When bits within the register are programmed, they lock blocks of memory address ranges as shown in the 9.5 FLASH 3 Block Protect Register. NON-DISCLOSURE 9.7 Charge Pump Frequency Control The internal charge pump for this array is to be operated over the specified frequency range (refer to 22.16 2-K FLASH Memory Electrical Characteristics). The PLL output clock, CGMVCLK, is used to derive the two quadrature clocks, VCLK12 and VCLK23 which are one-half CGMVCLK. Additional pump frequency control is provided using the FDIV0 bit to keep the VCLKs within the specified range. The PLL must be ON and locked (but not necessarily engaged) before program/erase operations can be performed. See Table 9-2. Advance Information 148 2-Kbyte FLASH Memory MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 2-Kbyte FLASH Memory FLASH Erase Operation Table 9-2. Charge Pump Clock Frequency FDIV0 0 1 Pump Clock Frequency CGMVCLK ÷ 2 CGMVCLK ÷ 4 . 9.8 FLASH Erase Operation NOTE: After a total of eight program operations have been applied to a row, the row must be erased before further use to avoid the disturb condition. An erased byte will read $00. 22.16 2-K FLASH Memory Electrical Characteristics has a detailed description of the times used in this algorithm. Use this step-by-step procedure to erase a block of FLASH memory: 1. Establish pump frequency by configuring PLL. 2. Unprotect target portion of the array (BPR0–BPR3.) 3. Set the ERASE bit, the BLK0, BLK1, and FDIV0 bit in the FLASH control register. 4. Write to any FLASH address with any data within the block address range desired. 5. Set the HVEN bit. 6. Wait for a time, tERASE. 7. Clear the HVEN bit. 8. Wait for a time, t Kill, for the high voltages to dissipate. 9. Clear the ERASE bit. 10. After time, tHVD, the memory can be accessed again in read mode. NOTE: These operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Do not exceed tErase maximum. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 2-Kbyte FLASH Memory Advance Information 149 NON-DISCLOSURE AGREEMENT REQUIRED 2-Kbyte FLASH Memory REQUIRED 9.9 FLASH Program and Margin Read Operation Programming of this FLASH array is done on a page basis where one page equals one byte. The purpose of the margin read mode is to ensure that data has been programmed with sufficient margin for long-term data retention. During a margin read, the control gates of the selected memory bits are held at a slightly negative voltage by an internal charge pump. Reading the data in margin mode is the same as for ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. In short, a margin read applies a more stringent condition on the bitcell during read which ensures the data will be valid throughout the life of the product. A margin read can only follow a program operation. All times listed here are specified in Section 22. Electrical Specifications. The procedure for programming the FLASH memory is: 1. Establish pump frequency by configuring the PLL. 2. Set the PGM bit and program FDIV0 to the appropriate value. This configures the memory for program operation and enables the latching of address and data for programming. 3. Write data to the page (1 byte) being programmed. 4. Set the HVEN bit. 5. Wait for a time, tSTEP. 6. Clear the HVEN bit. 7. Wait for a time, tHVTV. 8. Set the MARG bit. 9. Wait for a time, tVTP. 10. Clear the PGM bit. 11. Wait for a time, tHVD. 12. Read the page of data. (This is in margin mode.) 13. Clear the MARG bit. 14. If any programmed bits do not read correctly, repeat the process from step 2 through 13 up to maximum program pulses. (See 22.16 2-K FLASH Memory Electrical Characteristics.) NON-DISCLOSURE Advance Information 150 AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 2-Kbyte FLASH Memory MOTOROLA 2-Kbyte FLASH Memory FLASH Program and Margin Read Operation Note: This page program algorithm assumes the PLL is on and locked and the page in question has been erased before entry. PROGRAM 2-K FLASH INITIALIZE ATTEMPT COUNTER TO 0 SET PGM BIT AND FDIV BITS WRITE DATA TO SELECTED PAGE SET HVEN BIT WAIT tSTEP CLEAR HVEN BIT WAIT tHVTV SET MARGIN BIT WAIT tVTP CLEAR PGM BIT WAIT tHVD READ PAGE OF DATA INCREMENT ATTEMPT COUNTER CLEAR MARGIN BIT NO ATTEMPT COUNT EQUAL TO 5? YES PROGRAMMING OPERATION FAILED NO READ DATA EQUAL TO WRITE DATA? YES PROGRAMMING OPERATION COMPLETE Figure 9-3. Page Program Algorithm MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 2-Kbyte FLASH Memory Advance Information 151 NON-DISCLOSURE AGREEMENT REQUIRED 2-Kbyte FLASH Memory REQUIRED NON-DISCLOSURE Advance Information 152 2-Kbyte FLASH Memory AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 10. 48-Kbyte FLASH Memory 10.1 Contents 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 FLASH 1Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 FLASH 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .155 FLASH 1 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .158 FLASH 2 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .159 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . . .161 10.10 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 10.11 FLASH Program and Margin Read Operation . . . . . . . . . . . .162 10.2 Introduction This section describes the operation of the embedded 48-Kbyte FLASH memory. This is non-volatile memory which can be read, programmed, and erased from a single external supply. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory Advance Information 153 NON-DISCLOSURE AGREEMENT REQUIRED 48-Kbyte FLASH Memory REQUIRED 10.3 Functional Description The FLASH memory contains 48,676 bytes divided between two FLASH arrays. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH array is organized into pages and rows. There are eight pages of memory per row and for this array, 8 bytes per page. The minimum erase block size is a single row, 64 bytes. Programming is performed on a per page basis, or for this array, eight bytes at a time. The address ranges for the 48-Kbyte FLASH memory are: • • • $4000–$7FFF; FLASH 2 array $8000–$FDFF; FLASH 1 array $FFD4–$FFFF; user vector space and part of FLASH 1 array AGREEMENT NON-DISCLOSURE When programming the FLASH, just enough program time must be utilized via an iterative programming algorithm. Too much program time can result in a disturb condition in which an erased bit becomes programmed. This can be prevented as long as no more than eight program operations are performed per row before again performing an erase operation. Each programmed page is read in margin mode to ensure that the bits are programmed enough for data retention over device lifetime. The row architecture for this array is: • $8000–$803F; row 0 of FLASH 1 • $8040–$807F; row 1 of FLASH 1 • $8080–$80CF; row 2 of FLASH 1 • ---------------------------------------• $FFC0–$FFFF; row 511 of FLASH 1 • • • • • Advance Information 154 48-Kbyte FLASH Memory $4000–$403F; row 0 of FLASH 2 $4040–$407F; row 1 of FLASH 2 $4080–$40BF; row 2 of FLASH 2 ---------------------------------------$7FC0–$7FFF; row 255 of FLASH 2 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory FLASH 1Control Register 10.4 FLASH 1 Control Register The FLASH 1 control register (FL1CR) controls FLASH program, erase, and margin operations. Address: $FE0C Bit 7 Read: F1DIV1 Write: Reset: 0 0 0 0 0 0 0 0 F1DIV0 F1BLK1 F1BLK0 HVEN MARG ERASE PGM 6 5 4 3 2 1 Bit 0 Figure 10-1. FLASH 1 Control Register (FL1CR) 10.5 FLASH 2 Control Register The FLASH 2 control register (FL2CR) controls FLASH program, erase, and margin operations. Address: $FE0A Bit 7 Read: F2DIV1 Write: Reset: 0 0 0 0 0 0 0 0 F2DIV0 F2BLK1 F2BLK0 HVEN MARG ERASE PGM 6 5 4 3 2 1 Bit 0 Figure 10-2. FLASH 2 Control Register (FL2CR) NOTE: Devices with more than one FLASH have multiple control registers (FLCRs). Only one FLASH control register should be accessed at a time, so while accessing one control register, ensure that any others are cleared. F1DIV0, F2DIV0 — Frequency Divide Control Bit These bits are logically ORed together and the output selects the factor by which CGMVCLK is divided to derive the charge pump frequency. See Table 10-3. Note that F1DIV1 and F2DIV1 have no effect. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory Advance Information 155 NON-DISCLOSURE AGREEMENT REQUIRED 48-Kbyte FLASH Memory REQUIRED F1BLK1, F1BLK0, F2BLK1, F2BLK0— Block Erase Control Bits These bits control erasing of blocks of varying size. Table 10-1 and Table 10-2 show the various block sizes which can be erased in one erase operation. Table 10-1. 32-Kbyte Erase Block Sizes F1BLK1 0 F1BLK0 0 1 Block Size Full array: 32 Kbytes One-half array: 16 Kbytes Row Boundaries 0–511 ($8000–$FFFF) 0–255 ($8000–$BFFF) 256–511 ($C000–$FFFF) 0–7 ($8000–$81FF) 8–15 ($8200–$83FF) 16–23 ($8400–$86FF) --504–511 ($FE00–$FFFF) 0 ($8000–$803F) 1 ($8040–$807F) ---511 ($FFC0–$FFFF) AGREEMENT 0 1 0 Eight rows: 512 bytes 1 1 Single row: 64 bytes Table 10-2. 16-Kbyte Erase Block Sizes NON-DISCLOSURE F2BLK1 0 0 F2BLK0 0 1 Block Size Full array: 16 Kbytes One half array: 8 Kbytes Row Boundaries 0–255 ($4000–$7FFF) 0–127 ($4000–$5FFF) 128–255 ($6000–$7FFF) 0–7 ($4000–$41FF) 8–15 ($4200–$43FF) 16–23 ($4400–$45FF) --248–255 ($7E00–$7FFF) 0 ($4000–$403F) 1 ($4040–$407F) ---255 ($7FC0–$7FFF) 1 0 Eight rows: 512 bytes 1 1 Single row: 64 bytes Advance Information 156 48-Kbyte FLASH Memory MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory FLASH 2 Control Register In step 4 of the erase operation in 10.10 FLASH Erase Operation, the upper addresses are latched and used to determine the location of the block to be erased. For the full array, the only requirement is that the target address points to any byte in this array. Writing to any address in the array will enable the erase. HVEN — High-Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM or ERASE is set. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MARG — Program Margin Control Bit This read/write bit configures the memory for a program margin operation. It cannot be set if the HVEN bit is set, and if it is set when HVEN is set, it will return to 0 automatically. 1 = Margin operation selected 0 = Margin operation unselected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. It is interlocked with the PGM bit such that both bits cannot be set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. It is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory Advance Information 157 NON-DISCLOSURE AGREEMENT REQUIRED 48-Kbyte FLASH Memory REQUIRED 10.6 FLASH 1 Block Protect Register The FLASH 1 block protect register (FL1BPR) is implemented as an input/output (I/O) register. Each bit, when programmed, protects a range of addresses in the FLASH. Address: $001F Bit 7 Read: 6 5 4 3 2 1 Bit 0 AGREEMENT Write: Reset: X X X X F1BPR3 1 F1BPR2 1 F1BPR1 1 F1BPR0 1 = Unimplemented X = Indeterminate Figure 10-3. FLASH 1 Block Protect Register (FL1BPR) F1BPR3 — Block Protect Register Bit 3 This bit protects the memory contents in the address range $C000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program F1BPR2 — Block Protect Register Bit 2 NON-DISCLOSURE This bit protects the memory contents in the address range $A000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program F1BPR1 — Block Protect Register Bit 1 This bit protects the memory contents in the address range $9000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program F1BPR0 — Block Protect Register Bit 0 This bit protects the memory contents in the address range $8000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program Advance Information 158 48-Kbyte FLASH Memory MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory FLASH 2 Block Protect Register By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both F1BPR3 and F1BPR2 are set, for instance, the address range $A000 through $FFFF is locked. If all bits are cleared, then all of the memory is available for erase and program. 10.7 FLASH 2 Block Protect Register The FLASH 2 block protect register (FL2BPR) is implemented as an I/O register. Each bit, when programmed, protects a range of addresses in the FLASH. Address: $004F Bit 7 Read: Write: Reset: X X X X F2BPR3 1 F2BPR2 1 F2BPR1 1 F2BPR0 1 6 5 4 3 2 1 Bit 0 = Unimplemented X = Indeterminate Figure 10-4. FLASH 2 Block Protect Register (FL2BPR) F2BPR3 — Block Protect Register Bit 3 This bit protects the memory contents in the address range $6000 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program F2BPR2 — Block Protect Register Bit 2 This bit protects the memory contents in the address range $5000 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory Advance Information 159 NON-DISCLOSURE AGREEMENT REQUIRED 48-Kbyte FLASH Memory REQUIRED F2BPR1 — Block Protect Register Bit 1 This bit protects the memory contents in the address range $4800 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program F2BPR0 — Block Protect Register Bit 0 This bit protects the memory contents in the address range $4000 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both F2BPR3 and F2BPR2 are set, for instance, the address range $5000 through $7FFF is locked. If all bits are cleared, then all of the memory is available for erase and program. AGREEMENT 10.8 Block Protection Because of the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations. This protection is done by reserving a location in the I/O space for block protect information. If the address range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is allowed in the array. When the block protect register is cleared, the entire memory is accessible for program and erase. When bits within the register are programmed, they lock blocks of memory address ranges as shown in 10.7 FLASH 2 Block Protect Register. NON-DISCLOSURE Advance Information 160 MC68HC(9)08PT48 — Rev. 2.0 48-Kbyte FLASH Memory MOTOROLA 48-Kbyte FLASH Memory Charge Pump Frequency Control 10.9 Charge Pump Frequency Control The internal charge pump for this array is to be operated over the specified frequency range (refer to 22.16 2-K FLASH Memory Electrical Characteristics). The PLL output clock, CGMVCLK, is used to derive the two quadrature clocks, VCLK12 and VCLK23 which are one-half CGMVCLK. Additional pump frequency control is provided using the FxDIV0 bit in order to keep the VCLKs within the specified range. The PLL must be ON and Locked (but not necessarily engaged) before program/erase operations can be performed. Table 10-3. Charge Pump Clock Frequency FDIV0 0 1 Pump Clock Frequency CGMVCLK ÷ 2 CGMVCLK ÷ 4 10.10 FLASH Erase Operation NOTE: After a total of eight program operations have been applied to a row, the row must be erased before further use to avoid the disturb condition. An erased byte will read $00. Section 22. Electrical Specifications has a detailed description of the times used in this algorithm. Use this step-by-step procedure to erase a block of FLASH memory: 1. Establish pump frequency by configuring PLL. 2. Unprotect target portion of the array (FxBPR0–FxBPR3). 3. Set the ERASE bit, the FxBLK0, FxBLK1, and FxDIV0 bits in the FLASH control register. 4. Write to any FLASH address with any data within the block address range desired. 5. Set the HVEN bit. 6. Wait for a time, tErase. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory Advance Information 161 NON-DISCLOSURE AGREEMENT REQUIRED 48-Kbyte FLASH Memory REQUIRED 7. Clear the HVEN bit. 8. Wait for a time, t Kill, for the high voltages to dissipate. 9. Clear the ERASE bit. 10. After a time, tHVD, the memory can be accessed in read mode again. NOTE: AGREEMENT These operations must be performed in the order shown, but other unrelated operations may occur between the steps. Do not exceed tErase maximum. 10.11 FLASH Program and Margin Read Operation Programming of this FLASH array is done on a page basis where one page equals eight bytes. The purpose of the margin read mode is to ensure that data has been programmed with sufficient margin for longterm data retention. During a margin read, the control gates of the selected memory bits are held at a slightly negative voltage by an internal charge pump. Reading the data in margin mode is the same as for ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. In short, a margin read applies a more stringent condition on the bitcell during read which ensures the data will be valid throughout the life of the product. A margin read can only follow a program operation. All times listed here are specified in Section 22. Electrical Specifications. The step-by-step procedure for programming the FLASH memory is: 1. Establish pump frequency by configuring the PLL. 2. Set the PGM bit and program FxDIV0 appropriately. This configures the memory for program operation and enables the latching of address and data for programming. 3. Write data to the page (8 bytes) being programmed. 4. Set the HVEN bit. 5. Wait for a time, tStep. 6. Clear the HVEN bit. NON-DISCLOSURE Advance Information 162 MC68HC(9)08PT48 — Rev. 2.0 48-Kbyte FLASH Memory MOTOROLA 48-Kbyte FLASH Memory FLASH Program and Margin Read Operation 7. Wait for a time, tHVTV. 8. Set the MARG bit. 9. Wait for a time, tVTP. 10. Clear the PGM bit. 11. Wait for a time, tHVD. 12. Read the page of data. (This is in margin mode.) 13. Clear the MARG bit. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA 48-Kbyte FLASH Memory Advance Information 163 NON-DISCLOSURE AGREEMENT 14. If any programmed bits do not read correctly, repeat the process from step 2 through 13 up to maximum program pulses. (See 22.16 2-K FLASH Memory Electrical Characteristics.) REQUIRED 48-Kbyte FLASH Memory REQUIRED Note: This page program algorithm assumes the PLL is on and locked, and the page in question has been erased before entry. Program FLASH Initialize Attempt Counter to 0 Set PGM Bit and FxDIV bits AGREEMENT Write Data to Selected Page Set HVEN Bit Wait tSTEP Clear HVEN Bit Wait tHVTV Set MARGIN Bit Wait tVTP NON-DISCLOSURE Clear PGM Bit Wait tHVD Read Page of Data Increment Attempt Counter Clear MARGIN Bit NO Attempt Count Equal To 5? NO Read Data Equal To Write Data? YES Programming Operation Failed YES Programming Operation Complete Figure 10-5. Page Program Algorithm Advance Information 164 48-Kbyte FLASH Memory MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 11. Serial Peripheral Interface (SPI) Module 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.5 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 11.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.6.1 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . .171 11.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .171 11.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .173 11.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .174 11.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .176 11.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 11.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 11.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 11.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 11.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 11.11 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 11.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .185 11.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 11.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .186 11.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .186 11.13.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 11.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 11.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 11.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 11.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . .192 11.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 165 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED 11.2 Introduction This section describes the serial peripheral interface (SPI) module which allows full-duplex, synchronous, serial communications with peripheral devices. 11.3 Features Features of the SPI module include: AGREEMENT • • • • • • • • Full-duplex operation Master and slave modes Double-buffered operation with separate transmit and receive registers Four master mode frequencies (maximum = bus frequency ÷ 2) Maximum slave mode frequency = bus frequency Clock ground for reduced radio frequency (RF) interference Serial clock with programmable polarity and phase Two separately enabled interrupts: – SPRF (SPI receiver full) – SPTE (SPI transmitter empty) Mode fault error flag with CPU interrupt capability Overflow error flag with CPU interrupt capability Programmable wired-OR mode I2C (inter-integrated circuit) compatibility NON-DISCLOSURE • • • • 11.4 Functional Description Figure 11-1 shows the structure of the SPI module and Figure 11-2 shows the locations and contents of the SPI input/output (I/O) registers. Advance Information 166 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Functional Description INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT 2 (FROM SIM) 7 2 CLOCK DIVIDER 8 32 128 CLOCK SELECT MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS 6 SHIFT REGISTER 5 4 3 2 1 0 MISO SPMSTR SPE SPR1 SPR0 SPMSTR CPHA CPOL MODFEN TRANSMITTER CPU INTERRUPT REQUEST SPI CONTROL RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE SPTIE SPRIE SPWOM SPE SPRF SPTE OVRF MODF Figure 11-1. SPI Module Block Diagram The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interruptdriven. The following subsections describe the operation of the SPI module. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 167 NON-DISCLOSURE DMAS AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED Addr. Register Name Bit 7 6 DMAS 0 ERRIE 0 R6 T6 5 SPMSTR 1 OVRF 4 CPOL 0 MODF 3 CPHA 1 SPTE 2 SPWOM 0 MODFEN 1 SPE 0 SPR1 0 R1 T1 Bit 0 SPTIE 0 SPR0 0 R0 T0 $000F Read: SPRIE SPI Control Register Write: (SPCR) Reset: 0 Read: SPRF SPI Status and Control Write: Register (SPSCR) Reset: 0 Read: SPI Data Register Write: (SPDR) Reset: R7 T7 $0010 0 R5 T5 0 R4 T4 1 R3 T3 0 R2 T2 AGREEMENT $0011 Indeterminate after reset = Unimplemented Figure 11-2. SPI I/O Register Summary 11.4.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NON-DISCLOSURE NOTE: Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. (See 11.14.1 SPI Control Register.) Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. (See Figure 11-3.) The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 11.14.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. Advance Information 168 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Functional Description As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTE bit. When the DMAS bit is set, the SPI status and control register does not have to be read to clear the SPRF bit. A read of the SPI data register by either the CPU or the DMA clears the SPRF bit. A write to the SPI data register clears the SPTE bit. NOTE: This device has no DMA. DMAS should be cleared. MASTER MCU SLAVE MCU SHIFT REGISTER MISO MISO MOSI MOSI SHIFT REGISTER BAUD RATE GENERATOR SS VDD SS Figure 11-3. Full-Duplex Master-Slave Connections MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 169 NON-DISCLOSURE SPSCK SPSCK AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED 11.5 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. (See 11.8.2 Mode Fault Error.) In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise the byte already in the slave shift register shifts out on the MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. (See 11.6 Transmission Formats.) NON-DISCLOSURE AGREEMENT NOTE: SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge. Advance Information 170 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Transmission Formats 11.6 Transmission Formats During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate multiplemaster bus contention. 11.6.1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE). 11.6.2 Transmission Format When CPHA = 0 Figure 11-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information.Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 171 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 11.8.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB (most significant bit) capture strobe. Therefore the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 11-5. AGREEMENT SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 1 2 3 4 5 6 7 8 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB NON-DISCLOSURE SS; TO SLAVE CAPTURE STROBE Figure 11-4. Transmission Format (CPHA = 0) MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3 Figure 11-5. CPHA/SS Timing Advance Information 172 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Transmission Formats When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 173 NON-DISCLOSURE Figure 11-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 11.8.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line. AGREEMENT 11.6.3 Transmission Format When CPHA = 1 REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 1 2 3 4 5 6 7 8 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB AGREEMENT SS; TO SLAVE CAPTURE STROBE Figure 11-6. Transmission Format (CPHA = 1) 11.6.4 Transmission Initiation Latency When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 11-7.) The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 11-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. NON-DISCLOSURE Advance Information 174 MC68HC(9)08PT48 — Rev. 2.0 Serial Peripheral Interface (SPI) Module MOTOROLA Serial Peripheral Interface (SPI) Module Transmission Formats WRITE TO SPDR BUS CLOCK MOSI SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER INITIATION DELAY MSB BIT 6 BIT 5 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN      WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST SPSCK = INTERNAL CLOCK ÷ 128; 128 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 2; 2 POSSIBLE START POINTS Figure 11-7. Transmission Start Delay (Master) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 175 NON-DISCLOSURE AGREEMENT 1 2 3 REQUIRED    Serial Peripheral Interface (SPI) Module REQUIRED 11.7 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 11-8 shows the timing associated with doing back-to-back transmissions with the SPI. (SPSCK has CPHA:CPOL = 1:0.) AGREEMENT WRITE TO SPDR 1 3 8 SPTE 2 5 10 SPSCK; CPHA:CPOL = 1:0 MOSI MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 654321 654321 654 BYTE 1 BYTE 2 BYTE 3 4 9 SPRF NON-DISCLOSURE READ SPSCR 6 11 READ SPDR 1 2 3 4 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU READS SPSCR WITH SPRF BIT SET. 7 8 9 7 CPU READS SPDR, CLEARING SPRF BIT. CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. 12 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. 5 6 Figure 11-8. SPRF/SPTE CPU Interrupt Timing Advance Information 176 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Error Conditions The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. Also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. 11.8 Error Conditions These flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register. Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register. • 11.8.1 Overflow Error The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle 7. (See Figure 11-4 and Figure 11-6.) If an overflow occurs, all data received after the overflow and before the OVRF bit is cleared does not transfer to the receive data register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive data register before the overflow occurred can MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 177 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED still be read. Therefore, an overflow error always indicates the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register. NOTE: This device has no DMA. DMAS should be cleared. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. When the DMAS bit is high, SPRF generates a receiver DMA service request, and MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 11-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 11-9 shows how it is possible to miss an overflow. The first part of Figure 11-9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR are read. NON-DISCLOSURE AGREEMENT BYTE 1 1 BYTE 2 4 BYTE 3 6 BYTE 4 8 SPRF OVRF 2 5 READ SPSCR READ SPDR 1 2 3 4 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 5 6 7 8 7 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST. Figure 11-9. Missed Read of Overflow Condition Advance Information 178 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Error Conditions In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 11-10 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. BYTE 1 SPI RECEIVE COMPLETE SPRF 1 BYTE 2 5 BYTE 3 7 BYTE 4 11 OVRF 2 4 6 9 8 8 9 12 14 READ SPSCR READ SPDR 1 2 3 4 5 6 7 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 10 13 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure 11-10. Clearing SPRF When OVRF Interrupt Is Not Enabled MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 179 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED 11.8.2 Mode Fault Error Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR. To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if: • • The SS pin of a slave SPI goes high during a transmission. The SS pin of a master SPI goes low at any time. AGREEMENT For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. NOTE: This device has no DMA. DMAS should be cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. When the DMAS bit is high, SPRF generates a receiver DMA service request instead of a CPU interrupt request, but MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 11-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes these events to occur: • • • • • If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. The SPE bit is cleared. The SPTE bit is set. The SPI state counter is cleared. The data direction register of the shared I/O port regains control of port drivers. MC68HC(9)08PT48 — Rev. 2.0 Serial Peripheral Interface (SPI) Module MOTOROLA NON-DISCLOSURE Advance Information 180 Serial Peripheral Interface (SPI) Module Error Conditions NOTE: To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port before enabling the SPI. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its idle level following the shift of the last data bit. (See 11.6 Transmission Formats.) NOTE: Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference between a MODF occurring when the SPI is a master and when it is a slave. When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE: NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 181 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED 11.9 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests, see Table 11-1. Table 11-1. SPI Interrupts Flag SPTE Transmitter empty Request SPI transmitter CPU interrupt request DMAS = 0, SPTIE = 1, SPE = 1 SPI transmitter DMA service request DMAS = 1, SPTIE = 1, SPE = 1 SPI receiver CPU interrupt request DMAS = 0, SPRIE = 1 SPI receiver DMA service request DMAS = 1, SPRIE = 1 SPI receiver/error interrupt request ERRIE = 1 SPI receiver/error interrupt request ERRIE = 1 AGREEMENT SPRF Receiver full OVRF Overflow MODF Mode fault NOTE: This device has no DMA. DMAS should be cleared. The DMA select bit (DMAS) controls whether SPTE and SPRF generate CPU interrupt requests or DMA service requests. When DMAS = 0, reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. When DMAS = 1, any read of the receive data register clears the SPRF flag. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter interrupt requests provided that the SPI is enabled (SPE = 1). The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver interrupt requests regardless of the state of the SPE bit. (See Figure 11-11.) The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error CPU interrupt request. NON-DISCLOSURE Advance Information 182 MC68HC(9)08PT48 — Rev. 2.0 Serial Peripheral Interface (SPI) Module MOTOROLA Serial Peripheral Interface (SPI) Module Interrupts The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests. SPI TRANSMITTER DMA SERVICE REQUEST SPTE SPTIE SPE SPI TRANSMITTER CPU INTERRUPT REQUEST DMAS SPI RECEIVER DMA SERVICE REQUEST SPRIE SPRF SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF Figure 11-11. SPI Interrupt Request Generation NOTE: This device has no DMA. DMAS should be cleared. The following two sources in the SPI status and control register can generate interrupt requests. • SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF can generate either an SPI receiver/error CPU interrupt request or an SPRF DMA service request. If the DMA select bit, DMAS, is clear, SPRF generates an SPRF CPU interrupt request. If DMAS is set, SPRF generates an SPRF DMA service request. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 183 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED • SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE can generate either an SPTE CPU interrupt request or an SPTE DMA service request. If the DMAS bit is clear, SPTE generates an SPTE CPU interrupt request. If DMAS is set, SPTE generates an SPTE DMA service request. AGREEMENT 11.10 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: • • • • • The SPTE flag is set. Any transmission currently in progress is aborted. The shift register is cleared. The SPI state counter is cleared, making it ready for a new complete transmission. All the SPI port logic is disabled. NON-DISCLOSURE These items are reset only by a system reset: • • • All control bits in the SPCR register All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) The status flags SPRF, OVRF, and MODF By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. Advance Information 184 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Wait Mode 11.11 Wait Mode The SPI module remains active after the execution of a WAIT instruction. In wait mode, the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. 11.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 7.8.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 185 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED 11.13 I/O Signals The SPI module has five I/O (input/output) pins: • • • • • MISO — Data received MOSI — Data transmitted SPSCK — Serial clock SS — Slave select CGND — Clock ground AGREEMENT The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 11.13.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmit serial data. In fullduplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multipleslave system, a logic 1 on the SS pin puts the MISO pin in a highimpedance state. NON-DISCLOSURE 11.13.2 MOSI (Master Out/Slave In) MOSI is one of the two SPI module pins that transmit serial data. In fullduplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. Advance Information 186 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module I/O Signals 11.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 11.13.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 11.6 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format. See Figure 11-12. MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3 Figure 11-12. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. (See 11.14.2 SPI Status and Control Register.) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 187 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a highimpedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 11.8.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. (See Table 11-2.) Table 11-2. SPI Configuration SPE 0 SPMSTR X(1) 0 1 1 MODFEN X X 0 1 SPI Configuration Not enabled Slave Master without MODF Master with MODF State of SS Logic General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI NON-DISCLOSURE AGREEMENT 1 1 1 1. X = don’t care 11.13.5 CGND (Clock Ground) CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It is connected to the EVSS1 pad. Advance Information 188 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module I/O Registers 11.14 I/O Registers Three I/O registers control and monitor SPI operation: • • • SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR) 11.14.1 SPI Control Register The SPI control register (SPCR): • • • • • • Enables SPI module interrupt requests Selects CPU interrupt requests Configures the SPI module as master or slave Selects serial clock polarity and phase Configures the SPSCK, MOSI, and MISO pins as open-drain outputs Enables the SPI module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 189 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED Address: $000F Bit 7 6 DMAS 0 5 SPMSTR 1 4 CPOL 0 3 CPHA 1 2 SPWOM 0 1 SPE 0 Bit 0 SPTIE 0 Read: SPRIE Write: Reset: 0 Figure 11-13. SPI Control Register (SPCR) SPRIE — SPI Receiver Interrupt Enable Bit This read/write bit enables interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. 1 = SPRF CPU interrupt requests or SPRF DMA service requests enabled 0 = SPRF CPU interrupt requests or SPRF DMA service requests disabled DMAS —DMA Select Bit This read/write bit selects DMA service requests when the SPI receiver full bit, SPRF, or the SPI transmitter empty bit, SPTE, becomes set. Setting the DMAS bit disables SPRF CPU interrupt requests and SPTE CPU interrupt requests. 1 = SPRF DMA and SPTE DMA service requests enabled (SPRF CPU and SPTE CPU interrupt requests disabled) 0 = SPRF DMA and SPTE DMA service requests disabled (SPRF CPU and SPTE CPU interrupt requests enabled) NON-DISCLOSURE AGREEMENT NOTE: This device has no DMA. DMAS should be cleared. SPMSTR — SPI Master Bit This read/write bit selects master mode operation or slave mode operation. 1 = Master mode 0 = Slave mode Advance Information 190 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module I/O Registers CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 11-4 and Figure 11-6.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. CPHA — Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 11-4 and Figure 11-6.) To transmit data between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 11-12.) SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE — SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 11.10 Resetting the SPI.) 1 = SPI module enabled 0 = SPI module disabled SPTIE — SPI Transmit Interrupt Enable This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. 1 = SPTE interrupt requests enabled 0 = SPTE interrupt requests disabled MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 191 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED 11.14.2 SPI Status and Control Register The SPI status and control register (SPSCR) contains flags to signal these conditions: • • • Receive data register full Failure to clear SPRF bit before next byte is received (overflow error) Inconsistent logic level on SS pin (mode fault error) Transmit data register empty AGREEMENT • The SPI status and control register also contains bits that perform these functions: • • • Address: Enable error interrupts Enable mode fault error detection Select master SPI baud rate $0010 Bit 7 6 ERRIE 5 OVRF 4 MODF 3 SPTE MODFEN 0 0 1 0 SPR1 0 SPR0 0 2 1 Bit 0 NON-DISCLOSURE Read: Write: Reset: SPRF 0 0 = Unimplemented Figure 11-14. SPI Status and Control Register (SPSCR) SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates an interrupt request if the SPRIE bit in the SPI control register is set also. 1 = Receive data register full 0 = Receive data register not full Advance Information 192 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module I/O Registers ERRIE — Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests. 0 = MODF and OVRF cannot generate CPU interrupt requests. OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. 1 = Overflow 0 = No overflow MODF — Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE — SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an interrupt request if the SPTIE bit in the SPI control register is set also. 1 = Transmit data register empty 0 = Transmit data register not empty NOTE: Do not write to the SPI data register unless the SPTE bit is high. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 193 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED MODFEN — Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a general purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. (See 11.13.4 SS (Slave Select).) If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See 11.8.2 Mode Fault Error.) SPR1 and SPR0 — SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 11-3. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 11-3. SPI Master Baud Rate Selection NON-DISCLOSURE AGREEMENT SPR1:SPR0 00 01 10 11 Baud Rate Divisor (BD) 2 8 32 128 Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = ------------------------2 × BD CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor Advance Information 194 Serial Peripheral Interface (SPI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module I/O Registers 11.14.3 SPI Data Register The SPI data register (SPDR) consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. See Figure 11-1. Address: $0011 Bit 7 Read: Write: Reset: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 Indeterminate after reset Figure 11-15. SPI Data Register (SPDR) R7:R0/T7:T0 — Receive/Transmit Data Bits NOTE: Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Peripheral Interface (SPI) Module Advance Information 195 NON-DISCLOSURE AGREEMENT REQUIRED Serial Peripheral Interface (SPI) Module REQUIRED NON-DISCLOSURE Advance Information 196 Serial Peripheral Interface (SPI) Module AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 12. Serial Communications Interface (SCI) Module 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 12.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 12.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 12.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 12.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . .203 12.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 12.4.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 12.4.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .205 12.4.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .206 12.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .210 12.4.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 12.4.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 12.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 12.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.6 SCI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .215 12.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 12.7.1 PTG2/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .216 12.7.2 PTG1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .216 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 197 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED 12.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 12.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .217 12.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .220 12.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .222 12.8.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 12.8.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 12.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 12.8.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .229 AGREEMENT 12.2 Introduction This section describes the serial communications interface module (SCI, Version D), which allows high-speed asynchronous communications with peripheral devices and other MCUs. 12.3 Features Features of the SCI module include: • Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 32 programmable baud rates Selectable clock source for baud rate (see Section 14. Configuration Register (CONFIG)) Programmable 8-bit or 9-bit character length Separately enabled transmitter and receiver Separate receiver and transmitter CPU interrupt requests Separate receiver and transmitter DMA service requests Programmable transmitter output polarity Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup NON-DISCLOSURE • • • • • • • • • Advance Information 198 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Functional Description • Interrupt-driven operation with eight interrupt flags: – Transmitter empty – Transmission complete – Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection • • • 12.4 Functional Description Figure 12-1 shows the structure of the SCI module. The SCI allows fullduplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 199 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED INTERNAL BUS SCI DATA REGISTER TRANSMITTER INTERRUPT CONTROL DMA INTERRUPT CONTROL RECEIVER INTERRUPT CONTROL RECEIVE SHIFT REGISTER ERROR INTERRUPT CONTROL SCI DATA REGISTER TRANSMIT SHIFT REGISTER PTG1/RxD PTG2/TxD TXINV SCTIE TCIE R8 T8 AGREEMENT SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE OR NF FE PE LOOPS LOOPS WAKEUP CONTROL RECEIVE CONTROL FLAG CONTROL M WAKE ILTY CLOCK SOURCE ÷4 PRESCALER BAUD RATE GENERATOR PEN PTY DATA SELECTION CONTROL ENSCI DMARE DMATE ORIE NEIE FEIE PEIE TRANSMIT CONTROL NON-DISCLOSURE ENSCI BKF RPF ÷ 16 Figure 12-1. SCI Module Block Diagram Advance Information 200 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Functional Description Addr. Register Name Read: Bit 7 6 ENSCI 0 TCIE 0 T8 5 TXINV 0 SCRIE 0 DMARE 0 SCRF 4 M 0 ILIE 0 DMATE 0 IDLE 3 WAKE 0 TE 0 ORIE 0 OR 2 ILTY 0 RE 0 NEIE 0 NF 1 PEN 0 RWU 0 FEIE 0 FE Bit 0 PTY 0 SBK 0 PEIE 0 PE $0014 LOOPS SCI Control Register 1 Write: (SCC1) Reset: 0 TCIE SCTIE SCI Control Register 2 Write: (SCC2) Reset: 0 Read: R8 SCI Control Register 3 Write: (SCC3) Reset: SCI Status Register 1 Write: (SCS1) Reset: Read: SCI Status Register 2 Write: (SCS2) Reset: Read: SCI Data Register Write: (SCDR) Reset: Read: SCI Baud Rate Register Write: (SCBR) Reset: $0015 $0016 U U TC Read: SCTE $0017 1 1 0 0 0 0 0 BKF 0 RPF $0018 0 R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 Unaffected by reset SCP1 0 0 0 SCP0 0 0 SCR2 0 SCR1 0 SCR0 0 $001A = Unimplemented U = Undetermined Figure 12-2. SCI I/O Register Summary MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 201 NON-DISCLOSURE $0019 AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED 12.4.1 Data Format The SCI uses the standard non-return-to-zero (NRZ) mark/space data format illustrated in Figure 12-3. 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT POSSIBLE PARITY BIT BIT 6 BIT 7 STOP BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 NEXT START BIT AGREEMENT 9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 POSSIBLE PARITY BIT BIT 8 STOP BIT NEXT START BIT Figure 12-3. SCI Data Formats 12.4.2 Transmitter Figure 12-4 shows the structure of the SCI transmitter. NOTE: NON-DISCLOSURE The transmission output pin is enabled by TE bit of SCC2 instead of ENSCI bit of SCC1. 12.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). Advance Information 202 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Functional Description INTERNAL BUS ÷4 CLOCK SOURCE PRESCALER BAUD DIVIDER ÷ 16 SCI DATA REGISTER SCP1 SCP0 SCR1 SCR2 SCR0 TXINV MSB STOP H 8 7 6 5 4 3 2 1 0 START 11-BIT TRANSMIT SHIFT REGISTER L PTG2/TxD M CPU INTERRUPT REQUEST DMA SERVICE REQUEST PEN PTY PARITY GENERATION LOAD FROM SCDR T8 DMATE DMATE SCTE DMATE SCTE SCTIE TC TCIE TRANSMITTER CONTROL LOGIC SCTE RWU LOOPS SBK SCTIE TC TCIE ENSCI TE Figure 12-4. SCI Transmitter 12.4.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the PTG2/TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register 2 (SCC2). MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 203 NON-DISCLOSURE AGREEMENT SHIFT ENABLE PREAMBLE (ALL ONES) BREAK (ALL ZEROS) REQUIRED Serial Communications Interface (SCI) Module REQUIRED 3. Clear the SCI transmitter empty bit (SCTE) by reading SCI status register 1 (SCS1). 4. Write the data to transmit into the SCDR. 5. Repeat steps 3 and 4 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit (LSB) position of the transmit shift register. A logic 1 stop bit goes into the most significant bit (MSB) position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates an SCTE CPU interrupt request. When the transmit shift register is not transmitting a character, the PTG2/TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins. 12.4.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. NON-DISCLOSURE AGREEMENT Advance Information 204 MC68HC(9)08PT48 — Rev. 2.0 Serial Communications Interface (SCI) Module MOTOROLA Serial Communications Interface (SCI) Module Functional Description The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: • • • • • • Sets the framing error flag, FE Sets the SCI receiver full flag, SCRF Clears the SCI data register Clears the received bit 8, R8 Sets the break flag, BKF May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the reception in progress flag, RPF 12.4.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the PTG2/TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the PTG2/TxD pin. Setting TE after the stop bit appears on PTG2/TxD causes data previously written to the SCDR to be lost. A good time to toggle the TE bit is when the SCTE bit becomes set and just before writing the next byte to the SCDR. 12.4.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. (See 12.8.1 SCI Control Register 1.) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 205 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED 12.4.2.6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the SCI transmitter: • SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate an SCTE CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables SCTE CPU interrupts. Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The SCI transmitter interrupt enable bit, SCTIE, in SCC2 enables TC CPU interrupt requests. AGREEMENT • 12.4.3 Receiver Figure 12-5 shows the structure of the SCI receiver. 12.4.3.1 Character Length NON-DISCLOSURE The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). 12.4.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the PTG1/RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates an SCRF CPU interrupt request. Advance Information 206 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Functional Description INTERNAL BUS SCR1 SCP1 SCP0 ÷4 CLOCK SOURCE PTG1/Rx PRESCALER BAUD DIVIDER SCR2 SCR0 START ÷ 16 DATA RECOVERY ALL ZEROS ALL ONES SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0 H L BKF RPF ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST CPU INTERRUPT REQUEST M WAKE ILTY PEN PTY WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE DMARE SCRF DMARE OR ORIE NF NEIE FE FEIE PE PEIE SCRF IDLE SBK R8 RWU ILIE SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE Figure 12-5. SCI Receiver Block Diagram MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 207 NON-DISCLOSURE AGREEMENT MSB REQUIRED STOP Serial Communications Interface (SCI) Module REQUIRED 12.4.3.3 Data Sampling The receiver samples the PTG1/RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud-rate frequency. (See Figure 12-6.) • Start bit — To locate the start bit, recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. To verify a valid start bit, data recovery logic takes samples at RT3, RT5, and RT7. If any two of these three samples are logic 1s, the RT clock is reset and the search for start bit begins again. If all three samples are logic 0s, start bit verification is successful. If only one of the three samples is logic 1, start bit verification is successful, but the noise flag (NF) becomes set. Data bit — To detect noise in data bits, recovery logic takes samples at RT8, RT9, and RT10 of every data bit time. If all three samples are not unanimous, the noise flag becomes set. Stop bit — To detect noise in stop bits, recovery logic takes samples at RT8, RT9, and RT10. If all three samples are not unanimous, the noise flag becomes set. AGREEMENT • • • NON-DISCLOSURE START BIT PTG1/RxD LSB SAMPLES START BIT QUALIFICATION START BIT VERIFICATION DATA SAMPLING RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK STATE RT CLOCK RESET RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT16 RT1 RT2 RT3 RT4 Figure 12-6. Receiver Data Sampling Advance Information 208 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Functional Description To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 12-1 summarizes the results of the start bit verification samples. Table 12-1. Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 12-2 summarizes the results of the data bit samples. Table 12-2. Data Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0 NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s Advance Information Serial Communications Interface (SCI) Module 209 MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 12-3 summarizes the results of the stop bit samples. Table 12-3. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 AGREEMENT 000 001 010 011 100 101 110 111 12.4.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the SCRF bit is set. 12.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. NON-DISCLOSURE Advance Information 210 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Functional Description As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 12-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 12-7. Slow Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 12-7, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 – 147 ------------------------- × 100 = 4.54% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 12-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 211 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 – 163 ------------------------- × 100 = 4.12% 170 Fast Data Tolerance Figure 12-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. AGREEMENT STOP IDLE OR NEXT CHARACTER RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 12-8. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 12-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154 – 160 ˙ ------------------------- × 100 = 3.90% 154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 12-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles. Advance Information 212 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA NON-DISCLOSURE Serial Communications Interface (SCI) Module Functional Description The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 – 176 ------------------------- × 100 = 3.53% 170 12.4.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the MCU can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the MCU into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the PTG1/RxD pin can bring the MCU out of the standby state: • Address mark — An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full flag, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full flag, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. • NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 213 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED 12.4.3.7 Receiver Interrupts These two sources can generate CPU interrupt requests from the SCI receiver: • SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate an SCRF CPU interrupt request or an SCRF DMA service request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables SCRF CPU interrupts. Setting both the SCRIE bit and the DMA receive enable bit, DMARE, in SCC3 enables SCRF DMA service requests. Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the PTG1/RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables IDLE CPU interrupts. AGREEMENT • 12.4.3.8 Error Interrupts The following receiver error conditions can generate CPU interrupt requests: • Receiver overrun (OR) — The OR bit in SCS1 indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The overrun interrupt enable bit, ORIE, in SCC3 enables OR CPU interrupts. Noise flag (NF) — The NF bit in SCS1 is set when the SCI detects noise on incoming data, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF CPU interrupts. Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE CPU interrupts. Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE CPU interrupts. NON-DISCLOSURE • • • Advance Information 214 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Low-Power Modes 12.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 12.5.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. 12.5.2 Stop Mode The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect SCI register states. SCI module operation resumes after an external interrupt. 12.6 SCI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 7.8.3 SIM Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 215 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. 12.7 I/O Signals Port E shares two of its pins with the SCI module. The two SCI I/O (input/output) pins are: • • PTG2/TxD — Transmit data PTG1/RxD — Receive data AGREEMENT 12.7.1 PTG2/TxD (Transmit Data) The PTG2/TxD pin is the serial data output from the SCI transmitter. 12.7.2 PTG1/RxD (Receive Data) The PTG1/RxD pin is the serial data input to the SCI receiver. NON-DISCLOSURE 12.8 I/O Registers The following I/O registers control and monitor SCI operation: • • • • • • • SCI control register 1 (SCC1) SCI control register 2 (SCC2) SCI control register 3 (SCC3) SCI status register 1 (SCS1) SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR) Advance Information 216 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module I/O Registers 12.8.1 SCI Control Register 1 SCI control register 1 (SCC1): • • • • • • • • Address: Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method Controls idle character detection Enables parity function Controls parity type $0014 Bit 7 6 ENSCI 0 5 TXINV 0 4 M 0 3 WAKE 0 2 ILTY 0 1 PEN 0 Bit 0 PTY 0 Read: LOOPS Write: Reset: 0 Figure 12-9. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode, the PTE1/RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI — Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 217 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED TXINV — Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. M — Mode (Character Length) Bit AGREEMENT This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 12-4.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE — Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the PTE1/RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY — Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit. 0 = Idle character bit count begins after start bit. NON-DISCLOSURE Advance Information 218 MC68HC(9)08PT48 — Rev. 2.0 Serial Communications Interface (SCI) Module MOTOROLA Serial Communications Interface (SCI) Module I/O Registers PEN — Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 12-4.) When enabled, the parity function inserts a parity bit in the most significant bit position. (See Figure 12-3.) Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY — Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 12-4.) Reset clears the PTY bit. 1 = Odd parity 0 = Even parity Table 12-4. Character Format Selection Control Bits M 0 1 0 0 1 1 PEN:PTY 0X 0X 10 11 10 11 Start Bits 1 1 1 1 1 1 Data Bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd Stop Bits 1 1 1 1 1 1 Character Length 10 bits 11 bits 10 bits 10 bits 11 bits 11 bits MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 219 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED 12.8.2 SCI Control Register 2 SCI control register 2 (SCC2): • Enables the following interrupts: – Transmitter interrupts – Transmission complete interrupts – Receiver interrupts – Idle line interrupts Enables the transmitter Enables the receiver Enables SCI wakeup Transmits SCI break characters AGREEMENT • • • • Address: $0015 Bit 7 6 TCIE 0 5 SCRIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0 Read: SCTIE Write: Reset: 0 NON-DISCLOSURE Figure 12-10. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables SCTE CPU interrupt requests or SCTE DMA service requests. Setting the SCTIE bit and clearing the DMA transfer enable bit, DMATE, in SCC3 enables SCTE CPU interrupt requests. Setting both the SCTIE and DMATE bits enables SCTE DMA service requests. Reset clears the SCTIE bit. 1 = SCTE CPU interrupt requests or SCTE DMA service requests enabled 0 = SCTE CPU interrupt requests or SCTE DMA service requests disabled Advance Information 220 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module I/O Registers TCIE — Transmission Complete Interrupt Enable Bit This read/write bit enables TC CPU interrupt requests. Reset clears the TCIE bit. 1 = TC CPU interrupt requests enabled 0 = TC CPU interrupt requests disabled SCRIE — SCI Receive Interrupt Enable Bit This read/write bit enables SCRF CPU interrupt requests or SCRF DMA service requests. Setting the SCRIE bit and clearing the DMA receive enable bit, DMARE, in SCC3 enables SCRF CPU interrupt requests. Setting both the SCRIE and DMARE bits enables SCRF DMA service requests. Reset clears the SCRIE bit. 1 = SCRF CPU interrupt requests or SCRF DMA service requests enabled 0 = SCRF CPU interrupt requests or SCRF DMA service requests disabled ILIE — Idle Line Interrupt Enable Bit This read/write bit enables IDLE CPU interrupt requests when the IDLE bit becomes set. Reset clears the ILIE bit. 1 = IDLE CPU interrupts enabled 0 = IDLE CPU interrupts disabled TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the PTE2/TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the PTG2/TxD returns to the idle condition (three-state). Reset clears the TE bit. 1 = Transmission enabled 0 = Transmission disabled RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 221 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. Typically, data transmitted to the receiver clears the RWU bit and returns the receiver to normal operation. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK — Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted AGREEMENT 12.8.3 SCI Control Register 3 SCI control register 3 (SCC3): • • • • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted Enables SCI receiver full (SCRF) DMA service requests Enables SCI transmitter empty (SCTE) DMA service requests Enables the following interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts – Parity error interrupts NON-DISCLOSURE Advance Information 222 MC68HC(9)08PT48 — Rev. 2.0 Serial Communications Interface (SCI) Module MOTOROLA Serial Communications Interface (SCI) Module I/O Registers Address: $0016 Bit 7 6 T8 5 DMARE 0 4 DMATE 0 3 ORIE 0 2 NEIE 0 1 FEIE 0 Bit 0 PEIE 0 Read: Write: Reset: R8 U U = Unimplemented U = Undetermined Figure 12-11. SCI Control Register 3 (SCC3) R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only bit 8 of the received character. R8 is received at the same time that the SCDR receives the other eight bits. Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write bit 8 of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. DMARE — DMA Receive Enable Bit This read/write bit enables SCI receiver full (SCRF) DMA service requests. (See 12.8.4 SCI Status Register 1.) Setting the DMARE bit disables SCRF CPU interrupt requests. Reset clears the DMARE bit. 1 = SCRF DMA service requests enabled (SCRF CPU interrupt requests disabled) 0 = SCRF DMA service requests disabled (SCRF CPU interrupt requests enabled) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 223 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED DMATE — DMA Transfer Enable Bit This read/write bit enables SCI transmitter empty (SCTE) DMA service requests. (See 12.8.4 SCI Status Register 1.) Setting the DMATE bit disables SCTE CPU interrupt requests. Reset clears DMATE. 1 = SCTE DMA service requests enabled (SCTE CPU interrupt requests disabled) 0 = SCTE DMA service requests disabled (SCTE CPU interrupt requests enabled) ORIE — Receiver Overrun Interrupt Enable Bit This read/write bit enables receiver overrun (OR) CPU interrupt requests. (See 12.8.4 SCI Status Register 1.) Reset clears ORIE. 1 = OR CPU interrupt requests enabled 0 = OR CPU interrupt requests disabled NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables receiver noise error (NE) CPU interrupt requests. (See 12.8.4 SCI Status Register 1.) Reset clears NEIE. 1 = NE CPU interrupt requests enabled 0 = NE CPU interrupt requests disabled FEIE — Receiver Framing Error Interrupt Enable Bit This read/write bit enables receiver framing error (FE) CPU interrupt requests. (See 12.8.4 SCI Status Register 1.) Reset clears FEIE. 1 = FE CPU interrupt requests enabled 0 = FE CPU interrupt requests disabled PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables receiver parity error (PE) CPU interrupt requests. (See 12.8.4 SCI Status Register 1.) Reset clears PEIE. 1 = PE CPU interrupt requests enabled 0 = PE CPU interrupt requests disabled NON-DISCLOSURE Advance Information 224 AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 Serial Communications Interface (SCI) Module MOTOROLA Serial Communications Interface (SCI) Module I/O Registers 12.8.4 SCI Status Register 1 SCI status register 1 (SCS1) contains flags to signal these conditions: • • • • • • • • Address: Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error Parity error $0017 Bit 7 6 TC 5 SCRF 4 IDLE 3 OR 2 NF 1 FE Bit 0 PE Read: Write: Reset: SCTE 1 1 0 0 0 0 0 0 = Unimplemented Figure 12-12. SCI Status Register 1 (SCS1) SCTE — SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCTE CPU interrupt request or an SCTE DMA service request. When the SCTIE bit in SCC2 is set and the DMATE bit in SCC3 is clear, SCTE generates an SCTE CPU interrupt request. With both the SCTIE and DMATE bits set, SCTE generates an SCTE DMA service request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. In DMA transfers, the DMA automatically clears the SCTE bit when it writes to the SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 225 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED TC — Transmission Complete Bit This clearable, read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates a TC CPU interrupt request if the TCIE bit in SCC2 is also set. Clear the TC bit by reading SCS1 with TC set and then writing to the SCDR. When the DMA services an SCTE DMA service request, the DMA clears the TC bit by writing to the SCDR. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF — SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCRF CPU interrupt request or an SCRF DMA service request. When the SCRIE bit in SCC2 is set and the DMARE bit in SCC3 is clear, SCRF generates an SCRF CPU interrupt request. With both the SCRIE and DMARE bits set, SCRF generates an SCRF DMA service request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. In DMA transfers, the DMA clears the SCRF bit when it reads the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an IDLE CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. Once cleared, the IDLE bit can become set again only after the SCRF bit becomes set and another idle character appears on the receiver input. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active or idle since the IDLE bit was cleared NON-DISCLOSURE Advance Information 226 AGREEMENT MC68HC(9)08PT48 — Rev. 2.0 Serial Communications Interface (SCI) Module MOTOROLA Serial Communications Interface (SCI) Module I/O Registers OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an OR CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the PTG1/RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 occurs during a stop bit time. FE generates an FE CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE — Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 227 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED 12.8.5 SCI Status Register 2 SCI status register 2 (SCS2) contains flags to signal these conditions: • • Break character detected Incoming data Address: $0018 Bit 7 6 5 4 3 2 1 BKF Bit 0 RPF AGREEMENT Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 12-13. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the PTG1/RxD pin. BKF does not generate an interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the PTG1/RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF — Reception in Progress Flag Bit This read-only bit is set during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the stop bit or when the SCI detects false start bits, usually from noise or a baud rate mismatch. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress NON-DISCLOSURE Advance Information 228 MC68HC(9)08PT48 — Rev. 2.0 Serial Communications Interface (SCI) Module MOTOROLA Serial Communications Interface (SCI) Module I/O Registers 12.8.6 SCI Data Register The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0019 Bit 7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0 Read: Write: Reset: R7 T7 Unaffected by reset Figure 12-14. SCI Data Register (SCDR) R7/T7–R0/T0 — Receive/Transmit Data Bits Reading SCDR accesses the read-only received data bits, R7–R0. Writing to SCDR writes the data to be transmitted, T7–T0. Reset has no effect on the SCI data register. 12.8.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: $001A Bit 7 6 5 SCP1 4 SCP0 0 0 3 2 SCR2 0 1 SCR1 0 Bit 0 SCR0 0 Read: Write: Reset: 0 0 0 = Unimplemented Figure 12-15. SCI Baud Rate Register (SCBR) MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 229 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 12-5. Reset clears SCP1 and SCP0. Table 12-5. SCI Baud Rate Prescaling SCP1 and SCP0 00 01 Prescaler Divisor (PD) 1 3 4 13 AGREEMENT 10 11 RCHK — SCI Rate Check This bit is only available in Test Mode. Setting this bit enables the transmitter clock to be visible on the transmit data pin instead of the transmit data. SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 12-6. Reset clears SCR2–SCR0. Table 12-6. SCI Baud Rate Selection SCR2, SCR1, and SCR0 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 NON-DISCLOSURE Advance Information 230 MC68HC(9)08PT48 — Rev. 2.0 Serial Communications Interface (SCI) Module MOTOROLA Serial Communications Interface (SCI) Module I/O Registers Use this formula to calculate the SCI baud rate: CGMOUT ÷ 2 Baud rate = ----------------------------------64 × PD × BD where: CGMOUT÷2 = bus frequency PD = prescaler divisor BD = baud rate divisor SCI_BDSRC is an input to the SCI. Normally, it will be tied off low at the top level to select CGMXLCK as the clock source. If it is tied off high, it will select IT12 as the clock source. This makes the formula: IT12 Baud rate = ----------------------------------64 × PD × BD Table 12-7 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Serial Communications Interface (SCI) Module Advance Information 231 NON-DISCLOSURE AGREEMENT REQUIRED Serial Communications Interface (SCI) Module REQUIRED Table 12-7. SCI Baud Rate Selection Examples SCP1 and SCP0 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Prescaler Divisor (PD) 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR2, SCR1, and SCR0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 Baud Rate (CGMXCLK ÷ 2 = 0.8192 MHz) 12,800 6400 3200 1600 800 400 200 100 4267 2133 1067 533 267 133 67 33 3200 1600 800 400 200 100 50 25 984 492 246 123 62 31 15 8 NON-DISCLOSURE AGREEMENT Advance Information 232 Serial Communications Interface (SCI) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Advance Information — MC68HC(9)08PT48 Section 13. Analog-to-Digital Converter (ADC) Module 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 13.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 13.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 13.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 13.4.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 13.4.5 Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .236 13.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 13.7.1 ADC Analog Power Pin (VDDA2) . . . . . . . . . . . . . . . . . . . .237 13.7.2 ADC Analog Ground Pin (VSSA2) . . . . . . . . . . . . . . . . . . .238 13.7.3 ADC Voltage Reference Pin (VRH) . . . . . . . . . . . . . . . . . .238 13.7.4 ADC Voltage In (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . .238 13.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 13.8.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . .238 13.8.2 ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 13.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 13.2 Introduction This section describes the 8-bit analog-to-digital converter (ADC). MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Analog-to-Digital Converter (ADC) Module Advance Information 233 NON-DISCLOSURE AGREEMENT REQUIRED Analog-to-Digital Converter (ADC) Module REQUIRED 13.3 Features Features include: • • • • • • Four channels with multiplexed input Linear successive approximation 8-bit resolution Single or continous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock AGREEMENT 13.4 Functional Description Four pins for sampling external sources are located at pins PTE7/AD3–PTE4/AD0. An analog multiplexer allows the single ADC to select one of four ADC channels as ADC voltage input (ADVIN). ADVIN is converted by the successive approximation register based ADC. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. (See Figure 13-1.) NON-DISCLOSURE NOTE: References to DMA and associated functions are only valid if the MCU has a DMA module. If the MCU has no DMA, any DMA-related register bits should be left in their reset state for expected MCU operation. 13.4.1 ADC Port I/O Pins PTE7/AD3–PTE4/AD0 are general-purpose input/output (I/O) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any effect on the port pin that is selected by the ADC. A read of a port pin which is in use by the ADC will return a logic 0. Advance Information 234 Analog-to-Digital Converter (ADC) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Analog-to-Digital Converter (ADC) Module Functional Description INTERNAL DATA BUS READ DDRE WRITE DDRE RESET WRITE PTE DDREx PTEx DISABLE PTEx (ADC CHANNEL x) READ PTE ADC DATA REGISTER CONVERSION INTERRUPT COMPLETE LOGIC ADC ADC VOLTAGE IN ADCH[4:0] (ADVIN) CHANNEL SELECT AIEN COCO/IDMAS ADC CLOCK CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV[2:0] ADICLK Figure 13-1. ADC Block Diagram 13.4.2 Voltage Conversion When the input voltage to the ADC equals VRH, the ADC converts the signal to $FF (full scale). If the input voltage equals AVSS, the ADC converts it to $00. Input voltages between VRH and AVSS are a straightline linear conversion. All other input voltages will result in $FF, if greater than VRH. NOTE: Input voltage should not exceed the analog supply voltages. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Analog-to-Digital Converter (ADC) Module Advance Information 235 NON-DISCLOSURE AGREEMENT DISABLE REQUIRED Analog-to-Digital Converter (ADC) Module REQUIRED 13.4.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). Conversion time in terms of the number of bus cycles is a function of oscillator frequency, bus frequency, and ADIV prescaler bits. For example, with bus frequency of 4 MHz and ADC clock frequency of 1 MHz, one conversion will take between 16 ADC and 17 ADC clock cycles or between 16 µs and 17 µs. There will be 128 bus cycles between each conversion. Sample rate is approximately 30 kHz. Conversion time = 16–17 ADC cycles ADC frequency # Bus cycles = conversion time x bus frequency AGREEMENT 13.4.4 Conversion In the continuous conversion mode, the ADC data register (ADR) will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO/IDMAS bit is set after the first conversion and will stay set until the next write of the ADSCR or the next read of the ADR. In the single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs between writes to the ADSCR. NON-DISCLOSURE 13.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. 13.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating either CPU or DMA interrupts after each ADC conversion. A CPU interrupt is generated if the COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt is generated. The Advance Information 236 Analog-to-Digital Converter (ADC) Module MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Analog-to-Digital Converter (ADC) Module Low-Power Modes COCO/IDMAS bit is not used as a conversion complete flag when interrupts are enabled. 13.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low powerconsumption standby modes. The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4–ADCH0 bits in the ADSCR before executing the WAIT instruction. 13.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. 13.7 I/O Signals The ADC module has four pins shared with port E. 13.7.1 ADC Analog Power Pin (VDDA2) The ADC analog portion uses AVDD as its power pin. Connect the VDDA2 pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA2 for good results. NOTE: Route AVDD carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. MC68HC(9)08PT48 — Rev. 2.0 MOTOROLA Analog-to-Digital Converter (ADC) Module Advance Information 237 NON-DISCLOSURE AGREEMENT 13.6.1 Wait Mode REQUIRED Analog-to-Digital Converter (ADC) Module REQUIRED 13.7.2 ADC Analog Ground Pin (VSSA2) The ADC analog portion uses AVSS as its ground pin. Connect the VSSA2 pin to the same voltage potential as VSS. 13.7.3 ADC Voltage Reference Pin (VRH) VRH is the power supply for setting the reference voltage VRH. Connect the VRH pin to a voltage potential