900844

Freescale Semiconductor Advance Information Document Number: SC900844 Rev. 2.0, 5/2011 Integrated Power Management IC for Ultra-mobile and Embedded Applications The 900844 is a high efficiency Power Management Integrated Circuit (PMIC) capable of providing operating voltages for Ultra-mobile platforms for Netbook, Tablets, and embedded devices through its 20 voltage rails. It has 5 switching power supplies running at frequencies from 1.0 to 4.0 MHz,14 highly efficient LDOs, and one 3.3 V power switch. It incorporates a 10-bit ADC, Real Time Clock, 8 GPIOs and 8 GPOs. The 900844 is fully configurable and controllable through its SPI interface. It provides an optimized power management solution for ultramobile platforms used on netbooks, tablets, and slates. Optimum partitioning, high feature integration, and state-of-the-art technology, allow Freescale to effectively serve this growing market segment. Features • Main system power management integrated in a single chip • Fully programmable DC/DC switching, low drop-out regulators, and load switches • SPI interface (up to 25 MHz operation) • 10-bit ADC for internal and external sensing with touch screen interface • Real time clock (RTC) • 8 Interrupt capable GPIOs and 8 GPOs • I/O interrupt and reset controller 900844 POWER MANAGEMENT 98ASA10841D 11 mm x 11 mm 338-MAPBGA ORDERING INFORMATION Device SC900844JVK Temperature Range (TA) -40 °C to 85 °C Package 338-MAPBGA Applications • Netbooks • Tablet PC • Slates • Embedded Devices Freescale PMIC 900844 CORE PMIC VR VR VPWR ADC Inputs ADC / Touch Screen Inputs GPIO / GPO SPI Control System Control Interface 3-4 Cell Battery Pack Charger PWR SW 5 x DC/DC Converters 14 x LDOS 1 x 3.3 V Power Switch Input Power Path Core Rail CPU (central processing unit) Platform controller hub 3VA 3.3 V SMPS I/O Rails 1.8 V SMPS 5.0 V SMPS Memory Rails 5VA 19 V ADP Display EC CAM Memory Backlight SATA USB Ultra-mobile Platform Figure 1. 900844 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010-2011. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM REFGNDCHG VCOREDIG VCOREREF VCORE LDOREFP9 LDOREFP8 GNDCORE PGNDBKLT COINCELL GNDBKLT GNDLED VNTC VBAT NTC VPWR .... GNDBAT Power Path Manager Li-Cell Charger Power Fail Detect GPO Control GPIO Control Reference Generation REFGNDSW GNDREFVCC PVINCC CSPCC VCC 3600mA Output Driver HSCCGT SWFBCC LSCCGT PGNDCC VOUTFBCC PVINNN CSPNN VNN 1600mA Buck Output Driver HSNNGT SWFBNN LSNNGT PGNDNN VOUTFBNN Li-Cell Switch Voltage / Current Sensing /& Translation ADIN21 ADIN20 ADIN19 ADIN18 ADIN17 ADIN16 ADIN15 ADIN14 ADIN13 ADIN12 ADIN11 ADIN10 TSREF GNDADC SPIVCC SPICSB SPICLK MOSI MISO GNDSPI GNDAUD1 GNDAUD2 GNDAUD3 GNDAUD4 GNDRTC XTAL1 XTAL2 CLK32K 32.768KHz Crystal OSC VPWR VID[6:0] MUX 10 Bit ADC Shift Register VIDEN[1:0] A/D Control Trigger Handling Thermal Protection Shift Register SPI Interface SPI Control SPI Registers Control Trim Startup Sequencer VID Controller Buck Touch Screen Interface GNDSUB31 GNDSUB32 PGNDCHG ISNSBATN ISNSBATP GNDSUB1 GNDSUB2 GNDSUB3 PVINVIB GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 GPO0 GPOVCC GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIOVCC VDDQ 1500mA Buck Output Driver PVINDDQ SWDDQ PGNDDDQ FBDDQ Shift Register V21 1000mA Buck Output Driver PVIN21 SW21 PGND21 FB21 SC900844 900844 32.768KHz Internal OSC Timers SPI Registers V15 1500mA Buck Output Driver PVIN15 SW15 PGND15 FB15 GNDCTRL ICTEST VIDEN0 VIDEN1 VID0 VID1 VID2 VID3 VID4 VID5 VID6 THERMTRIPB PWRGD RESETB VRCOMP PMICINT EXITSTBY PWRBTN Package Pin Legend Output pin SC900844 Input pin Bi-directional pin System & Peripheral Interface RTC Calibration PLL VPNL33 SWITCH VCCPAOAC LDO VYMXYFI18 LDO VCCPDDR LDO VSDIO LDO / SWITCH Switchers VCC180 LDO VPNL18 LDO VIMG28 LDO VIMG25 LDO VPMIC LDO VAON LDO VCCP LDO VCCA LDO VMM LDO VBG LDO Enables & Control GNDCOMS1 GNDCOMS2 VOUTPNL33 Figure 2. 900844 Internal Block Diagram PVIN3P3 FBSDIO SDIOGT GNDIMG VOUTIMG28 PVINIMG VOUTIMG25 FBCCP GND1P5 VOUTCCP VOUTMM VOUTAON FBCCPDDR VOUTCCPDDR VOUTCCPAOAC PVIN1P5 VOUTYMXYFI18 PVINYMXYFI18 VOUTPMIC GND2P1 VOUTPNL18 PVIN2P1 VOUTCC180 GND1P8 VOUTCCA FBCCA PVIN1P8 VOUTBG 900844 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM PIN OUT DESCRIPTION AND BALL MAP Refer to Pin Description for a detailed list of pins and ball assignments. The ball map of the package is given in Figure 3 as a top view. The BGA footprint on the application PCB will have the same mapping as given in Figure 3. 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ NC3 NC3 VOUTYM XYFI18 NC SW15 PVIN21 PGND21 PGNDYM X3G SWDDQ HSNNGT PGNDCC CSPCC VID2 NC1 NC1 2 3 NC1 4 5 PVIN1P5 6 7 FBCCP 8 9 NC 10 11 PVIN2P1 12 13 VOUTPNL 18 14 15 SPICLK 16 17 NC 18 19 GNDLSP R 20 21 GNDLSPL 22 23 NC 24 25 NC 26 27 NC2 28 29 NC2 NC1 VOUTCC PAOAC VOUTCC A LDOREFP 8 VOUTAO N CS VOUTPMI C VOUTCC P VOUTCC 180 VCORER EF VCORE PMICINT VINLSPR NC NC NC NC NC2 PVIN1P5 PVIN2P1 RESETB NC VYMXPA EN VINLSPL NC NC2 VOUTBG VIDEN0 PVIN1P8 SPICSB NC NC NC VID0 VIDEN1 FBCCA NC GNDCP NC VID6 VID4 NC SWFBCC FBCCPD DR VOUTCC PDDR PWRBTN LDOREFP 9 GNDCOR E VCOREDI G MOSI THERMT RIPB NC GNDAUD 4 GNDAUD 1 NC GNDAUD XTAL LSCCGT LSCCGT VID1 GND1P5 SCK VRCOMP GNDSUB NC GNDSUB NC RX2 PGNDCC VID5 VID3 VOUTMM MISO EXITSTB Y GNDSUB GNDSUB GNDSUB FS2 BCL2 HSCCGT HSCCGT VOUTFB CC GNDREF VCC GNDAUD 2 NC NC BCL1 PVINNN PVINCC PVINCC PGNDNN GNDSPI SPIVCC GNDSUB GNDSUB RX1 I2SVCC FS1 NC LSNNGT VOUTFB NN PGNDDD Q PGNDDD Q PGNDDD Q PGNDDD Q GND2P1 GNDSUB PWRGD GNDSUB NC GNDSP SWDDQ SWFBNN CSPNN GND1P8 GNDSUB GNDSUB GNDSUB NC NC NC NC SWDDQ SWDDQ PVINDDQ PVINDDQ GNDSUB GNDSUB GNDSUB GNDSUB NC NC NC PGNDYM X3G PVINDDQ PVINDDQ FBDDQ GNDSUB GNDSUB GNDSUB GNDSUB GNDAUD 3 NC ICTEST NC GNDLED NC NC NC NC GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB NC NC PGND21 PGND21 REFGND SW NC GNDSUB GNDSUB GNDSUB GNDSUB GNDSUB NC NC NC NC NC SW21 SW21 SW21 FB21 GNDSUB GNDIMG GNDADC GNDSUB NC NC PGNDOT G PGNDOT G PVIN21 PVIN21 FB15 GNDCOM S2 NC ADIN20 TSREF NC NC NC NC NC NC PGND15 PGND15 PGND15 GPO4 NC PGNDBK LT PGNDBK LT SW15 SW15 GNDCOM S1 NC GPIO3 NC NC ADIN13 NC GNDBAT NC NC NC NC PVIN15 PVIN15 PVIN15 GPO7 GPIO1 SDIOGT GNDCTR L ADIN11 GPIO6 NC NC VPWR GNDBKLT NC GPO1 NC GPIOVCC FBSDIO ADIN21 ADIN15 GPIO4 REFGND CHG NTC CHGBYP GT ISNSBAT P VBAT COINCEL L PVINYMX YFI18 GPO2 PGNDYM XPA NC NC NC GPOVCC NC ADIN14 NC NC NC CHGGT VNTC NC GPO0 NC PGNDYM XPA VOUTPNL 33 VOUTIMG 28 VOUTIMG 25 XTAL2 GPIO5 NC NC PGNDCH G ISNSBAT N GPO3 GPO6 GPIO0 NC PVINVIB ADIN16 XTAL1 GPIO7 RAWCHG NC NC NC4 NC3 GPO5 NC NC NC PGNDYM XPA ADIN19 ADIN17 ADIN10 CLK32K NC PGNDCH G NC4 NC3 NC GPIO2 PVIN3P3 NC NC PVINIMG ADIN18 ADIN12 GNDRTC NC NC NC4 NC4 Figure 3. 900844 Package Ball Map 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 3 INTERNAL BLOCK DIAGRAM PIN DESCRIPTION The Type Column indicates the maximum average current through each ball assigned to the different nodes, 500 mA maximum for HIPWR, 300 mA maximum for MDPWR, and 100 mA maximum for LOPWR Table 1. 900844 Pin Description Node Name Type I/O Rating # of Balls BGA Location Pin Description VCC - (0.65 V-1.2 V) / 3.5 A VID CPU BUCK with External FETs PVINCC HSCCGT LSCCGT PGNDCC VOUTFBCC SWFBCC CSPCC HIPWR HIPWR HIPWR HIPWRGND SGNL SGNL SGNL I I I 4.8 V 4.8 V 4.8 V 4.8 V 3.6 V 3.6 V 2 2 2 2 1 1 1 L5, L7 K2, K4 H2, H4 J1, J3 K8 G3 G1 Gate drivers power supply input High side FET gate drive Low side FET gate drive Local ground for internal circuitry Output voltage sensing input and negative current sense terminal Switch node feedback Positive current sense terminal VNN - (0.65 V-1.2 V) / 1.6 A VID CPU BUCK with External FETs PVINNN HSNNGT LSNNGT PGNDNN VOUTFBNN SWFBNN CSPNN HIPWR HIPWR HIPWR HIPWRGND SGNL SGNL SGNL I I I 4.8 V 4.8 V 4.8 V 4.8 V 3.6 V 3.6 V 1 1 1 1 1 1 1 L3 L1 M2 L9 M4 N9 N11 Gate drivers power supply input High side FET gate drive Low side FET gate drive Local ground for internal circuitry Output voltage sensing input and negative current sense terminal Switch node feedback Positive current sense terminal VDDQ - 1.8 V / 1.3 A BUCK PVINDDQ SWDDQ PGNDDDQ FBDDQ HIPWR HIPWR HIPWRGND SGNL I 4.8 V 4.8 V 3.6 V 4 4 4 1 P6, P8, R5, R7 N1, N3, P2, P4 M6, M8, N5, N7 R9 Power supply input Switch node Power ground Output voltage feedback input V21 - 2.1 V / 1.0 A BUCK PVIN21 SW21 PGND21 FB21 HIPWR HIPWR HIPWRGND SGNL I 4.8 V 4.8 V 3.6 V 3 3 3 1 W1, W3, W5 V2, V4, V6 U1, U3, U5 V8 Power supply input Switch node Power ground Output voltage feedback input V15 - 1.5 V (or 1.6 V) / 1.5 A BUCK PVIN15 SW15 PGND15 FB15 HIPWR HIPWR HIPWRGND SGNL I 4.8 V 4.8 V 3.6 V 3 3 3 1 AB2, AB4, AB6 AA1, AA3, AA5 Y2, Y4, Y6 W7 Power supply input Switch node Power ground Output voltage feedback input 900844 4 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM Table 1. 900844 Pin Description Node Name Type I/O Rating # of Balls BGA Location Pin Description VBG - 1.25 V/2 mA LDO VCCA - 1.5 V/150 mA LDO PVIN1P8 GND1P8 VOUTBG VOUTCCA FBCCA LOPWR GND LOPWR LOPWR SGNL I 3.6 V 2.5 V 2.5 V 2.5 V 1 1 1 1 1 D6 N13 D2 C3 E7 Power supply input, shared by VBG and VCCA Ground reference VBG output voltage node VCCA output voltage node VCCA output voltage feedback input VCC180- 1.8 V/390 mA LDO VPNL18- 1.8 V/225 mA LDO VPMIC - 1.8 V/50 mA LDO PVIN2P1 GND2P1 VOUTCC180 VOUTPNL18 VOUTPMIC HIPWR GND HIPWR MDPWR LOPWR 3.6 V 2.5 V 2.5 V 2.5 V 2 1 1 1 1 A11, C11 M12 B12 A13 B10 Power supply input, shared by VCC180, VPNL18, and VPMIC Ground reference VCC180 output voltage node VPNL18 output voltage node VPMIC output voltage node VYMXYFI18 - (YMX:1.8 V/200 mA - YFI:1.8 V/200 mA) LDO PVINYMXYFI18 VOUTYMXYFI18 GNDCOMS1 GNDCOMS2 MDPWR MDPWR GND GND 4.8 V 3.6 V 1 1 1 1 AD2 AE1 AA7 W11 Power supply input for VYMXYFI18 VYMXYFI18 output voltage node Ground reference Ground reference VCCPAOAC- 1.05 V/155 mA LDO VCCPDDR - 1.05 V/60 mA LDO VAON - 1.2 V/250 mA LDO VMM- 1.2 V/5 mA LDO VCCP - 1.05 V/445 mA LDO PVIN1P5 GND1P5 VOUTCCPAOAC VOUTCCPDDR FBCCPDDR VOUTAON VOUTMM VOUTCCP FBCCP HIPWR GND LOPWR LOPWR SGNL MDPWR LOPWR HIPWR SGNL I I 3.6 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2 1 1 1 1 1 1 1 1 A5, C5 H10 B4 G9 G7 C7 J11 C9 A7 Power supply input, shared by VCCPAOAC, VCCPDDR, VAON, VMM, and VCCP Ground reference VCCPAOAC output voltage node VCCPDDR output voltage node VCCPDDR output voltage feedback input VAON output voltage node VMM output voltage node VCCP output voltage node VCCP output voltage feedback input VIMG25- 2.5 V/80 mA LDO VIMG28- 2.8 V/225 mA LDO PVINIMG GNDIMG VOUTIMG25 MDPWR GND LOPWR 4.8 V 3.6 V 1 1 1 AJ15 V14 AH14 Power supply input, shared by VIMG25 and VIMG28 Ground reference VIMG25 output voltage node 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 5 INTERNAL BLOCK DIAGRAM Table 1. 900844 Pin Description Node Name VOUTIMG28 Type MDPWR I/O Rating 3.6 V # of Balls 1 BGA Location AG15 Pin Description VIMG28 output voltage node VPNL33 - 3.3 V/100 mA Switch PVIN3P3 VOUTPNL33 MDPWR LOPWR 3.6 V 3.6 V 1 1 AJ9 AG9 Power supply input, shared by VPNL33 and VSDIO VPNL33 output voltage node VSDIO - 3.3 V/215 mA Switch OR 1.8 V/215 mA LDO SDIOGT FBSDIO LOPWR SGNL 3.6 V 3.6 V 1 1 AB12 AC13 Internal Supplies VCORE VCOREDIG VCOREREF LDOREFP8 LDOREFP9 GNDCORE LOPWR LOPWR LOPWR LOPWR LOPWR LOPWRGND 3.6 V 1.5 V 3.6 V 3.6 V 3.6 V 1 1 1 1 1 1 B14 J13 C13 B6 G13 H14 Input Power Path VPWR VBAT GNDBAT VNTC NTC ISNSBATP ISNSBATN PVINVIB MDPWR LOPWR LOPWRGND LOPWR SGNL SGNL SGNL MDPWR I I I 4.8 V 4.8 V 3.6 V 3.6 V 4.8 V 4.8 V 4.8 V 1 1 1 1 1 1 1 1 AB26 AC27 AA21 AE29 AC23 AD26 AF28 AG13 Coin Cell Charger COINCELL LOPWR 3.6 V 1 AC29 ADC + TS I/F ADIN10 ADIN11 ADIN12 ADIN13 ADIN14 ADIN15 ADIN16 ADIN17 SGNL SGNL SGNL SGNL SGNL SGNL SGNL SGNL I I I I I I I I 4.8 V 4.8 V 4.8 V 4.8 V 4.8 V 4.8 V 4.8 V 4.8 V 1 1 1 1 1 1 1 1 AH20 AB16 AJ19 AA17 AE17 AC17 AG17 AH18 ADC generic input 1, used as touchscreen input X1, TSX1 ADC generic input 2, used as touchscreen input X2, TSX2 ADC generic input 3, used as touchscreen input Y1, TSY1 ADC generic input 4, used as touchscreen input Y2, TSY2 ADC generic input 5 ADC generic input 6 ADC generic input 7 ADC generic input 8 Coin cell supply input, coin cell charger output Input power node for PMIC Battery voltage sensing input Input supply ground Bias voltage for NTC resistor stack NTC connection node Connect to VBAT Connect to VBAT Always connect to VPWR Internal supply output voltage node Internal supply output voltage node Internal band gap supply output voltage node Internal divided down band gap supply output voltage node dedicated for LDOs Internal divided down band gap supply output voltage node dedicated for LDOs Ground for internal supplies Gate driver output for VSDIO pass FET Feedback node when VSDIO is in Switch mode; Output voltage node when VSDIO is in LDO mode. 900844 6 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM Table 1. 900844 Pin Description Node Name ADIN18 ADIN19 ADIN20 ADIN21 TSREF GNDADC Type SGNL SGNL SGNL SGNL LOPWR LOPWRGND I/O I I I I Rating 4.8 V 4.8 V 4.8 V 4.8 V 3.6 V # of Balls 1 1 1 1 1 1 BGA Location AJ17 AH16 W15 AC15 W17 V16 ADC generic input 9 ADC generic input 10 ADC generic input 11 ADC generic input 12 Reference for touchscreen interface Ground reference for ADC Pin Description Oscillator and Real Time Clock - RTC XTAL1 XTAL2 CLK32K GNDRTC SGNL SGNL SGNL GND I O O 2.5 V 2.5 V 3.6 V 1 1 1 1 AG19 AF18 AH22 AJ21 32.768 kHz oscillator crystal connection 1 32.768 kHz oscillator crystal connection 2 32 kHz clock output Ground for the RTC block Platform Architecture Sideband Signals PMICINT SGNL O 2.5 V 1 B16 PMIC Interrupt. Asserted by PMIC to wake platform controller hub and begin communications. Level-sensitive, read to clear. Voltage regulator complete. Asserted high by the PMIC when a SPI voltage regulation request has been decoded. The signal is de-asserted on completion of the request (i.e. the rail is in regulation). Active low hard reset for platform controller hub. When asserted, the platform controller hub should return to its initial default state. POWER GOOD: The 900844 asserts this signal to indicate that all power rails to the platform controller hub are good. Assertion of PWRGD also means that VCCA_OSC has been valid for at least 30 microseconds. The Platform Controller Hub will remain “off” until this signal is asserted. EXIT Standby. When asserted, the 900844 exits the AOAC standby settings for regulating the platform supplies. When asserted, the 900844 switches VRs on which are defined in registers 0x09 through 0x0D. This is a low latency VR context switch. Thermal trip. Asserted by the CPU to indicate a catastrophic thermal event. Driven by the CPU to indicate which VR the VID bus is addressed to (VCC or VNN). Debounced inside the 900844 for 150 ns. The CPU will hold the value for at least 300 ns. VRCOMP SGNL O 2.5 V 1 H16 RESETB SGNL O 2.5 V 1 C15 PWRGD SGNL O 2.5 V 1 M16 EXITSTBY SGNL I 2.5 V 1 J17 THERMTRIPB VIDEN0 VIDEN1 VID0 VID1 VID2 VID3 VID4 VID5 VID6 GNDCTRL SGNL SGNL SGNL SGNL SGNL SGNL SGNL SGNL SGNL SGNL GND I I I I I I I I I I - 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V - 1 1 1 1 1 1 1 1 1 1 1 G17 D4 E5 E3 H8 E1 J9 F4 J7 F2 AB14 Driven by the CPU to indicate the output voltage setting for the VCC and VNN rails. Debounced inside the 900844 for 150 ns. The CPU will hold the value for at least 300 ns. Logic Control Ground 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 7 INTERNAL BLOCK DIAGRAM Table 1. 900844 Pin Description Node Name Type I/O Rating # of Balls BGA Location SPI Interface SPIVCC SPICLK MOSI MISO SPICSB GNDSPI LOPWR SGNL SGNL SGNL SGNL GND I I O I 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 1 1 1 1 1 1 L15 A15 G15 J15 D14 L13 Supply for SPI Bus SPI Clock Input SPI write input SPI read output SPI chip select input Ground for SPI interface Pin Description GPIOs & GPOs & Power Button GPIOVCC GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPOVCC GPO0 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 PWRBTN LOPWR SGNL SGNL SGNL SGNL SGNL SGNL SGNL SGNL LOPWR SGNL SGNL SGNL SGNL SGNL SGNL SGNL SGNL SGNL I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O I 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 1.5 V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AC11 AG7 AB10 AJ7 AA11 AC19 AF20 AB18 AG21 AE5 AF4 AC7 AD4 AG3 Y8 AH4 AG5 AB8 G11 Test Pins ICTEST SGNL I 7.5 V 1 R23 Reference Supplies VINLSPR VINLSPL I2SVCC MDPWR MDPWR LOPWR 5.5V 5.5V 3.6 V 1 1 1 B18 C21 L25 Always connect to VPWR Always connect to VPWR Always connect to VPMIC Always connect to GND PMIC hardware on/off button General purpose outputs GPO power Fully configurable GPIO inputs/outputs for general purpose sensing and platform control GPIO power 900844 8 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM Table 1. 900844 Pin Description Node Name Type I/O Rating # of Balls BGA Location Ground References PGNDCHG BCL1 FS1 RX1 BCL2 FS2 RX2 SCK GNDSP GNDLSPR GNDLSPL GNDCP PGNDYMXPA PGNDYMX3G PGNDOTG PGNDBKLT GNDAUDXTAL GNDAUD1 GNDAUD2 GNDAUD3 GNDAUD4 GNDBKLT GNDLED REFGNDCHG REFGNDSW GNDREFVCC GNDSUB HIPWRGND SGNL SGNL SGNL SGNL SGNL SGNL SGNL LOPWRGND MDPWRGND MDPWRGND LOPWRGND HIPWRGND HIPWRGND HIPWRGND HIPWRGND GND GND GND GND GND GND GND GND GND GND GND I/O I/O I I/O I/O I I 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 2 1 1 1 1 1 1 1 1 1 1 1 3 2 2 2 1 1 1 1 1 1 1 1 1 1 32 AF26, AH26 K28 L27 L23 J29 J27 H28 H12 M28 A19 A21 E27 Power GND Always connect to GND Always connect to GND Always connect to GND Always connect to GND Always connect to GND Always connect to GND Always connect to GND Analog GND Analog GND Analog GND Analog GND Pin Description AD12, AF12, AH12 Power GND R1, R3 V26, V28 Y26, Y28 G29 G23 L21 R19 G21 AB28 R29 AC21 U7 L11 H18, H22, J19, J21, J23, L17, L19, M14, M18, N15, N17, N19, P12, P14, P16, P18, R11, R13, R15, R17, T12, T14, T16, T18, T22, U11, U13, U15, U17, U19, V12, V18 Power GND Power GND Power GND Analog GND Analog GND Analog GND Analog GND Analog GND Analog GND Analog GND Dedicated reference ground for the input power path Dedicated reference ground for the switching regulators Dedicated reference ground for VCC regulator Substrate GND 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 9 INTERNAL BLOCK DIAGRAM Table 1. 900844 Pin Description Node Name Type I/O Rating # of Balls BGA Location Reserved RAWCHG CHGBYPGT CHGGT VYMXPAEN CS MDPWR MDPWR MDPWR SGNL SGNL I I 20 V 4.8 V 4.8 V 2.5 V 3.6 V 1 1 1 1 1 AG23 AC25 AE27 C19 B8 Reserved - Do not connect Reserved - Do not connect Reserved - Do not connect Reserved - Do not connect Reserved - Do not connect Pin Description Notes 1. The Type Column indicates the maximum average current through each ball assigned to the different nodes. 500 mA maximum for HIPWR, 300 mA maximum for MDPWR, and 100 mA maximum for LOPWR 900844 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section. Ratings ELECTRICAL RATINGS Input Voltage Coin Cell Voltage ESD Rating, All Pins, Human Body Model (HBM) (4) (4), (5) Symbol Value Unit VESDHBM VESDCDM -0.3 to +4.4 -0.3 to +3.6 ±2000 ±450 V V V V ESD Rating, All Pins, Charge Device Model (CDM) THERMAL RATINGS Ambient Operating Temperature Range Operating Junction Temperature Range Storage Temperature Range Peak Package Reflow Temperature POWER RATINGS Hard Mechanical Off (2), (3) TA TJ TST TPPRT -40 to +85 -30 to +125 -65 to +150 260 °C °C °C °C mW 0 mW 5.0 mW 100 There is no Valid VBAT voltage connected to the 900844, BATDET = 0 Soft Mechanical Off The 900844 has input power from 3.3 V Supply into VBAT. All VRs are programmed “OFF”, BATDET = 1 Power On The 900844 has input power from 3.3 V supply into VBAT. The cold-boot rails are “ON”. V21 = 2.1 V, V15 = 1.5 V, VAON = 1.2 V, VCCPAOAC = 1.05 V, VPMIC = 1.8 V, All VR outputs are set in PFM or APS mode driving purely capacitive loads. BATDET = 1 Notes 2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 3. Freescale's Package Reflow capability meets the Pb-free requirements for JEDEC standard J-STD-020C, for Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL) 4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 5. All pins meet 500 V CDM except VCOREREF. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS POWER DISSIPATION During operation, the temperature of the die must not exceed the maximum junction temperature. Depending on the operating ambient temperature and the total internal dissipation this limit can be exceeded. To optimize the thermal management scheme and avoid overheating, the 900844 provides a thermal management system that protects against overheating. This protection should be considered as a fail-safe mechanism, and the application design should initiate thermal shutdown under normal conditions. Reference Thermal Management for more details. POWER CONSUMPTION Table 2 defines the maximum power consumption specifications in the various system and device states. For each entry in the table, the component is assumed to be configured for driving purely capacitive loads, and the voltages listed in each entry are nominal output voltages. Note that the “Soft Mechanical Off” state is a transitional state. The device will spend less than 150 µs in this state before V15 starts to turn on, upon detection of a valid input voltage. 900844 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic SYSTEM CONTROL INTERFACE Input Low Voltage EXITSTBY, VID[6:0] THRMTRIPB, VIDEN[1:0] Input High Voltage EXITSTBY, VID[6:0] THRMTRIPB, VIDEN[1:0] Output Low Voltage PMICINT, VRCOMP, RESETB, PWRGD. Output High Voltage PMICINT, VRCOMP, RESETB, PWRGD. SPI INTERFACE LOGIC IO Operating Voltage Range (SPIVCC Pin) Input High SPICSB, MOSI, SPICLK Input Low SPICSB, MOSI, SPICLK Output Low MISO (Output sink 100 µA) Output High MISO (Output source 100 µA) OSCILLATOR AND CLOCK OUTPUTS MAIN CHARACTERISTICS Operating Voltage RTC OSC Consumption Current (RTC Mode: All blocks disabled, no main battery attached, coin cell is attached to COINCELL) Output Low CLK32K (Output sink 100 µA) Output High CLK32K (Output source 100 µA) CLK32K Output Duty Cycle RTC Input Voltage Range Consumption Current Crystal OSC Frequency Tolerance Crystal OSC Peak Temperature Frequency (Turn Over Temperature) Crystal OSC Maximum Series Resistance Crystal OSC Maximum Drive Level 1.2 -30 20 15 25 80 0.5 1.5 25 +30 30 V µA ppm °C KΩ µW 1.2 0 VSPIVCC 0.1 40 1.0 50 1.5 2.0 0.1 VSPIVCC 60 V µA V V % VSPIVCC 1.74 0.7* VSPIVCC 0 0 VSPIVCC -0.1 1.8 3.1 VSPIVCC +0.3 0.3* VSPIVCC 0.1 VSPIVCC V V V V V VOH VPMIC - 0.1 VPMIC VOL 0 0.1 V VIH 0.7*VCCP 0.7*VCCPA OAC Symbol Min Typ Max Unit VIL 0 0 0.3*VCCP 0.3*VCCPA OAC V V VCCP VCCPAOAC V 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic Crystal OSC Operating Drive Level Crystal OSC Nominal Lead Capacitance Crystal OSC Aging COIN CELL CHARGER Coin cell Charge Voltage (Selectable through VCOIN[2:0] bits) Coin cell Charge Voltage Accuracy Coin cell Charge Current Coin cell Charge Current Accuracy POWER STATES DETECTION THRESHOLDS Battery Cutoff Threshold (Depending on Battery Model) Coin Cell Disconnect Threshold Low Battery Threshold Valid Battery Threshold VPWR Rising Under-voltage Threshold VPWR Falling Under-voltage Threshold VCC ELECTRICAL CHARACTERISTICS Input Voltage Range Extended Input Voltage Range Output Voltage Programmability Range Low Power Mode Active Mode Output Voltage Programmability Step Size Output Voltage Accuracy 0.6 V < VCC < 12 V, 1.5 A < ICC < 3.5 A 0.6 V < VCC < 12 V, ICC < 1.5 A 0.3 V < VCC < 0.6 V Output Voltage Overshoot Maximum overshoot voltage above VID setting voltage. Maximum overshoot time is 10-30 s, output voltage = 0.9 V at 50 mA Continuous Output Load Current Low Power mode Active Mode Peak Current Limit Output Current Limit Accuracy Transient Load Change Low Power Mode Active Mode ILIMCC ΔICC 0.2 1.2 ICC 0.2 5.0 ±15 0.2 3.5 A % A VOS 50 A -5.0 -4.0 -7.0 5.0 4.0 7.0 mV VPWR VPWR VCC 0.3 0.65 12.5 0.7 1.2 mV % 3.0 2.8 3.6 3.6 4.4 4.7 V V V VBATOFF VCOINOFF VLOWBAT VTRKL VPWRUVR VPWRUVF 2.2 1.8 3.2 3.0 3.1 2.55 2.4 2.0 V V V V V V VCOINCELL ICOIN 2.5 -100 -15 60 3.3 100 15 V mV µA % Symbol Min 0.25 Typ 9.0 Max 0.5 3.0 Unit µW pF ppm/year 900844 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic VNN ELECTRICAL CHARACTERISTICS Input Voltage Range Extended Input Voltage Range Output Voltage Programmability Range (Set by VID Control Signals) Output Voltage Programmability Step Size Output Voltage Accuracy Output Voltage Overshoot Maximum overshoot voltage above VID setting voltage. Maximum overshoot time is 10 s, output voltage = 0.9 V at 50 mA Continuous Output Load Current Low Power Mode Active Mode Peak Current Limit Output Current Limit Accuracy Transient Load Change VDDQ ELECTRICAL CHARACTERISTICS Input Voltage Range Extended Input Voltage Range Output Voltage Setting Output Voltage Accuracy Continuous Output Load Current Peak Current Limit Output Current Limit Accuracy 0.5 A < IDDQ < 1.3 A IDDQ < 0.5 A Transient Load Change Effective Quiescent Current Consumption (PWM, No Load) V21 ELECTRICAL CHARACTERISTICS Input Voltage Range Extended Input Voltage Range Output Voltage Setting Output Voltage Accuracy Continuous Output Load Current Peak Current Limit Output Current Limit Accuracy Transient Load Change Effective Quiescent Current Consumption (PWM, No Load) VPWR VPWR V21 I21 ILIM21 I21 IQ21 3.0 2.8 -5.0 -20 3.6 3.6 2.1 1.42 30 4.4 4.7 5.0 1.0 +20 0.5 V V V % A A % A µA IDDQ IQDDQ VPWR VPWR VDDQ IDDQ ILIMDDQ -15 -20 30 +15 +20 0.5 A µA 3.0 2.8 -5.0 3.6 3.6 1.8 1.78 4.4 4.7 5.0 1.3 V V V % A A % ILIMNN ΔINN INN 0.2 2.5 ±20 0.2 1.6 0.5 A % A VPWR VPWR VNN VOS 50 A 3.0 2.8 0.65 -5.0 3.6 3.6 12.5 4.4 4.7 1.2 5.0 V V V mV % mV Symbol Min Typ Max Unit 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic V15 ELECTRICAL CHARACTERISTICS Input Voltage Range Extended Input Voltage Range Output Voltage Setting (Also programmable to 1.6 V, typical) Output Voltage Accuracy Continuous Output Load Current Peak Current Limit Output Current Limit Accuracy Transient Load Change Effective Quiescent Current Consumption (PWM, No Load) VBG ELECTRICAL CHARACTERISTICS Input Voltage Range VDDQ V21 Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IBG = 1.5 mA, VDDQ = 1.8 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VCCA ELECTRICAL CHARACTERISTICS Input Voltage Range VDDQ V21 Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode VCCA VCCAUV VCCAUVH ICCA 150 3.0 mA mA 1.71 1.995 -2.0 1.80 2.100 1.5 -12 1.0 1.89 2.205 2.0 V % % % V ILIMBG ΔIBG PSRRBG IQBG 18 10 IBG 50 94 60 2.0 40 1.0 mA µA mA mA dB µA VBG VBGUV VBGUVH 1.71 1.995 -2.0 1.80 2.100 1.25 -12 1.0 1.89 2.205 2.0 V % % % V VPWR VPWR V15 I15 ILIM15 I15 IQ15 3.0 2.8 -5.0 0 -20 3.6 3.6 1.5 0.75 1.6 30 4.4 4.7 5.0 1.5 +20 0.5 V V V % A A % A µA Symbol Min Typ Max Unit 900844 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCA = 112.5 mA, VDDQ = 1.8 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VCC180 ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICC180 = 292.5 mA, V21 = 2.1 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VPNL18 ELECTRICAL CHARACTERISTICS SPECIFICATION Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IPNL18 = 157.5 mA, V21 = 2.1 V) Effective Quiescent Current Consumption Active Mode Low Power Mode ILIMPNL18 ΔIPNL18 PSRRPNL18 IQPNL18 18 10 IPNL18 50 315 60 210 4.2 100 mA mA dB µA V21 VPNL18 VPNL18UV VPNL18UVH 1.995 -5.0 2.1 1.8 -12 1.0 2.205 5.0 V V % % % mA ILIMCC180 ΔICC180 PSRRCC180 IQCC180 18 10 V21 VCC180 VCC180UV VCC180UVH ICC180 50 585 60 390 7.8 350 mA mA mA mA dB µA 1.995 -5.0 2.1 1.8 -12 1.0 2.205 5.0 V V % % % Symbol ILIMCCA ΔICCA PSRRCCA IQCCA 18 10 Min 50 Typ 225 60 Max 50 Unit mA mA dB µA 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic VPMIC ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IPMIC = 75 mA, V21 = 2.1 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VYMXYFI18 ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IYMXYFI18 = 150 mA), (V21 = 2.1 V or VPWR = 3.6 V) Output Noise (10 Hz to 100 kHz, IYMXYFI18 = 200 mA), (V21 = 2.1 V or VPWR = 3.6 V) Effective Quiescent Current Consumption Active Mode Low Power Mode ILIMYMXYFI18 ΔIYMXYFI18 PSRRYMXYFI18 VNOISEYMXYFI18 IQYMXYFI18 18 10 V21 VYMXYFI18 VYMXYFI18UV VYMXYFI18UVH IYMXYFI18 40 300 200 4.0 100 40 mA mA dB µVRMS µA 1.995 -5.0 2.1 1.8 -12 1.0 2.205 5.0 V V % % % mA IQPMIC 18 10 ILIMPMIC ΔIPMIC PSRRPMIC V21 VPMIC VPMICUV VPMICUVH IPMIC 50 150 60 100 2.0 20 mA mA dB µA 1.995 -5.0 2.1 1.8 -12 1.0 2.205 5.0 V V % % % mA Symbol Min Typ Max Unit 900844 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic VCCPAOAC ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCPAOAC = 116 mA, V15 = 1.5 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VCCPDDR ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCPDDR = 45 mA, V15 = 1.5 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VAON ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis V15 VAON VAONUV VAONUVH 1.425 -5.0 1.5 1.2 -12 1.0 1.680 5.0 V V % % % ILIMCCPDDR ΔICCPDDR PSRRCCPDDR IQCCPDDR 18 10 V15 VCCPDDR VCCPDDRUV VCCPDDRUVH ICCPDDR 50 90 60 60 1.2 10 mA mA dB µA 1.425 -2.0 1.5 1.05 -12 1.0 1.680 2.0 V V % % % mA ILIMCCPAOAC ΔICCPAOAC PSRRCCPAOAC IQCCPAOAC 18 10 V15 VCCPAOAC VCCPAOACUV VCCPAOACUVH ICCPAOAC 50 232.5 60 155 3.1 50 mA mA dB µA 1.425 -5.0 1.5 1.05 -12 1.0 1.680 5.0 V V % % % mA Symbol Min Typ Max Unit 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IAON = 187.5 mA, V15 = 1.5 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VMM ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IMM = 4.0 mA, V15 = 1.5 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VCCP ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change ILIMCCP ΔICCP V15 VCCP VCCPUV VCCPUVH ICCP 667.5 445 8.9 100 mA mA 1.425 -5 1.5 1.05 -12 1.0 1.680 5.0 V V % % % mA ILIMMM ΔIMM PSRRMM IQMM 18 10 V15 VMM VMMUV VMMUVH IMM 50 25 60 5.0 0.1 3.0 mA mA dB µA 1.425 -5.0 1.5 1.2 -12 1.0 1.680 5.0 V V % % % mA ILIMAON ΔIAON PSRRAON IQAON 18 10 Symbol IAON 50 375 60 250 5.0 100 mA mA dB µA Min Typ Max Unit mA 900844 20 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ICCP = 334 mA, V15 = 1.5 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VIMG25 ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IIMG25 = 60 mA, VPWR = 3.3 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VIMG28 ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, IIMG28 = 169 mA, VPWR = 3.3 V) Effective Quiescent Current Consumption Active Mode Low Power Mode ILIMIMG28 ΔIIMG28 PSRRIMG28 IQIMG28 18 10 VPWR VIMG28 VIMG28UV VIMG28UVH IIMG28 50 337.5 60 225 4.5 100 mA mA dB µA 3.0 3.6 4.4 V V % % % mA ILIMIMG25 ΔIIMG25 PSRRIMG25 IQIMG25 18 10 VPWR VIMG25 VIMG25UV VIMG25UVH IIMG25 50 120 60 80 1.6 10 mA mA dB µA 3.0 -5.0 3.6 2.5 -12 1.0 4.4 5.0 V V % % % mA Symbol PSRRCCP IQCCP 18 10 Min 50 Typ 60 Max Unit dB µA (Selectable, see Table 43) -5.0 -12 1.0 5.0 - 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 21 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic VSDIO ELECTRICAL CHARACTERISTICS Input Voltage Range Output Voltage Setting Output Voltage Accuracy Under-voltage Detection Threshold (With respect to the output voltage) Under-voltage Detection Threshold Hysteresis Continuous Output Load Current Active Mode Low Power Mode Current Limit Transient Load Change Power Supply Rejection Ratio (PSRR) (20 to 100 kHz, ISDIO = 161 mA, VPWR = 3.3 V) Effective Quiescent Current Consumption Active Mode Low Power Mode VPNL33 POWER SWITCH ELECTRICAL CHARACTERISTICS Input Voltage Range Drop Across Switch with reference to VPWR Continuous Output Load Current ADC ELECTRICAL CHARACTERISTICS Conversion Current OFF Supply Current Converter Reference Voltage Integral Nonlinearity (Rs = 5.0 kΩ maximum) (6) Differential Nonlinearity (Rs = 5.0 kΩ maximum) (6) Zero Scale Error (Offset) (Rs = 5.0 kΩ maximum) (6) Full Scale Error (Gain) (Rs = 5.0 kΩ maximum) (6), (7) Drift Over Temperature Source Impedance No Bypass Capacitor at Input Bypass Capacitor at Input of (10 nF) Input Buffer Input Range(8) 0.02 5.0 30 2.4 kΩ kΩ V 2.4 1.2 1.0 ±3.0 ±1.0 10 11 ±2.0 mA μA V LSB LSB LSB LSB LSB VPWR IPNL33 3.135 3.3 3.465 3.0 100 V % mA ILIMSDIO ΔISDIO PSRRSDIO IQSDIO 18 10 VPWR VSDIO VSDIOUV VSDIOUVH ISDIO 50 322.5 60 215 4.3 100 mA mA dB µA 3.135 3.3 3.465 V V % % % mA Symbol Min Typ Max Unit (Selectable, see Table 44) -5.0 -12 1.0 5.0 - Notes 6. Rs represents a possible external series resistor between the voltage source and the ADIN input. 7. At room temperature. 8. Refer to Table 57 for analog valid input range and input buffer range characteristics for each ADC Channel 900844 22 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic GPIOS ELECTRICAL CHARACTERISTICS GPIO Voltage Level (This is wired externally though GPIOVCC pin) VGPIOVCC 1.8 V, 2.5 V, 3.3 V 1.8 V, 2.5 V, 3.3 V 20 V Symbol Min Typ Max Unit GPO Voltage Level (This is wired externally though GPOVCC pin) VGPOVCC - - V Accuracy for GPIOVCC, GPOVCC GPIO Output Drive Capability Input Low Voltage Input High Voltage Output Low Voltage (VCC = VCC_MIN, IOL = 4.0 mA) Output High Voltage (VCC = VCC_MIN, IOH = -4.0 mA) VIL VIH VOL VOL -5.0 0 0.7*VCC VCC-0.1 5.0 0.3*VCC VCC 0.1 - % Ω V V V V 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 23 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic SPI INTERFACE TIMING AND LOGIC IO Time SPICSB has to be low before the first rising edge of SPICLK Time SPICSB has to remain low after the last falling edge of SPICLK Time SPICSB has to remain high between two transfers Clock period of SPICLK (Equivalent to a maximum clock frequency of 25 MHz) Part of the clock period where SPICLK has to remain high Part of the clock period where SPICLK has to remain low Time MOSI has to be stable before the next falling edge of SPICLK Time MOSI has to remain stable after the falling edge of SPICLK Time MISO will be stable before the next falling edge of SPICLK Time MISO will remain stable after the falling edge of SPICLK Time MISO needs to become active after the falling edge of SPICSB Time MISO needs to become inactive after the rising edge of SPICSB VIDEN/VID TIMING SPECIFICATION VIDEN/VID Debounce time VIDEN Invalid State Hold Time OSCILLATOR AND CLOCK OUTPUTS MAIN CHARACTERISTICS RTC OSC Startup Time (Upon Application of Power) RTC RTC Clock Frequency, Crystal OSC Nominal Frequency VCC ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V (25 mV/s)) Turn Off Time (OFF to output voltage ramp down to 0 V) DAC Slew Rate Switching Frequency VNN ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 V to 1.0 V (25 mV/s)) Turn Off Time (OFF to output voltage ramp down to 0 V) DAC Slew Rate Switching Frequency INN/t tSSNN tNNOFF fSW 25 1.0 1.0 0.06 1.0 A/ns ms ms mV/µs MHz ICC/t tSSCC tCCOFF fSW 25 1.0 1.0 0.06 1.0 A/ns ms ms mV/µs MHz 32.768 KHz 500 ms tDB tHOLD 100 1.0 400 ns μs tSELSU tSELHLD tSELHIGH tCLKPER tCLKHIGH tCLKLOW tWRTSU tWRTHLD tRDSU tRDHLD tRDEN tRDDIS 20 20 20 40 18 18 5.0 5.0 5.0 5.0 ns ns ns ns ns ns ns ns ns ns Symbol Min Typ Max Unit Refer to Figure 6 for more details 5.0 ns 900844 24 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic VDDQ ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) Turn Off Time (OFF to output voltage ramp down to 0 V) Switching Frequency V21 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 V to 2.1 V) Turn Off Time (OFF to output voltage ramp down to 0 V) Switching Frequency V15 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 2.1 V) Turn Off Time (OFF to output voltage ramp down to 0 V) Switching Frequency VBG ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VCCA ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.5 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VCC180 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VPNL18 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VPMIC ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) Turn Off Time (OFF to output voltage ramp down to 0 V) IPMIC/t tSSPMIC tPMICOFF 0.01 700 5.0 A/µs µs ms IPNL18/t tSSPNL18 tPNL18OFF 0.1 140 5.0 A/µs µs ms ICC180/t tSSCC180 tCC180OFF 1.0 30 5.0 A/µs µs ms ICCA/t tSSCCA tCCAOFF 0.01 30 5.0 A/µs µs ms IBG/t tSSBG tBGOFF 0.001 20 5.0 A/µs µs ms I15/t tSS15 t15OFF fSW 4.0 0.1 100 1.0 A/µs µs ms MHz I21/t tSS21 t21OFF fSW 4.0 0.1 84 1.0 A/µs µs ms MHz IDDQ/t tSSDDQ tDDQOFF fSW 4.0 1.0 200 1.0 A/µs µs ms MHz Symbol Min Typ Max Unit 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 25 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic VYMXYFI18 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VCCPAOAC ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VCCPDDR ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VAON ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VMM ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.2 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VCCP ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.0 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VIMG25 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 2.5 V) Turn Off Time (OFF to output voltage ramp down to 0 V) VIMG28 ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 2.9 V) Turn Off Time (OFF to output voltage ramp down to 0 V) IIMG28/t tSSIMG28 tIMG28OFF 0.1 200 5.0 A/µs µs ms IIMG25/t tSSIMG25 tIMG25OFF 0.01 200 5.0 A/µs µs ms ICCP/t tSSCCP tCCPOFF 0.1 26 5.0 A/µs µs ms IMM/t tSSMM tMMOFF 0.01 125 5.0 A/µs µs ms IAON/t tSSAON tAONOFF 0.1 25 5.0 A/µs µs ms ICCPDDR/t tSSCCPDDR tCCPDDROFF 0.1 35 5.0 A/µs µs ms ICCPAOAC/t tSSCCPAOAC tCCPAOACOFF 0.1 30 5.0 A/µs µs ms IYMXYFI18/t tSSYMXYFI18 tYMXYFI18OFF 0.1 200 5.0 A/µs µs ms Symbol Min Typ Max Unit 900844 26 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics TA = -40 to 85 °C, VPWR = 3.0 to 4.4 V, in gathering these parametrics, Freescale used the external components described in the Hardware Design Considerations section of this document, over the full load current range, unless otherwise noted. Typical values are characterized at VPWR = 3.6 V and 25 °C. Characteristic VSDIO ELECTRICAL CHARACTERISTICS Transient Load Speed of Change Soft Start Time (Enable to output voltage ramp up from 0 to 1.8 V) Turn Off Time (OFF to output voltage ramp down to 0 V) POWER SWITCHES ELECTRICAL CHARACTERISTICS Ramp Up Time ADC ELECTRICAL CHARACTERISTICS Conversion Time Per Channel Turn on/off Time 10 31 μs μs 50 µs ISDIO/t tSSSDIO tSDIOOFF 0.01 100 5.0 A/µs µs ms Symbol Min Typ Max Unit 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION The 900844 is a high efficiency Power Management Integrated Circuit (PMIC). It is optimized for Ultra-mobile platforms for Netbook, Tablets, Slates, embedded devices, and other applications requiring “multi-cell” battery voltage. The 900844 PMIC, is designed to provide CPU power requirements and control as an integral part of Freescale's power management solution to meet the needs of Ultra-mobile platforms. Optimum partitioning, high feature integration, and state of the art technology, enable Freescale to support Ultra-mobile platforms that are cost effective, by reducing component count and board area. The Freescale solution also allows ease of system design, resulting in a faster time to market development cycle. It accepts input from a supply in the range of 3.0 to 4.4 V (for example, from a multi-cell battery scaled down to 3.3 V) to deliver regulated power to various components (CPU, chip sets, wireless, memory, storage, display, sensors, and others) on Ultramobile platforms. 5 x DC/DC multi-mode SWITCHERS 2 x VID 4.0 MHz Switching Core, I/O, MEM 14 x LDO REGULATORS +1 x Power Switch Low Noise High Performance 22 Channel 10 bit ADC PMIC Temp Monitoring 4-Wire Resistive Touch Screen Select Rails Current Monitoring General Purpose Inputs RTC 32.768 kHz Xtal Oscillator Control Interface 8 Interrupt Capable GPIOs SPI Interface + Status and Control Inputs / Outputs Freescale’s PMIC Platform Solution Power Control Logic State Machine Figure 4. Power Management Solution - High Level Block Diagram FEATURE LIST • Netbook, Tablets, and embedded devices, Ultra-mobile platform Architecture Support • Fully Programmable DC/DC Switching, Low Drop-Out Regulators, and Load Switches • Delivers regulated reliable power to various system components • High efficiency multi mode power conversion ensuring extended battery life • Fully programmable with extensive protection features and complete fault reporting for best in class overall system reliability • Internal Compensation • 5 Buck DC/DC Regulators - 2x VID Controlled with 1.0 MHz switching and external switches for CPU and Graphics core support - 3x with 4.0 MHz switching and integrated MOSFET for platform support and LDO supply for optimized thermal performance and power efficiency. • 14 Low Dropout (LDO) regulators. • One configurable LDO/Switch regulator for SDIO card support • A 3.3 V load switch for platform support • Coin Cell Backup battery charger • SPI communication interface (up to 25 MHz operation) • 22 channel (32 capable) 10-bit ADC for internal and external sensing with touch screen interface • Low power 32.786 kHz XTAL oscillator. • Real Time Clock (RTC) to provide time reference and alarm functions with wake up control. • Eight Interrupt capable GPIOs and 8 GPOs • Various control and status reporting I/Os • Interrupt and Reset controller. All interrupt signals can be masked. • Overall solution size target of < 400 mm2 (including clearance and routing) • Operating temperature of -40 to +85 °C 900844 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM V3A VPWR V3A CCOIN Optional Components CLDOREFP9 CCOREREF CLDOREFP8 CCOREDIG CCORE COINCELL RNTCEV RNTC REFGNDCHG GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIOVCC VCOREDIG VCOREREF VCORE PGNDBKLT VNTC NTC VBAT VPWR …… GNDSUB31 GNDSUB32 REFGNDSW GNDREFVCC PVINCC CSPCC VPWR MHSCC CINCC GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 GPO0 GPOVCC LDOREFP9 LDOREFP8 GNDCORE PGNDCHG ISNSBATN ISNSBATP GNDBAT Power Path Manager Li-Cell Charger Power Fail Detect GPO Control GPIO Control Reference Generation VCC GNDSUB1 GNDSUB2 GNDSUB3 GNDBKLT GNDLED PVINVIB HSCCGT Output Driver SWFBCC LSCCGT PGNDCC VOUTFBCC PVINNN CSPNN Li-Cell Switch 3600mA Buck VID[6:0] VID Controller VNN LCC MLSCC VCC COCC Voltage / Current Sensing /& Translation ADIN21 ADIN20 ADIN19 ADIN18 ADIN17 ADIN16 ADIN15 ADIN14 ADIN13 ADIN12 ADIN11 ADIN10 TSREF CADREF VPWR General Purpose ADC Inputs VIDEN[1:0] VPWR MNN CINNN MUX 10 Bit ADC HSNNGT Output Driver SWFBNN LSNNGT PGNDNN VOUTFBNN Shift Register 1600mA A/D Control Startup Sequencer Buck LNN VNN CONN Touch Screen Interface Touch Screen Interface Trigger Handling Thermal Protection Shift Register VDDQ 1500mA Buck SPI Control SPI Registers Control Trim V21 1000mA Buck Output Driver PVIN21 SW21 PGND21 FB21 VPWR L21 GNDADC RXINR SPIVCC SPICSB SPICLK MOSI MISO GNDSPI GNDAUD1 GNDAUD2 GNDAUD3 GNDAUD4 GNDRTC XTAL1 XTALRTC CXTALRTC2 Output Driver PVINDDQ SWDDQ PGNDDDQ FBDDQ VPWR LDDQ VDDQ CODDQ CINDDQ SPI Interface Shift Register V21 CO21 CIN21 From Button The component list for those items listed in this schematic can be found in the External Components BOM (23). Analog Integrated Circuit Device Data Freescale Semiconductor CXTALRTC1 XTAL2 CLK32K 32.768KHz Crystal OSC SC900844 900844 32.768KHz Internal OSC Timers SPI Registers V15 1500mA Buck Output Driver PVIN15 SW15 PGND15 FB15 L15 V15 CO15 VPWR CIN15 GNDCTRL ICTEST VIDEN0 VIDEN1 VID0 VID1 VID2 VID3 VID4 VID5 VID6 THERMTRIPB PWRGD RESETB VRCOMP PMICINT EXITSTBY PWRBTN System & Peripheral Interface From CPU To / From I/O Chip RTC Calibration PLL VPNL33 SWITCH VCCPAOAC LDO VYMXYFI18 LDO VCCPDDR LDO VSDIO LDO / SWITCH Switchers VCC180 LDO VPNL18 LDO VIMG28 LDO VIMG25 LDO VPMIC LDO VAON LDO VCCP LDO VCCA LDO VMM LDO VBG LDO Enables & Control VOUTPNL33 PVIN3P3 FBSDIO SDIOGT VOUTIMG28 PVINIMG VOUTIMG25 FBCCP GND1P5 VOUTCCP VOUTMM VOUTAON FBCCPDDR VOUTCCPDDR VOUTCCPAOAC GNDCOMS1 GNDCOMS2 PVIN1P5 VOUTYMXYFI18 PVINYMXYFI18 VOUTPMIC GND2P1 VOUTPNL18 PVIN2P1 VOUTCC180 VOUTCCA FBCCA PVIN1P8 VOUTBG GNDIMG GND1P8 Package Pin Legend Output pin SC900844 Input pin Bi-directional pin COCC180 COPMIC COPNL18 COCCPDDR COYMXYFI18 COCCPAOAC COCCP COAON COMM COIMG28 COIMG25 COCCA COBG COPNL33 COSDIO MSDIO VSDIO CINYMXYFI18 RSDIO CIN2P1 CIN1P5 CINIMG VPWR CIN1P8 V15 VPWR V21 V21 V21 CINSDIO Figure 5. 900844 Functional Block Diagram VPWR 900844 29 FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE OVERVIEW This section addresses the various interfaces and I/Os between the PMIC solution and the rest of the system. The system control interface includes the following: SPI interface. Interrupt controller Platform sideband signals Special registers • • • • SPI INTERFACE The 900844 contains a SPI interface port which allows a host controller to access the register set. Using these registers, 900844 resources can be controlled. The registers also provide information on the PMIC status, as well as information on external signals. The addressable register map spans 1024 registers of 8 data bits each. The map is not fully populated. A detailed structure of the register set along with bit names, positions, and basic descriptions, are given in Table 74. Expanded bit descriptions are included in the individual functional sections for application guidance. Note that not all bits are truly writable. Refer to the individual sub-circuit descriptions and Table 74 to determine the read/write capability of each bit. Table 5. SPI Interface Pin Functionality Pin Name SPICLK MOSI MISO SPICSB SPIVCC SPI Functionality SPI Clock Input (up to 25 MHz) Master Out / Slave In (Serial Data In) Master In / Slave Out (Serial Data Out) Chip Select (Active Low) SPI Bus Supply - 1.8 V typical The System Controller Unit (SCU) within the Platform Controller Hub (PCH) is the master, while the PMIC is the slave. The SPI interface operates at a typical frequency of 12.5 MHz, and at a maximum frequency of 25 MHz, with lower speeds supported. The SPI interface is configured in mode 1: clock polarity is active high (CPOL = 0), and data is latched on the falling edge of the clock (CPHA = 1). The chip select signal, SPICSB, is active low. The SPICSB line must remain active during the entire SPI transfer. The MISO line will be tri-stated while SPICSB is high. The SPI frame consists of 24 bits: a Read/Write bit, a 10-bit address code (MSB first), 5 "dead" bits and 8 data bits (also MSB first). The Read/Write bit selects whether the SPI transaction is a read or a write: for a write operation, the R/W bit must be a one; for a read operation, it must be a zero. For a read transaction, any data on the MOSI pin after the address bits is ignored. The MISO pin will output the data field pointed to by the 10-bit address loaded at the beginning of the SPI sequence. SPI read backs of the address field and unused bits are returned as zero. For read operations, the PMIC supports address auto-increment. For a write operation, once all the data bits are written, the data is transferred into the registers on the falling edge of the 24th clock cycle. All unused SPI bits in each register must be written to a zero. To start a new SPI transfer, the SPICSB line must go inactive and then active. After the LSB of data is sent, if the SPICSB line is held low, up to seven additional address/data packets may be sent as writes to the PMIC. Refer to the VRCOMP Pin section. The following diagrams illustrate the SPI Write Protocol, SPI Read Protocol, and SPI Timing. 900844 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE Figure 6. SPI Read from PMIC Diagram (One Address/Data Packet shown) Figure 7. SPI Write to PMIC Diagram (One address/Data Packet Shown) Figure 8. SPI Interface Timing Diagram (Processor Input capacitance is 3.0 pF) INTERRUPT CONTROLLER Control The PMIC informs the system of important events using interrupts. Unmasked interrupt events are signaled to the host by driving the PMICINT pin high. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. If a new interrupt occurs while the controller clears an existing interrupt bit, the interrupt line will remain high. Each interrupt can be masked by setting the corresponding mask bit to a ‘1’. As a result, when a masked interrupt bit goes high, the interrupt line will not go high. A masked interrupt can still be read from the register. If a masked interrupt bit was already high, the interrupt line will go high after unmasking. The following is the interrupt handling mechanism which has inherent latency that the clients must expect: 1. PMIC interrupts SCU, if both the 1st and 2nd level bits are not masked. 2. SCU reads PMIC master, 1st level, interrupt event register. 3. SCU then traverses all the branches of the interrupt tree where events are indicated. 4. SCU will service events in leaf node registers. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE When an unmasked interrupt event happens: • The 2nd level bit is set. • The 1st level bit is set by a rising edge sent from the 2nd level register, and the PMICINT signal goes from low to high • When the system controller, the SCU, reads the 1st level register the 2nd level registers that were set, remain set. Any unset registers are free to accept an interrupt event. • When the 1st level register is read, any 1st level register bits that were set at the point the SPI read strobe shifts the register value into the SPI transmit shift register, that bit will be cleared by the SPI self clear signal immediately following the read strobe. This allows new interrupts to be recorded without being lost. If all unmasked 1st level bits get cleared by the read, the PIMCINT pin will de-assert. If a new unmasked 1st level interrupt event happens, just after the read of the 1st level register, the PIMCINT pin interrupt pin will remain asserted. The SCU reads each 2nd level register and these are cleared on read. • When the 2nd level register is read, any 2nd level register bits that were set at the point the SPI read strobe sweeps, the register value into the SPI transmit shift register, that bit will be cleared by the SPI self clear signal immediately following the read strobe. This allows new interrupts to be recorded without being lost. If a new unmasked 2nd level interrupt event happens just after the read of the 2nd level register, the PMICINT pin will assert if the 1st level bit is not masked. Table 6. Interrupt Registers Summary Block IRQ IRQ RTC POWER POWER ADC ADC GPIO ADDR 0x04 0x05 0x1C 0x30 0x31 0x5F 0x60 0xE8 Register Name INTERRUPT INTMASK RTCC VRFAULTIN T MVRFAULTI NT ADCINT MADCINT GPIOINT RW R R/W R R R/W R R/W R D7 EXT MEXT IRQF RSVD RSVD RSVD RSVD GPIINT7 D6 AUX MAUX PF (=0) RSVD RSVD RSVD RSVD GPIINT6 D5 VRFAULT MVRFAUL T AF RSVD RSVD RSVD RSVD GPIINT5 D4 GPIO MGPIO UF RSVD RSVD RSVD RSVD GPIINT4 D3 RTC MRTC RSVD RSVD RSVD RSVD RSVD GPIINT3 D2 CHR MCHR RSVD VRFAIL MVRFAIL OVERFLOW MOVERFLO W GPIINT2 D1 ADC MADC RSVD BATOCP MBATOCP PENDET MPENDET GPIINT1 D0 PWRBTN MPWRBTN RSVD THRM MTHRM RND MRND GPIINT0 Initial 0x00 0xFA 0x00 0x00 0x03 0x00 0x00 0x00 Notes 9. Because of the design of the clear on read logic, any interrupt event is allowed to happen at any time. If the interrupt event happens close to when a read of the interrupt register happens, if the SPI read captures that interrupt bit as being set, then that bit will get cleared. If the read does not capture the bit as being set, it will not be cleared. In this way no interrupt events are lost. 10. The 2nd level interrupts that get "Ored" together to set the 1st level interrupt bits can block other 2nd level interrupts from setting the 1st level interrupt register. This is because if any of the 2nd level interrupts is high, the output of the OR will remain high, blocking the other 2nd level interrupt’s rising edge. This should not be a problem. because when the 2nd level register is read, the SCU will see all the bits that are active when it is read. The software will decide which one to service first, just as it needs to do when more than one 1st level interrupt bits are set when that register is read. 11. Masking has no affect on interrupt bits being set or cleared. Masking just prevents the interrupt event from asserting the interrupt pin. If an interrupt bit is set, but is masked, the interrupt pin does not assert. If the mask bit is cleared while the bit is still set, the interrupt pin will assert. Most interrupt registers have 1st and 2nd level mask bits. Both mask bits must be in the unmasked state to generate an interrupt to the SCU. 12. Some 2nd level interrupt registers are level sensitive. If the level that sets these interrupts registers is active when the register is read, it will clear during the active time of the clear on read signal and then reassert. This will reassert the 1st level interrupt bit. 13. The GPIO interrupts do not have interrupt masking bits, they have interrupt prevention bits. This is controlled by bits 5:4 of the GPIO control register. See GPIOs for more details on using the GPIO as interrupt inputs. 14. Interrupts generated by external events are de-bounced. Therefore, the event needs to be stable throughout the de-bounce period before an interrupt is generated. Nominal de-bounce periods for each event are documented in Table 7. Due to the asynchronous nature of the de-bounce timer, the effective de-bounce time can vary slightly. Interrupt Bit Summary Table 7 summarizes all 1st and 2nd level interrupt bits associated with the Interrupt Controller. For more detailed behavioral descriptions, refer to the related sections. 900844 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE Table 7. Interrupt Bit Summary 1st Level Name PWRBTN ADC Bit D0 D1 2nd Level Name RND PENDET RSVD CHR D2 RSVD BATOVP TEMP RSVD RSVD BATDET RSVD USBOVP RTC D3 RSVD UF AF RSVD IRQF GPIO D4 GPINT0 GPINT1 GPINT2 GPINT3 GPINT4 GPINT5 GPINT6 GPINT7 VRFAULT D5 THRM RSVD VRFAIL RSVD AUX D6 RSVD RSVD RSVD RSVD RSVD EXT D7 Bit D0 D1 D7:D2 D0 D1 D2 D3 D4 D5 D6 D7 D3:D0 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D7:D3 D0 D1 D0 D1 D7:D4 Interrupt Event Condition PWRBTN falling edge detection ADC Round Robin Cycle Complete Touch Screen Wake-up Battery Over-voltage Battery Temperature Outside Valid Window Battery Connect/Disconnect Input Over-voltage Reached Update Cycle Current Time = Alarm Time IRQF=UIE*UF + AIE*AF Edge Detect Edge Detect Edge Detect Edge Detect Edge Detect Edge Detect Edge Detect Edge Detect Junction Temperature > Thermal Warning Threshold Regulator Fault Present Not supported Detect Falling Hi Level Rising Rising/Falling Hi Level Hi Level Hi level Hi Level Hi Level Hi Level Rising/Falling/Both Rising/Falling/Both Rising/Falling/Both Rising/Falling/Both Rising/Falling/Both Rising/Falling/Both Rising/Falling/Both Rising/Falling/Both Hi Level Hi Level Debounce time 10 ms (16) 1.0 ms 0.5 sec 10 ms GPIDBNC0 GPIDBNC1 GPIDBNC2 GPIDBNC3 GPIDBNC4 GPIDBNC5 GPIDBNC6 GPIDBNC7 10 ms (15) - Notes 15. Varies by regulator. Normally it is 1.5 times the regulator turn on time. 16. 32 ms rising and 120 μs falling 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE SIDEBAND SIGNALS The following pins are included as part of the Sideband signals: Table 8. Sidebands Pin Functionality Pin Name PMICINT VRCOMP RESETB PWRGD EXITSTBY THRMTRIPB VIDEN[1:0] VID[6:0] I/O O O O O I I I I Pin Functionality Active high PMIC Interrupt Output pin Active high Voltage Regulator Complete signal Active low hard reset for Platform controller hub Active high Power Good Output signal Active high Exit Standby signal Active low Thermal Trip Assertion Input signal Active high Input signals driven by the CPU, to indicate if the VID bus is addressing VCC or VNN. Active high input signals driven by the CPU, to indicate the output voltage setting for the VCC and VNN rails. PMCINT Pin The PMICINT pin interrupts the platform controller hub by rising from low to high when an unmasked interrupt event occurs. It is a level sensitive pin and it is cleared when the platform controller hub reads the Interrupt registers. Reference Interrupt Controller for a more detailed explanation of the Interrupt mechanism. The PMICINT pin follows the DC Signaling specifications in Table 3 with a reference of 1.8 V (VPMIC). VRCOMP Pin This is an active high voltage regulator complete signal. It is asserted low by the PMIC when a SPI voltage regulation request, or other write request has been decoded. The signal is de-asserted on completion of the request (i.e. the rail is in regulation). This signal is relevant to the SPI initiated writes and EXITSTBY assertion. The VRCOMP pin follows the DC Signaling specifications in Table 3 with a reference of 1.8 V (VPMIC). Figure 9 illustrates the Voltage Regulators register write cycles and VRCOMP functionality. The rising edge on the SPICSB pin indicates the end of the block of Voltage Regulators configurations, at which point the VRCOMP pin is driven low. As an address/data block is written, the PMIC can start to ramp those rails (DC-DC, LDO, or switch). Once all of the rails are in regulation, the PMIC drives the VRCOMP pin high, indicating to the platform controller hub that the voltage regulator configuration request is completed, and the PMIC is ready for subsequent transactions. The maximum number of voltage regulator change packets (address/data combinations) is 8. The voltage regulators should ramp at the rate defined in the regulators tables. Due to the relatively long turn-off time of the voltage regulators, the VRCOMP signal is to be gated-off after a 500 ns minimum (30 ms max.) low time. SPI_CS# SPI Bus Idle SPI Packet SPI Packet SPI Packet SPI Packet Idle VR Status Existing Mode VR Reconfigure Idle VR_COMP 4 - tVR_COMP Figure 9. VRCOMP Functionality in a SPI Voltage Regulators Configuration 900844 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE RESET Pin This is an active low, hard reset for the platform controller hub. When this pin is asserted, the platform controller hub returns to its initial default state. This signal can be asserted when a cold or warm reset is initiated, depending on the settings in the CHIPCNTL register. The RESET pin follows the DC Signaling specifications in Table 3 with a VCC of 1.8 V (VPMIC) PWRGD Pin This is a Power Good output signal from the 900844 to the Platform controller hub. Assertion of PWRGD means that the VCCPAOAC, VAON, and VPMIC rails have been valid for at least 100 microseconds. The Platform Controller Hub will remain off until this signal is asserted. This signal is only de-asserted if VCCPAOAC, VAON, or VPMIC is out of regulation, or a cold reset is initiated by the firmware. The PWRGD pin follows the DC signaling specifications in Table 3 with a reference of 1.8 V (VPMIC) WARM and COLD RESET The RESET and PWRGD signals have two functions which are initiated through the register file. Together they define a warm reset or cold reset to the platform controller hub. The sequencing shown in Figure 10 and is controlled from the register CHIPCNTRL through bits WARMRST and COLDRST. The pulse will be held low for 5.0 μs < t < 31 μs. Table 9. CHIPCNTL Register Structure and Bit Description Name Bits Description CHIPCNTL (ADDR 0x 06 - R/W - Default Value: 0x00) COLDRST 0 Cold Reset Function Enable x0 = No Change x1 = Pulse RESET and PWRGD Low Warm Reset Function Enable x0 = No Change x1 = Pulse RESET Low Reserved WARMRST 1 Figure 10. Warm/Cold Reset Functionality EXITSTBY Pin Reserved 7:2 When the EXITSTBY pin is asserted high, the 900844 exits the AOAC standby settings for regulating the platform supplies. When asserted, the PMIC switches the voltage regulators, as defined in the voltage regulator registers from the CTL bits to the AOACTL bits. This is a low latency voltage regulators context switch. EXITSTBY pin follows the DC signaling specifications in Table 3 with a reference of 1.05 V (VCCP) AOAC Exit Standby When the EXITSTBY signal is asserted high from the Platform controller hub, the VRCOMP signal will be driven low. The AOACTL bits will be copied to the CTL bits in the different voltage regulator control registers on the rising edge of the EXITSTBY signal, unless Bit 5 is '0'. If Bit 5 is '0', then the CTL bits are not modified. The VRCOMP signal is de-asserted at this point. The rails defined in the new CTL registers will be ramped up together or remain in the same state, as if the AOACTL settings were the same as the previous CTL setting. Once all of the rails are in regulation, the VRCOMP signal will be driven high. Figure 11 shows the timing diagram of the EXITSTBY signal. There is a special case (optimized case) when the EXITSTBY signal is asserted with the VCCP, VCCPDDR, VCCA, and VCC180 rails. If some combination of these four rails turn on with the assertion of the EXITSTBY signal, the entire time for the re-configuration should take no longer than 30 ms. See Figure 12. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE EXIT_STBY SPI BUS AOACCTLVxx copied to TVxx IDLE VR Status Stats VR_COMP# Existing Mode VR Reconfigure New Mode tVR_COMP Figure 11. General Exit Standby Diagram 30 μsec EXIT_STBY SPI BUS AOACCTLVxx copied to CTLVxx IDLE VR Status VR_COMP# Existing Mode VR Reconfigure New Mode tVR_COMP Figure 12. Optimized Exit Standby Diagram The power-on default AOACCTLVxx register setting for the VCCP, VCCPDDR, VCCA, and VCC180 rails, are to be turned on by the assertion of the EXITSTBY signal. However, every regulator has an AOACCTLVxx register setting, and can be configured to turn on, turn off, or have no change. The power-on default AOACCTLVxx register setting for all other regulators is set to no change. Note that the VDDQ regulator has to be enabled in order for the VCCA regulator to turn on. THERMTRIPB Pin THERMTRIPB is an active low Thermal Trip input signal. It is asserted by the CPU to indicate a catastrophic thermal event. On the falling edge of THERMTRIPB, the PMIC has 500 ms to sequence off all rails from the highest to lowest. The PMIC will turn on automatically upon detecting a turn on event, at which point the cold boot flow should be followed as shown in Turn on Events. The PMIC provides a weak (50 -100 kΩ) pull-up to VCCPAOAC. The PMIC only responds to a THERMTRIPB signal if the VCCP regulator is on. The platform controller hub output driver is a nominal 55 Ω. The THERMTRIPB pin follows the DC Signaling specifications in Table 3 with a reference of 1.05 V (VCCPAOAC). VIDEN[1:0] & VID[6:0] Pins Both VCC and VNN regulators are variable in the CPU and supply two different sub-systems. The CPU implements a VID mechanism that minimizes the number of required pins. The VID for VNN and VCC are multiplexed on to the same set of pins, and a separate 2-bit enable/ID is defined to specify to which sub-system the driven VID corresponds. One of the combinations notifies that the VID is invalid. This is used when the CPU is in C6/Standby, to tri-state the VID pins to save power. 900844 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE Table 10. VIDEN Selections VIDEN[1:0] Bits 0 0 1 1 0 1 0 1 Selection Invalid VCC VNN Unused Both VCC and VNN have initial boot voltage (VCC VBOOT = 1.1 V; VNN VBOOT = 0.9 V) settings that the platform controller hub sets to the VNN and VCC regulators by a SPI write to the VNNLATCH and VCCLATCH registers. Once all of the platform voltage rails are up, the CPU will drive the VID and VIDEN signals to set the VNN and VCC output voltage to the appropriate level. The VID and VIDEN signals will go through the sequence INVALID >> VNN >> INVALID >> VCC. VID[6:0] and VIDEN[1:0] will transition together and the PMIC must de-bounce the VID[6:0] and VIDEN[1:0] for 100 to 400 ns. The CPU will hold these signals valid for at least 500 ns. VID signals are disabled from controlling VCC/VNN unless the VCCP regulator is enabled Both regulators support dynamic VID transitioning during normal runtime operation. Dynamic VIDs require the CPU to change the VIDEN signals for the VNN regulator to INVALID each time, to change the VNN output voltage. The VCC regulator is different in that it does not require the VIDEN signals to change to change the VCC output voltage. If the VIDEN signals are set for VCC (01), the VID signals can change and the VCC regulator will respond by changing the output voltage accordingly. Figure 13 shows how the VCC output voltage can change during normal runtime operation when the VIDEN signals are set to VCC (01). If the VIDEN signals are set to VCC (01), the VCC regulator must monitor the VID signals, latch any changes, and change the output voltage setting accordingly. When the CPU is dynamically changing the VID setting for the VCC regulator during normal operation, it will only change the VID combination by 1 step, which corresponds to a voltage step of ±12.5 mV. During these changes, the VCC regulator must follow the 25 mV/ms slew rate specification. The VNN regulator differs from the VCC regulator, in that dynamic changes to the VNN regulator output voltage require the VIDEN signals to change to INVALID each time. Figure 14 shows how the VNN output voltage can change during normal runtime operation. The VIDEN[1:0] pins are active high signals driven by the CPU to indicate if the VID bus is addressing VCC or VNN. They follow the DC Signaling specifications in Table 3 with a reference of 1.05 V (VCCPAOAC) The VID[6:0] pins are active high signals driven by the CPU to indicate the output voltage setting for the VCC and VNN rails. They follow the DC Signaling specifications in Table 3 with a reference of 1.05 V (VCCP) The VID output buffer driver is of the CMOS type. The platform controller hub output driver Impedance is a pull-up (55 Ω +20%/ -55%) and pull-down (55 Ω +20%/-55%). Motherboard Impedance is 55 Ω ±15%. Under extreme conditions, there could be ringing that cross the 70/30% threshold, hence the de-bounce requirements. Maximum leakage current on the VID pins is 100 mA. VID[6:0] for each of the VCC and VNN rails will be latched in an internal register that will be updated with every VID[6:0] pin signaling. Table 11. VCC and VNN Latch Register Structure and Bit Description Name Bits Description FSLVCCLATCH (ADDR 0x1C9 - R - Default Value: 0x7F) VCCVID Reserved 6:0 7 This register latches an Image of the last VID[6:0] signals for VCC Reserved FSLVNNLATCH (ADDR 0x1CA - R - Default Value: 0x7F) VNNVID Reserved 6:0 7 This register latches an Image of the last VID[6:0] signals for VNN Reserved Note that the term Reserved or RSVD is used throughout this document. This nomenclature refers to Reserved Registers that are not for designed customer use. For question regarding these registers, contact Freescale Semiconductor Technical Support. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE Figure 13. Dynamic VCC Timing Diagram Figure 14. Dynamic VNN Timing Diagram Figure 15 shows the 7-bit VID codes vs. the output voltage of VCC and VNN. 900844 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 32 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID (V) 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 32 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID (V) 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 32 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID (V) 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 32 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID (V) 0 0 0.3000 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF 0 OFF 1 OFF Figure 15. 7-Bit VID Code vs. VCC/VNN Output Voltage As explained previously, the output voltage setting for the VCC and VNN regulators can be set via the VID/VIDEN pins from the CPU, or by programming the VNNLATCH and VCCLATCH registers through the SPI interface via the platform controller hub. Figure 16 shows the relationship between the VID/VIDEN signals, the DVPxVRD bit in the Latch registers, and the VRCOMP output signal. The figure shows VCC as an example, but is also applicable to VNN The DVPxVRD bit in the VNNLATCH and VCCLATCH registers controls the select input to the multiplexer. If the DVPxVRD bit is set to a '0', the regulator uses the VID/VIDEN pins from the CPU, and if the DVPxVRD bit is set to a '1', the regulator uses the VNNLATCH and VCCLATCH registers to set the output voltage. When the DVPxVRD bit is set to a '0', any changes to the VNNLATCH and VCCLATCH registers should be ignored. When the DVPxVRD bit is set to a '1', any changes on the VID/VIDEN pins from the CPU should be ignored. As soon as the DVPxVRD bit is set to a '1', the regulator switches from using the VID/VIDEN pins to using the VCCLATCH register, and the output voltage of the regulator changes to what the VCCLATCH register is set. Figure 16 shows how the PMIC controls the VRCOMP signal. The PMIC toggles the VRCOMP signal any time the DVPxVRD bit is set to a '1' and the output voltage of the VNN or the VCC regulator changes. If the output voltage of the VCC/VNN regulator changes and the DVPxVRD bit is set to a '0', the VRCOMP signal should not toggle. VRCOMP only toggles for changes to VCC and VNN through the SPI registers. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE SCU SCU SCU SCU SCU Figure 16. Relationship Between the VID/VIDEN Pins, the DPV1VRD Bit, and VRCOMP Signal SPECIAL REGISTERS Vendor ID and Version ID The Vendor ID and other version details can be read via the Identification bits. These are hard-wired on the chip. Table 12. Vendor ID Registers Structure and Bits Description Name Bits Description ID1 (ADDR 0x00 - R - Default Value: 0x28) VENDID1 REV1 Reserved 2:0 5:3 7:6 Chip1 Vendor ID Chip1 Revision ID Reserved ID2 (ADDR 0x01 - R - Default Value: 0x00) VENDID2 REV2 Reserved 2:0 5:3 7:6 Chip2 Vendor ID Chip2 Revision ID Reserved ID3 (ADDR 0x02 - R - Default Value: 0x00) Reserved 7:0 Reserved ID4 (ADDR 0x03 - R - Default Value: 0x00) Reserved 7:0 Reserved Embedded Memory There are 24 memory registers of general purpose embedded memory, which are accessible by the processor to store critical data during power down. These registers consist of 8 in the general purpose registers area, and 16 more in the Freescale dedicated register area. General memory registers are called MEMx [MEM1, MEM2… MEM8]. The Freescale dedicated registers are called FSLMEMx [FSLMEM1, FSLMEM2… FSLMEM16]. The data written to these registers is maintained by the coin cell, when the main battery is deeply discharged or removed, and is part of the RTC block. The content of the embedded memory is reset by RTCPORB. The banks can be used for any system need, for bit retention with coin cell backup. 900844 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE X is from 1 to 8 in Table 13. Table 13. General Purpose Memory MEMx Register Structure and Bits Description Register MEMx Name Bits 7:0 Description General Purpose Memory Register x The rest of the 24 registers reside in the Freescale dedicated register space. X is from 1 to 16 in Table 14. Table 14. General Purpose Memory FSLMEMx Register Structure and Bits Description Register FSLMEMx Name Bits 7:0 Description General Purpose Memory Register x Output Driver Control Select output pins output drive capability can be programmed for 4 different settings as shows in the following tables. All of the following outputs follow the settings as shown. Table 15. Output Driver Control Selection Slope Select 0 0 1 1 0 1 0 1 Rise Time (ns) 8.4 6.2 Hi-Z 22.3 Fall Time (ns) 7.0 6.2 Hi-Z 21.3 Table 16. Output Driver Register Structure and Bit Description Name Bits Description FSLOUTDRVCNTL1 (ADDR 0x1BF - R/W - Default Value: 0x00) PWRGDDRV VRCOMPBDRV PMICINTDRV RESETBDRV 1:0 3:2 5:4 7:6 PWRGD Output Pin Driver Capability VRCOMP Output Pin Driver Capability PMICINT Output Pin Driver Capability RESETB Output Pin Driver Capability FSLOUTDRVCNTL3 (ADDR 0x1C1 - R/W - Default Value: 0x01) SPISDODRV RSVD 1:0 7:2 MISO Output Pin Driver Capability Reserved PLL Control The following register controls the PLL and the different divider values for different output frequencies. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 41 FUNCTIONAL DEVICE OPERATION SYSTEM CONTROL INTERFACE Table 17. PLL Control Register Structure and Bit Description Name Bits Description FSLPLLCNTL (ADDR 0x1E4 - R/W - Default Value: 0x1B) PLLDIVIDE 2:0 PLL Divide Ratio and Effective VCO Frequency Settings x0 = 112, 3.670 MHz x1 = 116, 3.801 MHz x2 = 120, 3.932 MHz x3 = 124, 4.063 MHz x4 = 128, 4.194 MHz x5 = 132, 4.325 MHz x6 = 136, 4.456 MHz x7 = 140, 4.588 MHz PLL16MEN 3 16 MHz frequency enable x0 = 16 MHz clock disabled x1 = 16 MHz clock enabled and PLL enabled PLLEN 4 PLL Enable, even if there is no block requesting a clock x0 = PLL enabled based on device enables only x1 = PLL enabled Reserved 7:5 Reserved TEST MODES Test Mode Configuration During evaluation and testing, the IC can be configured for normal operation or test mode via the ICTEST pin and other register configurations. Details of Test mode programmability are not documented herein, but should be referenced from other Design for Test documentation. Test modes are for Freescale use only, and must not be accessed in applications. In test modes, signals are multiplexed on existing functional pins. The ICTEST pin must therefore be tied to ground (for normal operation) at the board level, in product applications Test mode also disables the thermal protection for high temperature op life testing. A proprietary protocol is included for scan chain test configurations, which reuses the SPI pins. In-package Trimming During IC final test, several parameters are trimmed in the package, such as the main bandgap, and other precision analog functions. Trim registers are for Freescale use only and must not be accessed in product applications. Fuse programming circuitry will be blocked during normal and test mode operation. 900844 42 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) CLOCK GENERATION AND REAL TIME CLOCK (RTC) CLOCK GENERATION A system clock is generated for internal digital circuitry, as well as for external applications utilizing the clock output pins. A crystal oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running (for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. Clocking Scheme The internal 32 kHz oscillator is an integrated backup for the crystal oscillator and provides a 32.768 kHz nominal frequency at 50% accuracy, if running. The internal oscillator only runs if a valid supply is available at the battery or coin cell, and would not be used as long as the crystal oscillator is active. The crystal oscillator continues running, supplied from one of the sources as described previously, until all power is depleted or removed. All control functions will run off the crystal derived frequency, occasionally referred to as the "32 kHz". At system startup, the 32 kHz clock is driven to the CLK32K output pin, which is SPIVCC referenced. CLK32K is provided as a peripheral clock reference. The driver is enabled by the startup sequencer. Additionally, a SPI bit M32KCLK bit is provided for direct SPI control. The M32KCLK bit defaults to 0 to enable the driver and resets on the RTCPORB to ensure the buffer is activated at the first power up and configured as desired, for subsequent power ups. The drive strength of the output drivers is programmable with CLK32KDRV[1:0] (master control bits that affect the drive strength of CLK32K), see FSLOUTDRVCNTL2 Register in Table 16. If a switch over occurs between the two clock sources (such as when the crystal oscillator is starting up), it will occur during the active low phase of both clocks, to avoid clocking glitches. A status bit, OSCSTP, is available to indicate to the processor which clock is currently selected: OSCSTP=1 when the internal RC is used, and OSCSTP=0 if the XTAL source is used. Oscillator Specifications The 32 kHz crystal oscillator has been optimized for use in conjunction with the Abracon™ ABS07-32.768KHZ-T, or equivalent. The electrical characteristics of the 32 kHz Crystal oscillators are given in the Oscillator section on Table 3 and Table 4, taking into account the crystal characteristics noted previously. The oscillator accuracy depends largely on the temperature characteristics of the used crystal. Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component accuracy and/or tuning). Additionally, a clock calibration system is provided to adjust the 32.768 cycle counter that generates the 1.0 Hz timer and RTC registers; see Real Time Clock (RTC) for more detail. REAL TIME CLOCK (RTC) The RTC block provides a real-time clock with time-of-day, year, month, and date, as well as daily alarm capabilities. The realtime clock will use the 32.768 kHz oscillator as its input clock. The real-time clock will be powered by the coin cell backup battery as a last resort, if no other power source is available (Battery or USB/Wall plug). The register set is compatible with the Motorola™ MC146818 RTC device. Overview The RTC module uses a 15-bit counter to generate a 1.0 Hz clock for timekeeping. The seven time and calendar registers keep track of seconds, minutes, hours, day-of-week, day-of-month, month, and year. The three seconds, minutes, and hours alarm registers can be used to generate time-of-day alarm interrupts. The RTC time, alarm, and calendar values can be represented in 8-bit binary or BCD format. The hours and hours alarm values can be represented in 24 hour or 12 hour format, with AM/PM in the 12 hour mode. RTC control register B allows for software configurable clock formatting and interrupt masking. Control registers A, C, and D, report software testable RTC status, including interrupt flags, update-in-progress, and valid-RAM-time. The RTC resets when the RTCPORB signal is driven low. The clock and calendar registers will be initialized to 00:00:00, Sunday, January 1, 2000. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 43 FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) Features • • • • • • • • • • • • The RTC module includes the following features: Counts seconds, minutes, and hours of the day Counts days of the week, date, month, and year Binary or BCD representation of time, calendar, and alarm 12 or 24 hour clock with AM and PM in 12 hour mode Automatic leap year compensation Automatic end of month recognition 15 bytes of clock, calendar, RTC control, and coin cell registers Two interrupts are separately software maskable and testable Time-of-day Alarm End-of-clock update cycle interrupt 15-bit counter to generate 1.0 Hz RTC clock Software testable Valid-ram-and-time status bit indicates data integrity MODES OF OPERATION Normal mode In Normal mode, the RTC module updates time and calendar registers using the internal 1.0 Hz RTC clock. Once per second, the alarm registers are compared to the current time, and if enabled, an alarm interrupt will occur when the alarm time matches the current time. During normal operation, all 14 bytes of RTC and coin cell battery registers can be read through the SPI interface. Control register B may be updated to enable End-of-clock Update interrupts, alarm interrupts, or to put the RTC in Set mode. The coin cell charger register is available for R/W in normal mode. Coin Cell mode When the application is powered down, the RTC will continue to keep track of time using power provided by the coin cell battery. Since the system SPI will be powered down during this time, there is no read or write access to the RTC registers in Coin Cell mode. Set mode In Set mode, the clock and calendar updates are suspended, and the software may update the time, calendar, and alarm registers. The time and calendar formats must match the formats specified by the DM and 12/24 format bits in RTC register B. When the format bits are modified, all 14 time, calendar, and alarm registers must be updated in the specified format. Scan/Test mode Internal Test mode not available for the end application. Setting the Time, Calendar, and Alarm Before initializing the internal registers, the Set bit in Register B should be set to a "1" to prevent time/calendar updates from occurring. Select the RTC data format by writing the appropriate values to the DM and 24/12 bits in Register B. This can all be done simultaneously with one SPI write to register B. Next, the program should initialize all 10 time, calendar, and alarm locations, in the format specified by Register B (binary or BCD, 12 or 24 hour). All 10 time, calendar, and alarm bytes must use the same data mode, either binary or BCD. Both the alarm hours, and the hours bytes must use the same hours format, either 12 or 24. The Set bit may now be cleared to allow updates. Once initialized, the real-time clock makes all updates in the selected data mode. The data mode (DM) cannot be changed without re-initializing the 10 data bytes. The 24/12 bit in Register B establishes whether the hour locations represent 1-to-12 or 0-to-23. When the 12 hour format is selected the high order bit of the hour bytes represents PM when it is a "1". The 24/12 bit cannot be changed without re-initializing the hour and alarm-hour locations. Table 18 shows the binary and BCD formats of the 10 time, calendar, and alarm locations. 900844 44 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) Table 18. Time, Calendar, and Alarm Data Modes Address location 0x10 0x11 0x12 0x13 0x14 Function Decimal Range 0-59 0-59 0-59 0-59 1-12 0-23 1-12 0-23 1-7 1-31 1-12 0-99 Range Binary Data Mode $00-$3B $00-$3B $00-$3B $00-$3B $01-$0C(AM) / $81-$92(PM) $00-$17 $01-$0C(AM) / $81-$92(PM) $00-$17 $01-$07 $01-$1F $01-$0C $00-$63 BCD Data Mode $00-$59 $00-$59 $00-$59 $00-$59 $01-$12(AM) / $81-$92(PM) $00-$23 0B $01-$12(AM) / $81-$92(PM) $00-$23 $01-$07 $01-$31 $01-$12 $00-$99 05 0F 02 08 05 15 02 08 11 Example (17) Binary Data Mode 15 15 3A 3A 0B BCD Data Mode 21 21 58 58 11 Seconds Seconds Alarm Minutes Minutes Alarm Hours (12 Hour Mode) (24 Hour Mode) 0x15 Hours Alarm (12 Hour Mode) (24 Hour Mode) 0x16 0x17 0x18 0x19 Day of the Week Sunday=1 Date of the Month Month Year Notes 17. Example: 11:58:21 Thursday 15 February 2008 (time is AM) Reading the Time, Calendar, and Alarm Under normal operation, the current time and date may be read by accessing the RTC registers through the system SPI. Since the alarm is only updated by a SPI write instruction, the three alarm registers may be read at any time and will always be defined. The 900844 SPI will run at a minimum of 12.5 MHz. Each individual SPI read transaction requires 25 cycles (less for burstread). The RTC contains seven timekeeping registers to keep track of seconds, minutes, hours, day-of-week, day-of-month, month, and year. If the SPI is clocked at the slowest frequency, and the RTC is read using individual (not burst) SPI read commands, the following equation gives the maximum amount of time it takes the processor to read a complete date and time (assuming the reads are done sequentially, and uninterrupted): (25 * 7) / (12.5 MHz) = 14 μs. This equation shows that a program which randomly accesses the time and date information will find the data in transition statistically 14 times per million attempts. If a clock update occurs during the time it takes to read all seven timekeeping registers, the values read may be inconsistent. In other words, if the program starts to read the seven date/time registers and an RTC update occurs, the data collected may be in transition. In this event, it is possible to read transition data in one of the registers, resulting in undefined output. It is more likely that the registers read after the update would be incremented (by one second), and the registers read before the update would not. The time, calendar, and alarm bytes are always accessible by the processor program. Once per second, the seven bytes are advanced by one second and checked for an alarm condition. If any of the seven bytes are read at this time, the data outputs should be considered undefined. Similarly, all seven bytes should be read between updates to get a consistent time and date. Reading some of the bytes before an update and some after, may result in an erroneous output. The Update Cycle section explains how to accommodate the update cycle in the processor program. Update Cycle The RTC module executes an update cycle once per second, assuming one of the proper time bases is in place, and the SET bit in Register B is clear. The SET bit in the “1” state permits the program to initialize the time and calendar bytes, by stopping an existing update and preventing a new one from occurring. The primary function of the update cycle is to increment the Seconds byte, check for overflow, increment the Minutes byte when appropriate, and so forth, up through the month and year bytes. The update cycle also compares each alarm byte with the corresponding time byte, and issues an alarm if a match is present in all three positions. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 45 FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) Two methods of avoiding undefined output during updates are usable by the program. In discussing the two methods, it is assumed that at random points, user programs are able to call a subroutine to obtain the time of day. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every update cycle, which indicates that over 999 ms are available to read valid time and date information. Before leaving the interrupt service routine, the IRQF bit in Register C should be cleared. The second method uses the update-in-progress bit (UIP) in Register A, to determine if the update cycle is in progress. The UIP bit will pulse once per second. Statistically, the UIP bit will indicate that time and date information is unavailable once every 3,640 attempts. After the UIP bit goes high, the update cycle begins 244.1 μs later. Therefore, if a low is read on the UIP bit, the user has at least 244.1 μs before the time/calendar data will be changed. If a “1” is read in the UIP bit, the time/calendar data may not be valid. The user should avoid interrupt service routines which would cause the time needed to read valid time/calendar data to exceed 244.1 μs. The RTC uses seven synchronous counters to increment the time and calendar values. All seven timekeeping registers are clocked by the same internal 1.0 Hz clock, so updates occur simultaneously, even during rollover. After the counters are incremented, the current time is compared to the time-of-day alarm registers 30.5 μs later, and if they match, the AF bit in register C will be set. The Update-cycle begins when the clock and calendar registers are incremented, and ends when the alarm comparison is complete. During this 30.5 μs update cycle, the time, calendar, and alarm bytes are fully accessible by the processor program. If the processor reads these locations during an update, the transitional output may be undefined. The update in progress (UIP) status bit is set 244.1 μs before this interval, and is cleared when the update cycle completes. Interrupts The RTC includes two separate, fully automatic sources of interrupts to the processor. The alarm interrupt may be programmed to occur at a rate of once per day. The update-ended interrupt may be used to indicate to the program that an update cycle is completed. The processor program selects which interrupts, if any, it wishes to receive. Two bits in Register B enable the two interrupts. Writing a “1” to an interrupt-enable bit permits that interrupt to be initiated when the event occurs. A “0” in the interrupt-enable bit, prohibits the IRQF bit from being asserted due to the interrupt cause. If an interrupt flag is already set when the interrupt becomes enabled, the IRQF bit is immediately activated, though the interrupt initiating the event may have occurred much earlier. Thus, there are cases where the program should clear such earlier initiated interrupts before enabling new interrupts. When an interrupt event occurs, a flag bit is set to a “1” in Register C. Each of the two interrupt sources have separate flag bits in Register C, which are set independent of the state of the corresponding enable bits in Register B. The flag bit may be used with or without enabling the corresponding enable bits. In the software scanned case, the program does not enable the interrupt. The interrupt flag bit becomes a status bit, which the software interrogates when it wishes. When the software detects the flag is set, it is an indication to the software an interrupt event occurred since the bit was last read. However, there is one precaution. The flag bits in Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included with Register C, so the bits which are set are stable throughout the read cycle. All bits which are high when read by the program are cleared, and new interrupts (on any bits) are held until after the read cycle. One or two flag bits may be found to be set when Register C is used. The program should inspect all utilized flag bits every time Register C is read to insure that no interrupts are lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the IRQF bit is asserted high. IRQF is asserted as long as at least one of the two interrupt sources has its flag and enable bits both set. The processor program can determine that the RTC initiated the interrupt by reading Register C. A “1” in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the part. The act of reading Register C clears all the then active flag bits, plus the IRQF bit. When the program finds IRQF set, it should look at each of the individual flag bits in the same byte, which have the corresponding interrupt mask bits set and service each interrupt which is set. Again, more than one interrupt flag bit may be set. ALARM INTERRUPT The three alarm bytes may be used to generate a daily alarm interrupt. When the program inserts an alarm time in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day, if the alarm enable bit is high. 900844 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) Update-Ended Interrupt If enabled, an interrupt occurs after every update cycle which indicates that there is over 999 ms available to read valid time and date information. RTC Timer Calibration By default, the calibration circuit is off and clock accuracy is limited to the performance of the 32.768 kHz crystal input. For clock accuracy beyond the limits of the crystal oscillator, a calibration circuit is included. The processor can use a high-frequency clock to sample the 32.768 kHz output to determine if it is fast or slow, and calculate an adjustment value. The adjustment algorithm has a resolution of ±477 nanoseconds-per-second average adjustment, which equates to a time accuracy of approximately 1.2 seconds per month. Calibration can be turned on by setting the RTC ADJ bit of the ADJ register. A "0" in the ADJ bit turns calibration off. The Sign bit in the Trim register determines if periodic adjustments are made to speed up or slow down the clock. When calibration is enabled, the Trim register is used to grow or shrink the average 1.0 Hz clock period. By default, one second is defined as 32,768 periods of the CLK32K input pin. Each period of the input clock is approximately 30.5 μs. By occasionally adding (or subtracting) one extra cycle per second, the average second can be adjusted. If SIGN is high (subtract one), occasional seconds will be trimmed to 32,767 cycles. If SIGN is low (add one), occasional seconds will be trimmed to 32,769 cycles. The 6-bit TRIMVAL in the Trim register represents the number of seconds to adjust out of every 64 seconds, and can range from 0-63. For example, TRIMVAL = 0x08 then 8 seconds out of every 64 will be adjusted up or down, according to the SIGN bit. CLOCK GENERATION AND REAL TIME CLOCK (RTC) REGISTERS AND BITS DESCRIPTION Table 19. RTC Date/Time Configuration Register Structure and Bits Description Name Bits Description RTCS (ADDR 0x10 - R/W - Default Value: 0x00) SEC Reserved 6:0 7 Seconds Counter Register Reserved RTCSA (ADDR 0x11 - R/W - Default Value: 0x00) SECALARM Reserved 6:0 7 Seconds Alarm Setting Register Reserved RTCM1 (ADDR 0x12 -R/W - Default Value: 0x00) MIN Reserved 6:0 7 Minutes Counter Register Reserved RTCMA (ADDR 0x13 - R/W - Default Value: 0x00) MINALARM Reserved 6:0 7 Minutes Alarm Setting Register Reserved RTCH (ADDR 0x14 - R/W - Default Value: 0x00) HRS Reserved PA-H 5:0 6 7 Hours Counter Register Fixed to 0 AM/PM Indication, Only active during 12 Hr. mode x0 = AM x1 = PM 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 47 FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) Table 19. RTC Date/Time Configuration Register Structure and Bits Description Name Bits Description RTCHA (ADDR 0x15 - R/W - Default value: 0x00) HRSALARM Reserved PA-HA 5:0 6 7 Hours Alarm Setting Register Reserved (Fixed to 0) AM/PM Alarm Setting, Only active during 12 Hr. mode x0 = AM x1 = PM RTCDW (ADDR 0x16 - R/W - Default Value: 0x01) DOW Reserved 2:0 7:3 Day of Week counter register: 1= Sunday... 7= Saturday Reserved RTCDM (ADDR 0x17 - R/W - Default Value: 0x01) DOM Reserved 5:0 7:6 Day Of Month Counter Register Reserved RTCM2 (ADDR 0x18 - R/W - Default Value: 0x01) MONTH Reserved 19/20 4:0 6:5 7 Months Counter Register Reserved THIS BIT IS NOT SUPPORTED Always Reads 0 (treated as a reserved bit) RTCY (ADDR 0x19 - R/W - Default Value: 0x00) YEAR 7:0 Year Counter Register. Note: Values range from 0 to 99 Table 20. RTC Control Registers Structure and Bit Description Name Bits Description RTCA (ADDR 0x1A - R - Default Value: 0x20) Reserved UIP 6:0 7 Fixed to 010000 This is the Update In Progress (UIP) bit used as a status flag x0 = Update cycle not in progress x1 = Update cycle is in progress or will begin soon RTCB (ADDR 0x1B - R/W - Default Value: 0x02) Reserved HRMODE 0 1 Fixed to 0 Hour Format Control x0 = 12 Hour Mode x1 = 24 Hour Mode DM 2 Data Mode for Time and Calendar Updates x0 = Binary-Coded-Decimal (BCD) x1 = Binary Reserved UIE 3 4 Fixed to 0 Update-Ended Interrupt Enable x0 = Update-End (UF) bit in Register C is not permitted to assert the interrupt request flag (IRQF) in Register C x1 = Update-End (UF) bit in Register C is permitted to assert the interrupt request flag (IRQF) in Register C 900844 48 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK (RTC) Table 20. RTC Control Registers Structure and Bit Description Name AIE Bits 5 Alarm Interrupt Enable x0 = Alarm flag (AF) bit in Register C is not permitted to assert the interrupt request flag (IRQF) in Register C x1 = Alarm flag (AF) bit in Register C is permitted to assert the interrupt request flag (IRQF) in Register C Reserved SET 6 7 Fixed to 0 Set mode enable bit for the program to initialize the time and calendar bytes x0 = The update cycle functions normally by advancing the counts once-per-second. x1 = Any update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. RTCC (ADDR 0x1C - R - Default Value: 0x00) Reserved UF 3:0 4 Reserved Update-Ended Interrupt Flag. Set after each update cycle. X0 = UIE bit will not effect IRQF state x1 = When UIE bit goes high, the IRQF bit goes high AF 5 Alarm Interrupt Flag. Indicates that the current time has matched the alarm time. X0 = AIE bit will not effect IRQF state x1 = When AIE bit goes high, the IRQF bit goes high Reserved IRQF 6 7 Fixed to 0 Interrupt Request Flag. IRQF = (AF&AIE) + (UF&UIE) The interrupt request flag (IRQF) is set to a “1” when one or more of the following are true: AF = AIE = “1” UF = UIE = “1” x0 = Above Equation is not true x1 = Above Equation is true RTCD (ADDR 0x1D - R - Default Value: 0x00) Reserved VRT 6:0 7 Fixed to 000000 The Valid RAM and Time (VRT) bit indicates the condition of the contents of the RTC time and calendar registers. A "0" appears in the VRT bit when the RTC registers have been reset. The processor program should set the VRT bit after the time and calendar are initialized to indicate that the time and calendar are valid. The VRT bit can only be set by reading register D. RTCE (ADDR 0x1E - R/W - Default Value: 0x05) OSCSTP 0 Oscillator (32 kHz) Clock Stop Flag x0 = XTAL Oscillator x1 = Internal RC Oscillator BKDET 1 Coin Cell Backup Voltage Status x0 = No change x1 = Coin Cell below "low-voltage" threshold When this bit is set to 1, the SW takes corresponding action for a coin cell well below the operating voltage, and clears the BKDET to get ready for the next event. RTC Reset Flag x0 = No reset was detected x1 = POR occurred SCRATCH 7:3 These bits shall not exert any control over the operation of the RTC, and are intended to be used as scratch pad registers by the system controller. Their contents are erased on RTCPORB. Description POR 2 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 49 FUNCTIONAL DEVICE OPERATION POWER STATES AND CONTROL Table 20. RTC Control Registers Structure and Bit Description Name Bits Description ADJ (ADDR 0x1F - R/W - Default Value: 0x00) ADJ 0 RTC Trim Enable Signal x0 = Do Not Trim x1 = Trim Reserved 7:1 Fixed to 0000000 TRIM (ADDR 0x20 - R/W - Default Value: 0x00) TRIMVAL SIGN 5:0 6 6-Bit Trim Control This is a number from 0 to 63 that represents the number of seconds to adjust out of every 64 seconds RTC Calibration Sign Bit x0 = Add x1 = Subtract Reserved 7 Fixed to 0 CLKOUT (ADDR 0x21 - R/W - Default Value: 0x00) M32KCLK 0 32 kHz clock output mask x0 = 32 kHz clock output enabled x1 = 32 kHz clock output masked (disabled) Reserved 7:1 Fixed to 0000000 POWER STATES AND CONTROL OVERVIEW There are three different power states in the operation of the 900844 PMIC: 1. No Power State: No input voltage is available at the main supply or the coin cell battery input. 3. RTC State: The PMIC has enough power to support the RTC operation and the Keep Alive Registers, but not enough to power the rest of the system. 2. Active State: The PMIC has enough power to supply the system. The power state of the PMIC at any given time is determined by the conditions of the following inputs: 1. VPWR: This is the main supply to the system. It must be externally connected to VBAT. 2. VBAT: This is the main supply voltage sensing input. 3. VCOINCELL: This is the backup input voltage, typically from a rechargeable coin cell battery. INTERNAL SUPPLIES POWER TREE Figure 17 shows the 900844 internal power tree. 900844 50 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER STATES AND CONTROL VBAT VCOINCELL RTC STATE ACTIVE STATE VPWR UVDET VBOS EN Keep Alive Bandgap 1.2V VCORERTC 1.2V EN VCOREREF 0.9V CLOCK RC/XTAL Keep Alive Registers EN VCOREDIG VCORE EN 1.5V Digital Supply Closed when VCOREDIG > 1.2V 1.2V Reference Supply 2.775V Analog Supply Figure 17. 900844 Internal Power Tree Block Diagram As part of the turn on sequence, the 900844 enables a set of internal supplies that provide power to the rest of the circuitry: 1. VCOREREF: This is the main bandgap and reference voltage for all internal circuitries. 2. VCORE: This is the supply for the internal analog circuitry. 3. VCOREDIG: This is the supply for the internal digital circuitry. Table 21 summarizes the voltage references on the 900844. Table 21. 900844 Internal Power Supply Summary Reference VCOREREF (Bandgap & Regulators Reference) VCOREDIG (Digital Core Supply) VCORE (Analog Core Supply) Parameter Output Voltage Bypass Capacitor Output Voltage Bypass Capacitor Output Voltage Bypass Capacitor Target 1.2 V 100 nF typ. 1.5 V 2.2 μF typ. 2.775 V 2.2 μF typ. There is an internal node called the Best of Supply node (VBOS), which supplies the Real Time Clock and the Keep Alive Registers. This ensures that power to these critical circuits is maintained for maximum life. VBOS represents the highest of the VBAT and VCOINCELL input voltages. When VCOREDIG is > 1.2 V, an internal switch is closed, and the circuitry that was powered from VBOS is now powered from VCOREDIG. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 51 FUNCTIONAL DEVICE OPERATION POWER STATES AND CONTROL POWER STATES Figure 18 shows the flow of power, the different power states, and the conditions necessary to transition between the different states. This diagram serves as the basis for the description in the remainder of this section. NO PWR VBAT < VBATOFF VCOIN < VCOINOFF VBAT > VBATOFF VBAT < VBATOFF & VCOIN < VCOINOFF RTC STATE * RTC Is Powered * Time of Day is kept * Keep alive registers are powered * All other Circuits OFF VBAT < VLOWBAT & VCOIN > VCOINOFF VBAT > VLOWBAT RAMP UP VBAT > VLOWBAT BAT Operation * VPWR = VBAT * VPWR > VPWRUVR BATDET INT= 1 * Internal supplies/references ON * Logic is Reset * Initial power sequence performed * SPI Ready * SCU Interrupted VBAT < VBATOFF & VCOIN < VCOINOFF VPWR < VPWRUVF & VCOIN > VCOINOFF ACTIVE STATE SCU CONTROL (BAT Operation) * VPWR = VBAT RDSTATE = 0x00 * SCU takes control * SCU Sets the system VBAT < Vtrkl & VCOIN > VCOINOFF Figure 18. 900844 Power States 900844 52 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER STATES AND CONTROL No Power State In this state, every source of power has been removed or is fully depleted: • VBAT < VBATOFF: The input voltage is under the cutoff threshold, indicating that the main supply has been removed, or has been isolated by its own protection circuitry, and • VCOIN < VCOINOFF: The coin cell backup battery has been removed or has been isolated by the 900844 coin cell discharge prevention circuitry (see Coin Cell Battery Backup/Charger) The 900844 has lost any source of power to maintain the RTC and its keep alive registers, and all the internal circuits power down and time of day cannot be kept. RTC State In this state, the 900844 has limited power. The VBOS is available and powers the RTC and the Keep Alive Registers. However, the system does not have enough power to enter the active state: • VCOIN > COINOFF: The backup battery is above the coin cell disconnect threshold. • VPWR < VPWRUVF: The system voltage is less than the under-voltage falling threshold. During this mode, all voltage regulators are off and cannot be powered. The RTC is operating (Real Time Clock (RTC)), and the time of day and all keep alive registers are maintained. Active State In this state, the 900844 internal circuits are fully powered: • VPWR > VPWRUVR: The system voltage, VPWR, is available and valid, and • VBAT > VLOWBAT: The main input voltage is above a low battery condition. All features of the 900844 are either operating or can be enabled, which is under the control of the System Control Unit (SCU) within the Platform Controller Hub (PCH). Power State Transitions When power is applied to the 900844 for the first time, it goes from the No Power state into the Active state, with a brief transition through the RTC state. The RTC and the Keep Alive Registers are powered, and the time of day is initialized to a factory set value (See Real Time Clock (RTC)). When VPWR crosses the under-voltage rising detection threshold (VPWRUVR), the internal supplies power on, the logic is reset, the initial power sequence is performed, SPI communication is enabled, and an interrupt to the Platform Controller Hub is generated. The PMIC enters the Active state and the system is under control of the SCU. If VPWR crosses the under-voltage falling detection threshold (VPWRUVF), and at least one of the VBOS supplies (VCOIN or VBAT) is still valid, the 900844 enters the RTC state. Only the RTC is operating and the RTC and Keep Alive registers are maintained. If the 900844 is in the RTC state, full operation is obtained when the voltage at VPWR crosses again the under-voltage rising detection threshold (VPWRUVR). TURN ON EVENTS A turn on event occurs when a valid input voltage is present at VBAT (VBAT > VLOWBAT), and the system voltage goes above the under-voltage rising threshold (VPWR > VPWRUVR). Otherwise, the 900844 is in the RTC or No Power State. When a turn on event occurs, the BATDET interrupt bit is set. Reference Interrupt Controller for more information on the different system interrupts. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 53 FUNCTIONAL DEVICE OPERATION POWER STATES AND CONTROL Battery or Brick Inserted VPWR VCCPAOAC Figure 19. 900844 Initial Power Up Sequence Initial Power Up Sequence Figure 19 shows the 900844 initial power up sequence: 1. A valid system voltage is applied 2. VPWR ramps up 3. The 900844 internal circuits are powered 4. The 900844 turns on a minimal set of voltage rails as outlined in Figure 19 5. SPI communication is ready 6. PMICINT pin is asserted 7. The system controller unit (SCU) reads the 900844 interrupt flag register (over SPI) to see why the 900844 interrupted the platform controller hub. 8. The SCU decides whether to boot the rest of the system, or just run SCU code to manage various functions. 9. If the SCU decides to power up system, then CPU (central processing unit) drives VNN VID, VIDEN[1:0] = 10 to the 900844 and BSEL to the Platform controller hub. 10. The 900844 drives CPU selected voltage for VNN 11. There will be no explicit signaling from the 900844 that indicates that the VNN ramp has been complete. 12. VIDEN[1:0] is driven to 00 to avoid it switching from 10 to 01 directly. 13. The CPU drives the VCC boot VID on the VID pins. The VIDEN[1:0] = 1 enables, only after HPLL has locked. 14. X86 Instruction Executions starts. Table 22. 900844 Initial Power Up Timing Parameter t1 t2 t3 t4 t5 Description PMIC internal regulator Ramp-up V15 turn on delay V15 Ramp-up VAON/VCCPAOAC turn on delay VAON/VCCPAOAC ramp-up Min 18 ms 0 μs Typ Max 100 μs 550 ms 10 μs 31 μs 700 μs 900844 54 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER STATES AND CONTROL Table 22. 900844 Initial Power Up Timing Parameter t6 t7 t8 t9 t10 t11 t12 Description V21 turn on delay V21 ramp-up VPMIC turn on delay VPMIC ramp-up PWRGD delay RESET delay PMICINT delay Min 0 μs 0 μs 70 ms 1.0 μs 31 μs Typ Max 31 μs 100 μs 31 μs 700 μs 90 ms 31 μs 124 μs TURN OFF EVENTS The following conditions cause the 900844 to power off the system, including the SCU, but the 900844 internal circuitry and logic are still active: • PWRBTN pressed for more than 5 seconds. See Power Button Functionality (PWRBTN). • The 900844 junction temperature is above the thermal shutdown threshold. See Thermal Management for more details. • A THERMTRIPB assertion. See THERMTRIPB Pin for more details. Power Button Functionality (PWRBTN) The Power Button is pulled up internally through a 132 k resistor to the VCOREDIG output voltage node. See Figure 20 for more details. . VCOREDIG 132k PWRBTN Figure 20. PWRBTN Circuit Diagram Figure 21 describes the functionality of the PWRBTN Figure 21. PWRBTN Function Flow Diagram 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 55 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES DETECTION THRESHOLDS Table 23 summarizes the various detection thresholds between the different states: Table 23. Power States Detection Thresholds Characteristic Input Voltage Cutoff Threshold Coin Cell Disconnect Threshold Low input voltage Threshold Valid input voltage Threshold VPWR Rising Under-voltage Threshold VPWR Falling Under-voltage Threshold Symbol VBATOFF VCOINOFF VLOWBAT VTRKL VPWRUVR VPWRUVF Min 2.2 1.8 3.2 Typ 3.0 3.1 2.55 Max 2.4 2.0 Unit V V V V V V POWER SUPPLIES POWER MAP Figure 22 is a power map of Freescale’s power management solution for Ultra-mobile platforms for Netbooks/ and tablet PC: VCC (0.65V-1.2V) DC/DC Max Current VNN (0.65V-1.2V) 3500mA DC/DC Max Current VDDQ (1.5V) 1600mA DC/DC Max Current VBG (1.25V) 1000mA 2mA LDO Max Current VCCA (1.5V) Max Current V21 (2.1V) 75mA DC/DC LDO Max Current VCC180 (1.8V) 1035mA 390mA LDO LDO Max Current VPNL18 (1.8V) Max Current VCCPDDR (1.05V) 225mA LDO Max Current VMM (1.2V) 60mA LDO Max Current Max Current VCCP (1.05V) 3mA LDO VCCPAOAC (1.05V) 40mA 418mA LDO LDO Max Current PVIN INPUT POWER ADAPTER OR BATTERY VPWR VAON (1.2V) Max Current V15 (1.5V) 250mA 1185.8mA 80mA LDO DC/DC Max Current 3.3 V POWER PATH Always on MANAGER VIMG25 (2.5V) Max Current VSDIO LDO/Switch 1.8V - LDO 3.3V - Switch VPMIC (1.8V) 207.5mA 207.5mA LDO Max Current VIMG28 (2.8V) 50mA 225mA Switch LDO Max Current VPNL33 (3.3V) Max Current VYMXYFI18 100mA LDO YFI - 1.8V YMX - 1.8V 200mA 200mA Figure 22. 900844 Power Map 900844 56 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES DC/DC POWER SUPPLIES Freescale’s power management solution for the Ultra-mobile platform for Netbook/Tablets and Slates, includes 5 DC/DC switching regulators integrated on the 900844 PMIC. the five DC-DC regulators are Buck converters, and these can be set to work in the following operation modes: Buck converters Operation Modes Selections (VCC, VNN, VDDQ, V21, V15) • OFF - The regulator is switched off and the output voltage is discharged. • PFM - The regulator is switched on and set to PFM mode operation. In this mode, the regulator is always running in PFM mode. Useful at light loads for optimized efficiency. • Automatic Pulse Skip - The regulator is switched on and set to Automatic Pulse Skipping. In this mode, the regulator moves automatically between pulse skipping and full PWM mode depending on load conditions. • PWM - The regulator is switched on and set to PWM mode. In this mode, the regulator is always in full PWM mode operation regardless of load conditions. • TEST/TRIM - This is not a functional mode, thus requiring certain steps to prevent unintentional activation of this mode. During this mode, the device performs measurements and trimming. DC-DC Power Supply Summary Table Table 24 provides a summary of all DC/DC regulators on the 900844. Table 24. 900844 DC-DC power supplies. Regulator VCC Typ. Voltage 0.3 - 1.2 V Max Continuous Current 3.5 A Description 1.0 MHz synchronous Buck converter with external switching MOSFETs. Internally compensated. VID is controlled using a shared 7-bit bus for voltage coding and 2 VID enable signals for VCC or VNN selection. 1.0 MHz synchronous Buck converter with external switching MOSFETs. Internally compensated. VID is controlled using a shared 7-bit bus for voltage coding and 2 VID enable signals for VCC or VNN selection. 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage mode control DC/DC regulator. 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage mode control DC/DC regulator. 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage mode control DC/DC regulator. VNN 0.3 - 1.2 V 1.6 A VDDQ V21 V15 1.8 V/1.5 V 2.1 V 1.5 V 1.3 A 1.0 A 1.5 A Note that all of the DC/DC regulators specify an extended input voltage range beyond the 3.0 to 4.4 V applications range. Below this, extended range functionality is maintained, but parametric performance could be compromised. VCC This is a VID controlled single-phase 1.0 MHz 2-switch synchronous Buck PWM voltage mode control DC/DC regulator, designed to power high performance CPUs. VCC uses external MOSFETs, P-Ch high side and N-Ch low side. VCC includes support for VID active voltage positioning requirements. A 7-bit DAC reads the VID input signals and sets the output voltage level. The output voltage has a range of 0.3 to 1.2 V. The programming step size is 12.5 mV. Values will be read in real time and will be stored in internal registers not accessible to the system host. Reference VIDEN[1:0] & VID[6:0] Pins for more details. The same VID input signals are shared between VCC and VNN, where a latch signal for each regulator decides which regulator takes control of the VID input signals. The DAC value represents the output voltage value. The output voltage node is connected directly to the inverting input of the error amplifier that uses the DAC output as its reference, unity gain configuration. Using this configuration with internal compensation eliminates the need for the feedback and compensation network, which saves board space and cost. The DAC/ output voltage slew rate is internally set 25 mV/µs to minimize transient currents and audible noise. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 57 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode. The above selection is optimized to maximum battery life based on load conditions. VCC will be discharged every time the regulator is shutting down. The output current will be sensed using an intelligent implementation of the DCR sensing method using internal sensing circuitry, which eliminates the need for an external RC filter network in parallel with the output inductor and its winding resistance. DCR sensing theory is that if the impedance of the two filters are matching by insuring that R*C = L/RW, then the voltage across the capacitor is equal to the value of the voltage across the winding resistance RW, VCAP = ILOAD*RW. Based on this, the voltage across the capacitor is measured, and with a known RW value, the load current can be extracted. The measured current value will be digitized by the ADC and stored in a register for the processor to access. The method used on the 900844 measures the voltage across RW in a similar fashion, while using internal sensing circuitry. The sensed output current value will also be used for over-current protection. If an over-current condition is detected, the regulator will limit the current through cycle by cycle operation, and alert the system through the VCCFAULT signal, which will in turn assert the VRFAULT Interrupt signal. VPWR CINCC HSCCGT VCC COCC LCC MHSCC Driver MLSCC LSCCGT PGNDCC Current Sense Amp ICC Internal Compensation VOUTFBCC Z1 EA VREF DAC GNDREFVCC VIDEN0 VIDEN1 VCCFAULT SPI Interface Controller CTLVCC AOACCTLVCC PVINCC SWFBCC CSPCC Figure 23. VCC Detailed Internal Block Diagram Main Features • • • • • • • • • • Uses the VPWR rail as its power supply It is used to provide power to the CPU Core. Single-phase Solution with Integrated Drivers and external MOSFETs VID Controlled for dynamic voltage scaling requirements of high performance processors 1.0 MHz switching frequency High efficiency operating modes depending on load conditions Output can be discharged through the low side switch. Loss-Less Output Current Sensing with over-current protection Uses internal compensation Gate drive circuits are supplied directly from VPWR Efficiency Curves The efficiency curves in Figure 24 are calculated under PWM mode, based on the recommended external component values and typical output voltage of 1.2 V. 3.0 V ≤ VPWR ≤ 4.4 V. 900844 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Z2 58 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES 4 Figure 24. VCC Efficiency Curve VCC Status/Control Registers and Bits Description Reference the register map for read/write conditions and default state for each of these registers. Table 25. VCC Status Registers Structure and Bits Description Name Bits Description VCCCNT (ADDR 0X35 - R/W - DEFAULT VALUE: 0X24) CTLVCC 2:0 VCC State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVCC 5:3 x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM VCC State Control during AOAC Exit (when Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM Reserved 7:6 Reserved VCCLATCH (ADDR 0X32 - R/W - DEFAULT VALUE: 0X7F) VIDVCC DVP1VRD 6:0 7 VID VCC Control Through SPI. Signal codes are identical to the VID signal codes. Reference Figures 15 for more details VCC Register override enable bit. X0 = VCC VID control follows the external pins x1 = VCC VID control follows the VIDVCC control register bits VNN This is a VID controlled single-phase 1.0 MHz 2-switch synchronous Buck PWM voltage mode control DC/DC regulator, designed to power high performance CPUs. VNN uses external MOSFETs, P-ch high side and N-ch low side. VNN includes support for VID active voltage positioning requirements. A 7-bit DAC reads the VID input signals and sets the output voltage level. The output voltage has a range of 0.3 to 1.2 V. The programming step size is 12.5 mV. Values will be read in real time and will be stored in internal registers not accessible to the system host. Reference VIDEN[1:0] & VID[6:0] Pins. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 59 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES The same VID input signals are shared between VNN and VNN, where a latch signal for each regulator decides which regulator takes control of the VID input signals. The DAC value represents the output voltage value. The output voltage node is connected directly to the inverting input of the error amplifier that uses the DAC output as its reference, unity gain configuration. Using this configuration with internal compensation eliminates the need for the feedback and compensation network, which saves board space and cost. The DAC/ output voltage slew rate is internally set 25 mV/µs to minimize transient currents and audible noise. The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode. The previous selection is optimized to maximum battery life based on load conditions. VNN will be discharged every time the regulator is shutting down. The output current is sense in the same way as it is done on VCC regulator. (See VCC) The sensed output current value will also be used for over-current protection. If an over-current condition is detected, the regulator will limit the current through cycle by cycle operation and alert the system through the VNNFAULT signal, which will in turn assert the VRFAULT Interrupt signal. VPWR CINCC HSNNGT VNN CONN LNN MHSNN Driver MLSNN LSNNGT PGNDNN Current Sense Amp INN Internal Compensation VOUTFBNN Z1 EA VREF DAC VIDEN0 VIDEN1 VNNFAULT SPI Interface Controller CTLVNN AOACCTLVNN PVINNN SWFBNN CSPNN Figure 25. VNN Detailed Internal Block Diagram Main Features • • • • • • • • • • Uses the VPWR rail as its power supply It is used to provide power to the Graphics Core. Single-phase Solution with Integrated Drivers and external MOSFETs VID Controlled for dynamic voltage scaling requirements of high performance processors 1.0 MHz switching frequency High efficiency operating modes depending on load conditions Output can be discharged through the low side switch. Loss-Less Output Current Sensing with over-current protection Uses internal compensation Gate drive circuits are supplied directly from VPWR Efficiency Curves Figure 26 efficiency curves are calculated under PWM mode based on the recommended external component values and typical output voltage of 1.2 V. 3.0 V ≤ VPWR ≤ 4.4 V. 900844 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Z2 60 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES 4 Figure 26. VNN Efficiency Curve VNN Status/Control Registers and Bits Description Reference the register map for read/write conditions and default state for each of these registers Table 26. VNN Status and Control Registers Structure and Bits Description Name Bits Description VNNCNT (ADDR 0x36 - R/W - Default value: 0x04) CTLVNN 2:0 VNN State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVNN 5:3 x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM VNN State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM Reserved 7:6 Reserved VNNLATCH (ADDR 0x33 - R/W - Default value: 0x7F) VIDVNN DVP1VRD 6:0 7 VID VNN Control Through SPI. Signal codes are identical to the VID signal codes. Reference Figure 15 for more details VNN Register override enable bit. X0 = VNN VID control follows the external pins x1 = VNN VID control follows the VIDVNN control register bits VDDQ This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage mode control DC/DC regulator. The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode. VDDQ will be discharged every time the regulator is shutting down. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 61 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES The output current is measured internally, digitized by the ADC, and stored in a register for the processor to access. The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator will limit the current through a cycle by cycle operation and alert the system through the VDDQFAULT signal, which will in turn assert the VRFAULT Interrupt signal. VDDQ is originally prepared to provide 1.8 V by connecting VDDQ output voltage directly to FBDDQ node, refer to Figure 27. To provide flexibility, VDDQ can also be set to 1.5 V by adding a resistor divider from VDDQ output to the FBDDQ using VCORE as voltage reference, refer to Figure 28. The following are the recommended resistor values for the feedback divider: • RFBDDQ15_1 = 680 Ω • RFBDDQ15_2 = 2.21 kΩ VPWR CINDDQ V DDQ L DDQ CODDQ PGNDDDQ PVINDDQ ISENSE 5 CTLVDDQ AOACCTLVDDQ SWDDQ Controller Driver VDDQFAULT SPI Interface Internal Compensation FBDDQ Z1 Z2 EA V REF Figure 27. VDDQ Detailed Internal Block Diagram (VDDQ at 1.8 V) VPWR CINDDQ VDDQ LDDQ CODDQ PVINDDQ ISENSE5 CTLVDDQ AOACCTLVDDQ SWDDQ Controller Driver VDDQFAULT SPI Interface PGNDDDQ RFBDDQ15_1 FBDDQ Internal Compensation Z1 Z2 EA RFBDDQ15_2 VREF VCORE Figure 28. VDDQ Detailed Internal Block Diagram (VDDQ at 1.5 V) Main Features • Uses the VPWR rail as its power supply • It is used as a pre-regulator to many LDO rails, for enhanced efficiency and reduced thermal dissipation. It also supplies power to rails in the CPU (central processing unit), Platform controller hub, and the platform • Uses Integrated MOSFETs • 4.0 MHz switching frequency • High efficiency operating modes depending on load conditions • Output can be discharged through the low side switch. • Peak current sensing with over-current protection 900844 62 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES • Uses internal compensation • Gate drive circuits are supplied directly from VPWR Efficiency Curves Figure 29 efficiency curves are calculated under PWM mode, based on the recommended external component values and typical output voltage of 1.8 V. 3.0 V ≤ VPWR ≤ 4.4 V. 4 Figure 29. VDDQ Efficiency Curves VDDQ Status/Control Registers and Bits Description Reference the register map for read/write conditions and default state for each of these registers. Table 27. VDDQ Status and Control Register Structure and Bits Description Name Bits Description VDDQCNT (ADDR 0x37 - R/W - Default Value: 0x04) CTLVDDQ 2:0 VDDQ State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVDDQ 5:3 x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM VDDQ State Control during AOAC Exit (when EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM Reserved 7:6 Reserved V21 This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage-mode control DC/DC regulator. The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode. The previous selection is optimized to maximum battery life based on load conditions. V21 will be discharged every time the regulator is shutting down. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 63 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES The output current is measured internally, digitized by the ADC, and stored in a register for the processor to access. The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator will limit the current through cycle by cycle operation and alert the system through the V21FAULT signal, which will in turn assert the VRFAULT Interrupt signal. VPWR CIN 21 V 21 L 21 CO21 PGND21 PVIN 21 ISENSE 5 CTLV21 AOACCTLV21 SW21 Controller Driver V21FAULT SPI Interface Internal Compensation FB21 Z1 Z2 EA V REF Figure 30. V21 Detailed Internal Block Diagram Main Features • • • • • • • • • Uses the VPWR rail as its power supply It is used as a pre-regulator to many LDO rails, for enhanced efficiency and reduced thermal dissipation. Uses Integrated MOSFETs 4.0 MHz switching frequency High efficiency operating modes depending on load conditions Output can be discharged through the low side switch. Peak current sensing with over-current protection Uses internal compensation Gate drive circuits are supplied directly from VPWR Efficiency Curves Figure 31 efficiency curves are calculated under PWM mode, based on the recommended external component values and typical output voltage of 2.1 V. 3.0 V ≤ VPW ≤ 4.4 V. 900844 64 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES 4 Figure 31. V21 Efficiency Waveforms 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 65 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES V21 Status/Control Registers and Bits Description Reference the register map for read/write conditions and default state for each of these registers. Table 28. V21 Status/Control Registers Structure and Bits Description Name Bits Description V21CNT (ADDR 0x38 - R/W - Default value: 0x07) CTLV21 2:0 V21 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLV21 5:3 x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM V21 State Control during AOAC Exit (when EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM Reserved 7:6 Reserved V15 This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage-mode control DC/DC regulator. The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode. The above selection is optimized to maximum battery life based on load conditions. V15 will be discharged every time the regulator is shutting down. The output current is measured internally, digitized by the ADC, and stored in a register for the processor to access. The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator will limit the current through cycle by cycle operation and alert the system through the V15FAULT signal, which will in turn assert the VRFAULT Interrupt signal. VPWR CIN 15 V 15 L 15 CO15 PGND15 PVIN 15 ISENSE 5 CTLV15 AOACCTLV15 SELV15 Controller SW15 Driver V15FAULT SPI Interface Internal Compensation FB15 Z1 Z2 EA V REF Figure 32. V15 Detailed Internal Block Diagram Main Features • Uses the VPWR rail as its power supply • It is used as a pre-regulator to many LDO rails, for enhanced efficiency and reduced thermal dissipation. It also supplies power to rails in the Platform controller hub • Uses Integrated MOSFETs 900844 66 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES • • • • • • 4.0 MHz switching frequency High efficiency operating modes depending on load conditions Output can be discharged through the low side switch. Peak current sensing with over-current protection Uses internal compensation Gate drive circuits are supplied directly from VPWR Efficiency Curves Figure 33 efficiency curves are calculated under PWM mode, based on the recommended external component values and typical output voltage of 1.5 V. 3.0 V ≤ VPWR ≤ 4.4 V. 4 Figure 33. V15 Efficiency Curves V15 Status/Control Registers and Bits Description Reference the register map for read/write conditions and default state for each of these registers. Table 29. V15CNT Register Structure and Bits Description Name Bits Description V15CNT (ADDR 0x39 - R/W - Default value: 0x07) CTLV15 2:0 V15 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLV15 5:3 x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM V15 State Control during AOAC Exit (when EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = PFM x6 = Automatic Pulse Skipping x7 = PWM SELV15 7:6 V15 Output Voltage Selection (FSL Usage Only) X0 = 1.5 V x1 = 1.6 V x2, x3 = Reserved 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 67 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES LDO POWER SUPPLIES Freescale’s power management solution for the Ultra-mobile platform for Netbooks, Tablets, and Slates includes 14 LDO regulators, all of which are housed in the 900844 PMIC. LDO OPERATION MODES SELECTIONS OFF - The regulator is switched off ACTIVE - The regulator is switched on and the output is at the programmed level. The maximum load current is allowed. LOW POWER - The regulator is switched on and the outputs is at the programmed level. The load current is limited. TEST/TRIM - This is not a functional mode, thus requiring certain steps to prevent unintentional activation of this mode. During this mode, the device performs measurements and trimming. All LDOS are able to work in a low power mode, in which the bias current is reduced. The output drive capability and performance are limited in this mode. This mode occurs automatically when the load current decreases below the low power mode limit, except on VBG and VMM, in which this mode can only be set through SPI programming. All other LDOS can set the low power mode through SPI programming. Note: If low power mode is set through the SPI at a load current higher than the maximum allowed, the performance of the LDO is not guaranteed. Table 30 is a summary of LDO characteristics • • • • Table 30. 900844 LDO Power Supplies Summary Regulator VBG VCCA VCC180 VPNL18 VPMIC VYMXYFI18 VCCPAOAC VCCPDDR VAON VMM VCCP VIMG25 VIMG28 VSDIO Typ. Voltage 1.25 V 1.5 V 1.8 V 1.8 V 1.8 V 1.8 V 1.05 V 1.05 V 1.2 V 1.2 V 1.05 V 2.5 V 1.5 - 2.9 V 1.8 or 3.3 V Max Continuous Current 2.0 mA 150 mA 390 mA 225 mA 50 mA 200 mA 155 mA 60 mA 250 mA 5.0 mA 445 mA 80 mA 225 mA 215 mA Description Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. Low Dropout (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR with a low quiescent current and fast transient response. VSDIO is a combo Low Dropout (LDO) and power switch. It uses an external P-CH Pass FET, applicable only in power switch mode. VSDIO serves as an LDO when its output voltage is set to 1.8 V, and as a switch when its output voltage is set to 3.3 V. 900844 68 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES VBG VBG is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VBG is actively discharged during shutdown. VBG shares an input voltage pin (PVIN1P8) and a reference ground pin (GND1P8) with the VCCA regulator, yet each has independent control. PVIN1P8 is supplied from the VDDQ voltage if VDDQ output is set to 1.8 V, otherwise connect to V21 when VDDQ is set to 1.5 V. V DDQ PVIN 1P8 CIN1P8 + VOBG VOUTBG COBG Z VOBG IOBG Discharge Controller _ VREF CTLVBG AOACCTLVBG SPI Interface Output Monitor VBGFAULT GND1P8 Figure 34. VBG Detailed Internal Block Diagram Main Features • • • • • Uses VDDQ or V21 as the main power supply 2.0 mA maximum continuous output current Optimized for a 1.0 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events VBG Status/Control Registers and Bits Description Reference the register map for read/write conditions and default state for each of these registers. Table 31. VBG Control Register Structure and Bits Description Name Bits Description VLBGCNT (ADDR 0x3F - R/W - Default Value: 0 x24) CTLVBG 2:0 VBG State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVBG 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VBG State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VCCA VCCA is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCA is actively discharged during shutdown. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 69 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES VCCA shares an input voltage pin (PVIN1P8) and a reference ground pin (GND1P8) with VBG regulator, yet each has independent control. PVIN1P8 is supplied from the VDDQ voltage if VDDQ output is set to 1.8 V, otherwise connect to V21 when VDDQ is set to 1.5 V. (Shared with VBG) PVIN 1P8 Controller _ + V REF CTLVCCA AOACCTLVCCA SPI Interface VOCCA C OCCA VOUTCCA FBCCA VOCCA I OCCA Discharge Z Output Monitor VCCAFAULT (Shared with VBG) GND1P8 Figure 35. VCCA Detailed Internal Block Diagram Main Features • • • • • Uses VDDQ or V21 as the main power supply 150 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 32. VCCA Control Register Structure and Bits Description Name Bits Description VCCACNT (ADDR 0x40 - R/W - Default Value: 0x3C) CTLVCCA 2:0 VCCA State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVCCA 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VCCA State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VCC180 VCC180 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCC180 is actively discharged during shutdown. VCC180 shares an input voltage pin (PVIN2P1) and a reference ground pin (GND2P1) with VPNL18 and VPMIC regulators, yet each has independent control. PVIN2P1 is supplied from the V21 voltage. The output current for VCC180 is measured and reported through the ADC. Reference ADC Subsystem for more information. 900844 70 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES V21 PVIN 2P1 CIN2P1 + VOCC180 VOUTCC180 COCC180 Z VOCC180 IOCC180 Discharge Controller _ V REF CTLVCC180 AOACCTLVCC 180 SPI Interface Output Monitor VCC180FAULT GND2P1 Figure 36. VCC180 Detailed Internal Block Diagram Main Features • • • • • Uses V21 as the main power supply 390 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 33. VCC180CNT Register Structure and Bits Description Name Bits Description VCC180CNT (ADDR 0x43 - R/W - 0x3C) CTLVCC180 2:0 VCC180 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVCC180 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VCC180 State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VPNL18 VPNL18 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VPNL18 is actively discharged during shutdown. VPNL18 shares an input voltage pin (PVIN2P1) and a reference ground pin (GND2P1) with VCC180 and VPMIC regulators, yet each has independent control. PVIN2P1 is supplied from the V21 voltage. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 71 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES ( Shared with VCC180 and VPMIC) PVIN 2P1 Controller _ + V REF CTLVPNL18 AOACCTLVPNL18 SPI Interface VOPNL18 VOUTPNL18 COPNL18 Z VOPNL18 IOPNL18 Discharge Output Monitor VPNL18FAULT GND2P1 ( Shared with VCC180 and VPMIC) Figure 37. VPNL18 Detailed Internal Block Diagram Main Features • • • • • Uses V21 as the main power supply 225 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 34. VPNL18 Control Register Structure and Bits Description Name Bits Description VPANEL18CNT (ADDR 0x46 - R/W - Default value: 0x24) CTLVPANEL18 2:0 VPNL18 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVPANEL18 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VPNL18 State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VPMIC VPMIC is a low drop-out (LDO) fully integrated regulator with a P-CH pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VPMIC is actively discharged during shutdown. VPMIC shares an input voltage pin (PVIN2P1) and a reference ground pin (GND2P1) with VCC180 and VPNL18 regulators, yet each has independent control. PVIN2P1 is supplied from the V21 voltage. 900844 72 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES (Shared with VCC180 and VPNL18) PVIN 2P1 Controller _ + V REF CTLVPMIC AOACCTLVPMIC SPI Interface VOPMIC VOUTPMIC C OPMIC Z V OPMIC IOPMIC Discharge Output Monitor VPMICFAULT (Shared with VCC180 and VPNL18) GND2P1 Figure 38. VPMIC Detailed Internal Block Diagram Main Features • • • • • Uses V21 as the main power supply 100 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 35. VPMIC Register Structure and Bits Description Name Bits Description VPMICCNT (ADDR 0x41 - R/W - Default Value: 0x07) CTLVPMIC 2:0 VPMIC State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVPMIC 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VPMIC State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VYMXYFI18 VYMXYFI18 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VYMXYFI18 is actively discharged during shutdown. VYMXYFI18 can be supplied by either the V21 output voltage (V21) or directly from the VPWR node. Using V21 as the input voltage supply offers enhanced thermal performance and higher efficiency. Using the VPWR node can offer enhanced performance against noise coupling from an output of a DC/DC regulator. Users are encouraged to take the resulting thermal dissipation in account when supplying VYMXYFI18 directly from VPWR. For more information about package thermal capabilities, reference Thermal Management. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 73 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES V 21 or VPWR PVINYMXYFI18 CINYMXYFI 18 + VOYMXYFI 18 VOUTYMXYFI18 COYMXYFI 18 Z VOYMXYFI 18 IOYMXYFI 18 Discharge Two GND pins shared between VYMXYFI18, VYMXYFI , and VYMXGPS Controller _ VREF CTLVYMXYFI18 AOACCTLVYMXYFI 18 SPI Interface Output Monitor VYMXYFI18FAULT GNDCOMMS1 GNDCOMMS2 Figure 39. VYMXYFI18 Detailed Internal Block Diagram Main Features • • • • • Uses V21 or VPWR as the main power supply 200 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 36. VYMXYFI18 Register Structure and Bits Description Name Bits Description VWYMXARFCNT (ADDR 0x4C - R/W - Default Value: 0x24) CTLVWYMXARF 2:0 VYMXYFI18 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVWYMXARF 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VYMXYFI18 State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VCCPAOAC VCCPAOAC is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCPAOAC is actively discharged during shutdown. VCCPAOAC shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with VCCPDDR, VAON, VMM, and the VCCP regulator. Each has independent control. PVIN1P5 is supplied from the V15 voltage. 900844 74 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES V15 PVIN1P5 CIN1P 5 + VOCCPAOAC VOUTCCPAOAC COCCPAOAC Z VOCCPAOAC I OCCPAOAC Discharge Controller _ V REF CTLVCCPAOAC AOACCTLVCCPAOAC SPI Interface Output Monitor VCCPAOACFAULT GND1P5 Figure 40. VCCPAOAC Detailed Internal Block Diagram Main Features • • • • • Uses V15 as the main power supply. 155 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 37. VCCPAOACCNT Register Structure and Bits Description Name Bits Description VCCPAOACCNT (ADDR 0x3D - R/W - Default Value: 0x07) CTLVCCPAOAC 2:0 VCCPAOAC State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVCCPAOAC 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VCCPAOAC State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VCCPDDR VCCPDDR is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCPDDR is actively discharged during shutdown. VCCPDDR shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VAON, VMM, and VCCP regulators, yet each has independent control. PVIN1P5 is supplied from the V15 voltage. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 75 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES PVIN 1P5 (Shared with VCCPAOAC, VAON , VMM, and VCCP) Controller _ + VREF CTLVCCPDDR AOACCTLVCCPDDR SPI Interface VOCCPDDR COCCPDDR VOUTCCPDDR FBCCPDDR VOCCPDDR I OCCPDDR Discharge Z Output Monitor VCCPDDRFAULT (Shared with VCCPAOAC, VAON , VMM, and VCCP ) GND1P5 Figure 41. VCCPDDR Detailed Internal Block Diagram Main Features • • • • • Uses V15 as the main power supply 60 mA maximum continuous output current Optimized for a 1.0 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 38. VCCPDDR Control Register Structure and Bits Description Name Bits Description VCCPDDRCNT (ADDR 0x3E - R/W - Default value: 0x3C) CTLVCCPDDR 2:0 VCCPDDR State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVCCPDDR 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VCCPDDR State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VAON VAON is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VAON is actively discharged during shutdown. VAON shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VCCPDDR, VMM, and VCCP regulators, yet each has independent control. PVIN1P5 is supplied from the V15 voltage. 900844 76 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES PVIN 1P5 (Shared with VCCPAOAC, VCCPDDR, VMM, and VCCP) Controller _ + VREF CTLVAON AOACCTLVAON SPI Interface VOAON VOUTAON COAON Z V OAON I OAON Discharge Output Monitor VAONCFAULT (Shared with VCCPAOAC , VCCPDDR, VMM, and VCCP ) GND1P5 Figure 42. VAON Detailed Internal Block Diagram Main Features • • • • • Uses V15 as the main power supply 250 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 39. VAON Control Register Structure and Bits Description Name Bits Description VAONCNT (ADDR 0x45 - R/W - Default Value: 0x07) CTLVAON 2:0 VAON State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVAON 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VAON State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VMM VMM is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VMM will be actively discharged during shutdown. VMM shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VCCPDDR, VAON, and VCCP regulators, yet each has independent control. PVIN1P5 is supplied from V15 voltage. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 77 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES PVIN 1P5 (Shared with VCCPAOAC, VCCPDDR, VAON, and VCCP) Controller _ + VREF CTLVMM AOACCTLVMM SPI Interface VOMM VOUTMM COMM Z VOMM I OMM Discharge Output Monitor VMMCFAULT GND1P5 (Shared with VCCPAOAC , VCCPDDR, VAON , and VCCP ) Figure 43. VMM Detailed Internal Block Diagram Main Features • • • • • Uses V15 as the main power supply 5.0 mA maximum continuous output current Optimized for a 1.0 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 40. VMM control Register Structure and Bits Description Name Bits Description VMMCNT (ADDR 0x47 - R/W - Default Value: 0x24) CTLVMM 2:0 VMM State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVMM 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VMM State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VCCP VCCP is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VCCP is actively discharged during shutdown. VCCP shares an input voltage pin (PVIN1P5) and a reference ground pin (GND1P5) with the VCCPAOAC, VCCPDDR, VAON, and VMM regulators, yet each has independent control. PVIN1P5 is supplied from V15 voltage. 900844 78 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES PVIN1P5 (Shared with VCCPAOAC, VCCPDDR, VAON , and VMM ) Controller _ + VREF CTLVCCP AOACCTLVCCP SPI Interface VOCCP C OCCP VOUTCCP FBCCP VOCCP IOCCP Discharge Z Output Monitor VCCPFAULT (Shared with VCCPAOAC , VCCPDDR, VAON , and VMM ) GND1P5 Figure 44. VCCP Detailed Internal Block Diagram Main Features • • • • • Uses V15 as the main power supply 445 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 41. VCCP Control Register Structure and Bits Description Name Bits Description VCCPCNT (ADDR 0x44 - R/W - Default Value: 0x3C) CTLVCCP 2:0 VCCP State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVCCP 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VCCP State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VIMG25 VIMG25 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VIMG25 is actively discharged during shutdown. VIMG25 shares an input voltage pin (PVINIMG) and a reference ground pin (GNDIMG) with the VIMG28 regulator, yet each has independent control. Both can be supplied by the VPWR (3.3 V) node. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 79 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES V 33 or VPWR PVINIMG CINIMG + VOIMG 25 VOUTIMG25 COIMG 25 Z V OIMG25 I OIMG25 Discharge Controller _ VREF CTLVIMG25 AOACCTLVIMG 25 SPI Interface Output Monitor VIMG 25FAULT GNDIMG Figure 45. VIMG25 Detailed Internal Block Diagram Main Features • • • • • Uses VPWR (3.3V) as the main power supply 80 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 42. VIMG25 Register Structure and Bits Description Name Bits Description VIMG25CNT (ADDR 0x42 - R/W - Default Value: 0x04) CTLVIMG25 2:0 VIMG25 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVIMG25 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VIMG25 State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved VIMG28 VIMG28 is a low drop-out (LDO) fully integrated regulator with a P-CH Pass FET. It is high performance, low noise, and high PSRR, with a low quiescent current and fast transient response. VIMG28 is actively discharged during shutdown. VIMG28 shares an input voltage pin (PVINIMG) and a reference ground pin (GNDIMG) with the VIMG25 regulator, yet each has independent control. Both can be supplied by the VPWR (3.3 V) node. This LDO is optimized to work with 300 mV headroom, which leaves enough margin between the input and the highest output of this LDO. For more information about package thermal capabilities, reference Thermal Management. • Note: At high VIMG28 output voltage selections, the output will start tracking the battery voltage when VBAT decreases below VOIMG28 + 300 mV. 900844 80 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES PVINIMG (Shared with VIMG 25) Controller _ + VREF CTLVIMG 28 AOACCTLVIMG 28 SELVIMG28 VOIMG 28 VOUTIMG28 COIMG 28 Z V OIMG28 I OIMG28 Discharge SPI Interface Output Monitor VIMG28CFAULT (Shared with VIMG 25) GNDIMG Figure 46. VIMG28 Detailed Internal Block Diagram Main Features • • • • • Uses 3.3 V or VPWR as the main power supply 225 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses internal pass FET The output for each LDO is monitored for over-current conditions and under-voltage events Table 43. VIMG28 Control Register Structure and Bits Description Name Bits Description VIMGACNT (ADDR 0x0x48 - R/W - Default Value: 0x24) CTLVIMGA 2:0 VIMG28 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVIMGA 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VIMG28 State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active SELVIMGA 7:6 VIMG28 output voltage selections: X0 = 1.5 V x1 = 2.7 V x2 = 2.8 V x3 = 2.9 V VSDIO VSDIO is a combo low drop-out (LDO) and power switch. It uses an external P-CH pass FET in Switch mode, and internal pass FET on LDO mode. VSDIO serves as an LDO when its output voltage is set to 1.8 V, and as a switch when its output voltage is set to 3.3 V. It takes its input voltage directly from the 3.3 V output voltage node. VSDIO supplies the SDIO card module. The card is initially powered up to 3.3 V. If the card is detected to be a low voltage card, then the rail will be shutdown, configured as 1.8 V, and then turned on. VSDIO will be actively discharged during shutdown. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 81 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES V 33 SDIOGT CINSDIO VOSDIO COSDIO MSDIO LDO/Switch Controller _ + Z FBSDIO VOCCP Discharge VREF CTLVSDIO AOACCTLVSDIO SELVSDIO SPI Interface Output Monitor VSDIOFAULT Figure 47. VSDIO Detailed Internal Block Diagram MAIN FEATURES • • • • • Uses 3.3 V as the main power supply 215 mA maximum continuous output current Optimized for a 2.2 µF external filter capacitor with a maximum of 10 mΩ ESR Uses an internal pass FET on LDO mode, and external pass FET on Switch mode. The output is monitored for under-voltage and over-current conditions in LDO mode. Table 44. VSDIO Control Register Structure and Bits Description Name Bits Description VSDIOCNT (ADDR 0x4D - R/W - Default Value: 0x64) CTLVSDIO 2:0 VSDIO State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVSDIO 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VSDIO State Control during AOAC Exit (when Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active SELVSDIO 7:6 VSDIO output voltage selections: X0 = 1.8 V x1 = 3.3 V x2 = Reserved x3 = Reserved POWER SWITCHES Freescale’s power management solution for the Ultra-mobile platform for Netbooks, Tablets and Slates, includes 1 dedicated power switch, housed in the 900844 PMIC. Table 45 shows its power characteristics. VPNL33 uses an internal switch and are supplied from the 3.3 V output voltage. Table 45. 900844 Power Switch Voltage Rail Switch VPNL33 Typ. Voltage 3.3 V Max Current 100 mA Description Power Switch with integrated MOSFET and less than 1% voltage drop. VPNL33 uses an internal switch and are supplied from the 3.3 V output voltage. 900844 82 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES Table 46. Power Switches Control Registers Structure and Bits Description Name Bits Description VPANEL33CNT (ADDR 0x4F - R/W - Default Value: 0x24) CTLVPANEL33 2:0 VPNL33 State Control x0 = Reserved x1 = Reserved x2 = Reserved x3 = Reserved AOACCTLVPANEL33 5:3 x4 = OFF x5 = Low Power x6 = Active x7 = Active VPNL33 State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the system SPI controller after power up. X0 = Do not copy x1 = Do not copy x2 = Do not copy x3 = Do not copy x4 = OFF x5 = Low Power x6 = Active x7 = Active Reserved 7:6 Reserved POWER SUPPLY REGISTER MASK Mask writes to the power supply registers, in order to avoid the need for the system controller to do read-modify-write cycles. The mask register is shown in Table 47. Table 47. Mask Register Register name PWRMASK ADDR 0x34 R/W R/W D7 M7 D6 M6 D5 M5 D4 M4 D3 M3 D2 M2 D1 M1 D0 M0 initial 0x00 Figure 48 shows an example of the operation of the PWRMASK register. D7 1 1 1 1 D6 0 1 1 0 D5 1 1 1 1 D4 0 1 1 0 D3 1 0 1 1 D2 0 0 1 1 D1 1 0 1 1 D0 0 0 1 1 Power Supply Register Before Write PWRMASK Register Settings Example SPI Write to Power Supply Power Supply Register After Write Figure 48. PWRMASK Register Implementation Example POWER SUPPLY PROGRAMMABLE RAMP RATE Turn on time of all buck regulators can be programmed through the SPI, reference Table 48 Table 48. Ramp Rate Control Registers (Freescale Defined) Name Bits Description FSLTONTCNTL1 (ADDR 0x1C8 - R/W - Default Value: 0xAA) VCCTONT 1:0 Turn On Time Settings for VCC Regulator x0 = 180 μs x1 = 90 μs x2 = 45 μs x3 = 22 μs Turn On Time Settings for VNN Regulator x0 = 180 μs x1 = 90 μs x2 = 45 μs x3 = 22 μs VNNTONT 3:2 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 83 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES Table 48. Ramp Rate Control Registers (Freescale Defined) Name VDDQTONT Bits 5:4 Description Turn On Time Settings for VDDQ Regulator x0 = 240 μs x1 = 120 μs x2 = 60 μs x3 = 30 μs RSVD RSVD 7:6 FSLTONTCNTL2 (ADDR 0x1CB - R/W - Default Value: 0xAA) V21TONT 1:0 Turn On Time Settings for V21 Regulator x0 = 320 μs x1 = 160 μs x2 = 80 μs x3 = 40 μs Turn On Time Settings for V15 Regulator x0 = 200 μs x1 = 100 μs x2 = 50 μs x3 = 25 μs Reserved V15TONT 3:2 Reserved 7:4 POWER SUPPLIES FAULT MANAGEMENT This section discusses faults related to, or caused by power supplies (directly or indirectly) operating outside their specified boundaries. Reference Interrupt Controller for more information on the various interrupt signals, and the interrupt mechanism used to communicate to the system controller. THERMAL MANAGEMENT The thermal protection is based on a circuit with a voltage output that is proportional to the absolute temperature. This voltage can be read out via the ADC for precise temperature readouts. See ADC Subsystem. This voltage is monitored by an integrated comparator. Interrupt THRM will be generated, if not masked, when crossing the thermal warning threshold TWARN, and sets the VRFAULT 1st level interrupt that causes the PMICINT pin to assert, notifying the system controller of a system event. In addition to the previous, the 900844 includes integrated thermal protection that shuts down and powers off the system, in cases of over dissipation, if the junction temperature exceeds the TSHUTDOWN threshold. This thermal protection will act above the maximum junction temperature, to avoid any unwanted power downs. The protection is de-bounced by one period of the 32 kHz clock in order to suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism. Therefore, the application design should execute a thermal shutdown under normal conditions. Once the thermal event is cleared and the temperature is back to its normal range, the 900844 restarts automatically, by following the steps outlined in Initial Power Up Sequence Table 49. Thermal Warning/Shutdown Thresholds Parameter Thermal Warning Threshold Thermal Warning Hysteresis Thermal Shutdown Threshold Min 115 2 130 Typ 120 140 Max 125 4 150 Unit °C °C °C 900844 84 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION POWER SUPPLIES VRFAULT Every supply is equipped with a fault reporting signal called xxxFAULT, where xxx is the name of the power supply. This FAULT signal is an OR function of all of the following possible faults, or just a subset of them depending on the power supply: • Output under-voltage • Output over-voltage • Over-current • Short-circuit Reference each power supply’s section for more information on what faults are included, and how the supply protects itself and the load in response to the fault. All of the xxxFAULT signals from all power supplies are ORed together into the BATOCP interrupt signal, which if unmasked, sets the VRFAULT 1st level interrupt that causes the PMICINT pin to assert, notifying the SC of a system event. The SC can service the VRFAULT register and access the FAULTx registers for more information on which supply caused the fault. The SC can then take different measures, depending on the supply in question. The xxxFAULT signals are stored in the Freescale defined registers section (Addr 0x180 - 0x1FF), which is meant for extended functionality. Table 50. FSLFAULT1 Fault Status Register Structure and Bit Description Name Bits Description Table 51. FSLFAULT2 Fault Status Register Structure and Bit Description Name Bits Description FSLFAULT1 (ADDR 0X1CC - R/W - DEFAULT VALUE: 0X00) VCCFAULT 0 VCC Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VNN Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VDDQ Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists V21 Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists V15 Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists Reserved FSLFAULT2 (ADDR 0X1CD - R/W - DEFAULT VALUE: 0X00) RSVD VBGFAULT 2:0 3 Reserved VBG Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VCCA Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VCC180 Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VPNL18 Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VPMIC Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VNNFAULT 1 VCCAFAULT 4 VDDQFAULT 2 VCC180FAULT 5 V21FAULT 3 VPNL18FAULT 6 V15FAULT 4 VPMICFAULT 7 RSVD 7:5 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 85 FUNCTIONAL DEVICE OPERATION POWER SUPPLIES Table 52. FSLFAULT3 Fault Status Register Structure and Bit Description Name Bits Description Power Supplies Fault Management Interrupt/Mask Registers. Table 54. Fault Management Status and Control Register Structure and Bits Description Name Bits Description FSLFAULT3 (ADDR 0X1CE - R/W - DEFAULT VALUE: 0X00) VYMXYFI18FA ULT RSVD VCCPAOACFA ULT VCCPDDRFAU LT VAONFAULT 0 VYMXYFI18 Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists Reserved VCCPAOAC Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VCCPDDR Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VAON Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VMM Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VCCP Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VRFAULTINT (ADDR 0X30 - R - DEFAULT VALUE: 0X00) THRM 0 PMIC Thermal Warning Flag x0 = PMIC temperature below warning threshold x1 = PMIC temperature above warning threshold Reserved 2:1 3 RSVD 1 4 VRFAIL 2 5 Regulator fault present flag x0 = No fault x1 = Fault Exists Reserved Reserved 7:3 VMMFAULT 6 MVRFAULTINT (ADDR 0X31 - R/W - DEFAULT VALUE: 0X03) MTHRM 0 PMIC Thermal Warning Flag Mask x0 = Flag unmasked x1 = Flag masked Reserved VCCPFAULT 7 RSVD 1 VRFAIL 2 Table 53. FSLFAULT4 Fault Status Register Structure and Bit Description Name Bits Description Reserved 7:3 Regulator fault present flag Mask x0 = Flag unmasked x1 = Flag masked Reserved FSLFAULT4 (ADDR 0X1CF - R/W - DEFAULT VALUE: 0X00) VIMG25FAULT 0 VIMG25 Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists VIMG28 Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists Reserved VSDIO Regulator Fault Signal x0 = No Fault Exists x1 = Fault Exists Reserved VIMG28FAULT 1 RSVD VSDIOFAULT 2 3 Reserved 7:4 900844 86 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION COIN CELL BATTERY CHARGER INTERFACE COIN CELL BATTERY CHARGER INTERFACE COIN CELL BATTERY BACKUP/CHARGER The COIN CELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged or removed, and in the absence of a USB/Wall input source, the RTC system and coin cell maintained logic, will switch over to the COIN CELL for backup power. A small capacitor should be placed from the COIN CELL pin to ground under all circumstances. The coin cell charger circuit will function as a current limited voltage source, resulting in the CC/CV taper characteristic, typically used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHGEN bit. which is enabled by default. The output voltage (VCOIN) is programmable through the VCOIN[2:0] bits. The coin cell charger voltage is programmable in the active state, where the charge current is fixed at ICOINHI. The coin cell charging will be stopped when VPWR goes below VPWRUVF. Reference Power Path Manager SPI Registers for a more detailed description of the coin cell related bits. A large capacitor, electrolytic or super cap, can also be used instead of a lithium based coin cell. To avoid discharge by leakage currents from external components or by the 900844, the COINCHGEN bit should always remain set. Coin cell charge is equipped with a disconnect circuitry that isolates the coin cell from any loads, if VCOIN goes below 2.0 V, to prevent the coin cell from being deeply discharged and damaged. This will also cause the ADC reading of the coin cell voltage to yield zero. POWER PATH MANAGER SPI REGISTERS Table 55. Input Power Interrupt/Mask Registers Structure and Bits Description Name Bits Description CHRGINT (ADDR 0XD0 - R - DEFAULT VALUE: 0X00) Reserved BATOVP 0 1 Reserved Input voltage over-voltage Interrupt Signal (VBAT > VCHGCV + VOVRVOLT) x0 = No over-voltage condition x1 = Over-voltage condition Battery over/under-temperature Interrupt Signal (Battery temperature is out of valid window) x0 = No over/under-temperature condition x1 = Over/under-temperature condition Reserved Reserved Input voltage detection Interrupt Signal This is a dual edge interrupt signal that is set any time a valid Input Voltage (VBAT > VTRKL) is connected or disconnected x0 = No interrupts pending x1 = 3.3 V supply is connected/disconnected (refer to the SCHRGINT register) Reserved TEMP 2 RSVD RSVD BATDET 3 4 5 RSVD 7:6 MCHRGINT (ADDR 0XD1 - R/W - DEFAULT VALUE: 0X00) Reserved MBATOVP 0 1 Reserved Input voltage over-voltage Interrupt Signal Mask x0 = Unmask x1 = Mask Input voltage over/under-temperature Interrupt Signal Mask x0 = Unmask x1 = Mask Reserved Reserved MTEMP 2 RSVD RSVD 3 4 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 87 FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 55. Input Power Interrupt/Mask Registers Structure and Bits Description Name MBATDET Bits 5 Description Battery Detection Interrupt Signal Mask x0 = Unmask x1 = Mask Reserved RSVD 7:6 SCHRGINT (ADDR 0XD2 - R - DEFAULT VALUE: 0X00) Reserved SBATOVP 0 1 Reserved Input voltage over-voltage Status x0 = Input voltage is lower than the limit (< VCHGCV + VOVRVOLT) x1 = Input voltage is higher than the limit (> VCHGCV + VOVRVOLT) Battery temperature Status x0 = Battery temperature is within valid window x1 = Battery temperature is out of valid window Reserved Reserved Battery Present Status Signal x0 = Battery not present (VBAT < VTRKL) x1 = Battery present (VBAT > VTRKL) Reserved STEMP 2 RSVD RSVD SBATDET 3 4 5 RSVD 7:6 INPUT POWER PATH REGISTERS AND BITS DESCRIPTION Table 56. FSL Charger Control Register Structure and Bits Description Name Bits Description FSLCHRGCNTL (ADDR 0X1D1 - R/W - DEFAULT VALUE: 0X13) RSVD COINCHEN 0 1 Reserved Coin cell Charger Enable/Disable x0 = Disable x1 = Enable (Default) Coin cell Charger Output Voltage Setting x0 = 2.5 V x1 = 2.7 V x2 = 2.8 V x3 = 2.9 V x4 = 3.0 V (Default) x5 = 3.1 V x6 = 3.2 V x7 = 3.3 V Reserved VCOIN 4:2 Reserved 7:5 ADC SUBSYSTEM CONVERTER CORE The ADC core is a 10 bit converter. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz. If an ADC conversion is requested while the PLL was not active, it will automatically be enabled by the ADC. A 32.768 kHz equivalent time base is derived from the 2.0 MHz clock to time ADC events. The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain errors. 900844 88 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM The ADC will be used for sensing the current through select voltage regulators, touch screen support, PMIC thermal sensor, battery voltage, current, and temperature. Figure 49 is a representation of the ADC block. Figure 49. ADC Block Representation INPUT SELECTOR The ADC has 22 input channels selected through the ADSEL[4:0] bits in the ADCADDRx register. Table 57 gives an overview of the characteristics of each of these channels. Table 57. ADC Inputs Channel 0 1 2 3 4 5 6 7 SELECT[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 ADC Input Signal PMIC Die Temperature VCC Current Sense VNN Current Sense VCC180 Current Sense Reserved Reserved Input voltage (VBAT) Reserved Input Level 1.2 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V Reserved Reserved 0 – 4.8 V Reserved Scaling x1 x1 x1 x1 Reserved Reserved /2 Reserved Scaled Version 1.2 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V Reserved Reserved 0 – 2.4 V Reserved 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 89 FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 57. ADC Inputs Channel 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SELECT[4:0] 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 ADC Input Signal Reserved Battery Pack Thermistor General Purpose ADIN10 Touch screen X+ General Purpose ADIN11 Touch screen XGeneral Purpose ADIN12 Touch screen Y+ General Purpose ADIN13 Touch screen YGeneral Purpose ADIN14 General Purpose ADIN15 General Purpose ADIN16 General Purpose ADIN17 General Purpose ADIN18 General Purpose ADIN19 General Purpose ADIN20 General Purpose ADIN21 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input Level Reserved 0 – 2.4 V 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Scaling Reserved x1 10x / 1x x2 10x / 1x x2 10x / 1x x2 10x / 1x x2 10x / 1x 10x / 1x 10x / 1x 10x / 1x 10x / 1x 10x / 1x 10x / 1x 10x / 1x Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Scaled Version Reserved 0– 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V 0 – 2.4 V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Notes 18. Equivalent to -3.0 to +3.0 A of current with a 20 mOhm sense resistor Some of the internal signals are first scaled to adapt the range to the input range of the ADC. Note that the 10 bit ADC core will convert over the entire scaled version of the input channel, so always from a 2.40 V, full scale. For some applications, an external resistor divider network may be used to scale down the voltage to be measured to the ADC input range. The source resistance presented by this may be greater than the maximum specified Rs, see ADC Section on Table 3. In that case, the readout value will be lower than expected due to the dynamic input impedance of the ADC converter. This readout error presents itself as a gain error which can be compensated for by factory phasing. An alternative is to place a 100 nF bypass capacitor at the ADIN input concerned. RESERVED CHANNELS POSSIBLE USAGE Only 22 of the possible 32 ADC channels are currently associated with an specific function. The remaining channels are currently designated as reserved channels for future needs. Table 58 is a proposed usage for some of these channels for additional flexibility. 900844 90 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 58. Possible Reserved Channels Usage Channel 22 23 24 25 26 27 28 29 30 31 ADC Input Signal Application Supply (VPWR) Reserved Reserved Backup Voltage (VCOINCELL) Reserved Reserved Reserved Reserved Reserved Reserved Input Level 0 – 4.8 V Reserved Reserved 0 – 3.6 V Reserved Reserved Reserved Reserved Reserved Reserved Scaling /2 Reserved Reserved x2/3 Reserved Reserved Reserved Reserved Reserved Reserved Scaled Version 0 – 2.4 V Reserved Reserved 0 – 2.4 V Reserved Reserved Reserved Reserved Reserved Reserved Activating the prior channels to provide the signal specified occurs by asserting the following bits to 1. If the following bits are 0, then these channels are reserved: • VPWRCON for channel 22 • LICON for channel 25 CONTROL The ADC block consists of a 5-bit wide, 32-entry register file, which stores the address of the analog input for sampling. The 10-bit result is then stored in a separate register file 10+1 bits wide and 32 entries deep. In order to operate the ADC, it has to be enabled first by setting the ADEN bit high in the ADCCNTL1 register. When the register ADCCNTL1 ADSTRT bit is enabled, the PMIC will cycle through the 3 + 5 bit selector addresses in registers ADCADDRx. The high 3-bits control the touch screen bias FETs, as described in Touch Screen Interface. The lower 5-bits address the ADC selector to connect one of 32 channels to the ADC. The result of the ADC conversion is stored into the result registers (ADCSNSx), along with the input gain setting (1 MSB). An address in the selector table of 0x1F designates the stop location of the selection loop. At which point the interrupt flag bit 0 (RND), which can be masked through the MRND bit in the MADCINT register, is set in register ADCINT, bit 1 of the INTERRUPT register (ADC) is set, and the external PMICINT signal is asserted, if bit 1 of the INTMASK register is clear. The ADC sleeps for 0 to 27 ms as set by ADC register ADCCNTL1 through the ADSLP[2:0] bits and then repeats the selector cycle. The new data overwrites the old in the result registers. At most, all 32 result registers will be filled within 15.625 ms (2048/32 = 1/64 Hz). The result registers will not be read until the RND flag is set. DEDICATED CHANNELS READING Two different LSB value settings are possible by using the LSBSEL bit in the FSLADCCNTL register. LSBSEL = 0 is the default setting. See Table 59 for more information Table 59. ADC LSB Settings # 0 1 2 3 4 5 6 SELECT[4:0] 00000 00001 00010 00011 00100 00101 00110 ADC INPUT SIGNAL PMIC Die Temperature VCC Current Sense VNN Current Sense VCC180 Current Sense Reserved Reserved Battery Voltage (VBAT) SIGNAL RANGE 1.2 – 2.4 V 4.2 A 1.9 A 0.5 A Reserved Reserved 4.8 V LSB VALUE (LSBSEL = 0) 0.4244 K 4.1015 mA 1.8554 mA 0.4883 mA Reserved Reserved 4.6875 mV LSB VALUE (LSBSEL = 1) 1C 10 mA 10 mA 10 mA Reserved Reserved 10 mV 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 91 FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 59. ADC LSB Settings # 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SELECT[4:0] 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 ADC INPUT SIGNAL Reserved Reserved Battery Pack Thermistor General Purpose ADIN10 Touch screen X+ General Purpose ADIN11 Touch screen XGeneral Purpose ADIN12 Touch screen Y+ General Purpose ADIN13 Touch screen YGeneral Purpose ADIN14 General Purpose ADIN15 General Purpose ADIN16 General Purpose ADIN17 General Purpose ADIN18 General Purpose ADIN19 General Purpose ADIN20 General Purpose ADIN21 Application Supply (VPWR) Reserved Reserved Backup Voltage (VCOINCELL) Reserved Reserved Reserved Reserved Reserved Reserved SIGNAL RANGE Reserved Reserved 2.4 V 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0 – 1.2 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0-200 mV / 0-2.0 V 0 – 4.8 V Reserved Reserved 0 – 3.6 V Reserved Reserved Reserved Reserved Reserved Reserved LSB VALUE (LSBSEL = 0) Reserved Reserved 2.3438 mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 4.6875 mV Reserved Reserved 3.5156 mV Reserved Reserved Reserved Reserved Reserved Reserved LSB VALUE (LSBSEL = 1) Reserved Reserved 10mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 1.17 mV 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 195.3 μV - 1.953 mv 4.6875 mV Reserved Reserved 3.5156 mV Reserved Reserved Reserved Reserved Reserved Reserved PMIC DIE TEMPERATURE The die temperature can be read out on Channel 0 of the ADC. The relation between the read out code and temperature is given in Table 60. 900844 92 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 60. PMIC Die Temperature Voltage Reading Parameter Die Temperature Read Out Code at 25 °C Temperature change per LSB Customer Defined LSB Value Multiplier Value for Output Register Typical 1011000001 +0.4244 °C 1.0000 °C x2.36 CURRENT SENSING The load current sourced by a select set of regulators can be measured and recorded by the ADC on channels 1 through 5. Table 61 shows a summary of these regulators, type, and their current ranges. Table 61. Regulators Current Sensing Regulator VCC VNN VCC180 Type Buck Buck LDO Current Range 0 – 3.5 A 0 – 1.6 A 0 – 0.39 A INPUT VOLTAGE The input voltage is read at the VBAT pin at channel 6. The input voltage is first scaled by subtracting 2.40 V in order to fit the input range of the ADC. Table 62. Battery Voltage Reading Coding Conversion Code 1 111 111 111 1 000 010 100 0 000 000 000 Voltage at ADC input 2.400 V 1.250 V 0.000 V Voltage at VBAT 4.800 V 2.500 V 0.000 V GENERAL PURPOSE ANALOG INPUTS There are twelve general purpose analog input channels that can be measured through the ADIN10-ADIN21 pins. Two voltage scaling (gain) settings can be selected to accommodate a wider range of inputs through the ADCCNTL3 and ADCCNTL4 registers. A gain of 0 sets a corresponding scaling factor of 1 (for an input range of 2.0 V) and a gain of 1 sets a corresponding scaling factor of 10 (for an input range of 200 mV). Table 63. General Purpose Analog Inputs Reading Coding Conversion Code 1 111 111 111 1 011 111 111 0 011 111 111 0 000 000 000 1 111 111 111 1 011 111 111 0 011 111 111 0 000 000 000 Voltage at ADC input 2.400 1.800 0.600 0.000 2.400 1.800 0.600 0.000 Voltage at ADINx Input 0.200 0.150 0.050 0.000 2.000 1.500 0.500 0.000 0 GAIN 1 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 93 FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM APPLICATION SUPPLY (IF USED) Channel 22 can be used to read the application supply voltage at the VPWR pin. This can be enabled by setting the VPWRCON bit in the FSLADCCNTL register high. The battery voltage is first scaled as VPWR/2 in order to fit the input range of the ADC. Table 64. Application Supply Voltage Reading Coding Conversion Code 1 111 111 111 1 000 010 100 0 000 000 000 Voltage at ADC input 2.400 V 1.250 V 0.000 V Voltage at VPWR 4.800 V 2.500 V 0.000 V BACKUP VOLTAGE (IF USED) Channel 25 can be used to read the voltage of the coin cell connected to the COINCELL. This is enabled by setting the LICON bit in the FSLADCCNTL register to 1. Since the voltage range of the coin cell exceeds the input voltage range of the ADC, the COINCELL voltage is first scaled as VCOIN*2/3. Table 65. Backup (Coin Cell) Voltage Reading Coding Conversion Code Voltage at ADC input Voltage at COINCELL 1 111 111 111 1 000 000 000 0 000 000 000 2.400 V 1.200 V 0.000 V 3.600 V 1.800 V 0.000 V TOUCH SCREEN INTERFACE The PMIC touch screen support consists of four analog input channels with built in bias control. The BIAS FET control bits are part of the ADC round robin address register ADCADDRx. The touch screen X plate is connected to ADIN10 (X+) and ADIN11 (X-), while the Y plate is connected to ADIN12(Y+) and ADIN13(Y-). A local supply, TSREF, of 1.2 V will serve as a reference. The system processor will handle the touch screen sequencing and any necessary conversion delays. The system processor will direct the desired bias control for every reading though the ADCADDRx registers. If FET biasing is enabled though the ADCADDRx registers, then touch screen readings will start according based on the channels chosen, and also by the ADCADDRx registers. If the touch screen is not used, then the above inputs can be used as general purpose inputs. In this case, the bias control will always be programmed to no bias. Figure 50 is a touch screen representation. Figure 50. Touch Screen Configuration Example 900844 94 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Touch Screen Pen detection bias can be enabled via the PENDETEN bit in the ADCCNTL1 register. When this bit is enabled and a pen touch is detected, the PENDET bit in register ADCINT is set and the PMICINT pin is asserted. This is to interrupt the system, because a touch screen pen touch has been detected at the next ADC cycle, unless the interrupt is masked. The prior reference for the touch screen (Touch Bias) is TSREF and is powered from VCORE. In touch screen operation, TSREF is a dedicated regulator. No loads other than the touch screen should be connected here. When the ADC performs non touch screen conversions, the ADC does not rely on TSREF and the reference can be disabled. The readouts are designed such that the on chip switch resistances are of no influence to the overall readout. The readout scheme does not account for contact resistances, as present in the touch screen connectors. Therefore, the touch screen readings have to be calibrated by the user or in the factory, where one has to point with a stylus to the opposite corners of the screen. When reading out the X-coordinate, the 10-bit ADC reading represents a 10-bit coordinate with '0' for a coordinate equal to X- and full scale '1023' when equal to X+. When reading out the Y-coordinate, the 10-bit ADC reading represents a 10-bit coordinate with '0' for a coordinate equal to Y- and full scale '1023' when equal to Y+. When reading the contact resistance the 10-bit ADC reading represents the voltage drop over the contact resistance created by the known current source multiplied by 2. Table 66. Touch Screen System Requirements Description Plate Resistance X, Y Resistance Between Plates, Contact Capacitance Between Plates Contact Resistance Current Source Interrupt Current Source Interrupt Threshold Current Source Inaccuracy Quiescent Current (Active Mode) Max Load Current (Active Mode) Settling Time (Position Measurement) Symbol Min 100 180 0.5 40 3.0 Typ 2.0 100 20 20 Max 1000 1200 60 20 20 5.5 Unit Ω Ω nF μA μA kΩ % μA mA μs ADC STATUS/CONTROL REGISTERS AND BIT DESCRIPTION Reference the Table 67 for read/write conditions and default state for each of these registers Table 67. ADC Interrupt/Mask Registers Structure and Bits Description Name Bits Description ADCINT (ADDR 0x5F - R - Default Value: 0x00) RND 0 ADC Round Robin Cycle Completion Interrupt x0 = Not Completed x1 = Completed Touch Screen Pen Detection Interrupt x0 = Pen Not Detected x1 = Pen Detected Reserved PENDET 1 Reserved 7:2 MADCINT (ADDR 0x60 - R/W -Default Value: 0x00) MRND 0 ADC Round Robin Cycle Completion Interrupt Mask x0 = Unmask x1 = Mask Touch Screen Pen Detection Interrupt Mask x0 = Unmask x1 = Mask Reserved MPENDET 1 Reserved 7:2 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 95 FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 68. ADC Control Registers Structure and Bits Description Name Bits Description ADCCNTL2 (ADDR 0x61 - R/W -Default Value: 0x00) ADSLP 2:0 ADC sleep time before starting another cycle x0 = Continuous Loop x1 = 4.5 ms x2 = 9.0 ms x3 = 13.5 ms RSVD PENDETEN 4:3 5 Reserved Enable Touch Screen Pen Detect Bias x0 = Disabled x1 = Enabled ADC Round Robin Start Signal x0 = Stop round robin after the current cycle x1 = Start round robin Bring the ADC out of low power state, this overrides wake from sleep x0 = Disable in low power x1 = Enable at full power ADCCNTL3 (ADDR 0x62 - R/W -Default Value: 0x00) ADEXGAIN10 0 Gain bit for ADC channel 10, ignore when touch screen is biased x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 11, ignore when touch screen is biased x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 12, ignore when touch screen is biased x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 13, ignore when touch screen is biased x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 14 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 15 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 16 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 17 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) ADCCNTL4 (ADDR 0X63 - R/W -DEFAULT VALUE: 0X00) ADEXGAIN18 0 Gain bit for ADC channel 18 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 19 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) x4 = 18 ms x5 = 22.5 ms x6 = 27 ms x7 = No Loop ADSTRT 6 ADEN 7 ADEXGAIN11 1 ADEXGAIN12 2 ADEXGAIN13 3 ADEXGAIN14 4 ADEXGAIN15 5 ADEXGAIN16 6 ADEXGAIN17 7 ADEXGAIN19 1 900844 96 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 68. ADC Control Registers Structure and Bits Description Name ADEXGAIN20 Bits 2 Gain bit for ADC channel 20 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Gain bit for ADC channel 21 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) Reserved Description ADEXGAIN21 3 Reserved 7:4 Table 69. ADC Channel Selector/Configuration Structure and bit Description Name Bits Description ADCSNSxH (x = 0 to 31) ADCHxH GAINx 6:0 7 7 MSBs of ADC result for Channel x Gain bit for ADC channel x, x = 0 to 31 x0 = x1 (0-2.0 V input range) x1 = x10 (0-200 mV input range) ADCSNSxL (x = 0 to 31) ADCHxL Reserved 2:0 7:3 3 LSBs of ADC result for Channel x Reserved ADCADDRX (X = 0 TO 31) ADSELx 4:0 ADC Channel to be read Selection bits x00 = Channel 0 x01 = Channel 1 ... x1F = Channel 31 Turns on X+ and X- bias FETs, Refer to Figure 50 x0 = FETS Off x1 = FETS On Turns on Y+ and Y- bias FETs, Refer to Figure 50 x0 = FETS Off x1 = FETS On Turns on X- and Y+ bias FETs, Refer to Figure 50 x0 = FETS Off x1 = FETS On XPXMx 5 YPYMx 6 XMYPx 7 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 97 FUNCTIONAL DEVICE OPERATION GPIOS ADC STATUS/CONTROL REGISTERS AND BIT DESCRIPTION Table 70. Extended ADC Control Register Structure and Bits Description Name Bits Description FSLADCCNTL (ADDR 0x1DE - R/W - Default Value: 0x00) VPWRCON 0 Enable channel 22 to read the VPWR voltage x0 = Disable (Default) x1 = Enable Enable channel 24 to read the Battery charging current x0 = Disable (Default) x1 = Enable Enable channel 25 to read the Backup Battery voltage x0 = Disable (Default) x1 = Enable Reserved ADC LSB Selection Bit x0 = Refer to Table 59 x1 = Refer to Table 59 Reserved CHRGICON 1 LICON 2 RSVD LSBSEL 3 4 RSVD 7:4 GPIOS DESCRIPTION The 900844 has eight GPIOs, and eight GPOs for platform control. As outputs, the GPIOs support CMOS/OD signaling levels, based on the voltage level on the GPIOVCC. The GPOs support CMOS signaling levels, based on the voltage level on the GPOVCC pin. As inputs, they are 3.6 V tolerant and are de-bounced for a period of no more than 10 ms minimum. The 900844 provides one bank of eight configurable GPIO inputs/outputs, GPIO[7:0] for general purpose sensing and platform control. Only GPIOs support an input function. GPIOs switch between a high-impedance (>1.0 MΩ) state and a low-impedance (20 Ω nominal) state when operating in open drain mode. When operating in CMOS mode, the outputs drive from the voltage supplied on the GPIOVCC pin with a 20 Ω output drive capability (for GPIOs). The electrical characteristics of the output buffer will therefore be specified as relative percentages of the driving supply. Any unused GPIO pin should be tied to ground on the board. When any GPIO is configured as an open drain, the pull-up voltage cannot exceed that of the GPIOVCC Voltage level. Table 71 shows the default state of the different GPIOs and their capabilities. Table 71. GPIOs Capabilities and Default States GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPO0 GPO1 900844 Input Output CMOS OD Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Slew CNTL No No No No No No No No No No Default Mode Input Input Input Input Input Input Input Input CMOS CMOS Default Level HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z Low Low 98 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION GPIOS Table 71. GPIOs Capabilities and Default States GPIO GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 Input Output CMOS OD No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No Slew CNTL No No No No No No Default Mode CMOS CMOS CMOS CMOS CMOS CMOS Default Level Low Low Low Low Low Low GPIO MODULE STRUCTURE Figure 51 illustrates the logical structure of the GPIOx modules. Figure 51. GPIO Module Structure 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 99 FUNCTIONAL DEVICE OPERATION GPIOS GPIO STATUS/CONTROL REGISTERS AND BIT DESCRIPTION GPIO module has a single 8-bit status and control register assigned to it. See Table 72 for details. The “x” in the bit names in the tables is from 0 to 7 for the GPIOs. Table 72. GPIO Register Structure and Bits Description Name Bits Description GPIOCNTLx (x = 0 to 7) DRVx 0 GPIOx Output Driver Type x0 = Open Drain x1 = CMOS GPIOx Direction Configuration x0 = Output (Type selected by Bit 0) x1 = Input (Bit 0 is ignored) The value in the DATA_IN bit reflects the electrical state of the GPIOx pin at the time the register read was initiated. When Bit 1, DIRECTION, is 0 (Output Mode), the contents of this register are not required to be updated on reads and is assumed to be invalid by the system controller. The PMIC should de-bounce the inputs over 1-10 ms to insure a clean transition. X0 = Electrical Low (19) x1 = Electrical High (19) The value in the DATA_OUT bit reflects the desired electrical output state of the GPIOx pin. When Bit 1, DIRECTION, is 1 (Input Mode), the contents of this register may still be read or written, but will not be reflected until the GPIOx is reverted to an output (Bit 1, DIRECTION, is 0) x0 = Electrical Low (19) x1 = Electrical High (CMOS) or High-impedance Output (Open-Drain) (19) These bits set the interrupt definition. The MASK (00) determines if the corresponding interrupt flag bit is set or not on an interrupt. The other logic levels will set the corresponding interrupt flag bit in the register upon the specific edge detection defined by the level. They will also set bit 4 of the 1st level INTERRUPT register, see section Interrupt Controller for more details. (20) x0 = Mask. x1 = Negative Edge x2 = Positive Edge x3 = Both Edges These bits set the debounce time on the GPIOx when configured as inputs x0 = No Debounce x1 = 10 ms x2 = 20 ms x3 = 30 ms GPIOINT (ADDR 0xE8 - R - Default Value: 0x00) GPIINT0 0 GPIO0 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred GPIO1 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred GPIO2 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred GPIO3 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred DIRx 1 DATAINx 2 DATAOUTx 3 INTCTLx 5:4 GPIDBNCx 7:6 GPIINT1 1 GPIINT2 2 GPIINT3 3 Notes 19. See GPIOs electrical characteristics on Table 3 20. An unintended interrupt is caused if interrupt settings are reconfigured in the middle of an application, e.g. re-setting interrupt detection from detecting an interrupt on both edges to an interrupt on the rising edge. In this case, to mask any unwanted interrupt, change the GPIO interrupt detection to the new configuration, then clear Level 1 and level 2 interrupts, finally unmask the GPIO Interrupt. 900844 100 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 72. GPIO Register Structure and Bits Description Name GPIINT4 Bits 4 GPIO4 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred GPIO5 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred GPIO6 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred GPIO7 Interrupt Flag x0 = No Interrupt occurred or Masked Interrupt x1 = Interrupt occurred Description GPIINT5 5 GPIINT6 6 GPIINT7 7 Table 73. GPO Register Structure and Bits Description Name GPO0 Bits 0 GPO0 Output Level x0 = Low0 x1 = High (To voltage supplied on GPOVCC Pin) GPO1 Output Level x0 = Low x1 = High (To voltage supplied on GPOVCC Pin) GPO2 Output Level x0 = Low x1 = High (To voltage supplied on GPOVCC Pin) GPO3 Output Level x0 = Low x1 = High (To voltage supplied on GPOVCC Pin) GPO4 Output Level x0 = Low x1 = High (To voltage supplied on GPOVCC Pin) GPO5 Output Level x0 = Low x1 = High (To voltage supplied on GPOVCC Pin) GPO6 Output Level x0 = Low x1 = High (To voltage supplied on GPOVCC Pin) GPO7 Output Level x0 = Low x1 = High (To voltage supplied on GPOVCC Pin) Description GPO (ADDR 0xF4 - R/W - Default Value: 0x00) GPO1 1 GPO2 2 GPO3 3 GPO4 4 GPO5 5 GPO6 6 GPO7 7 SPI REGISTER MAP OVERVIEW The SPI frame is organized as 24 bits. The first 16 bits is the write enable bit, 10-bit address and 5 "dead" bits between the data and address fields. The next 8 bits are the data bits. The one write enable bit selects whether the SPI transaction is a read or a write. The addressable register map spans 1024 registers of 8 data bits each. The map is not fully populated. A summarized structure of the register set is given in the following tables. Expanded bit descriptions are included in the individual functional sections for application guidance. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 101 FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP SPI BIT MAP • • • • • • • • • • • The tables include the following fields: Block: This corresponds directly to the chapter, section or topic in which the detailed register description is included. Address: The register memory map address allocation in HEX format Register Name R/W: Defines if the register is a Read/Write register or only a Read register D7-D0: The 8-bit data included in the register with each bit's name and location within the field included Initial: The register's default value after power up Function: A short description of the register's function Some important notes about data in the table: Reserved registers/bits are not implemented in the design and they will always read as a 0 Registers under the "FSL" block are Freescale dedicated registers and are not defined in the customer specifications. These registers represent additional functionality that Freescale is offering to enhance the performance of the overall system Registers under the "VD2" and "VD3" blocks are blocked from being used by Freescale The table only displays up to address 0x2FF. Address space between 0x300 and 0x3FF is reserved for future application use. Freescale is currently using the 0x300 to 0x3FF space for test and debug register implementation. This will not effect the application or any future use plans for this address space. The details of this space implementation are not discussed in this document. Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function Chip1 Chip2 Chip3 Chip4 IRQ IRQ CNTRL RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RTC RTC RTC RTC RTC RTC RTC RTC RTC 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 ID1 ID2 ID3 ID4 INTERRUPT INTMASK CHIPCNTRL RTCS RTCSA RTCM1 RTCMA RTCH RTCHA RTCDW RTCDM RTCM2 R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RSVD RSVD RSVD RSVD EXT MEXT RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PA-H PA-HA RSVD RSVD 19/20 RSVD RSVD RSVD RSVD AUX MAUX RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VRFAULT MVRFAULT RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD REV1[2:0] REV2[2:0] RSVD RSVD GPIO MGPIO RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RTC MRTC RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SEC[6:0] SECALARM[6:0] MIN[6:0] MINIALARM[6:0] RSVD RSVD CHR MCHR RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VENDID1[2:0] VENDID2[2:0] RSVD RSVD ADC MADC WARMRST RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PWRBTN MPWRBTN COLDRST RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x38 Chip1 ID 0x00 Chip2 ID 0x00 Chip3 ID 0x00 Chip4 ID 0x00 PMIC_INT sources, read clears 0xFA IRQ mask 0x00 PWRGD/RESET# control 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 RTC Second 0x00 RTC Second Alarm 0x00 RTC Minutes 0x00 RTC Minutes Alarm 0x00 RTC Hours 0x00 RTC Hours Alarm RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD HRS[5:0] HRSALARM[5:0] RSVD DOM[5:0] MONTH[4:0] DOW[2:0] 0x01 RTC Day Of Week 0x01 RTC Day Of Month 0x01 RTC Month 900844 102 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function RTC RTC RTC RTC RTC RTC RTC RTC RTC RSVD POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER RSVD RSVD RSVD POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER RSVD RSVD RSVD POWER 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x220x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C RTCY RTCA RTCB RTCC RTCD RTCE ADJ TRIM CLKOUT VRFAULTINT MVRFAULTINT VCCLATCH VNNLATCH PWRMASK VCCCNT VNNCNT VDDQCNT V21CNT V15CNT RSVD RSVD RSVD R/W R R/W R R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RSVD RSVD RSVD RSVD RSVD RSVD DVP1VRD DVP2VRD M7 RSVD RSVD RSVD RSVD M6 RSVD RSVD RSVD RSVD M5 RSVD SIGN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD UIP SET IRQF VRT DV[2:0] (=010b FIXED) PIE (=0) FIX PF (=0) FIX RSVD AIE AF RSVD SCRATCH[4:0] RSVD YEAR[7:0] RS[3:0] (=000b FIXED) UIE UF RSVD SQWE (=0) FIX RSVD RSVD DM RSVD RSVD POR RSVD RSVD RSVD HRMODE RSVD RSVD BKDET RSVD DSE (=0) FIX RSVD RSVD OSCST ADJ 0x00 RTC 0x20 RTC Control A 0x02 RTC Control B 0x00 RTC Control C 0x00 RTC Control D 0x05 RTC Optional Detection 0x00 RTC Adjustment 0x00 RTC Trimming RSVD RSVD BATOCP MBATOCP M32KCLK RSVD THRM MTHRM 0x00 32kHz clock output enable 0x00 Reserved 0x00 Voltage Regulators Fault interrupt 0x03 Voltage Regulators Fault interrupt Mask 0x7F VCC VID CONTROL 0x7F VNN VID CONTROL M2 M1 CTLVCC[2:0] CTLVNN[2:0] CTLVDDQ[2:0] CTLV21[2:0] CTLV15[2:0] M0 0x00 Power register write mask 0x24 VCC 0x04 VNN 0x04 VDDQ 0x07 V21 0x07 V15 RSVD RSVD RSVD 0x00 RSVD 0x00 RSVD 0x00 RSVD 0x07 VCCPAOAC 0x3C VCCPDDR 0x24 VLBG 0x3C VCCA 0x07 VPMIC 0x04 VIMG25 0x3C VCC180 0x3C VCCP 0x07 VAON 0x24 VPANEL18 0x24 VMM 0x24 VIMGA RSVD RSVD RSVD 0x00 RSVD 0x00 RSVD 0x00 RSVD 0x24 WiFiBT_YMX_ANA LOGRF TRIMVAL[5:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VIDVCC[6:0] VIDVNN[6:0] M4 AOACTLVCC[2:0] AOACTLVNN[2:0] AOACTLVDDQ[2:0] AOACTLV21[2:0] AOACTLV15[2:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD M3 RSVD RSVD VRFAIL MVRFAIL SELV15[1:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCCPAOACCNT R/W VCCPDDRCNT VLBGCNT VCCACNT VPMICCNT VIMG25CNT VCC180CNT VCCPCNT VAONCNT VPANEL18CNT VMMCNT VIMGACNT RSVD RSVD RSVD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W AOACTLVCCPAOAC[2:0] AOACTLVCCPDDR[2:0] AOACTLVLBG[2:0] AOACTLVCCA[2:0] AOACTLVPMIC[2:0] AOACTLVIMG25[2:0] AOACTLVCC180[2:0] AOACTLVCCP[2:0] AOACTLVAON[2:0] AOACTLVPANEL18[2:0] AOACTLVMM[2:0] AOACTLVIMGA[2:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CTLVCCPAOAC[2:0] CTLVCCPDDR[2:0] CTLVLBG[2:0] CTLVCCA[2:0] CTLVPMIC[2:0] CTLVIMG25[2:0] CTLVCC180[2:0] CTLVCCP[2:0] CTLVAON[2:0] CTLVPANEL18[2:0] CTLVMM[2:0] CTLVIMGA[2:0] RSVD RSVD RSVD RSVD RSVD RSVD SELIMGA[1:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VWYMXARFCNT R/W AOACTLVWYMXARF[2:0] CTLVWYMXARF[2:0] 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 103 FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function POWER RSVD POWER RSVD RSVD RSVD RSVD RSVD MEMORY MEMORY MEMORY MEMORY MEMORY MEMORY MEMORY MEMORY RSVD RSVD ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 VSDIOCNT RSVD VPANEL33CNT RSVD RSVD MEM1 MEM2 MEM3 MEM4 MEM5 MEM6 MEM7 MEM8 ADCINT MADCINT ADCCNTL2 ADCCNTL3 ADCCNTL4 ADCSNS0H ADCSNS0L ADCSNS1H ADCSNS1L ADCSNS2H ADCSNS2L ADCSNS3H ADCSNS3L ADCSNS4H ADCSNS4L ADCSNS5H ADCSNS5L ADCSNS6H ADCSNS6L ADCSNS7H ADCSNS7L ADCSNS8H ADCSNS8L ADCSNS9H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W SELVSDIO[1:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD AOACTLVSDIO[2:0] RSVD RSVD RSVD CTLVSDIO[2:0] RSVD CTLVPANEL33[2:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x64 VSDIO 0x00 RSVD 0x24 VCC_PANEL_3.3 0x00 RSVD 0x00 RSVD 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory AOACTLVPANEL33[2:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] RSVD RSVD RSVD RSVD ADEN RSVD RSVD RSVD RSVD ADSTRT RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CCEN ADEXGAIN 13 ADEXGAIN 21 ADCH0H[9:3] RSVD RSVD RSVD RSVD ADCH1H[9:3] RSVD RSVD RSVD RSVD ADCH2H[9:3] RSVD RSVD RSVD RSVD ADCH3H[9:3] RSVD RSVD RSVD RSVD ADCH4H[9:3] RSVD RSVD RSVD RSVD ADCH5H[9:3] RSVD RSVD RSVD RSVD ADCH6H[9:3] RSVD RSVD RSVD RSVD ADCH7H[9:3] RSVD RSVD RSVD RSVD ADCH8H[9:3] RSVD RSVD RSVD RSVD ADCH9H[9:3] ADCH8L[2:0] ADCH7L[2:0] ADCH6L[2:0] ADCH5L[2:0] ADCH4L[2:0] ADCH3L[2:0] ADCH2L[2:0] ADCH1L[2:0] ADCH0L[2:0] ADEXGAI N12 ADEXGAI N20 RSVD RSVD OVERFLO W RSVD RSVD PENDET RSVD RSVD RND MRND 0x00 Reserved 0x00 Reserved 0x00 ADC interrupt 0x00 ADC interrupt Mask 0x00 ADC control 0x00 GAIN for AN10AN17 0x00 GAIN for AN18AN21 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result 0x00 ADC result MOVERFL MPENDET OW ADSLP[2:0] PENDETEN CCCLEAR ADEXGAI N14 RSVD R/W ADEXGAIN1 ADEXGAIN ADEXGAIN 7 16 15 R/W R R R R R R R R R R R R R R R R R R R RSVD GAIN0 RSVD GAIN1 RSVD GAIN2 RSVD GAIN3 RSVD GAIN4 RSVD GAIN5 RSVD GAIN6 RSVD GAIN7 RSVD GAIN8 RSVD GAIN9 RSVD RSVD ADEXGAIN ADEXGAIN 11 10 ADEXGAIN ADEXGAIN 19 18 900844 104 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 ADCSNS9L ADCSNS10H ADCSNS10L ADCSNS11H ADCSNS11L ADCSNS12H ADCSNS12L ADCSNS13H ADCSNS13L ADCSNS14H ADCSNS14L ADCSNS15H ADCSNS15L ADCSNS16H ADCSNS16L ADCSNS17H ADCSNS17L ADCSNS18H ADCSNS18L ADCSNS19H ADCSNS19L ADCSNS20H ADCSNS20L ADCSNS21H ADCSNS21L ADCSNS22H ADCSNS22L ADCSNS23H ADCSNS23L ADCSNS24H ADCSNS24L ADCSNS25H ADCSNS25L ADCSNS26H ADCSNS26L ADCSNS27H ADCSNS27L ADCSNS28H ADCSNS28L ADCSNS29H ADCSNS29L ADCSNS30H ADCSNS30L ADCSNS31H ADCSNS31L R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R RSVD GAIN10 RSVD GAIN11 RSVD GAIN12 RSVD GAIN13 RSVD GAIN14 RSVD GAIN15 RSVD GAIN16 RSVD GAIN17 RSVD GAIN18 RSVD GAIN19 RSVD GAIN20 RSVD GAIN21 RSVD GAIN22 RSVD GAIN23 RSVD GAIN24 RSVD GAIN25 RSVD GAIN26 RSVD GAIN27 RSVD GAIN28 RSVD GAIN29 RSVD GAIN30 RSVD GAIN31 RSVD RSVD RSVD RSVD RSVD ADCH10H[9:3] ADCH9L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH11H[9:3] ADCH10L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH12H[9:3] ADCH11L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH13H[9:3] ADCH12L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH14H[9:3] ADCH13L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH15H[9:3] ADCH14L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH16H[9:3] ADCH15L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH17H[9:3] ADCH16L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH18H[9:3] ADCH17L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH19H[9:3] ADCH18L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH20H[9:3] ADCH19L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH21H[9:3] ADCH20L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH22H[9:3] ADCH21L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH23H[9:3] ADCH22L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH24H[9:3] ADCH23L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH25H[9:3] ADCH24L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH26H[9:3] ADCH25L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH27H[9:3] ADCH26L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH28H[9:3] ADCH27L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH29H[9:3] ADCH28L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH30H[9:3] ADCH29L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH31H[9:3] ADCH30L[2:0] 0x00 ADC result 0x00 ADC result RSVD RSVD RSVD RSVD ADCH31L[2:0] 0x00 ADC result 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 105 FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 ADCADDR0 ADCADDR1 ADCADDR2 ADCADDR3 ADCADDR4 ADCADDR5 ADCADDR6 ADCADDR7 ADCADDR8 ADCADDR9 ADCADDR10 ADCADDR11 ADCADDR12 ADCADDR13 ADCADDR14 ADCADDR15 ADCADDR16 ADCADDR17 ADCADDR18 ADCADDR19 ADCADDR20 ADCADDR21 ADCADDR22 ADCADDR23 ADCADDR24 ADCADDR25 ADCADDR26 ADCADDR27 ADCADDR28 ADCADDR29 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XMYP0 XMYP1 XMYP2 XMYP3 XMYP4 XMYP5 XMYP6 XMYP7 XMYP8 XMYP9 XMYP10 XMYP11 XMYP12 XMYP13 XMYP14 XMYP15 XMYP16 XMYP17 XMYP18 XMYP19 XMYP20 XMYP21 XMYP22 XMYP23 XMYP24 XMYP25 XMYP26 XMYP27 XMYP28 XMYP29 YPYM0 YPYM1 YPYM2 YPYM3 YPYM4 YPYM5 YPYM6 YPYM7 YPYM8 YPYM9 YPYM10 YPYM11 YPYM12 YPYM13 YPYM14 YPYM15 YPYM16 YPYM17 YPYM18 YPYM19 YPYM20 YPYM21 YPYM22 YPYM23 YPYM24 YPYM25 YPYM26 YPYM27 YPYM28 YPYM29 XPXM0 XPXM1 XPXM2 XPXM3 XPXM4 XPXM5 XPXM6 XPXM7 XPXM8 XPXM9 XPXM10 XPXM11 XPXM12 XPXM13 XPXM14 XPXM15 XPXM16 XPXM17 XPXM18 XPXM19 XPXM20 XPXM21 XPXM22 XPXM23 XPXM24 XPXM25 XPXM26 XPXM27 XPXM28 XPXM29 ADSEL0[4:0] ADSEL1[4:0] ADSEL2[4:0] ADSEL3[4:0] ADSEL4[4:0] ADSEL5[4:0] ADSEL6[4:0] ADSEL7[4:0] ADSEL8[4:0] ADSEL9[4:0] ADSEL10[4:0] ADSEL11[4:0] ADSEL12[4:0] ADSEL13[4:0] ADSEL14[4:0] ADSEL15[4:0] ADSEL16[4:0] ADSEL17[4:0] ADSEL18[4:0] ADSEL19[4:0] ADSEL20[4:0] ADSEL21[4:0] ADSEL22[4:0] ADSEL23[4:0] ADSEL24[4:0] ADSEL25[4:0] ADSEL26[4:0] ADSEL27[4:0] ADSEL28[4:0] ADSEL29[4:0] 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 0x00 ADC selector address 900844 106 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function ADC ADC RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CHARGER CHARGER CHARGER CHARGER RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO RSVD RSVD RSVD 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB ADCADDR30 ADCADDR31 RSVD RSVD CHRGINT MCHRGINT SCHRGINT RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPIOCNTL0 GPIOCNTL1 GPIOCNTL2 GPIOCNTL3 GPIOCNTL4 GPIOCNTL5 GPIOCNTL6 GPIOCNTL7 GPIOINT - R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R - XMYP30 XMYP31 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD YPYM30 YPYM31 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD XPXM30 XPXM31 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD BATDET MBATDET SBATDET RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DATAOUT0 DATAOUT0 DATAOUT0 DATAOUT0 DATAOUT0 DATAOUT0 DATAOUT0 DATAOUT0 GPIINT3 RSVD RSVD RSVD ADSEL30[4:0] ADSEL31[4:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD TEMP MTEMP STEMP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DATAIN0 DATAIN0 DATAIN0 DATAIN0 DATAIN0 DATAIN0 DATAIN0 DATAIN0 GPIINT2 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD BATOVP MBATOVP SBATOVP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DIR0 DIR0 DIR0 DIR0 DIR0 DIR0 DIR0 DIR0 GPIINT1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD DRV0 DRV0 DRV0 DRV0 DRV0 DRV0 DRV0 DRV0 GPIINT0 RSVD RSVD RSVD 0x00 ADC selector address 0x00 ADC selector address 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Charger Interrupt 0x00 Charger Interrupt Mask 0x00 Charger State 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x03 GPIO control 0x03 GPIO control 0x03 GPIO control 0x03 GPIO control 0x03 GPIO control 0x03 GPIO control 0x03 GPIO control 0x03 GPIO control 0x00 GPIO Interrupt 0x00 Reserved 0x00 Reserved 0x00 Reserved GPIDBNC0[1:0] GPIDBNC0[1:0] GPIDBNC0[1:0] GPIDBNC0[1:0] GPIDBNC0[1:0] GPIDBNC0[1:0] GPIDBNC0[1:0] GPIDBNC0[1:0] GPIINT7 RSVD RSVD RSVD GPIINT6 RSVD RSVD RSVD INTCTL0[1:0] INTCTL0[1:0] INTCTL0[1:0] INTCTL0[1:0] INTCTL0[1:0] INTCTL0[1:0] INTCTL0[1:0] INTCTL0[1:0] GPIINT5 RSVD RSVD RSVD GPIINT4 RSVD RSVD RSVD 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 107 FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPIO RSVD RSVD RSVD RSVD VD2 VD3 RSVD FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFF 0x100 0x132 0x133 0x199 0x19A 0x19B 0x19C 0x19D 0x19E 0x19F 0x1A0 0x1A1 0x1A2 0x1A3 0x1A4 0x1A5 0x1A6 0x1A7 0x1A8 0x1A9 0x1AA 0x1AB 0x1AC 0x1AD 0x1AE 0x1AF 0x1B0 0x1B1 0x1B2 GPO FSLMEM1 FSLMEM2 FSLMEM3 FSLMEM4 FSLMEM5 R/W R/W R/W R/W R/W R/W RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO7 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO6 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO5 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO4 RSVD RSVD RSVD RSVD VD2 VD3 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO3 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO2 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPO0 RSVD RSVD RSVD RSVD 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 GPO control 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved Reserved Reserved RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] 900844 108 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL 0x1B3 0x1B4 0x1B5 0x1B6 0x1B7 0x1B8 0x1B9 0x1BA 0x1BB 0x1BC 0x1BD 0x1BE 0x1BF 0x1C0 0x1C1 0x1C2 0x1C3 0x1C4 0x1C5 0x1C6 0x1C7 0x1C8 0x1C9 0x1CA 0x1CB 0x1CC 0x1CD 0x1CE 0x1CF 0x1D0 0x1D1 0x1D2 0x1D3 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 FSLMEM6 FSLMEM7 FSLMEM8 FSLMEM9 FSLMEM10 FSLMEM11 FSLMEM12 FSLMEM13 FSLMEM14 FSLMEM15 FSLMEM16 FSLOUTDRVCN TL1 FSLOUTDRVCN TL2 FSLOUTDRVCN TL3 - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RSVD RSVD RSVD SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] SCRATCH[7:0] RSVD RSVD RSVD RSVD RSVD 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Backup memory 0x00 Reserved 0x00 Digital Outputs Drive Strength 0x04 Digital Outputs Drive Strength 0x01 Digital Outputs Drive Strength 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0xAA Buck Turn On time control (DVS Clk) 0x7F VCC VID CONTROL 0x7F VNN VID CONTROL RSVD VDDQFAU LT RSVD RSVD RSVD RSVD V21TONT VNNFAUL T RSVD RSVD VIMG28FA ULT RSVD COINCHE N RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCCFAULT RSVD VYMXYFI18 FAULT VIMG25FA ULT RSVD CHGBYP RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0xAA Buck Turn On time control (DVS Clk) 0x00 Regulator Fault Flag 0x00 Regulator Fault Flag 0x00 Regulator Fault Flag 0x00 Regulator Fault Flag 0x00 Reserved 0x13 Charger Control 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved RESETBDRV[1:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PMICINTDRV[1:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VRCOMPBDRV[1:0] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PWRGDDRV[1:0] CLK32KDRV[1:0] SPISDODRV RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD FSLTONTCNTL1 R/W FSLVCCLATCH FSLVNNLATCH R R VDDQTONT VNNTONT VIDVCC[6:0] VIDVNN[6:0] VCCTONT FSLTONTCNTL2 R/W FSLFAULT1 FSLFAULT2 FSLFAULT3 FSLFAULT4 FSLCHRGCNTL R R R R R/W - RSVD RSVD VCC180FA ULT RSVD V15TONT V15FAULT V21FAULT VCCAFAU VBGFAULT LT VCCPAOA CFAULT VSDIOFAU LT RSVD VCOIN[4:2] RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VPMICFAUL VPNL18FA T ULT VCCPFAULT VMMFAUL VAONFAUL VCCPDDR T T FAULT RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 109 FUNCTIONAL DEVICE OPERATION SPI REGISTER MAP Table 74. SPI Register Map Block Address Register Name R/W D7 D6 D5 D4 D3 D2 D1 D0 Initial Function FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL FSL RSVD FSL FSL FSL FSL RSVD VD2 RSVD 0x1D9 0x1DA 0x1DB 0x1DC 0x1DD 0x1DE 0x1DF 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1FA 0x1FB 0x1FC 0x1FD 0x1FE 0x1FF 0x200 0x227 0x228 0x2FF FSLADCCNTL FSLPLLCNTL - R/W R/W - RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD TSPAS RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD ADCCAL RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD LSBSEL RSVD RSVD RSVD RSVD RSVD PLLEN RSVD RSVD RSVD RSVD RSVD RSVD BATDETVC ON RSVD RSVD RSVD RSVD RSVD PLL16MEN RSVD RSVD RSVD RSVD RSVD RSVD LICON RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CHRGICO N RSVD RSVD RSVD RSVD RSVD PLLDIVIDE[2:0] RSVD RSVD RSVD RSVD RSVD VPWRCON RSVD RSVD RSVD RSVD RSVD 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 ADC Spare Channel Control 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x00 Reserved 0x1B Reserved RSVD RSVD RSVD 0x00 Reserved 0x7F Switching Regulator Debug 0x7F Switching Regulator Debug BUCK_TOP_LVS R/W BUCK_V15_ H_5 EN BUCK_TOP_LVS R/W BUCK_V21_ H_4 EN RSVD BUCK_VDD Q_EN RSVD RSVD RSVD RSVD RSVD BUCK_V15_PWRSTG_EN BUCK_V21_PWRSTG_EN RSVD RSVD RSVD RSVD RSVD 0x00 Reserved 0x7F Switching Regulator Debug BUCK_TOP_LVS R/W H_2 - BUCK_VDDQ_PWRSTG_EN[6:0] RSVD VD2 RSVD RSVD RSVD RSVD 0x00 Reserved Reserved RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 0x00 Reserved Notes 21. RSVD: Reserved registers, not for customer use. 22. FSL: Freescale dedicated Registers for special PMIC control 900844 110 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION HARDWARE DESIGN CONSIDERATIONS HARDWARE DESIGN CONSIDERATIONS EXTERNAL COMPONENT REQUIREMENT Table 75. External Components BOM (23) Component Value Package Description Freescale Package 900844 MAPBGA Integrated Power Management IC for Ultra-mobile Platforms for Netbook Computers VCC - (0.65 - 1.2 V) / 3.5 A VID CPU BUCK with External FETs CINCC COCC LCC MHSCC MLSCC 10 μF 22 μF 0.68 μH 46 mohm 23 mohm 0603 0603 4x4x2 BGA BGA Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 4.0 V, X5R Saturation current = 4.8 A for 10% drop, DCR_max = 25.3 mohm High Side P-FET Low Side N-FET VNN - (0.65 - 1.2 V) / 1.6 A VID CPU BUCK with External FETs CINNN CONN LNN MNN 10 μF 22 μF 1.0 μH 95 mohm 68 mohm 0603 0603 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 4.0 V, X5R 1 2 1 1 GRM188R60J106ME47D AMK107BJ226MA-T LPS3314-102ML FDMA1032CZ Murata Taiyo Yuden Coilcraft Fairchild 1 4 1 1 1 GRM188R60J106ME47D AMK107BJ226MA-T XPL4020-681MLB FDZ293P, FDC638APZ or FDMA291P FDZ294N, FDC637BNZ or FDMA430NZ Murata Taiyo Yuden Coilcraft Fairchild Fairchild 1 SC900844JVK Freescale Qty Part # Manufacturer 3.3x3.3x1.4 Saturation current = 2.3 A for 10% drop, DCR_max = 55 mohm MicroFET High Side P-FET and Low Side N-FET housed in one package VDDQ - 1.8/1.5 V / 1.3 A BUCK CINDDQ CODDQ LDDQ RFBDDQ15_1 (24) 10 μF 22 μF 0.50 μH 681 ohm 2.21 kohm 0603 0603 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 4.0 V, X5R 1 2 1 1 1 GRM188R60J106ME47D AMK107BJ226MA-T XPL2010-501ML CRCW0402681RFKED CRCW04022K21FKED Murata Taiyo Yuden Coilcraft Vishay/Dale Vishay/Dale 2.0x2.0x1.0 Saturation current = 1.8 A for 10% drop, DCR_max = 45 mohm 0402 0402 Chip resistor 1% 1/10W Chip resistor 1% 1/10W V21 - 2.1 V / 1.0 A BUCK RFBDDQ15_2(24) CIN21 CO21 L21 10 μF 22 μF 0.50 μH 0603 0603 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 4.0 V, X5R 1 1 1 GRM188R60J106ME47D AMK107BJ226MA-T XPL2010-501ML Murata Taiyo Yuden Coilcraft 2.0x2.0x1.0 Saturation current = 1.8 A for 10% drop, DCR_max = 45 mohm V15 - 1.5 V(or 1.6 V) / 1.5 A BUCK CIN15 CO15 L15 10 μF 22 μF 0.50 μH 0603 0603 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 4.0 V, X5R 1 2 1 GRM188R60J106ME47D AMK107BJ226MA-T XPL2010-501ML Murata Taiyo Yuden Coilcraft 2.0x2.0x1.0 Saturation current = 1.8 A for 10% drop, DCR_max = 45 mohm Notes 23. Throughout this document, there are references to non-Freescale components. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. 24. To operate the VDDQ as a 1.5 V buck regulator, the recommended resistors, RFBDDQ15_1 and RFBDDQ15_2 are needed in the feedback path, as shown in Figure 28. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 111 FUNCTIONAL DEVICE OPERATION HARDWARE DESIGN CONSIDERATIONS Table 75. External Components BOM (23) Component Value Package Description VBG - 1.25 V/2.0 mA LDO & VCCA - 1.5 V/150 mA LDO CIN1P8 COBG COCCA 100 nF 1.0 μF 2.2 μF 0201 0402 0402 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R 1 1 1 GRM033R60J104KE19D GRM155R60J105ME19D GRM155R60J225ME15D Murata Murata Murata Qty Part # Manufacturer VCC180- 1.8 V/390 mA LDO & VPNL18- 1.8 V/225 mA LDO & - 1.8 V/50 mA LDO CIN2P1 COCC180 COPNL18 COPMIC 0.47 μF 2.2 μF 2.2 μF 2.2 μF 0402 0402 0402 0402 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R VYMXYFI18 - (YMX:1.8 V/200 mA - YFI:1.8 V/200 mA) LDO CINYMXYFI18 COYMXYFI18 100 nF 2.2 μF 0201 0402 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R 1 1 GRM033R60J104KE19D GRM155R60J225ME15D Murata Murata 1 1 1 1 GRM155R60J474KE19D GRM155R60J225ME15D GRM155R60J225ME15D GRM155R60J225ME15D Murata Murata Murata Murata VCCPAOAC- 1.05 V/155 mA LDO & VCCPDDR - 1.05 V/60 mA LDO & VAON - 1.2 V/250 mA LDO &VMM- 1.2 V/5.0 mA LDO & VCCP - 1.05 V/445 mA LDO CIN1P5 COCCPAOAC COCCPDDR COAON COMM COCCP 0.47 μF 2.2 μF 1.0 μF 2.2 μF 1.0 μF 2.2 μF 0402 0402 0402 0402 0402 0402 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R VIMG25- 2.5 V/80 mA LDO & VIMG28- 2.8 V/225 mA LDO CINIMG COIMG25 COIMG28 100 nF 2.2 μF 2.2 μF 0201 0402 0402 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R VPNL33 - 3.3 V/100 mA Switch COPNL33 100 nF 0201 Ceramic Capacitor, 6.3 V, X5R VSDIO - 3.3 V/215 mA Switch OR 1.8 V/215 mA LDO CINSDIO COSDIO RSDIO MSDIO 100 nF 2.2 μF 0 ohm 95 mohm 0201 0402 0402 SC70 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Chip Resistor, 1% PFET, switch Internal Supplies CCORE CCOREDIG CCOREREF 2.2 μF 2.2 μF 100 nF 0402 0402 0201 Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Ceramic Capacitor, 6.3 V, X5R Input power path RNTCEV RNTC CBAT 10 kohm 10 kohm 22 μF 0201 0201 0805 Chip Resistor, 1% Chip Resistor, 1% Ceramic Capacitor, 10 V, X5R Coin cell CCOIN 100 nF 0201 Ceramic Capacitor, 6.3 V, X5R 1 GRM033R60J104KE19D Murata 1 1 2 ERJ-1GEF1002C ERJ-1GEF1002C LMK212BJ226MG-T Panasonic Panasonic Taiyo Yuden 1 1 1 GRM155R60J225ME15D GRM155R60J225ME15D GRM033R60J104KE19D Murata Murata Murata 1 1 1 1 GRM033R60J104KE19D GRM155R60J225ME15D ERJ-2GE0R00X FDG332PZ Murata Murata Panasonic Fairchild 1 GRM033R60J104KE19D Murata 1 1 1 GRM033R60J104KE19D GRM155R60J225ME15D GRM155R60J225ME15D Murata Murata Murata 1 1 1 1 1 1 GRM155R60J474KE19D GRM155R60J225ME15D GRM155R60J105ME19D GRM155R60J225ME15D GRM155R60J105ME19D GRM155R60J225ME15D Murata Murata Murata Murata Murata Murata 900844 112 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION HARDWARE DESIGN CONSIDERATIONS Table 75. External Components BOM (23) Component Value Package Description ADC CADREF 1.0 μF 0402 Ceramic Capacitor, 6.3 V, X5R Oscillator and Real Time Clock - RTC XTALRTC CXTALRTC1 CXTALRTC2 32.768 kHz 22 pF 22 pF 3.2x1.5x0.9 0201 0201 CRYSTAL 32.768 kHZ 12.5 pF SMD Ceramic Capacitor, 25 V, C0G Ceramic Capacitor, 25 V, C0G 1 1 1 ABS07-32.768KHZ-T GRM0335C1E220JD01D GRM0335C1E220JD01D Abracon Murata Murata 1 GRM155R60J105ME19D Murata Qty Part # Manufacturer GPIOs & GPOs & Power Button RPULLUPX(25) 100 kohm 0201 Chip Resistor, 1% - Pull-up Resistors for OD configured GPIOs Total Component Count 0 62 ERJ-1GEF1003C Panasonic Notes 25. This is a recommended resistor when required by a specific GPIO. 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 113 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. JVK SUFFIX 338-PIN 98ASA10841D REVISION 0 900844 114 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS JVK SUFFIX 338-PIN 98ASA10841D REVISION 0 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 115 PACKAGING PACKAGE DIMENSIONS PACKAGE MECHANICAL OUTLINE DRAWING The package style is an 11x11 fine interstitial pitch, thin profile PBGA. The package has a semi populated matrix that includes 338 balls. The ball count includes 322 assigned signal pins and four sets of 4 corner balls. PACKAGE ASSEMBLY RECOMMENDATIONS For improved protection against mechanical shock, Freescale recommends applying corner glue to the mounted 900844 MAPBGA package. This corner glue application is described in the AN3954 - "PCB Layout Guidelines for SC900841 and SCCSP900842" application note. Freescale’s preferred material for the corner glue application is the Loctite 3128 board level adhesive, applied at a 0° or 45° dispense angle in a continuous motion, and with the fillet length extended to a minimum of 3 ball rows and columns, at each corner. 900844 116 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION 1.0 DATE 8/2010 DESCRIPTION OF CHANGES • • • • • • Initial release Ball map updates Fix Default Values for Various VR control registers. Fix Package Suffix to “JVK” Freescale format, form and style corrections. No parametrics were altered. Only various adjustments, corrections, and clarifications were made to text, tables, and images, for improved accuracy. 2.0 5/2011 900844 Analog Integrated Circuit Device Data Freescale Semiconductor 117 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2010-2011. All rights reserved. SC900844 Rev. 2.0 5/2011