KMPC875ZT80

Freescale Semiconductor MPC875EC Rev. 3.0, 07/2004 MPC875/MPC870 Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC875/MPC870. The CPU on the MPC875/MPC870 is a 32-bit PowerPC™ core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set. This hardware specification covers the following topics: 1 Overview The MPC875/MPC870 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Calculation and Measurement . . . . . . . . . . 11 Power Supply and Power Sequencing . . . . . . . . . . . 13 Mandatory Reset Configurations . . . . . . . . . . . . . . . 14 Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44 CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46 USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67 FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67 Mechanical Data and Ordering Information . . . . . . . 71 Document Revision History . . . . . . . . . . . . . . . . . . . 82 © Freescale Semiconductor, Inc., 2004. All rights reserved. PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Features Table 1 shows the functionality supported by the members of the MPC875/MPC870. Table 1. MPC875/870 Devices Cache Part I Cache MPC875 MPC870 8 Kbyte 8 Kbyte D Cache 8 Kbyte 8 Kbyte 10BaseT 1 — 10/100 2 2 1 — 1 1 1 1 Ethernet SCC SMC USB Security Engine Yes No 2 Features The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC875/870 features: • • Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) — The 133-MHz core frequency supports 2:1 mode only. — The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch and without conditional execution. — 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) – Instruction cache is two-way, set-associative with 256 sets in 2 blocks – Data cache is two-way, set-associative with 256 sets – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups — Advanced on-chip emulation debug mode Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank. — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line • • • • MPC875/MPC870 Hardware Specifications, Rev. 3.0 2 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Features • • • • • — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbyte–256 Mbyte) — Selectable write protection — On-chip bus arbitration logic General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting. — Interrupt can be masked on reference match and event capture Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that interface through MII and/or RMII interfaces System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Clock synthesizer — Decrementer and time base — Reset controller — IEEE 1149.1 test access port (JTAG) Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP, 802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are: — Data encryption standard execution unit (DEU) – DES, 3DES – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES — Advanced encryption standard unit (AESU) – Implements the Rinjdael symmetric key cipher – ECB, CBC, and counter modes – 128-, 192-, and 256-bit key lengths — Message digest execution unit (MDEU) – SHA with 160- or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either algorithm — Master/slave logic, with DMA – 32-bit address/32-bit data – Operation at 8xx bus frequency — Crypto-channel supporting multi-command descriptors – Integrated controller managing crypto-execution units – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes Interrupts — Six external interrupt request (IRQ) lines MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 3 Features • • • • • • — 12 port pins with interrupt capability — 23 internal interrupt sources — Programmable priority between SCCs — Programmable highest priority request Communications processor module (CPM) — RISC controller — Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) — Supports continuous mode transmission and reception on all serial channels — 8-Kbytes of dual-port RAM — Several serial DMA (SDMA) channels to support the CPM — Three parallel I/O registers with open-drain capability On-chip 16 × 16 multiply accumulate controller (MAC) — One operation per clock (two-clock latency, one-clock blockage) — MAC operates concurrently with other instructions — FIR loop—Four clocks per four multiplies Four baud-rate generators — Independent (can be connected to any SCC or SMC) — Allows changes during operation — Autobaud support option SCC (serial communication controller) — Ethernet/IEEE 802.3 optional on the SCC, supporting full 10-Mbps operation — HDLC/SDLC — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support point-to-point protocol (PPP) — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC)) SMC (serial management channel) — UART (low-speed operation) — Transparent Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host controller, or both for testing purposes (loopback diagnostics) — USB 2.0 full-/low-speed compatible — The USB function mode has the following features: – Four independent endpoints support control, bulk, interrupt, and isochronous data transfers. MPC875/MPC870 Hardware Specifications, Rev. 3.0 4 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Features • • • • • • • • – CRC16 generation and checking – CRC5 checking – NRZI encoding/decoding with bit stuffing – 12- or 1.5-Mbps data rate – Flexible data buffers with multiple buffers per frame – Automatic retransmission upon transmit error — The USB host controller has the following features: – Supports control, bulk, interrupt, and isochronous data transfers – CRC16 generation and checking – NRZI encoding/decoding with bit stuffing – Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. – Flexible data buffers with multiple buffers per frame – Supports local loopback mode for diagnostics (12 Mbps only) Serial peripheral interface (SPI) — Supports master and slave modes — Supports multiple-master operation on the same bus Inter-integrated circuit (I2C) port — Supports master and slave modes — Supports a multiple-master environment The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb). — Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking — Allows dynamic changes — Can be internally connected to two serial channels (one SCC and one SMC) PCMCIA interface — Master (socket) interface, release 2.1-compliant — Supports one independent PCMCIA socket on the MPC875/MPC870 — 8 memory or I/O windows supported Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = ≠ < > — Each watchpoint can generate a break point internally. Normal high and normal low power modes to conserve power 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility The MPC875/870 comes in a 256-pin ball grid array (PBGA) package. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 5 Features The MPC875 block diagram is shown in Figure 1. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller External Internal Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII/RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Security Engine Controller Channel AESU DEU MDEU Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SCC4 SMC1 SPI I2C Time Slot Assigner Serial Interface Figure 1. MPC875 Block Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 6 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Maximum Tolerated Ratings The MPC870 block diagram is shown in Figure 2. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller External Internal Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII / RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SMC1 SPI I2C Serial Interface Figure 2. MPC870 Block Diagram 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC875/870. Table 2 displays the maximum tolerated ratings, and Table 3 displays the operating temperatures. MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 7 Maximum Tolerated Ratings Table 2. Maximum Tolerated Ratings Rating Supply voltage 1 Symbol VDDL (core voltage) VDDH (I/O voltage) VDDSYN Difference between VDDL and VDDSYN Input voltage 2 Storage temperature range 1 The 2 Value –0.3 to 3.4 –0.3 to 4 –0.3 to 3.4 100 KHz) timings. Table 29. I2C Timing (SCL > 100 KHZ) All Frequencies Num Characteristic Expression Min 200 200 202 203 204 205 206 207 208 209 210 211 1 SCL Unit Max BRGCLK/48 BRGCLK/48 — — — — — — — 1/(10 × fSCL) 1/(33 × fSCL) — Hz Hz s s s s s s s s s s SCL clock frequency (slave) SCL clock frequency (master) 1 fSCL fSCL — — — — — — — — — — 0 BRGCLK/16512 1/(2.2 × fSCL) 1/(2.2 × fSCL) 1/(2.2 × fSCL) 1/(2.2 × fSCL) 1/(2.2 × fSCL) 0 1/(40 × fSCL) — — 1/2(2.2 × fSCL) Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) × pre_scalar × 2). The ratio SyncClk/(Brg_Clk/pre_scalar) must be greater than or equal to 4/1. MPC875/MPC870 Hardware Specifications, Rev. 3.0 66 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor USB Electrical Characteristics Figure 63 shows the I2C bus timing. SDA 202 205 SCL 206 209 210 211 203 207 204 208 Figure 63. I2C Bus Timing Diagram 14 USB Electrical Characteristics This section provides the AC timings for the USB interface. 14.1 USB Interface AC Timing Specifications The USB Port uses the transmit clock on SCC1. Table 30 lists the USB interface timings. Table 30. USB Interface AC Timing Specifications All Frequencies Name US1 Characteristic Min USBCLK frequency of operation 1 Low speed Full speed USBCLK duty cycle (measured at 1.5 V) 45 6 48 55 Max MHz MHz % Unit US4 1 USBCLK accuracy should be ± 500 ppm or better. USBCLK may be stopped to conserve power. 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 15.1 MII and Reduced MII Receive Signal Timing The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. The reduced MII (RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%. MPC875/MPC870 Hardware Specifications, Rev. 3.0 67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics Table 31 provides information on the MII receive signal timing. Table 31. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold MII_RX_CLK pulse width high MII_RX_CLK pulse width low Min 5 5 35% 35% 4 2 Max — — 65% 65% — — Unit ns ns MII_RX_CLK period MII_RX_CLK period ns ns M1_R RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK MII setup M2_R RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR MII hold Figure 64 shows MII receive signal timing. M3 MII_RX_CLK (input) M4 MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER M1 M2 Figure 64. MII Receive Signal Timing Diagram 15.2 MII and Reduced MII Transmit Signal Timing The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%. Table 32 provides information on the MII transmit signal timing. Table 32. MII Transmit Signal Timing Num M5 M6 M7 M8 Characteristic MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid MII_TX_CLK pulse width high MII_TX_CLK pulse width low Min 5 — 35% 35% Max — 25 65% 65% Unit ns ns MII_TX_CLK period MII_TX_CLK period MPC875/MPC870 Hardware Specifications, Rev. 3.0 68 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics Table 32. MII Transmit Signal Timing (continued) Num Characteristic Min 4 2 Max — — Unit ns ns M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup MII M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising MII edge Figure 65 shows the MII transmit signal timing diagram. M7 MII_TX_CLK (input) M5 M8 MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER M6 Figure 65. MII Transmit Signal Timing Diagram 15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 33 provides information on the MII async inputs signal timing. Table 33. MII Async Inputs Signal Timing Num M9 Characteristic MII_CRS, MII_COL minimum pulse width Min 1.5 Max — Unit MII_TX_CLK period Figure 66 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure 66. MII Async Inputs Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 69 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 34 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 34. MII Serial Management Channel Timing Num M10 M11 M12 M13 M14 M15 Characteristic MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) MII_MDC falling edge to MII_MDIO output valid (max prop delay) MII_MDIO (input) to MII_MDC rising edge setup MII_MDIO (input) to MII_MDC rising edge hold MII_MDC pulse width high MII_MDC pulse width low Min 0 — 10 0 40% 40% Max — 25 — — 60% 60% Unit ns ns ns ns MII_MDC period MII_MDC period Figure 67 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (output) M10 MII_MDIO (output) M11 MII_MDIO (input) M12 M13 Figure 67. MII Serial Management Channel Timing Diagram MPC875/MPC870 Hardware Specifications, Rev. 3.0 70 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 35 identifies the packages and operating frequencies available for the MPC875/870. Table 35. Available MPC875/870 Packages/Frequencies Package Type Plastic ball grid array ZT suffix — Leaded VR suffix — Lead-Free are available as needed Temperature (Tj) Frequency (MHz) 0°C to 95°C 66 Order Number KMPC875ZT66 KMPC870ZT66 MPC875ZT66 MPC870ZT66 KMPC875ZT80 KMPC870ZT80 MPC875ZT80 MPC870ZT80 KMPC875ZT133 KMPC870ZT133 MPC875ZT133 MPC870ZT133 KMPC875CZT66 KMPC870CZT66 MPC875CZT66 MPC870CZT66 KMPC875CZT133 KMPC870CZT133 MPC875CZT133 MPC870CZT133 80 133 Plastic ball grid array CZT suffix — Leaded CVR suffix — Lead-Free are available as needed -40°C to 100°C 66 133 16.1 Pin Assignments Figure 68 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC885 PowerQUICC Family User’s Manual. NOTE The pin numbering starts with B2 in order to conform to the JEDEC standard for 23-mm body size using a 16 × 16 array. MPC875/MPC870 Hardware Specifications, Rev. 3.0 71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information NOTE: This is the top view of the device. 2 B MODCK2 TEXP EXTCLK MODCK1 OP0 ALEA IPB0 BURST IRQ6 BR TEA BI CS0 CS3 CS5 N/C 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 C IPA7 RSTCONF SRESET BADDR29 OP1 AS ALEB IRQ2 BB TS TA BDIP CS2 CE1A GPLAB3 GPLA0 D IPA4 IPA2 WAITA PORESET XTAL EXTAL BADDR30 IPB1 BG GPLA4 GPLA5 WR CE2A CS7 WE2 WE1 E D31 IPA5 IPA3 VSSSYN VDDSYN HRESET BADDR28 IRQ4 IRQ3 CS1 GPLB4 CS4 GPLAB2 WE0 BSA1 BSA2 F D29 D30 IPA6 IPA1 VSSSYN1 VDDL VDDL CS6 OE BSA0 BSA3 TSIZ0 A31 G D7 D28 CLKOUT D26 IPA0 VDDH VDDH WE3 TSIZ1 A26 A22 A18 H D22 D6 D24 D25 VDDL VDDH GND VDDH VDDL A28 A30 A25 A24 J D18 D19 D20 D21 GND A23 A21 A20 A29 K D5 D15 D16 D14 VDDL GND VDDL A14 A19 A27 A17 L D3 D2 D27 D0 VDDH GND VDDH VDDH A10 A12 A15 A16 M D11 D9 D12 PE18 IRQ0 VDDH VDDH MII_MDIO A2 A8 A11 A13 N D10 D1 D13 IRQ7 PA2 VDDL VDDL PB26 PB27 A1 A6 A7 A9 P D23 D17 PE22 IRQ1 PA0 PA4 PE14 PE31 PC6 PA6 PC11 TDO PA15 A3 A5 A4 R D4 D8 PE25 PA3 PE19 PE28 PE30 PA11 MII_COL PA7 PA10 TCK PB28 PC15 A0 PB29 T PE26 PD8 PA1 PB31 PE27 PE15 PE17 PE21 PC7 PB19 PB24 TDI TMS PC12 N/C PB30 U N/C PE20 PE23 MII-TX-EN PE16 PE29 PE24 PC13 MII-CRS PC10 PB23 PB25 TRST GND PA14 N/C Figure 68. Pinout of the PBGA Package—JEDEC Standard Table 36 contains a list of the MPC875/870 input and output signals and shows multiplexing and pin assignments. Table 36. Pin Assignments—JEDEC Standard Name A[0:31] Pin Number Type R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16, Bidirectional L15, M17, K14, L16, L17, K17, G17, K15, J16, J15, G16, J14, H17, Three-state (3.3 V only) H16, G15, K16, H14, J17, H15, F17 F16 Bidirectional Three-state (3.3 V only) TSIZ0 REG MPC875/MPC870 Hardware Specifications, Rev. 3.0 72 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name TSIZ1 RD/WR BURST BDIP GPL_B5 TS TA TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT D[0:31] CR IRQ3 FRZ IRQ6 BR BG BB IRQ0 IRQ1 IRQ7 CS[0:5] CS6 CE1_B CS7 CE2_B G14 D13 B9 C13 C11 C12 B12 B13 C9 E9 Pin Number Type Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Output Bidirectional Active pull-up (3.3 V only) Bidirectional Active pull-up (3.3 V only) Open-drain Bidirectional Active pull-up (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) L5, N3, L3, L2, R2, K2, H3, G2, R3, M3, N2, M2, M4, N4, K5, K3, K4, Bidirectional P3, J2, J3, J4, J5, H2, P2, H4, H5, G5, L4, G3, F2, F3, E2 Three-state (3.3 V only) E10 B10 B11 D10 C10 M6 P5 N5 B14, E11, C14, B15, E13, B16 F12 D15 Input Bidirectional Three-state (3.3 V only) Bidirectional (3.3 V only) Bidirectional (3.3 V only) Bidirectional Active pull-up (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Output Output Output MPC875/MPC870 Hardware Specifications, Rev. 3.0 73 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2–3] UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK TEXP ALE_A CE1_A CE2_A WAIT_A E15 Pin Number Output Type D17 Output D16 Output G13 Output F14, E16, E17, F15 C17 F13 Output Output Output E14, C16 Output D11 E12 D12 D5 C3 E7 C4 D6 D7 G4 B4 B3 B7 C15 D14 D4 Bidirectional (3.3 V only) Bidirectional Output Input (3.3 V only) Input (3.3 V only) Open-drain Open-drain Analog output Analog input (3.3 V only) Output Input (3.3 V only) Output Output Output Output Input (3.3 V only) MPC875/MPC870 Hardware Specifications, Rev. 3.0 74 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 ALE_B DSCK IP_B[0:1] IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG AS PA15 USBRXD PA14 USBOE PA11 RXD4 MII1-TXD0 RMII1-TXD0 PA10 MII1-TXERR TIN4 CLK7 G6 F5 D3 E4 D2 E3 F4 C2 C8 B8, D9 Pin Number Type Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional (3.3 V only) B6 C6 B5 Bidirectional (3.3 V only) Output Bidirectional (3.3 V only) B2 Bidirectional (3.3 V only) E8, C5 D8 C7 P14 U16 R9 Output Output Input (3.3 V only) Bidirectional Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) R12 MPC875/MPC870 Hardware Specifications, Rev. 3.0 75 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name PA7 CLK1 BRGO1 TIN1 PA6 CLK2 TOUT1 PA4 CTS4 MII1-TXD1 RMII-TXD1 PA3 MII1-RXER RMII1-RXER BRGO3 PA2 MII1-RXDV RMII1-CRS_DV TXD4 PA1 MII1-RXD0 RMII1-RXD0 BRGO4 PA0 MII1-RXD1 RMII1-RXD1 TOUT4 PB31 SPISEL MII1 - TXCLK RMII1-REFCLK PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 PB27 I2CSDA BRGO1 PB26 I2CSCL BRGO2 R11 Pin Number Type Bidirectional P11 Bidirectional P7 Bidirectional R5 Bidirectional (5-V tolerant) N6 Bidirectional (5-V tolerant) T4 Bidirectional (5-V tolerant) P6 Bidirectional (5-V tolerant) T5 Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T17 R17 R14 N13 N12 MPC875/MPC870 Hardware Specifications, Rev. 3.0 76 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name PB25 SMTXD1 PB24 SMRXD1 PB23 SDACK1 SMSYN1 PB19 MII1-RXD3 RTS4 PC15 DREQ0 L1ST1 PC13 MII1-TXD3 SDACK1 PC12 MII1-TXD2 TOUT1 PC11 USBRXP PC10 USBRXN TGATE1 PC7 CTS4 L1TSYNCB USBTXP PC6 CD4 L1RSYNCB USBTXN PD8 RXD4 MII-MDC RMII-MDC PE31 CLK8 L1TCLKB MII1-RXCLK PE30 L1RXDB MII1-RXD2 U13 Pin Number Type Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional Bidirectional T12 U12 T11 R15 U9 T15 P12 U11 T10 Bidirectional (5-V tolerant) P10 Bidirectional (5-V tolerant) T3 Bidirectional (5-V tolerant) P9 Bidirectional (Optional: open-drain) R8 Bidirectional (Optional: open-drain) MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 77 Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name PE29 MII2-CRS PE28 TOUT3 MII2-COL PE27 L1RQB MII2-RXERR RMII2-RXERR PE26 L1CLKOB MII2-RXDV RMII2-CRS_DV PE25 RXD4 MII2-RXD3 L1ST2 PE24 SMRXD1 BRGO1 MII2-RXD2 PE23 TXD4 MII2-RXCLK L1ST1 PE22 TOUT2 MII2-RXD1 RMII2-RXD1 SDACK1 PE21 TOUT1 MII2-RXD0 RMII2-RXD0 PE20 MII2-TXER PE19 L1TXDB MII2-TXEN RMII2-TXEN PE18 SMTXD1 MII2-TXD3 U7 R7 Pin Number Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T6 T2 Bidirectional (Optional: open-drain) R4 Bidirectional (Optional: open-drain) U8 Bidirectional (Optional: open-drain) U4 Bidirectional (Optional: open-drain) P4 Bidirectional (Optional: open-drain) T9 Bidirectional (Optional: open-drain) U3 R6 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) M5 Bidirectional (Optional: open-drain) MPC875/MPC870 Hardware Specifications, Rev. 3.0 78 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name PE17 TIN3 CLK5 BRGO3 SMSYN1 MII2-TXD2 PE16 L1RCLKB CLK6 MII2-TXCLK RMII2-REFCLK PE15 TGATE1 MII2-TXD1 RMII2-TXD1 PE14 MII2-TXD0 RMII2-TXD0 TMS TDI DSDI TCK DSCK TRST TDO DSDO MII1_CRS MII_MDIO MII1_TX_EN RMII1_TX_EN MII1_COL VSSSYN VSSSYN1 VDDSYN GND VDDL T8 Pin Number Type Bidirectional (Optional: open-drain) U6 Bidirectional (Optional: open-drain) T7 Bidirectional P8 Bidirectional T14 T13 R13 U14 P13 U10 M13 U5 R10 E5 F6 E6 H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10, L11, U15 F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8, N9, N10, N11 Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Output (5-V tolerant) Input Bidirectional (5-V tolerant) Output (5-V tolerant) Input PLL analog GND PLL analog GND PLL analog VDD Power Power MPC875/MPC870 Hardware Specifications, Rev. 3.0 79 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36. Pin Assignments—JEDEC Standard (continued) Name VDDH N/C Pin Number G7, G8, G9, G10, G11, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7, Power M8, M9, M10, M11, M12 B17, T16, U2, U17 No-connect Type MPC875/MPC870 Hardware Specifications, Rev. 3.0 80 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information 16.2 Mechanical Dimensions of the PBGA Package Figure 69 shows the mechanical dimensions of the PBGA package. NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/870VRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/870ZTXXX. Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 81 Document Revision History 17 Document Revision History Table 37 lists significant changes between revisions of this hardware specification. Table 37. Document Revision History Revision Number 0 0.1 0.2 Date 2/2003 3/2003 5/2003 Initial release. Took out the time-slot assigner and changed the SCC for SCC3 to SCC4. Changed the package drawing, removed all references to Data Parity. Changed the SPI Master Timing Specs. 162 and 164. Added the RMII and USB timing. Added the 80-MHz timing. Made sure the pin types were correct. Changed the Features list to agree with the MPC885. Corrected the signals that had overlines on them. Made corrections on two pins that were typos. Changed the pin descriptions for PD8 and PD9. Changed a few typos. Put back the I2C. Put in the new reset configuration, corrected the USB timing. Changed the pin descriptions per the June 22 spec, removed Utopia from the pin descriptions, changed PADIR, PBDIR, PCDIR and PDDIR to be 0 in the Mandatory Reset Config. Added the reference to USB 2.0 to the Features list and removed 1.1 from USB on the block diagrams. Changed the USB description to full-/low-speed compatible. Added the DSP information in the Features list. Put a new sentence under Mechanical Dimensions. Fixed table formatting. Nontechnical edits. Released to the external web. Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5 Serial Interface AC Electrical Specifications, and removed TDMa from the pin descriptions. Changes 0.3 0.4 0.5 0.6 0.7 5/2003 5/2003 5/2003 5/2003 6/2003 0.8 0.9 1.0 8/2003 8/2003 9/2003 1.1 10/2003 MPC875/MPC870 Hardware Specifications, Rev. 3.0 82 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Document Revision History Table 37. Document Revision History (continued) Revision Number 2.0 Date 12/2003 Changes Changed DBGC in the Mandatory Reset Configuration to X1. Changed the maximum operating frequency to 133 MHz. Put the timing in the 80 MHz column. Put in the orderable part numbers. Rounded the timings to hundredths in the 80 MHz column. Put the pin numbers in footnotes by the maximum currents in Table 6. Changed 22 and 41 in the Timing. Put TBD in the Thermal table. • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values • Added a footnote to Spec 41 specifying that EDM = 1 • Added the thermal numbers to Table 4. • Added RMII1_EN under M1II_EN in Table 36 Pin Assignments • Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the I2C Standard • Put the new part numbers in the Ordering Information Section 3.0 1/07/2004 7/19/2004 MPC875/MPC870 Hardware Specifications, Rev. 3.0 Freescale Semiconductor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 83 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 Japan: Freescale Semiconductor Japan Ltd. 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Learn More: For more information about Freescale Semiconductor products, please visit www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004. MPC875EC Rev. 3.0 07/2004 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE