MC908QC8VDSER

MC68HC908QC16 MC68HC908QC8 MC68HC908QC4 Data Sheet M68HC08 Microcontrollers MC68HC908QC16 Rev. 2 10/2006 freescale.com MC68HC908QC16 MC68HC908QC8 MC68HC908QC4 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 3 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date April, 2006 Revision Level 1.0 Initial release 19.5 5-V DC Electrical Characteristics — Updated values 19.8 3.3-V DC Electrical Characteristics — Updated values May, 2006 1.1 19.11 Oscillator Characteristics — Updated values Figure 19-9. Typical 5-Volt Run Current versus Bus Frequency (25°C) and Figure 19-10. Typical 3.3-Volt Run Current versus Bus Frequency (25°C) — added 1.7 Unused Pin Termination — Added new section 11.2 Unused Pin Termination — Replaced note with new section 19.5 5-V DC Electrical Characteristics — New values for: DC injection current Low-voltage inhibit reset, trip rising voltage October, 2006 2.0 19.8 3.3-V DC Electrical Characteristics — New values for: DC injection current Low-voltage inhibit reset, trip rising voltage 19.12 Supply Current Characteristics — New values for stop mode supply currents at –40 to 125°C 20.3 Package Dimensions — Updated package dimension drawing for the 28-lead TSSOP. Description Page Number(s) N/A 237 240 243 247 24 107 237 240 246 261 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 4 Freescale Semiconductor List of Sections Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 3 Analog-to-Digital Converter (ADC10) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 4 Configuration Registers (CONFIG1 and CONFIG2) . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 5 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Chapter 6 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 7 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Chapter 8 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Chapter 9 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Chapter 10 Oscillator Mode (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Chapter 11 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Chapter 12 Periodic Wakeup Module (PWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 13 Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . . 123 Chapter 14 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Chapter 15 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Chapter 16 Timer Interface Module (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 Chapter 17 Timer Interface Module (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 257 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 5 List of Sections MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 19 19 19 24 24 Chapter 2 Memory 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Memory Emulation Using FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 35 36 36 37 38 39 41 41 42 Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 7 45 45 45 47 48 48 48 48 48 49 50 50 50 50 Table of Contents 3.3.4.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.5 Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 ADC10 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 ADC10 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 ADC10 Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 ADC10 Voltage Reference High Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 ADC10 Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 ADC10 Channel Pins (ADn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 ADC10 Result High Register (ADRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 ADC10 Result Low Register (ADRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 ADC10 Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 51 51 52 52 52 52 52 53 53 53 53 53 54 54 54 56 56 56 Chapter 4 Configuration Registers (CONFIG1 and CONFIG2) 4.1 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 5 Computer Operating Properly (COP) 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.4 5.5 5.6 5.7 5.7.1 5.7.2 5.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 63 64 64 64 64 64 64 64 65 65 65 65 65 65 65 65 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 8 Freescale Semiconductor Chapter 6 Central Processor Unit (CPU) 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 67 68 68 69 69 70 71 71 71 71 71 72 77 Chapter 7 External Interrupt (IRQ) 7.1 7.2 7.3 7.3.1 7.3.2 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 79 81 82 82 82 82 82 82 83 83 83 Chapter 8 Keyboard Interrupt Module (KBI) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1.1 MODEK = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1.2 MODEK = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 85 85 87 87 87 88 88 88 88 88 89 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 9 Table of Contents 8.7 8.7.1 8.8 8.8.1 8.8.2 8.8.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KBI Input Pins (KBI7:KBI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register (KBSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Polarity Register (KBIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 89 89 89 90 91 Chapter 9 Low-Voltage Inhibit (LVI) 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.4 9.5 9.5.1 9.5.2 9.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 93 93 94 94 94 94 95 95 95 95 95 Chapter 10 Oscillator Mode (OSC) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.3.1 Internal Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.3.1.1 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.3.1.2 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.1.3 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.1.4 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.1.5 Bus Clock Times 4 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.1.6 Bus Clock Times 2 (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.2 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.2.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.3.2.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.2.3 External to Internal Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.3 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.4 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.5 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6 OSC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.7.1 Oscillator Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.7.2 Oscillator Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 10 Freescale Semiconductor 10.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.8.1 Oscillator Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 11 Input/Output Ports (PORTS) 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.4 11.4.1 11.4.2 11.4.3 11.5 11.5.1 11.5.2 11.5.3 11.6 11.6.1 11.6.2 11.6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 107 107 108 108 109 110 110 110 111 112 112 112 113 114 114 114 115 Chapter 12 Periodic Wakeup Module (PWU) 12.1 12.2 12.3 12.4 12.5 12.5.1 12.5.2 12.6 12.7 12.8 12.8.1 12.8.2 12.8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Wakeup Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Wakeup Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Wakeup Modulo Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 117 118 118 118 119 119 119 119 119 120 121 Chapter 13 Enhanced Serial Communications Interface (ESCI) Module 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 11 123 123 125 126 126 126 Table of Contents 13.3.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.3 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 ESCI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.1 ESCI Transmit Data (TxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.2 ESCI Receive Data (RxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.1 ESCI Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.2 ESCI Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.3 ESCI Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.4 ESCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.5 ESCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.7 ESCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.8 ESCI Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9.1 ESCI Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9.2 ESCI Arbiter Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9.3 Bit Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9.4 Arbitration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 127 128 128 128 128 128 130 131 131 133 134 134 134 134 135 135 135 135 135 135 136 136 136 138 140 141 143 144 144 145 149 149 150 150 151 Chapter 14 System Integration Module (SIM) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 12 Freescale Semiconductor 153 153 153 155 155 155 155 155 156 157 14.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 158 158 158 158 158 158 159 159 159 159 162 162 163 163 163 163 164 164 164 164 165 166 167 168 Chapter 15 Serial Peripheral Interface (SPI) Module 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3.1 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.5 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.6.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.6.2 Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 169 169 172 172 173 173 173 174 175 177 178 178 178 180 181 182 182 182 182 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 13 Table of Contents 15.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 183 183 183 183 184 184 186 188 Chapter 16 Timer Interface Module (TIM1) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1 TIM1 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6 TIM1 During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.7.1 TIM1 Channel I/O Pins (T1CH3:T1CH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.7.2 TIM1 Clock Pin (T1CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.1 TIM1 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.2 TIM1 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.3 TIM1 Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.4 TIM1 Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.5 TIM1 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 189 189 192 192 192 192 192 193 194 194 195 196 196 196 196 197 197 197 197 197 197 199 200 200 204 Chapter 17 Timer Interface Module (TIM2) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.1 TIM2 Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 14 Freescale Semiconductor 205 205 205 205 207 207 207 208 17.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6 TIM2 During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.7.1 TIM2 Channel I/O Pins (T2CH1:T2CH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.7.2 TIM2 Clock Pin (T2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8.1 TIM2 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8.2 TIM2 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8.3 TIM2 Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8.4 TIM2 Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8.5 TIM2 Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 209 210 210 211 211 211 211 211 212 212 212 212 212 214 215 215 218 Chapter 18 Development Support 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.1.2 TIM1 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 219 219 221 221 221 222 222 222 223 223 223 224 224 224 228 229 229 230 230 230 230 234 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 15 Table of Contents Chapter 19 Electrical Specifications 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.14 19.15 19.16 19.17 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 3.3-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 235 236 236 237 239 240 240 242 243 243 246 248 250 251 254 255 Chapter 20 Ordering Information and Mechanical Specifications 20.1 20.2 20.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 16 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction The MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4 are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4 Table 1-1. Summary of Device Variations Device MC68HC908QC16 MC68HC908QC8 MC68HC908QC4 FLASH Memory Size 16 Kbytes 8 Kbytes 4 Kbytes RAM 512 bytes 384 bytes 384 bytes Pin Count 16, 20, 28 pins 16, 20, 28 pins 16, 20, 28 pins 1.2 Features Features include: • • • • • High-performance M68HC08 CPU core Fully upward-compatible object code with M68HC05 Family 5.0-V and 3.3-V operating voltages (VDD) 8-MHz internal bus operation at 5 V, 4-MHz at 3.3 V Trimmable internal oscillator – Software selectable 1 MHz, 2 MHz, 3.2 MHz, or 6.4 MHz internal bus operation – 8-bit trim capability – ± 25% untrimmed – Trimmable to approximately 0.4%(1) Software selectable crystal oscillator range, 32–100 kHz, 1–8 MHz, and 8–32 MHz Software configurable input clock from either internal or external source Auto wakeup from STOP capability using dedicated internal 32-kHz RC or bus clock source FLASH security(2) On-chip in-application programmable FLASH memory (with internal program/erase voltage generation) • • • • • 1. See 19.11 Oscillator Characteristics for internal oscillator specifications 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 17 General Description • • • • • • Enhanced serial communications interface (ESCI) module Serial peripheral interface (SPI) module 4-channel, 16-bit timer interface (TIM1) module 2-channel, 16-bit timer interface (TIM2) module 10-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) Up to 24 bidirectional input/output (I/O) lines and two input only: – Six shared with keyboard interrupt function – Ten shared with ADC – Four shared with TIM1 – Two shared with TIM2 – Two shared with ESCI – Four shared with SPI – One input only shared with external interrupt (IRQ) – High current sink/source capability on all port pins – Selectable pullups on all ports, selectable on an individual bit basis – Three-state ability on all port pins 6-bit keyboard interrupt with wakeup feature (KBI) – Programmable for rising/falling edge or high/low level detection Low-voltage inhibit (LVI) module features: – Software selectable trip point in CONFIG register System protection features: – Computer operating properly (COP) watchdog – Low-voltage detection with reset – Illegal opcode detection with reset – Illegal address detection with reset External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input pin Master asynchronous reset pin with internal pullup (RST) shared with general-purpose input/output (I/O) pin Memory mapped I/O registers Power saving stop and wait modes MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4 are available in these packages: – 28-pin small outline integrated circuit package (SOIC) – 28-pin thin shrink small outline package (TSSOP) – 20-pin SOIC – 20-pin TSSOP – 16-pin SOIC – 16-pin TSSOP • • • • • • • • MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 18 Freescale Semiconductor MCU Block Diagram Features of the CPU08 include the following: • • • • • • • • • • Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 × 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4. 1.4 Pin Assignments The MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4 are available in 16-pin, 20-pin, and 28-pin packages. Figure 1-2 shows the pin assignment for these packages. 1.5 Pin Functions Table 1-2 provides a description of the pin functions. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 19 General Description PTA0/T1CH0/AD0/KBI0 PTA1/T1CH1/AD1/KBI1 DDRA PTA PTA2/IRQ/KBI2/T1CLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0/SPSCK/AD4 PTB1/MOSI/T2CH1/AD5 PTB2/MISO/T2CH0/AD6 PTB3/SS/T2CLK/AD7 PTB4/RxD/T2CH0/AD8 PTB5/TxD/T2CH1/AD9 PTB6/T1CH2 PTB7/T1CH3 PTC0 DDRC PTC PTC1 PTC2 PTC3 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 LOW-VOLTAGE INHIBIT MC68HC908QC16 16,384 BYTES MC68HC908QC8 8192 BYTES MC68HC908QC4 4096 BYTES USER FLASH 4-CHANNEL 16-BIT TIMER MODULE 2-CHANNEL 16-BIT TIMER MODULE COP MODULE 10-CHANNEL 10-BIT ADC ENHANCED SERIAL COMMUNICATIONS INTERFACE MODULE SERIAL PERIPHERAL INTERFACE CLOCK GENERATOR KEYBOARD INTERRUPT MODULE SINGLE INTERRUPT MODULE BREAK MODULE PERIODIC WAKEUP MODULE MC68HC908QC16 512 BYTES MC68HC908QC8 384 BYTES MC68HC908QC4 384 BYTES USER RAM DDRD PTD DDRB PTB MONITOR ROM VDD POWER SUPPLY VSS All port pins can be configured with internal pullup PTC not available on 16-pin devices (see note in 11.1 Introduction) PTD not available on 16-pin or 20-pin devices (see note in 11.1 Introduction) Figure 1-1. Block Diagram MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 20 Freescale Semiconductor Pin Functions VDD PTB7/T1CH3 PTB6/T1CH2 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTB5/TxD/T2CH1/AD9 PTB4/RxD/T2CH0/AD8 PTA3/RST/KBI3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS PTB0/SPSCK/AD4 PTB1/MOSI/T2CH1/AD5 PTA0/T1CH0/AD0/KBI0 PTA1/T1CH1/AD1/KBI1 PTB2/MISO/T2CH0/AD6 PTB3/SS/T2CLK/AD7 PTA2/IRQ/KBI2/T1CLK PTA0/T1CH0/AD0/KBI0 PTB1/MOSI/T2CH1/AD5 PTB0/SPSCK/AD4 VSS VDD PTB7/T1CH3 PTB6/T1CH2 PTA5/OSC1/AD3/KBI5 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTA1/T1CH1/AD1/KBI1 PTB2/MISO/T2CH0/AD6 PTB3/SS/T2CLK/AD7 PTA2/IRQ/KBI2/T1CLK PTA3/RST/KBI3 PTB4/RxD/T2CH0/AD8 PTB5/TxD/T2CH1/AD9 PTA4/OSC2/AD2/KBI4 16-PIN ASSIGNMENT MC68HC908QCxx SOIC 16-PIN ASSIGNMENT MC68HC908QCxx TSSOP VDD PTB7/T1CH3 PTB6/T1CH2 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTC1 PTC0 PTB5/TxD/T2CH1/AD9 PTB4/RxD/T2CH0/AD8 PTA3/RST/KBI3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VSS PTB0/SPSCK/AD4 PTB1/MOSI/T2CH1/AD5 PTA0/T1CH0/AD0/KBI0 PTC2 PTC3 PTA1/T1CH1/AD1/KBI1 PTB2/MISO/T2CH0/AD6 PTB3/SS/T2CLK/AD7 PTA2/IRQ/KBI2/T1CLK PTC2 PTA0/T1CH0/AD0/KBI0 PTB1/MOSI/T2CH1/AD5 PTB0/SPSCK/AD4 VSS VDD PTB7/T1CH3 PTB6/T1CH2 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PTC3 PTA1/T1CH1/AD1/KBI1 PTB2/MISO/T2CH0/AD6 PTB3/SS/T2CLK/AD7 PTA2/IRQ/KBI2/T1CLK PTA3/RST/KBI3 PTB4/RxD/T2CH0/AD8 PTB5/TxD/T2CH1/AD9 PTC0 PTC1 20-PIN ASSIGNMENT MC68HC908QCxx SOIC 20-PIN ASSIGNMENT MC68HC908QCxx TSSOP VDD PTB7/T1CH3 PTB6/T1CH2 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTC1 PTD3 PTD2 PTD1 PTD0 PTC0 PTB5/TxD/T2CH1/AD9 PTB4/RxD/T2CH0/AD8 PTA3/RST/KBI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS PTB0/SPSCK/AD4 PTB1/MOSI/T2CH1/AD5 PTA0/T1CH0/AD0/KBI0 PTC2 PTD4 PTD5 PTD6 PTD7 PTC3 PTA1/T1CH1/AD1/KBI1 PTB2/MISO/T2CH0/AD6 PTB3/SS/T2CLK/AD7 PTA2/IRQ/KBI2/T1CLK PTD5 PTD4 PTC2 PTA0/T1CH0/AD0/KBI0 PTB1/MOSI/T2CH1/AD5 PTB0/SPSCK/AD4 VSS VDD PTB7/T1CH3 PTB6/T1CH2 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTC1 PTD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PTD6 PTD7 PTC3 PTA1/T1CH1/AD1/KBI1 PTB2/MISO/T2CH0/AD6 PTB3/SS/T2CLK/AD7 PTA2/IRQ/KBI2/T1CLK PTA3/RST/KBI3 PTB4/RxD/T2CH0/AD8 PTB5/TxD/T2CH1/AD9 PTC0 PTD0 PTD1 PTD2 28-PIN ASSIGNMENT MC68HC908QCxx SOIC NOTE: T2CH0 and T2CH1 can be repositioned using TIM2POS in CONFIG2. 28-PIN ASSIGNMENT MC68HC908QCxx TSSOP Figure 1-2. MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4 Pin Assignments MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 21 General Description Table 1-2. Pin Functions Pin Name VDD VSS Power supply Power supply ground PTA0 — General purpose I/O port PTA0 T1CH0 — Timer Channel 0 I/O AD0 — A/D channel 0 input KBI0 — Keyboard interrupt input 0 PTA1 — General purpose I/O port PTA1 T1CH1 — Timer Channel 1 I/O AD1 — A/D channel 1 input KBI1 — Keyboard interrupt input 1 PTA2 — General purpose input-only port PTA2 IRQ — External interrupt with programmable pullup and Schmitt trigger input KBI2 — Keyboard interrupt input 2 T1CLK — TIM1 timer clock input PTA3 — General purpose I/O port PTA3 RST — Reset input, active low with internal pullup and Schmitt trigger KBI3 — Keyboard interrupt input 3 PTA4 — General purpose I/O port PTA4 OSC2 —XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) AD2 — A/D channel 2 input KBI4 — Keyboard interrupt input 4 PTA5 — General purpose I/O port PTA5 OSC1 — XTAL, RC, or external oscillator input AD3 — A/D channel 3 input KBI5 — Keyboard interrupt input 5 PTB0 — General-purpose I/O port PTB0 SPSCK— SPI serial clock AD4 — A/D channel 4 input PTB1 — General-purpose I/O port MOSI — SPI data transmitted PTB1 T2CH1(1) — TIM2 channel 1 AD5 — A/D channel 5 input Description Input/Output Power Power Input/Output Input/Output Input Input Input/Output Input/Output Input Input Input Input Input Input Input/Output Input Input Input/Output Output Output Input Input Input/Output Input Input Input Input/Output Input/Output Input Input/Output Input/Output Input/Output Input — Continued on next page MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 22 Freescale Semiconductor Pin Functions Table 1-2. Pin Functions (Continued) Pin Name PTB2 — General-purpose I/O port MISO — SPI data received PTB2 T2CH0(1) — TIM2 channel 0 AD6 — A/D channel 6 input PTB3 — General-purpose I/O port PTB3 SS — SPI slave select T2CLK — TIM2 timer clock input AD7 — A/D channel 7 input PTB4 — General-purpose I/O port RxD — ESCI receive data I/O PTB4 T2CH0 (1) Description Input/Output Input/Output Input/Output Input/Output Input Input/Output Input Input Input Input/Output Input Input/Output Input Input/Output Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output — TIM2 channel 0 AD8 — A/D channel 8 input PTB5 — General-purpose I/O port TxD — ESCI transport data I/O PTB5 T2CH1(1) — TIM2 channel 1 AD9 — A/D channel 9 input PTB6 PTB6 — General-purpose I/O port T1CH2 — Timer channel 2 I/O PTB7 — General-purpose I/O port T1CH3 — Timer channel 3 I/O PTB7 PTC0–PTC2(2) General-purpose I/O port PTC3(2) General-purpose input port PTD0–PTD7(3) General-purpose I/O port 1. T2CH0 and T2CH1 can be repositioned using TIM2POS in CONFIG2. 2. Pins not available on 16-pin devices (see note in 11.1 Introduction). 3. Pins not available on 16-pin or 20-pin devices (see note in 11.1 Introduction). MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 23 General Description 1.6 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE Upon reset all pins come up as input ports regardless of the priority table. Table 1-3. Function Priority in Shared Pins Pin Name PTA0(1) PTA1(1) PTA2 PTA3 PTA4(1) PTA5(1) PTB0(1) PTB1 (1) Highest-to-Lowest Priority Sequence AD0 → T1CH0 → KBI0 → PTA0 AD1 → T1CH1 → KBI1 → PTA1 IRQ → T1CLK → KBI2 → PTA2 RST → KBI3 → PTA3 OSC2 → AD2 → KBI4 → PTA4 OSC1 → AD3 → KBI5 → PTA5 AD4 → SPSCK → PTB0 AD5 → MOSI → T2CH1(2) → PTB1 AD6 → MISO → T2CH0(2) → PTB2 AD7 → SS → T2CLK → PTB3 AD8 → RxD → T2CH0(2) → PTB4 AD9 → TxD → T2CH1(2) → PTB5 T1CH2 → PTB6 T1CH3 → PTB7 PTCx PTDx PTB2(1) PTB3(1) PTB4 (1) PTB5(1) PTB6 PTB7 PTCx PTDx 1. When a pin is to be used as an ADC pin, the I/O port function should be left as an input and all other shared modules should be disabled. The ADC does not override additional modules using the pin. 2. T2CH0 and T2CH1 can be repositioned using TIM2POS in CONFIG2 (see Figure 2-2. Control, Status, and Data Registers). 1.7 Unused Pin Termination Input pins and I/O port pins that are not used in the application must be terminated. This prevents excess current caused by floating inputs, and enhances immunity during noise or transient events. Termination methods include: 1. Configuring unused pins as outputs and driving high or low; 2. Configuring unused pins as inputs and enabling internal pull-ups; 3. Configuring unused pins as inputs and using external pull-up or pull-down resistors. Never connect unused pins directly to VDD or VSS. Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method 1 or 2 above are appropriate. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 24 Freescale Semiconductor Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map is shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1, unimplemented locations are shaded. 2.3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1, reserved locations are marked with the word reserved or with the letter R. 2.4 Direct Page Registers Figure 2-2 shows the memory mapped registers. Registers with addresses between $0000 and $00FF are considered direct page registers and all instructions including those with direct page addressing modes can access them. Registers between $0100 and $FFFF require non-direct page addressing modes. See Chapter 6 Central Processor Unit (CPU) for more information on addressing modes. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 25 Memory $0000 ↓ $003F $0040 ↓ $023F $0240 ↓ $024F $0250 ↓ $27FF $2800 ↓ $2A1F $2A20 ↓ $2F7D $2F7E ↓ $2FFF $3000 ↓ $BDFF $BE00 ↓ $FDFF $FE00 ↓ $FE1F $FE20 ↓ $FF7D $FF7E ↓ $FFAF $FFB0 ↓ $FFBD $FFBE ↓ $FFC1 $FFC2 ↓ $FFCF $FFD0 ↓ $FFFF FLASH 14 BYTES USER VECTORS 48 BYTES MC68HC908QC16 Memory Map MC68HC908QC8 Memory Map MC68HC908QC4 Memory Map MISCELLANEOUS REGISTERS MISCELLANEOUS REGISTERS 32 BYTES MONITOR ROM 350 BYTES UNIMPLEMENTED 50 BYTES FLASH 14 BYTES FLASH MEMORY 8192 BYTES FLASH MEMORY 16,384 BYTES DIRECT PAGE REGISTERS 64 BYTES RAM 512 BYTES REGISTERS 16 BYTES UNIMPLEMENTED 9648 BYTES AUXILIARY ROM 544 BYTES UNIMPLEMENTED 1374 BYTES AUXILIARY ROM 130 BYTES UNIMPLEMENTED 36,352 BYTES RESERVED 8192 BYTES $BE00 ↓ $DDFF $DE00 ↓ $FDFF FLASH MEMORY 4096 BYTES $BE00 RESERVED 12,288 BYTES ↓ $EDFF $EE00 ↓ $FDFF RAM 384 BYTES RESERVED 128 BYTES $0040 ↓ $01BF $01C0 ↓ $023F RAM 384 BYTES RESERVED 128 BYTES $0040 ↓ $01BF $01C0 ↓ $023F Figure 2-1. Memory Map MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 26 Freescale Semiconductor Direct Page Registers Addr. $0000 Register Name Port A Data Register Read: (PTA) Write: See page 108. Reset: Port B Data Register Read: (PTB) Write: See page 110. Reset: Port C Data Register (PTC) Write: See page 112. Reset: Port D Data Register Read: (PTD) Write: See page 114. Reset: Data Direction Register A Read: (DDRA) Write: See page 108. Reset: Data Direction Register B Read: (DDRB) Write: See page 110. Reset: Data Direction Register C (DDRC) Write: See page 112. Reset: Data Direction Register D Read: (DDRD) Write: See page 114. Reset: Reserved Read: Read: Bit 7 0 6 R 0 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0 Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 $0001 Unaffected by reset 0 0 0 0 PTC3 PTC2 PTC1 PTC0 $0002 Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 $0003 Unaffected by reset 0 0 DDRB7 0 0 0 DDRD7 0 0 0 DDRB6 0 0 0 DDRD6 0 DDRA5 0 DDRB5 0 0 0 DDRD5 0 DDRA4 0 DDRB4 0 0 0 DDRD4 0 DDRA3 0 DDRB3 0 0 0 DDRD3 0 0 0 DDRB2 0 DDRC2 0 DDRD2 0 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 $0004 $0005 $0006 $0007 $0008 $0009 Port C Input Pullup Enable Read: Register (PTCPUE) Write: See page 113. Reset: Read: 0 0 0 0 PTDPUE6 0 0 0 PTBPUE6 0 = Unimplemented 0 0 PTDPUE5 0 PTAPUE5 0 PTBPUE5 0 0 0 PTDPUE4 0 PTAPUE4 0 PTBPUE4 0 R PTCPUE3 0 PTDPUE3 0 PTAPUE3 0 PTBPUE3 0 = Reserved PTCPUE2 0 PTDPUE2 0 PTAPUE2 0 PTBPUE2 0 PTCPUE1 0 PTDPUE1 0 PTAPUE1 0 PTBPUE1 0 PTCPUE0 0 PTDPUE0 0 PTAPUE0 0 PTBPUE0 0 $000A Port D Input Pullup Enable PTDPUE7 Register (PTDPUE) Write: See page 115. Reset: 0 Port A Input Pullup Enable Read: OSC2EN Register (PTAPUE) Write: See page 109. Reset: 0 Port B Input Pullup Enable Read: PTBPUE7 Register (PTBPUE) Write: See page 111. Reset: 0 $000B $000C U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 27 Memory Addr. $000D Register Name SPI Control Register (SPCR) Write: See page 185. Reset: SPI Status and Control Read: Register (SPSCR) Write: See page 186. Reset: SPI Data Register Read: (SPDR) Write: See page 188. Reset: ESCI Control Register 1 Read: (SCC1) Write: See page 136. Reset: ESCI Control Register 2 (SCC2) Write: See page 138. Reset: ESCI Control Register 3 Read: (SCC3) Write: See page 141. Reset: ESCI Status Register 1 Read: (SCS1) Write: See page 141. Reset: ESCI Status Register 2 Read: (SCS2) Write: See page 143. Reset: ESCI Data Register (SCDR) Write: See page 144. Reset: Read: Read: Read: Bit 7 SPRIE 0 SPRF 0 R7 T7 6 R 0 ERRIE 0 R6 T6 5 SPMSTR 1 OVRF 0 R5 T5 4 CPOL 0 MODF 0 R4 T4 3 CPHA 1 SPTE 1 R3 T3 2 SPWOM 0 MODFEN 0 R2 T2 1 SPE 0 SPR1 0 R1 T1 Bit 0 SPTIE 0 SPR0 0 R0 T0 $000E $000F Unaffected by reset LOOPS 0 SCTIE 0 R8 U SCTE 1 0 0 R7 T7 ENSCI 0 TCIE 0 T8 0 TC 1 0 0 R6 T6 TXINV 0 SCRIE 0 R 0 SCRF 0 0 0 R5 T5 M 0 ILIE 0 R 0 IDLE 0 0 0 R4 T4 WAKE 0 TE 0 ORIE 0 OR 0 0 0 R3 T3 ILTY 0 RE 0 NEIE 0 NF 0 0 0 R2 T2 PEN 0 RWU 0 FEIE 0 FE 0 BKF 0 R1 T1 PTY 0 SBK 0 PEIE 0 PE 0 RPF 0 R0 T0 $0010 $0011 $0012 $0013 $0014 $0015 Unaffected by reset LINT 0 PDS2 0 AM1 0 LINR 0 PDS1 0 R 0 = Unimplemented SCP1 0 PDS0 0 AM0 0 SCP0 0 PSSB4 0 ACLK 0 R R 0 PSSB3 0 AFIN 0 = Reserved SCR2 0 PSSB2 0 ARUN 0 U = Unaffected SCR1 0 PSSB1 0 AROVFL 0 SCR0 0 PSSB0 0 ARD8 0 $0016 ESCI Baud Rate Register Read: (SCBR) Write: See page 144. Reset: ESCI Prescaler Register Read: (SCPSC) Write: See page 146. Reset: ESCI Arbiter Control Read: Register (SCIACTL) Write: See page 149. Reset: $0017 $0018 Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 28 Freescale Semiconductor Direct Page Registers Addr. $0019 Register Name ESCI Arbiter Data Register (SCIADAT) Write: See page 150. Reset: Keyboard Status and Read: Control Register (KBSCR) Write: See page 90. Reset: Keyboard Interrupt Read: Enable Register (KBIER) Write: See page 90. Reset: Keyboard Interrupt Polarity Read: Register (KBIPR) Write: See page 91. Reset: IRQ Status and Control Register (INTSCR) Write: See page 83. Reset: Configuration Register 2 Read: (CONFIG2)(1) Write: See page 59. Reset: Read: Read: Bit 7 ARD7 0 0 0 0 0 0 0 0 0 IRQPUD 0 6 ARD6 0 0 0 R 0 0 0 0 0 IRQEN 0 5 ARD5 0 0 0 KBIE5 0 KBIP5 0 0 0 0 0 4 ARD4 0 0 0 KBIE4 0 KBIP4 0 0 0 0 0 3 ARD3 0 KEYF 0 KBIE3 0 KBIP3 0 IRQF 0 2 ARD2 0 0 ACKK 0 KBIE2 0 KBIP2 0 0 ACK 0 1 ARD1 0 IMASKK 0 KBIE1 0 KBIP1 0 IMASK 0 OSCENINSTOP 0 Bit 0 ARD0 0 MODEK 0 KBIE0 0 KBIP0 0 MODE 0 RSTEN 0(2) $001A $001B $001C $001D $001E TIM2POS ESCIBDSRC 0 0 1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only. Configuration Register 1 Read: (CONFIG1)(1) Write: See page 60. Reset: $001F COPRS 0 LVISTOP 0 LVIRSTD 0 LVIPWRD LVITRIP 0(2) SSREC 0 STOP 0 COPD 0 0 1. One-time writable register after each reset. 2. LVI5OR3 reset to 0 by a power-on reset (POR) only. TIM1 Status and Control Read: Register (T1SC) Write: See page 198. Reset: TIM1 Counter Register Read: High (T1CNTH) Write: See page 199. Reset: TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 0 TRST 0 Bit 12 0 Bit 4 0 Bit 12 1 R 0 Bit 11 0 Bit 3 0 Bit 11 1 = Reserved 0 $0020 TOIE 0 Bit 14 0 Bit 6 0 Bit 14 1 TSTOP 1 Bit 13 0 Bit 5 0 Bit 13 1 PS2 0 Bit 10 0 Bit 2 0 Bit 10 1 PS1 0 Bit 9 0 Bit 1 0 Bit 9 1 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 $0021 TIM1 Counter Register Low Read: $0022 (T1CNTL) Write: See page 199. Reset: $0023 TIM1 Counter Modulo Register High (T1MODH) Write: See page 200. Reset: Read: = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 29 Memory Addr. $0024 Register Name TIM1 Counter Modulo Register Low (T1MODL) Write: See page 200. Reset: TIM1 Channel 0 Status and Read: Control Register (T1SC0) Write: See page 201. Reset: TIM1 Channel 0 Read: Register High (T1CH0H) Write: See page 204. Reset: TIM1 Channel 0 Read: Register Low (T1CH0L) Write: See page 204. Reset: TIM1 Channel 1 Status and Control Register (T1SC1) Write: See page 198. Reset: TIM1 Channel 1 Read: Register High (T1CH1H) Write: See page 204. Reset: TIM1 Channel 1 Read: Register Low (T1CH1L) Write: See page 204. Reset: Reserved Read: Read: Bit 7 Bit 7 1 CH0F 0 0 Bit 15 6 Bit 6 1 CH0IE 0 Bit 14 5 Bit 5 1 MS0B 0 Bit 13 4 Bit 4 1 MS0A 0 Bit 12 3 Bit 3 1 ELS0B 0 Bit 11 2 Bit 2 1 ELS0A 0 Bit 10 1 Bit 1 1 TOV0 0 Bit 9 Bit 0 Bit 0 1 CH0MAX 0 Bit 8 $0025 $0026 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0027 Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 Bit 14 0 0 Bit 13 MS1A 0 Bit 12 ELS1B 0 Bit 11 ELS1A 0 Bit 10 TOV1 0 Bit 9 CH1MAX 0 Bit 8 $0028 $0029 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $002A $002B ↓ $002F Indeterminate after reset TIM1 Channel 2 Status and Read: $0030 Control Register (T1SC2) Write: See page 201. Reset: $0031 TIM1 Channel 2 Register High (T1CH2H) Write: See page 204. Reset: TIM1 Channel 2 Read: Register Low (T1CH2L) Write: See page 204. Reset: Read: CH2F 0 0 Bit 15 CH2IE 0 Bit 14 0 0 Bit 13 MS2A 0 Bit 12 ELS2B 0 Bit 11 ELS2A 0 Bit 10 TOV2 0 Bit 9 CH2MAX 0 Bit 8 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0032 Indeterminate after reset CH3F 0 0 CH3IE 0 = Unimplemented 0 0 MS3A 0 R ELS3B 0 = Reserved ELS3A 0 U = Unaffected TOV3 0 CH3MAX 0 TIM1 Channel 3 Status and Read: $0033 Control Register (T1SC3) Write: See page 201. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 30 Freescale Semiconductor Direct Page Registers Addr. $0034 Register Name TIM1 Channel 3 Register High (T1CH3H) Write: See page 204. Reset: TIM1 Channel 3 Read: Register Low (T1CH3L) Write: See page 204. Reset: Read: Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0035 Indeterminate after reset ICFS1 0 ICFS0 0 ECFS1 0 ECFS0 0 ECGON 0 ECGST 0 $0036 Oscillator Status and Read: OSCOPT1 OSCOPT0 Control Register (OSCSC) Write: See page 104. Reset: 0 0 Reserved $0037 $0038 Oscillator Trim Register (OSCTRIM) See page 105. Read: Write: Reset: TRIM7 1 TRIM6 0 TRIM5 0 TRIM4 0 TRIM3 0 TRIM2 0 TRIM1 0 TRIM0 0 $0039 ↓ $003B Reserved $003C ADC10 Status and Control Read: Register (ADSCR) Write: See page 54. Reset: ADC10 Data Register High Read: (ADRH) Write: See page 56. Reset: ADC10 Data Register Low Read: (ADRL) Write: See page 56. Reset: ADC10 Clock Register Read: (ADCLK) Write: See page 56. Reset: TIM2 Status and Control Register (T2SC) Write: See page 213. Reset: TIM2 Counter Register High Read: (T2CNTH) Write: See page 214. Reset: Read: COCO 0 0 R 0 AD7 R 0 ADLPC 0 TOF 0 0 Bit 15 0 AIEN 0 0 R 0 AD6 R 0 ADIV1 0 TOIE 0 Bit 14 0 ADCO 0 0 R 0 AD5 R 0 ADIV0 0 TSTOP 1 Bit 13 0 ADCH4 1 0 R 0 AD4 R 0 ADICLK 0 0 TRST 0 Bit 12 0 R ADCH3 1 0 R 0 AD3 R 0 MODE1 0 0 0 Bit 11 0 = Reserved ADCH2 1 0 R 0 AD2 R 0 MODE0 0 PS2 0 Bit 10 0 ADCH1 1 AD9 R 0 AD1 R 0 ADLSMP 0 PS1 0 Bit 9 0 ADCH0 1 AD8 R 0 AD0 R 0 ADACKEN 0 PS0 0 Bit 8 0 $003D $003E $003F $0240 $0241 = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 31 Memory Addr. Register Name Read: Bit 7 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 6 Bit 6 0 Bit 14 1 Bit 6 1 CH0IE 0 Bit 14 5 Bit 5 0 Bit 13 1 Bit 5 1 MS0B 0 Bit 13 4 Bit 4 0 Bit 12 1 Bit 4 1 MS0A 0 Bit 12 3 Bit 3 0 Bit 11 1 Bit 3 1 ELS0B 0 Bit 11 2 Bit 2 0 Bit 10 1 Bit 2 1 ELS0A 0 Bit 10 1 Bit 1 0 Bit 9 1 Bit 1 1 TOV0 0 Bit 9 Bit 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 TIM2 Counter Register Low $0242 (T2CNTL) Write: See page 214. Reset: $0243 TIM2 Counter Modulo Read: Register High (T2MODH) Write: See page 215. Reset: TIM2 Counter Modulo Read: Register Low (T2MODL) Write: See page 215. Reset: $0244 TIM2 Channel 0 Status and Read: $0245 Control Register (T2SC0) Write: See page 215. Reset: $0246 TIM2 Channel 0 Register High (T2CH0H) Write: See page 218. Reset: TIM2 Channel 0 Register Read: Low (T2CH0L) Write: See page 218. Reset: Read: Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0247 Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 Bit 14 0 0 Bit 13 MS1A 0 Bit 12 ELS1B 0 Bit 11 ELS1A 0 Bit 10 TOV1 0 Bit 9 CH1MAX 0 Bit 8 TIM2 Channel 1 Status and Read: $0248 Control Register (T2SC1) Write: See page 215. Reset: $0249 TIM2 Channel 1 Register Read: High (T2CH1H) Write: See page 218. Reset: TIM2 Channel 1 Register Low (T2CH1L) Write: See page 218. Reset: Reserved Read: Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $024A Indeterminate after reset $024B $024C Periodic Wakeup Status Read: and Control Register Write: (PWUSC) See page 119. Reset: 0 0 PWUON 0 0 0 Bit 5 0 PWUCLKSEL 0 0 0 Bit 4 0 R PWUF 0 PWUACK PWUIE 0 PS1 0 Bit 1 0 SMODE 0 PS0 0 Bit 0 0 0 0 0 Bit 7 0 0 0 0 Bit 6 0 = Unimplemented 0 PS3 0 Bit 3 0 = Reserved 0 PS2 0 Bit 2 0 U = Unaffected Periodic Wakeup Prescaler Read: $024D Register (PWUP) Write: See page 120. Reset: $024E Periodic Wakeup Modulo Read: Register (PWUMOD) Write: See page 121. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 32 Freescale Semiconductor Direct Page Registers Addr. $024F Register Name Reserved Bit 7 6 5 4 3 2 1 Bit 0 $FE00 Break Status Register Read: (BSR) Write: See page 223. Reset: SIM Reset Status Register (SRSR) See page 167. Read: Write: POR: R R R R R R SBSW 0 0 LVI 0 0 0 R R POR 1 0 0 BCFE 0 IF6 R 0 IF14 R 0 IF22 R 0 PIN 0 0 0 R COP 0 0 0 R ILOP 0 0 0 R ILAD 0 0 0 R MODRST 0 0 0 R 0 0 BDCOP 0 R $FE01 $FE02 Break Auxiliary Register Read: (BRKAR) Write: See page 223. Reset: Break Flag Control Register Read: $FE03 (BFCR) Write: See page 223. Reset: $FE04 Interrupt Status Register 1 (INT1) Write: See page 163. Reset: Read: IF5 R 0 IF13 R 0 IF21 R 0 IF4 R 0 IF12 R 0 IF20 R 0 IF3 R 0 IF11 R 0 IF19 R 0 IF2 R 0 IF10 R 0 IF18 R 0 IF1 R 0 IF9 R 0 IF17 R 0 0 R 0 IF8 R 0 IF16 R 0 0 R 0 IF7 R 0 IF15 R 0 $FE05 Interrupt Status Register 2 Read: (INT2) Write: See page 163. Reset: Interrupt Status Register 3 Read: (INT3) Write: See page 163. Reset: Reserved $FE06 $FE07 $FE08 FLASH Control Register Read: (FLCR) Write: See page 36. Reset: Break Address High Read: Register (BRKH) Write: See page 222. Reset: Break Address low Read: Register (BRKL) Write: See page 222. Reset: Break Status and Control Read: Register (BRKSCR) Write: See page 223. Reset: 0 0 Bit 15 0 Bit 7 0 BRKE 0 0 0 Bit 14 0 Bit 6 0 BRKA 0 = Unimplemented 0 0 Bit 13 0 Bit 5 0 0 0 0 0 Bit 12 0 Bit 4 0 0 0 R HVEN 0 Bit 11 0 Bit 3 0 0 0 = Reserved MASS 0 Bit 10 0 Bit 2 0 0 0 ERASE 0 Bit 9 0 Bit 1 0 0 0 PGM 0 Bit 8 0 Bit 0 0 0 0 $FE09 $FE0A $FE0B U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 33 Memory Addr. $FE0C $FE0D ↓ $FE0F Register Name LVI Status Register (LVISR) Write: See page 95. Reset: Reserved Read: Bit 7 LVIOUT 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 R 0 $FFBE FLASH Block Protect Read: Register (FLBPR) Write: See page 41. Reset: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Unaffected by reset $FFBF Read: $FFC0 Internal Oscillator Trim Value Write: Reset: $FFC1 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 FLASH location with factory programmed trim value. $FFFF COP Control Register Read: (COPCTL) Write: See page 65. Reset: LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 34 Freescale Semiconductor Random-Access Memory (RAM) Table 2-1. Vector Addresses Vector Priority Lowest Vector IF22IF20 IF19 IF18 IF17 IF16 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 — Highest — Address $FFD0$FFD5 $FFD6,7 $FFD8,9 $FFDA,B $FFDC,D $FFDE,F $FFE0,1 $FFE2,3 $FFE4,5 $FFE6,7 $FFE8,9 $FFEA,B — $FFEE,F $FFF0,1 $FFF2,3 $FFF4,5 $FFF6,7 — $FFFA,B $FFFC,D $FFFE,F Vector Unused vectors (available for user program) PWU vector TIM2 overflow vector TIM2 channel 1 vector TIM2 channel 0 vector ADC conversion complete vector Keyboard vector SPI transmit vector SPI receive vector ESCI transmit vector ESCI receive vector ESCI error vector Not used TIM1 Channel 3 vector TIM1 Channel 2 vector TIM1 overflow vector TIM1 Channel 1 vector TIM1 Channel 0 vector Not used IRQ vector SWI vector Reset vector . 2.5 Random-Access Memory (RAM) This MCU includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait or stop mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HC08 resets the stack pointer to $00FF. In the devices that have RAM above $00FF, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM). LDHX TXS #RamLast+1 ;point one past RAM ;SP VDD Vin < VSS Ports Hi-Z leakage current Capacitance Ports (as input)(3) POR rearm voltage POR rise time ramp rate(3)(7) Monitor mode entry voltage (3) Pullup resistors(8) PTA0–PTA5, PTB0–PTB7, PTC3–PTC0, PTD7–PTD0 Pulldown resistors(6) PTA0–PTA5 Low-voltage inhibit reset, trip falling voltage(9) Low-voltage inhibit reset, trip rising voltage Low-voltage inhibit reset/recover hysteresis Symbol Min Typ(2) Max Unit IIC 0 0 0 0 — — — — — — — — — 26 26 4.20 4.30 100 2 –0.2 25 –5 ±1 8 — — 9.1 36 36 4.50 4.60 — mA IIL CIN VPOR RPOR VTST RPU RPD VTRIPF VTRIPR VHYS 0 — 750 0.035 VDD + 2.5 16 16 3.90 4.00 — μA pF mV V/ms V kΩ kΩ V V mV 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. Typical values are for reference only and are not tested in production. 3. Values are based on characterization results, not tested in production. 4. All functional non-supply pins are internally clamped to VSS and VDD. 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 7. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 8. RPU and RPD, is measured at VDD = 5.0 V. Pulldown resistors only available when KBIx is enabled with KBIxPOL =1. 9. Functionality of MCU guaranteed by production test down to minimum LVI trip point. The electrical parameters are only guaranteed within the specified operating voltage range. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 238 Freescale Semiconductor Typical 5-V Output Drive Characteristics 19.6 Typical 5-V Output Drive Characteristics 1.6 1.4 1.2 VDD-VOH (V) 1.0 0.8 0.6 0.4 0.2 0.0 0 -5 -10 -15 IOH (mA) -20 -25 -30 5V PTA 5V PTB,PTC,PTD Figure 19-1. Typical 5-Volt Output High Voltage versus Output High Current (25°C) 1.6 1.4 1.2 1.0 VOL (V) 0.8 0.6 0.4 0.2 0.0 0 5 10 15 IOL (mA) 20 25 30 5V PTA 5V PTB,PTC,PTD Figure 19-2. Typical 5-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 239 Electrical Specifications 19.7 5-V Control Timing Characteristic(1) Internal operating frequency Internal clock period (1/fOP) RST input pulse width low(2) IRQ interrupt pulse width low (edge-triggered)(2) IRQ interrupt pulse period(2) Symbol fOP (fBUS) tCYC tRL tILIH tILIL Min — 125 100 100 Note(3) Max 8 — — — — Unit MHz ns ns ns tCYC 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Values are based on characterization results, not tested in production. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC. tRL RST tILIL tILIH IRQ Figure 19-3. RST and IRQ Timing 19.8 3.3-V DC Electrical Characteristics Characteristic(1) Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only Maximum combined IOH (all I/O pins) Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10.0 mA, PTA0, PTA1, PTA3–PTA5 only Maximum combined IOL (all I/O pins) Input high voltage PTA0–PTA5, PTB0–PTB7, PTC3–PTC0, PTD7–PTD0 Input low voltage PTA0–PTA5, PTB0–PTB7, PTC3–PTC0, PTD7–PTD0 Symbol Min Typ(2) — — — — Max Unit VOH VDD –0.3 VDD –1.0 VDD –0.8 — — — — 50 V IOHT mA VOL — — — — 0.7 x VDD VSS — — — — — — 0.3 1.0 0.8 50 VDD 0.3 x VDD V IOHL VIH VIL mA V V — Continued on next page MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 240 Freescale Semiconductor 3.3-V DC Electrical Characteristics Characteristic(1) Input hysteresis DC injection current(3) (4) (5) (6) Single pin limit Vin > VDD Vin < VSS Total MCU limit, includes sum of all stressed pins Vin > VDD Vin < VSS Ports Hi-Z leakage current Capacitance Ports (as input)(3) POR rearm voltage POR rise time ramp rate(3)(7) Monitor mode entry voltage (3) Pullup resistors(8) PTA0–PTA5, PTB0–PTB7, PTC3–PTC0, PTD7–PTD0 Pulldown resistors(6) PTA0–PTA5 Low-voltage inhibit reset, trip falling voltage(9) Low-voltage inhibit reset, trip rising voltage Low-voltage inhibit reset/recover hysteresis Symbol VHYS Min 0.06 x VDD Typ(2) — Max — Unit V IIC 0 0 0 0 — — — — — — — — — 26 26 2.85 2.93 80 2 –0.2 25 –5 ±1 8 — — VDD + 4.0 36 36 3.0 3.08 — mA IIL CIN VPOR RPOR VTST RPU RPD VTRIPF VTRIPR VHYS 0 — 750 0.035 VDD + 2.5 16 16 2.65 2.73 — μA pF mV V/ms V kΩ kΩ V V mV 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25°C only. 3. Values are based on characterization results, not tested in production. 4. All functional non-supply pins are internally clamped to VSS and VDD. 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 7. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 8. RPU and RPD measured at VDD = 3.3 V. Pulldown resistors only available when KBIx is enabled with KBIxPOL =1. 9. Functionality of MCU guaranteed by production test down to minimum LVI trip point. The electrical parameters are only guaranteed within the specified operating voltage range. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 241 Electrical Specifications 19.9 Typical 3.3-V Output Drive Characteristics 1.2 1.0 0.8 VDD-VOH (V) 0.6 3.3V PTA 3.3V PTB,PTC,PTD 0.4 0.2 0.0 0 -5 -10 IOH (mA) -15 -20 -25 Figure 19-4. Typical 3.3-Volt Output High Voltage versus Output High Current (25°C) 1.2 1.0 0.8 3.3V PTA VOL (V) 0.6 3.3V PTB,PTC,PTD 0.4 0.2 0.0 0 5 10 IOL (mA) 15 20 25 Figure 19-5. Typical 3.3-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 242 Freescale Semiconductor 3.3-V Control Timing 19.10 3.3-V Control Timing Characteristic(1) Internal operating frequency Internal clock period (1/fOP) RST input pulse width low(2) IRQ interrupt pulse width low (edge-triggered)(2) IRQ interrupt pulse period(2) Symbol fOP (fBus) tCYC tRL tILIH tILIL Min — 250 200 200 Note(3) Max 4 — — — — Unit MHz ns ns ns tCYC 1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Values are based on characterization results, not tested in production. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC. tRL RST tILIL tILIH IRQ Figure 19-6. RST and IRQ Timing 19.11 Oscillator Characteristics Characteristic Internal oscillator frequency(1) ICFS1:ICFS0 = 00 ICFS1:ICFS0 = 01 ICFS1:ICFS0 = 10 ICFS1:ICFS0 = 11 (not allowed if VDD < 4.5 V) Trim accuracy(2)(3) Deviation from trimmed Internal 4, 8, 12.8, 25.6MHz, VDD ± 10%, 0 to 70°C 4, 8, 12.8, 25.6MHz, VDD ± 10%, –40 to 125°C External RC oscillator frequency, RCCLK(1) (3) VDD ≥ 4.5 V VDD < 4.5 V External clock reference frequency (1) (5) (6) VDD ≥ 4.5 V VDD ≥ 3.0 V oscillator(3)(4) Symbol Min — — — — — — — Typ 4 8 12.8 25.6 ± 0.4 ±2 — Max — — — — — — ±5 12 8.4 Unit fINTCLK MHz ΔTRIM_ACC ΔINT_TRIM % % fRCCLK 2 2 — — MHz fOSCXCLK dc dc — — 32 16 MHz — Continued on next page MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 243 Electrical Specifications Characteristic RC oscillator external resistor VDD = 5 V VDD = 3.3 V Crystal frequency, XTALCLK (1) (7) (8) ECFS1:ECFS0 = 00 (VDD ≥ 4.5 V) ECFS1:ECFS0 = 00 ECFS1:ECFS0 = 01 ECFS1:ECFS0 = 10 ECFS1:ECFS0 = 00(9) (fOSCXCLK: 8–32 MHz) Feedback bias resistor Crystal load capacitance(10) Crystal capacitors(10) ECFS1:ECFS0 = 01(9) (fOSCXCLK: 1–8 MHz) Crystal series damping resistor fOSCXCLK = 1 MHz fOSCXCLK = 4 MHz fOXCSCLK = 8 MHz Feedback bias resistor Crystal load capacitance(10) Crystal capacitors(10) ECFS1:ECFS0 = 10(9) (fOSCXCLK: 30–100 kHz) Feedback bias resistor Crystal load capacitance(10) Crystal capacitors(10) PWU module Internal RC oscillator frequency Symbol REXT Min Typ See Figure 19-7 See Figure 19-8 8 8 1 30 — — — — 32 16 8 100 Max Unit — fOSCXCLK MHz MHz MHz kHz MΩ pF pF RB CL C1, C2 — — — 1 20 (2 x CL) – 5pF — — — RS — — — — — — 20 10 0 5 18 (2 x CL) –10pF — — — — — — RB CL C1, C2 kΩ kΩ kΩ MΩ pF pF RB CL C1, C2 fINTRC — — — — 10 12.5 (2 x CL) –10 32 — — — — MΩ pF pF kHz 1. Bus frequency, fOP, is oscillator frequency divided by 4. 2. Factory trimmed to provided 12.8MHz accuracy requirement (± 5%, @ 25°C and VDD = 5.0 V) for forced monitor mode communication. User should trim in-circuit to obtain the most accurate internal oscillator frequency for his application. 3. Values are based on characterization results, not tested in production. 4. Deviation values assumes trimming in target application @25°C and midpoint of voltage range, for example 5.0 V for 5 V ± 10% operation. 5. No more than 10% duty cycle deviation from 50%. 6. When external oscillator clock is greater than 1 MHz, ECFS1:ECFS0 must be 00 or 01. 7. Use fundamental mode only, do not use overtone crystals or overtone ceramic resonators. 8. Due to variations in electrical properties of external components such as, ESR and Load Capacitance, operation above 16 MHz is not guaranteed for all crystals or ceramic resonators. Operation above 16 MHz requires that a Negative Resistance Margin (NRM) characterization and component optimization be performed by the crystal or ceramic resonator vendor for every different type of crystal or ceramic resonator which will be used. This characterization and optimization must be performed at the extremes of voltage and temperature which will be applied to the microcontroller in the application. The NRM must meet or exceed 10x the maximum ESR of the crystal or ceramic resonator for acceptable performance. 9. Do not use damping resistor when ECFS1:ECFS0 = 00 or 10. 10. Consult crystal vendor data sheet. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 244 Freescale Semiconductor Oscillator Characteristics 14 5 V 25°C 12 RC FREQUENCY, f RCCLK (MHz) 10 8 6 4 2 0 0 10 20 30 R EXT (k Ω) 40 50 60 Figure 19-7. RC versus Frequency (5 Volts @ 25°C) 12 3.3V 25 oC 10 RC FREQUENCY,RCCLK (MHz) f 8 6 4 2 0 0 10 20 30 Rext ( k ohms) 40 50 60 Figure 19-8. RC versus Frequency (3.3 Volts @ 25°C) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 245 Electrical Specifications 19.12 Supply Current Characteristics Characteristic(1) Run mode VDD supply current(3) Wait mode VDD supply current(4) Stop mode VDD supply current(5) –40 to 85°C –40 to 105°C –40 to 125°C 25°C with PWU enabled Incremental current with LVI enabled at 25°C Stop mode VDD supply current(5) –40 to 85°C –40 to 105°C –40 to 125°C 25°C with PWU enabled Incremental current with LVI enabled at 25°C Voltage 5.0 3.3 5.0 3.3 Bus Frequency (MHz) 3.2 3.2 3.2 3.2 Symbol Typ(2) 5.0 2.6 1.8 1.2 0.40 — — 12 125 SIDD 0.23 — — 2 100 1.5 2.0 5.0 — — Max 8.5 4.5 3.3 2.2 1.5 2.0 6.5 — — Unit RIDD WIDD mA mA 5.0 μA 3.3 μA 1. VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurement at 25°C only. Typical values are for reference only and are not tested in production. 3. Run (operating) IDD measured using trimmed internal oscillator, ADC off, all modules enabled. All pins configured as inputs and tied to 0.2 V from rail. 4. Wait IDD measured using trimmed internal oscillator, ADC off, all modules enabled. All pins configured as inputs and tied to 0.2 V from rail. 5. Stop IDD measured with all pins configured as inputs and tied to 0.2 V from rail. On the 8-pin versions, port B is configured as inputs with pullups enabled. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 246 Freescale Semiconductor Supply Current Characteristics 12 10 8 Internal Oscillator No A/D Serial IDD (mA) 6 4 2 0 0 1 2 3 4 5 6 7 BUS FREQUENCY (MHz) Internal Oscillator A/D Serial Crystal No A/D Serial Crystal A/D Serial Figure 19-9. Typical 5-Volt Run Current versus Bus Frequency (25°C) 5 4 IDD (mA) 3 Internal Oscillator No A/D Serial Internal Oscillator A/D Serial Crystal No A/D Serial 2 Crystal A/D Serial 1 0 0 1 2 BUS FREQUENCY (MHz) 3 4 Figure 19-10. Typical 3.3-Volt Run Current versus Bus Frequency (25°C) MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 247 Electrical Specifications 19.13 ADC10 Characteristics Characteristic Supply voltage Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 ADC internal clock Low power (ADLPC = 1) Conversion time(4) 10-bit Mode Conversion time(4) 8-bit Mode Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) Short sample (ADLSMP = 0) Sample time Long sample (ADLSMP = 1) Input voltage Input capacitance Input impedance Analog source impedance 10-bit mode Ideal resolution (1 LSB) 8-bit mode 10-bit mode Total unadjusted error 8-bit mode ETUE RES 7.031 0 0 20 ±1.5 ±0.7 21.48 ±2.5 ±1.0 LSB tADS VADIN CADIN RADIN RAS tADC tADC Conditions Absolute VDD < 3.6 V (3.3 V Typ) VDD < 5.5 V (5.0 V Typ) VDD < 3.6 V (3.3 V Typ) VDD < 5.5 V (5.0 V Typ) VDD < 3.6 V (3.3 V Typ) VDD < 5.5 V (5.0 V Typ) VDD < 3.6 V (3.3 V Typ) VDD < 5.5 V (5.0 V Typ) High speed (ADLPC = 0) fADCK IDD (2) Symbol VDD Min 3.0 — Typ(1) — 55 75 120 175 140 180 340 440 — — 19 39 16 36 4 24 — 7 5 — 5 Max 5.5 — Unit V Comment IDD (2) μA — — — — μA — — — — — 0.40(3) 0.40(3) 19 39 16 36 4 24 VSS — — — 1.758 — — μA — — μA 615 2.00 MHz 1.00 21 41 18 38 4 24 VDD 10 15 10 5.371 mV tADCK cycles tADCK cycles tADCK cycles V pF kΩ kΩ Not tested Not tested External to MCU VREFH/2N Includes quantization tADCK = 1/fADCK IDD (2) IDD(2) — Continued on next page MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 248 Freescale Semiconductor ADC10 Characteristics Characteristic Conditions 10-bit mode DNL Differential non-linearity 8-bit mode 0 Symbol Min 0 Typ(1) ±0.5 ±0.3 Max — LSB — Unit Comment Monotonicity and no-missing-codes guaranteed 10-bit mode Integral non-linearity 8-bit mode 10-bit mode Zero-scale error 8-bit mode 10-bit mode Full-scale error 8-bit mode 10-bit mode Quantization error 8-bit mode 10-bit mode Input leakage error 8-bit mode Bandgap voltage input(3(6) EIL VBG EQ EFS EZS INL 0 0 0 0 0 — — 0 0 1.17 0 ±0.5 ±0.3 ±0.5 ±0.3 ±0.5 ±0.3 — — ±0.2 ±0.1 1.245 — LSB — — LSB — — LSB — ±0.5 ±0.5 ±5 ±1.2 1.32 LSB V LSB VADIN = VDD 8-bit mode is not truncated Pad leakage(5) * RAS VADIN = VSS 1. Typical values assume VDD = 5.0 V, temperature = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. Incremental IDD added to MCU mode current. 3. Values are based on characterization results, not tested in production. 4. Reference the ADC module specification for more information on calculating conversion times. 5. Based on typical input pad leakage current. 6. LVI must be enabled, (LVIPWRD = 0, in CONFIG1). Voltage input to ADCH4:0 = $1A, an ADC conversion on this channel allows user to determine supply voltage. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 249 Electrical Specifications 19.14 5.0-Volt SPI Characteristics Diagram Number(1) Characteristic(2) Operating frequency Master Slave 1 2 3 4 Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(S) tLag(S) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S) fOP/128 dc 2 1 1 1 tCYC –25 1/2 tCYC –25 tCYC –25 1/2 tCYC –25 30 30 30 30 0 0 — fOP/2 fOP 128 — — — 64 tCYC — 64 tCYC — — — — — 40 40 40 MHz MHz tCYC tCYC tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns 5 6 7 8 9 10 — — 0 0 50 50 — — ns ns ns ns 11 1. Numbers refer to dimensions in Figure 19-11 and Figure 19-12. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 250 Freescale Semiconductor 3.3-Volt SPI Characteristics 19.15 3.3-Volt SPI Characteristics Diagram Number(1) Characteristic(2) Operating frequency Master Slave 1 2 3 4 Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(S) tLag(S) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S) fOP/128 DC 2 1 1 1 tCYC –35 1/2 tCYC –35 tCYC –35 1/2 tCYC –35 40 40 40 40 0 0 — fOP/2 fOP 128 — — — 64 tCYC — 64 tCYC — — — — — 50 50 50 MHz MHz tCYC tCYC tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns 5 6 7 8 9 10 — — 0 0 60 60 — — ns ns ns ns 11 1. Numbers refer to dimensions in Figure 19-11 and Figure 19-12. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 251 Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE 5 4 SPSCK OUTPUT CPOL = 1 NOTE 5 4 6 7 LSB IN 10 BITS 6–1 11 MASTER LSB OUT MISO INPUT MSB IN 11 BITS 6–1 MOSI OUTPUT MASTER MSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin. a) SPI Master Timing (CPHA = 0) SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 5 4 NOTE SPSCK OUTPUT CPOL = 1 5 4 6 7 LSB IN 10 BITS 6–1 MASTER LSB OUT NOTE MISO INPUT 10 MOSI OUTPUT MSB IN 11 MASTER MSB OUT BITS 6–1 Note: This last clock edge is generated internally, but is not seen at the SPSCK pin. b) SPI Master Timing (CPHA = 1) Figure 19-11. SPI Master Timing MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 252 Freescale Semiconductor 3.3-Volt SPI Characteristics SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO INPUT SLAVE 6 MOSI OUTPUT MSB IN MSB OUT 7 10 BITS 6–1 BITS 6–1 11 LSB IN SLAVE LSB OUT 11 5 4 9 NOTE 5 4 3 Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO OUTPUT 5 4 10 NOTE SLAVE 6 MOSI INPUT MSB IN MSB OUT 7 10 BITS 6–1 BITS 6–1 11 LSB IN 9 SLAVE LSB OUT 5 4 3 Note: Not defined but normally LSB of character previously transmitted b) SPI Slave Timing (CPHA = 1) Figure 19-12. SPI Slave Timing MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 253 Electrical Specifications 19.16 Timer Interface Module Characteristics Characteristic Timer input capture pulse width(1) Timer input capture period Timer input clock pulse width(1) Symbol tTH, tTL tTLTL tTCL, tTCH Min 2 Note(2) tCYC + 5 Max — — — Unit tCYC tCYC ns 1. Values are based on characterization results, not tested in production. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC. tTLTL tTH INPUT CAPTURE RISING EDGE tTLTL tTL INPUT CAPTURE FALLING EDGE tTLTL tTH INPUT CAPTURE BOTH EDGES tTL tTCH TCLK tTCL Figure 19-13. Timer Input Timing MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 254 Freescale Semiconductor Memory Characteristics 19.17 Memory Characteristics Characteristic RAM data retention voltage (2) FLASH program bus clock frequency FLASH PGM/ERASE supply voltage (VDD) FLASH read bus clock frequency FLASH page erase time FLASH mass erase time FLASH PGM/ERASE to HVEN setup time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program hold time FLASH program time FLASH return to read time FLASH cumulative program HV period FLASH endurance(6) FLASH data retention time(7) Symbol VRDR — VPGM/ERASE fRead(3) tErase tMErase tNVS tNVH tNVHL tPGS tPROG tRCV(4) tHV(5) — — Min 1.3 1 2.7 0 3.6 4 10 5 100 5 30 1 — 10 k 15 Typ(1) — — — — 4 — — — — — — — — 100 k 100 Max — — 5.5 8M 5.5 — — — — — 40 — 4 — — Unit V MHz V Hz ms ms μs μs μs μs μs μs ms Cycles Years 1. Typical values are for reference only and are not tested in production. 2. Values are based on characterization results, not tested in production. 3. fRead is defined as the frequency range for which the FLASH memory can be read. 4. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum. 6. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. 7. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 255 Electrical Specifications MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 256 Freescale Semiconductor Chapter 20 Ordering Information and Mechanical Specifications 20.1 Introduction This section contains order numbers for the MC68HC908QC16, MC68HC908QC8, and MC68HC908QC4. See Table 20-1 and Figure 20-1. 20.2 MC Order Numbers Table 20-1. MC Order Numbers Temp. Range C = –40°C to 85°C Automotive 16 TSSOP S908QC16CDTE(R) S908QC8CDTE 16 SOIC 20 TSSOP S908QC16CDSE S908QC8CDSE S908QC16VDSE S908QC8VDSE S908QC16MDTE M = –40°C to 125°C S908QC8MDTE S908QC16MDSE(R) S908QC8MDSE(R) S908QC4MDSE(R) MC908QC16CDTE MC908QC16CDXE MC908QC16CDSE Consumer and Industrial C = –40°C to 85°C MC908QC8CDTE MC908QC8CDXE MC908QC8CDSE S908QC16MDRE S908QC8 MDRE S908AC4MDRE MC908QC16CDYE MC908QC16CDRE MC908QC16CDZE MC908QC8CDYE MC908QC8CDRE MC908QC4CDRE V = –40°C to 105°C Temperature designators: C = –40°C to +85°C V = –40°C to +105°C M = –40°C to +125°C MC908QC16VDSE MC908QC8VDSE Package designators: DX = 16-pin SOIC DY = 20-pin SOIC DZ = 28-pin SOIC DT = 16-pin TSSOP DS = 20-pin TSSOP DR = 28-pin TSSOP MC908QC16VDRE MC908QC8VDRE MC908QC8CDZE 20 SOIC 28 TSSOP S908QC16CDRE S908QC8CDRE 28 SOIC V = –40°C to 105°C X 908 QCX X XX E R Device Grade: S = Auto MC = Consumer Tape and Reel Family Pb Free Package Designator Temperature Range Figure 20-1. Device Numbering System 20.3 Package Dimensions Refer to the following pages for detailed package dimensions. MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 2 Freescale Semiconductor 257 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 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Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. All rights reserved. MC68HC908QC16 Rev. 2, 10/2006