MC9S08AC48

MC9S08AC60 MC9S08AC48 MC9S08AC32 Data Sheet HCS08 Microcontrollers MC9S08AC60 Rev. 2 3/2008 freescale.com MC9S08AC60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • • • 40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) On-chip in-circuit emulator (ICE) Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Supports both tag and force breakpoints. Support for up to 32 interrupt/reset sources Up to 60 KB of on-chip FLASH memory with security options Up to 2 KB of on-chip RAM Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming using ICG module Optional watchdog computer operating properly (COP) reset with option to run from independent 1kHz internal clock source or bus clock Low-voltage detection with reset or interrupt Illegal opcode detection with reset Cyclic Redundancy Check (CRC) Module to support fast cyclic redundancy checks on memory. Wait plus two stops Peripherals • • ADC — Up to 16-channel, 10-bit analog-to-digital converter with automatic compare function SCI — Two serial communications interface modules with optional 13-bit break. supports LIN 2.0 Protocol and SAE J2602; Master extended break generation; Slave extended break detection SPI — Serial peripheral interface module IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; capable of higher baudrates with reduced loading. 10-bit address extension option. Timers — Up to two 2-channel and one 6-channel 16-bit timer/pulse-width modulator (TPM) module: Selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels KBI — Up to 8-pin keyboard interrupt module CRC - Hardware CRC generation using a 16-bit shift register Up to 54 general-purpose input/output (I/O) pins Software selectable pullups on ports when used as inputs Software selectable slew rate control on ports when used as outputs Software selectable drive strength on ports when used as outputs Master reset pin and power-on reset (POR) Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost 64-pin quad flat package (QFP) 64-pin low-profile quad flat package (LQFP) 48-pin quad flat pack no lead package (QFN) 44-pin low-profile quad flat package (LQFP) 32-pin low-profile quad flat package (LQFP) Development Support • • • • • • • Memory Options • • Clock Source Options Input/Output • • • • • • System Protection • • • • Package Options • • • • • Power-Saving Modes • MC9S08AC60 Series Data Sheet Covers MC9S08AC60 MC9S08AC48 MC9S08AC32 MC9S08AC60 Series Rev. 2 3/2008 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision Number 1 2 Revision Date 2/2008 3/2008 Market Launch Release. Description of Changes Preliminary customer release. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved. MC9S08AC60 Series Data Sheet, Rev. 2 6 Freescale Semiconductor List of Chapters Chapter Title Page Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Appendix A Appendix B Introduction.............................................................................. 19 Pins and Connections ............................................................. 25 Modes of Operation ................................................................. 35 Memory ..................................................................................... 41 Resets, Interrupts, and System Configuration ..................... 65 Parallel Input/Output ............................................................... 83 Central Processor Unit (S08CPUV2) .................................... 107 Cyclic Redundancy Check (S08CRCV1).............................. 127 Analog-to-Digital Converter (S08ADC10V1)........................ 135 Internal Clock Generator (S08ICGV4) .................................. 161 Inter-Integrated Circuit (S08IICV2) ....................................... 189 Keyboard Interrupt (S08KBIV1) ............................................ 209 Serial Communications Interface (S08SCIV4)..................... 215 Serial Peripheral Interface (S08SPIV3) ................................ 235 Timer/PWM (S08TPMV3) ....................................................... 251 Development Support ........................................................... 281 Electrical Characteristics and Timing Specifications ....... 303 Ordering Information and Mechanical Drawings............... 329 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 7 Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 Overview .........................................................................................................................................19 MCU Block Diagrams .....................................................................................................................20 System Clock Distribution ..............................................................................................................22 Chapter 2 Pins and Connections 2.1 2.2 2.3 Introduction .....................................................................................................................................25 Device Pin Assignment ...................................................................................................................25 Recommended System Connections ...............................................................................................29 2.3.1 Power (VDD, VSS, VDDAD, VSSAD) ..................................................................................31 2.3.2 Oscillator (XTAL, EXTAL) ..............................................................................................31 2.3.3 RESET Pin ........................................................................................................................31 2.3.4 Background/Mode Select (BKGD/MS) ............................................................................32 2.3.5 ADC Reference Pins (VREFH, VREFL) ..............................................................................32 2.3.6 External Interrupt Pin (IRQ) .............................................................................................32 2.3.7 General-Purpose I/O and Peripheral Ports ........................................................................33 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................35 Features ...........................................................................................................................................35 Run Mode ........................................................................................................................................35 Active Background Mode ................................................................................................................35 Wait Mode .......................................................................................................................................36 Stop Modes ......................................................................................................................................36 3.6.1 Stop2 Mode .......................................................................................................................37 3.6.2 Stop3 Mode .......................................................................................................................38 3.6.3 Active BDM Enabled in Stop Mode .................................................................................38 3.6.4 LVD Enabled in Stop Mode ..............................................................................................39 3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................39 Chapter 4 Memory 4.1 MC9S08AC60 Series Memory Map ...............................................................................................41 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................43 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 9 Section Number 4.2 4.3 4.4 Title Page 4.5 4.6 Register Addresses and Bit Assignments ........................................................................................44 RAM ................................................................................................................................................50 FLASH ............................................................................................................................................51 4.4.1 Features .............................................................................................................................51 4.4.2 Program and Erase Times .................................................................................................51 4.4.3 Program and Erase Command Execution .........................................................................52 4.4.4 Burst Program Execution ..................................................................................................53 4.4.5 Access Errors ....................................................................................................................55 4.4.6 FLASH Block Protection ..................................................................................................55 4.4.7 Vector Redirection ............................................................................................................56 Security ............................................................................................................................................56 FLASH Registers and Control Bits .................................................................................................57 4.6.1 FLASH Clock Divider Register (FCDIV) ........................................................................57 4.6.2 FLASH Options Register (FOPT and NVOPT) ................................................................59 4.6.3 FLASH Configuration Register (FCNFG) ........................................................................59 4.6.4 FLASH Protection Register (FPROT and NVPROT) .......................................................61 4.6.5 FLASH Status Register (FSTAT) ......................................................................................61 4.6.6 FLASH Command Register (FCMD) ...............................................................................62 Chapter 5 Resets, Interrupts, and System Configuration 5.1 5.2 5.3 5.4 5.5 Introduction .....................................................................................................................................65 Features ...........................................................................................................................................65 MCU Reset ......................................................................................................................................65 Computer Operating Properly (COP) Watchdog .............................................................................66 Interrupts .........................................................................................................................................67 5.5.1 Interrupt Stack Frame .......................................................................................................68 5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................69 5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................69 Low-Voltage Detect (LVD) System ................................................................................................71 5.6.1 Power-On Reset Operation ...............................................................................................71 5.6.2 LVD Reset Operation ........................................................................................................71 5.6.3 LVD Interrupt Operation ...................................................................................................71 5.6.4 Low-Voltage Warning (LVW) ...........................................................................................71 Real-Time Interrupt (RTI) ...............................................................................................................71 MCLK Output .................................................................................................................................72 Reset, Interrupt, and System Control Registers and Control Bits ...................................................72 5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................73 5.9.2 System Reset Status Register (SRS) .................................................................................74 5.9.3 System Background Debug Force Reset Register (SBDFR) ............................................75 5.9.4 System Options Register (SOPT) .....................................................................................75 5.9.5 System MCLK Control Register (SMCLK) .....................................................................76 MC9S08AC60 Series Data Sheet, Rev. 2 10 Freescale Semiconductor 5.6 5.7 5.8 5.9 Section Number 5.9.6 5.9.7 5.9.8 5.9.9 5.9.10 Title Page System Device Identification Register (SDIDH, SDIDL) ................................................77 System Real-Time Interrupt Status and Control Register (SRTISC) ................................78 System Power Management Status and Control 1 Register (SPMSC1) ...........................79 System Power Management Status and Control 2 Register (SPMSC2) ...........................80 System Options Register 2 (SOPT2) ................................................................................81 Chapter 6 Parallel Input/Output 6.1 6.2 6.3 6.4 Introduction .....................................................................................................................................83 Pin Descriptions ..............................................................................................................................83 Parallel I/O Control .........................................................................................................................83 Pin Control ......................................................................................................................................84 6.4.1 Internal Pullup Enable .......................................................................................................85 6.4.2 Output Slew Rate Control Enable .....................................................................................85 6.4.3 Output Drive Strength Select ............................................................................................85 Pin Behavior in Stop Modes ............................................................................................................86 Parallel I/O and Pin Control Registers ............................................................................................86 6.6.1 Port A I/O Registers (PTAD and PTADD) .......................................................................86 6.6.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) .................................................87 6.6.3 Port B I/O Registers (PTBD and PTBDD) .......................................................................89 6.6.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) .................................................90 6.6.5 Port C I/O Registers (PTCD and PTCDD) .......................................................................92 6.6.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) .................................................93 6.6.7 Port D I/O Registers (PTDD and PTDDD) .......................................................................95 6.6.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) ................................................96 6.6.9 Port E I/O Registers (PTED and PTEDD) ........................................................................98 6.6.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) ..................................................99 6.6.11 Port F I/O Registers (PTFD and PTFDD) .......................................................................101 6.6.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ................................................102 6.6.13 Port G I/O Registers (PTGD and PTGDD) .....................................................................104 6.6.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ..............................................105 6.5 6.6 Chapter 7 Central Processor Unit (S08CPUV2) 7.1 7.2 Introduction ...................................................................................................................................107 7.1.1 Features ...........................................................................................................................107 Programmer’s Model and CPU Registers .....................................................................................108 7.2.1 Accumulator (A) .............................................................................................................108 7.2.2 Index Register (H:X) .......................................................................................................108 7.2.3 Stack Pointer (SP) ...........................................................................................................109 7.2.4 Program Counter (PC) ....................................................................................................109 7.2.5 Condition Code Register (CCR) .....................................................................................109 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 11 Section Number 7.3 Title Page 7.4 7.5 Addressing Modes .........................................................................................................................111 7.3.1 Inherent Addressing Mode (INH) ...................................................................................111 7.3.2 Relative Addressing Mode (REL) ...................................................................................111 7.3.3 Immediate Addressing Mode (IMM) ..............................................................................111 7.3.4 Direct Addressing Mode (DIR) ......................................................................................111 7.3.5 Extended Addressing Mode (EXT) ................................................................................112 7.3.6 Indexed Addressing Mode ..............................................................................................112 Special Operations .........................................................................................................................113 7.4.1 Reset Sequence ...............................................................................................................113 7.4.2 Interrupt Sequence ..........................................................................................................113 7.4.3 Wait Mode Operation ......................................................................................................114 7.4.4 Stop Mode Operation ......................................................................................................114 7.4.5 BGND Instruction ...........................................................................................................115 HCS08 Instruction Set Summary ..................................................................................................116 Chapter 8 Cyclic Redundancy Check (S08CRCV1) 8.1 Introduction ...................................................................................................................................127 8.1.1 Features ...........................................................................................................................127 8.1.2 Modes of Operation ........................................................................................................129 8.1.3 Block Diagram ................................................................................................................129 External Signal Description ..........................................................................................................129 Register Definition .......................................................................................................................130 8.3.1 Memory Map ..................................................................................................................130 8.3.2 Register Descriptions ......................................................................................................130 Functional Description ..................................................................................................................131 8.4.1 ITU-T (CCITT) Recommendations and Expected CRC Results ....................................132 Initialization Information ..............................................................................................................133 8.2 8.3 8.4 8.5 Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.1 9.2 Overview .......................................................................................................................................135 Channel Assignments ....................................................................................................................135 9.2.1 Alternate Clock ...............................................................................................................136 9.2.2 Hardware Trigger ............................................................................................................136 9.2.3 Temperature Sensor ........................................................................................................137 9.2.4 Features ...........................................................................................................................139 9.2.5 Block Diagram ................................................................................................................139 External Signal Description ..........................................................................................................140 9.3.1 Analog Power (VDDAD) ..................................................................................................141 9.3.2 Analog Ground (VSSAD) .................................................................................................141 9.3.3 Voltage Reference High (VREFH) ...................................................................................141 MC9S08AC60 Series Data Sheet, Rev. 2 12 Freescale Semiconductor 9.3 Section Number Title Page 9.4 9.5 9.6 9.7 9.3.4 Voltage Reference Low (VREFL) .....................................................................................141 9.3.5 Analog Channel Inputs (ADx) ........................................................................................141 Register Definition ........................................................................................................................141 9.4.1 Status and Control Register 1 (ADCSC1) ......................................................................141 9.4.2 Status and Control Register 2 (ADCSC2) ......................................................................143 9.4.3 Data Result High Register (ADCRH) .............................................................................144 9.4.4 Data Result Low Register (ADCRL) ..............................................................................144 9.4.5 Compare Value High Register (ADCCVH) ....................................................................145 9.4.6 Compare Value Low Register (ADCCVL) .....................................................................145 9.4.7 Configuration Register (ADCCFG) ................................................................................145 9.4.8 Pin Control 1 Register (APCTL1) ..................................................................................147 9.4.9 Pin Control 2 Register (APCTL2) ..................................................................................148 Functional Description ..................................................................................................................149 9.5.1 Clock Select and Divide Control ....................................................................................149 9.5.2 Input Select and Pin Control ...........................................................................................150 9.5.3 Hardware Trigger ............................................................................................................150 9.5.4 Conversion Control .........................................................................................................150 9.5.5 Automatic Compare Function .........................................................................................153 9.5.6 MCU Wait Mode Operation ............................................................................................153 9.5.7 MCU Stop3 Mode Operation ..........................................................................................153 9.5.8 MCU Stop1 and Stop2 Mode Operation .........................................................................154 Initialization Information ..............................................................................................................154 9.6.1 ADC Module Initialization Example .............................................................................154 Application Information ................................................................................................................156 9.7.1 External Pins and Routing ..............................................................................................156 9.7.2 Sources of Error ..............................................................................................................158 Chapter 10 Internal Clock Generator (S08ICGV4) 10.1 Introduction ...................................................................................................................................161 10.2 Introduction ...................................................................................................................................164 10.2.1 Features ...........................................................................................................................164 10.2.2 Modes of Operation ........................................................................................................165 10.2.3 Block Diagram ................................................................................................................166 10.3 External Signal Description ..........................................................................................................166 10.3.1 EXTAL — External Reference Clock / Oscillator Input ................................................166 10.3.2 XTAL — Oscillator Output ............................................................................................166 10.3.3 External Clock Connections ...........................................................................................167 10.3.4 External Crystal/Resonator Connections ........................................................................167 10.4 Register Definition ........................................................................................................................168 10.4.1 ICG Control Register 1 (ICGC1) ....................................................................................168 10.4.2 ICG Control Register 2 (ICGC2) ....................................................................................170 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 13 Section Number Title Page 10.4.3 ICG Status Register 1 (ICGS1) .......................................................................................171 10.4.4 ICG Status Register 2 (ICGS2) .......................................................................................172 10.4.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ..................................................................172 10.4.6 ICG Trim Register (ICGTRM) .......................................................................................173 10.5 Functional Description ..................................................................................................................173 10.5.1 Off Mode (Off) ................................................................................................................174 10.5.2 Self-Clocked Mode (SCM) .............................................................................................174 10.5.3 FLL Engaged, Internal Clock (FEI) Mode .....................................................................175 10.5.4 FLL Engaged Internal Unlocked ....................................................................................176 10.5.5 FLL Engaged Internal Locked ........................................................................................176 10.5.6 FLL Bypassed, External Clock (FBE) Mode ..................................................................176 10.5.7 FLL Engaged, External Clock (FEE) Mode ...................................................................176 10.5.8 FLL Lock and Loss-of-Lock Detection ..........................................................................177 10.5.9 FLL Loss-of-Clock Detection .........................................................................................178 10.5.10Clock Mode Requirements .............................................................................................179 10.5.11Fixed Frequency Clock ...................................................................................................180 10.5.12High Gain Oscillator .......................................................................................................180 10.6 Initialization/Application Information ..........................................................................................180 10.6.1 Introduction .....................................................................................................................180 10.6.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ...........................182 10.6.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ..............................184 10.6.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ......................186 10.6.5 Example #4: Internal Clock Generator Trim ..................................................................188 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction ...................................................................................................................................189 11.1.1 Features ...........................................................................................................................191 11.1.2 Modes of Operation ........................................................................................................191 11.1.3 Block Diagram ................................................................................................................192 11.2 External Signal Description ..........................................................................................................192 11.2.1 SCL — Serial Clock Line ...............................................................................................192 11.2.2 SDA — Serial Data Line ................................................................................................192 11.3 Register Definition ........................................................................................................................192 11.3.1 IIC Address Register (IICA) ...........................................................................................193 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................193 11.3.3 IIC Control Register (IICC1) ..........................................................................................196 11.3.4 IIC Status Register (IICS) ...............................................................................................197 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................198 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................198 11.4 Functional Description ..................................................................................................................199 11.4.1 IIC Protocol .....................................................................................................................199 MC9S08AC60 Series Data Sheet, Rev. 2 14 Freescale Semiconductor Section Number Title Page 11.4.2 10-bit Address .................................................................................................................203 11.4.3 General Call Address ......................................................................................................204 11.5 Resets ............................................................................................................................................204 11.6 Interrupts .......................................................................................................................................204 11.6.1 Byte Transfer Interrupt ....................................................................................................204 11.6.2 Address Detect Interrupt .................................................................................................204 11.6.3 Arbitration Lost Interrupt ................................................................................................204 11.7 Initialization/Application Information ..........................................................................................206 Chapter 12 Keyboard Interrupt (S08KBIV1) 12.1 Introduction ...................................................................................................................................209 12.1.1 Features ...........................................................................................................................209 12.1.2 KBI Block Diagram ........................................................................................................211 12.2 Register Definition ........................................................................................................................211 12.2.1 KBI Status and Control Register (KBISC) .....................................................................212 12.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................213 12.3 Functional Description ..................................................................................................................213 12.3.1 Pin Enables ......................................................................................................................213 12.3.2 Edge and Level Sensitivity ..............................................................................................213 12.3.3 KBI Interrupt Controls ....................................................................................................214 Chapter 13 Serial Communications Interface (S08SCIV4) 13.1 Introduction ...................................................................................................................................215 13.1.1 Features ...........................................................................................................................217 13.1.2 Modes of Operation ........................................................................................................217 13.1.3 Block Diagram ................................................................................................................218 13.2 Register Definition ........................................................................................................................220 13.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................220 13.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................221 13.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................222 13.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................223 13.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................225 13.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................226 13.2.7 SCI Data Register (SCIxD) .............................................................................................227 13.3 Functional Description ..................................................................................................................227 13.3.1 Baud Rate Generation .....................................................................................................227 13.3.2 Transmitter Functional Description ................................................................................228 13.3.3 Receiver Functional Description .....................................................................................229 13.3.4 Interrupts and Status Flags ..............................................................................................231 13.3.5 Additional SCI Functions ...............................................................................................232 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 15 Section Number Title Chapter 14 Serial Peripheral Interface (S08SPIV3) Page 14.1 Introduction ...................................................................................................................................235 14.1.1 Features ...........................................................................................................................237 14.1.2 Block Diagrams ..............................................................................................................237 14.1.3 SPI Baud Rate Generation ..............................................................................................239 14.2 External Signal Description ..........................................................................................................240 14.2.1 SPSCK — SPI Serial Clock ............................................................................................240 14.2.2 MOSI — Master Data Out, Slave Data In ......................................................................240 14.2.3 MISO — Master Data In, Slave Data Out ......................................................................240 14.2.4 SS — Slave Select ...........................................................................................................240 14.3 Modes of Operation .......................................................................................................................241 14.3.1 SPI in Stop Modes ..........................................................................................................241 14.4 Register Definition ........................................................................................................................241 14.4.1 SPI Control Register 1 (SPIC1) ......................................................................................241 14.4.2 SPI Control Register 2 (SPIC2) ......................................................................................242 14.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................243 14.4.4 SPI Status Register (SPIS) ..............................................................................................244 14.4.5 SPI Data Register (SPID) ................................................................................................245 14.5 Functional Description ..................................................................................................................246 14.5.1 SPI Clock Formats ..........................................................................................................246 14.5.2 SPI Interrupts ..................................................................................................................249 14.5.3 Mode Fault Detection .....................................................................................................249 Chapter 15 Timer/PWM (S08TPMV3) 15.1 Introduction ...................................................................................................................................251 15.2 Features .........................................................................................................................................251 15.3 TPMV3 Differences from Previous Versions ................................................................................253 15.3.1 Migrating from TPMV1 ..................................................................................................255 15.3.2 Features ...........................................................................................................................256 15.3.3 Modes of Operation ........................................................................................................256 15.3.4 Block Diagram ................................................................................................................257 15.4 Signal Description .........................................................................................................................259 15.4.1 Detailed Signal Descriptions ...........................................................................................259 15.5 Register Definition ........................................................................................................................263 15.5.1 TPM Status and Control Register (TPMxSC) ................................................................263 15.5.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................264 15.5.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................265 15.5.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................266 15.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................268 15.6 Functional Description ..................................................................................................................269 MC9S08AC60 Series Data Sheet, Rev. 2 16 Freescale Semiconductor Section Number Title Page 15.6.1 Counter ............................................................................................................................270 15.6.2 Channel Mode Selection .................................................................................................272 15.7 Reset Overview .............................................................................................................................275 15.7.1 General ............................................................................................................................275 15.7.2 Description of Reset Operation .......................................................................................275 15.8 Interrupts .......................................................................................................................................275 15.8.1 General ............................................................................................................................275 15.8.2 Description of Interrupt Operation ..................................................................................276 15.9 The Differences from TPM v2 to TPM v3 ....................................................................................277 Chapter 16 Development Support 16.1 Introduction ...................................................................................................................................281 16.1.1 Features ...........................................................................................................................282 16.2 Background Debug Controller (BDC) ..........................................................................................282 16.2.1 BKGD Pin Description ...................................................................................................283 16.2.2 Communication Details ..................................................................................................284 16.2.3 BDC Commands .............................................................................................................288 16.2.4 BDC Hardware Breakpoint .............................................................................................290 16.3 On-Chip Debug System (DBG) ....................................................................................................291 16.3.1 Comparators A and B ......................................................................................................291 16.3.2 Bus Capture Information and FIFO Operation ...............................................................291 16.3.3 Change-of-Flow Information ..........................................................................................292 16.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................292 16.3.5 Trigger Modes .................................................................................................................293 16.3.6 Hardware Breakpoints ....................................................................................................295 16.4 Register Definition ........................................................................................................................295 16.4.1 BDC Registers and Control Bits .....................................................................................295 16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................297 16.4.3 DBG Registers and Control Bits .....................................................................................298 Appendix A Electrical Characteristics and Timing Specifications A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 Introduction ....................................................................................................................................303 Parameter Classification.................................................................................................................303 Absolute Maximum Ratings...........................................................................................................304 Thermal Characteristics..................................................................................................................305 ESD Protection and Latch-Up Immunity .......................................................................................306 DC Characteristics..........................................................................................................................308 Supply Current Characteristics.......................................................................................................311 ADC Characteristics.......................................................................................................................314 Internal Clock Generation Module Characteristics ........................................................................317 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 17 Section Number Title Page A.9.1 ICG Frequency Specifications .........................................................................................318 A.10 AC Characteristics..........................................................................................................................320 A.10.1 Control Timing ................................................................................................................320 A.10.2 Timer/PWM (TPM) Module Timing ...............................................................................321 A.11 SPI Characteristics .........................................................................................................................323 A.12 FLASH Specifications....................................................................................................................326 A.13 EMC Performance..........................................................................................................................327 A.13.1 Conducted Transient Susceptibility .................................................................................327 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................329 B.2 Orderable Part Numbering System ................................................................................................329 B.3 Mechanical Drawings.....................................................................................................................329 MC9S08AC60 Series Data Sheet, Rev. 2 18 Freescale Semiconductor Chapter 1 Introduction 1.1 Overview The MC9S08AC60 Series are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for memory sizes and package types. Table 1-1. Devices in the MC9S08AC60 Series Device FLASH RAM Package 64 QFP 64 LQFP 48 QFN 44 LQFP 32 LQFP 64 QFP 64 LQFP 48 QFN 44 LQFP 32 LQFP 64 QFP 64 LQFP 48 QFN 44 LQFP 32 LQFP MC9S08AC60 63,280 49,152 MC9S08AC48 2048 32,768 MC9S08AC32 Table 1-2 summarizes the feature set available in the MC9S08AC60 Series of MCUs. Table 1-2. MC9S08AC60 Series Peripherals Available per Package Type MC9S08AC60/48/32 Feature CRC ADC IIC IRQ KBI1 SCI1 64-pin 16-ch 48-pin yes 8-ch yes yes 7 yes 6 44-pin 32-pin 6-ch 8 4 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 19 Chapter 1 Introduction Table 1-2. MC9S08AC60 Series Peripherals Available per Package Type MC9S08AC60/48/32 Feature SCI2 SPI1 TPM1 TPM1CLK1 TPM2 TPM2CLK1 TPM3 TPMCLK 1 I/O pins 1 64-pin 48-pin yes yes 4-ch 44-pin 32-pin no 2-ch 6-ch yes yes no 2-ch no 2-ch yes 54 38 34 22 TPMCLK, TPM1CLK, and TPM2CLK options are configured via software using the TPMCCFG bit; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Reference the TPM chapter for a functional description of the TPMxCLK signal. 1.2 MCU Block Diagrams The block diagram shows the structure of the MC9S08AC60 Series MCU. MC9S08AC60 Series Data Sheet, Rev. 2 20 Freescale Semiconductor Chapter 1 Introduction PORT A HCS08 CORE ICE DEBUG MODULE (DBG) 8 PTA[7:0] BKGD/MS BDC CPU CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT B 6 HCS08 SYSTEM CONTROL RESET IRQ/TPMCLK RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD TPMCLK VDDAD VSSAD VREFL VREFH USER FLASH 63,280 BYTES 49,152 BYTES 32,768 BYTES 2-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CH1 TPM3CH0 RxD2 TxD2 SDA1 PTB[7:2]/AD1P[7:2] PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 IIC MODULE (IIC1) SCL1 8 AD1P[7:0] PORT D 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) 8 AD1P[15:8] SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USER RAM 2048 BYTES 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CLK TPM1CH[5:2] RxD1 TxD1 TPM2CH1 TPM2CH0 TPM2CLK 3 5 KBI1P[7:5] KBI1P[4:0] PORT E PORT C SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VDD VSS SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) 2-CHANNEL TIMER/PWM MODULE (TPM2) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VOLTAGE REGULATOR EXTAL XTAL PORT G Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. Pin contains integrated pullup device. 4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). 5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 1-1. MC9S08AC60 Series Block Diagram MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 21 PORT F Chapter 1 Introduction Table 1 lists the functional versions of the on-chip modules. Table 1. Versions of On-Chip Modules Module Cyclic Redundancy Check Generator Analog-to-Digital Converter Internal Clock Generator Inter-Integrated Circuit Keyboard Interrupt Serial Communications Interface Serial Peripheral Interface Timer Pulse-Width Modulator Central Processing Unit Debug Module (CRC) (ADC) (ICG) (IIC) (KBI) (SCI) (SPI) (TPM) (CPU) (DBG) Version 1 1 4 2 1 4 3 3 2 2 1.3 System Clock Distribution TPM1CLK SYSTEM CONTROL LOGIC RTI TPM1 TPM2CLK TPM2 IIC1 SCI1 SCI2 SPI1 ICGERCLK FFE ÷2 ICG XCLK** 1 kHz ICGOUT ICGLCLK* ÷2 BUSCLK CPU COP BDC TPM3 ADC1 RAM FLASH TPMCLK CRC * ICGLCLK is the alternate BDC clock source for the MC9S08AC60 Series. ** Fixed frequency clock. Figure 1-2. System Clock Distribution Diagram Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator MC9S08AC60 Series Data Sheet, Rev. 2 22 Freescale Semiconductor Chapter 1 Introduction • • • — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module — Control bits inside the ICG determine which source is connected. FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2. Otherwise the fixed-frequency clock will be BUSCLK. ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. Can also be used as the ALTCLK input to the ADC module. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 23 Chapter 1 Introduction MC9S08AC60 Series Data Sheet, Rev. 2 24 Freescale Semiconductor Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment Figure 2-1. shows the 64-pin package assignments for the MC9S08AC60 Series devices. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 25 Chapter 2 Pins and Connections PTD6/TPM1CLK/AD1P14 PTD4/TPM2CLK/AD1P12 50 47 46 45 44 43 42 PTD7/KBI1P7/AD1P15 PTD5/AD1P13 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTC3/TxD2 64 PTC4 1 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF2/TPM1CH4 PTF3/TPM1CH5 PTF4/TPM2CH0 PTC6 PTF7 PTF5/TPM2CH1 PTF6 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 16 18 17 PTA4 PTA5 PTA0 PTA1 PTG0/KBI1P0 PTE7/SPSCK1 PTG1/KBI1P1 PTG2/KBI1P2 PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTA2 PTA3 VSS VDD 19 20 21 22 23 24 25 26 27 28 29 30 31 2 3 4 5 6 7 8 9 10 11 12 13 14 15 63 62 61 60 59 58 57 56 55 54 53 52 51 PTG4/KBI1P4 49 48 PTG3/KBI1P3 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 VSSAD VDDAD PTD1/AD1P9 PTD0/AD1P8 PTB7/AD1P7 PTB6/AD1P6 PTB5/AD1P5 PTB4/AD1P4 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 33 PTA7 32 PTA6 41 40 39 38 37 36 35 34 PTG6/EXTAL PTC5/RxD2 PTG5/XTAL BKGD/MS 64-Pin QFP 64-Pin LQFP Figure 2-1. MC9S08AC60 Series in 64-Pin QFP or LQFP Package MC9S08AC60 Series Data Sheet, Rev. 2 26 Freescale Semiconductor VREFH VREFL VSS Chapter 2 Pins and Connections Figure 2-2 shows the 48-pin QFN pin assignments for the MC9S08AC60 Series device. PTC4 1 IRQ/TPMCLK 2 RESET 3 PTF0/TPM1CH2 4 PTF1/TPM1CH3 5 PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 PTF6 8 PTE0/TxD1 9 PTE1/RxD1 10 PTE2/TPM1CH0 11 PTE3/TPM1CH1 12 PTE4/SS1 13 PTE5/MISO1 14 PTE6/MOSI1 15 PTE7/SPSCK1 16 VSS 17 VDD 18 PTG0/KBI1P0 19 PTG1/KBI1P1 20 PTG2/KBI1P2 21 PTA0 22 PTA1 23 48-Pin QFN Figure 2-2. MC9S08AC60 Series in 48-Pin QFN Package MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 27 PTA2 24 37 PTG4/KB1IP4 48 PTC5/RxD2 42 PTG6/EXTAL 46 PTC2/MCLK 45 PTC1/SDA1 44 PTC0/SCL1 41 PTG5/XTAL 47 PTC3/TxD2 40 BKGD/MS 38 VREFH 39 VREFL 43 VSS 36 PTG3/KBI1P3 35 PTD3/KBI1P6/AD1P11 34 PTD2/KBI1P5/AD1P10 33 VSSAD 32 VDDAD 31 PTD1/AD1P9 30 PTD0/AD1P8 29 PTB3/AD1P3 28 PTB2/AD1P2 27 PTB1/TPM3CH1/AD1P1 26 PTB0/TPM3CH0/AD1P0 25 PTA7 Chapter 2 Pins and Connections Figure 2-3. shows the 44-pin LQFP pin assignments for the MC9S08AC60 Series device. PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTG6/EXTAL PTC5/RxD2 PTC3/TxD2 PTG5/XTAL BKGD/MS 44 PTC4 1 IRQ/TPMCLK RESET PTF0/TPM1CH2 PTF1/TPM1CH3 PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 11 13 12 PTA0 PTE4/SS1 PTE7/SPSCK1 PTE5/MISO1 PTE6/MOSI1 VSS PTG0/KBI1P0 PTG1/KBI1P1 PTG2/KBI1P2 VDD 14 15 16 17 18 19 20 21 2 3 4 5 6 7 8 9 10 43 42 41 40 39 38 37 36 35 34 33 PTG3/KBI1P3 32 31 30 29 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 VSSAD VDDAD PTD1/AD1P9 PTD0/AD1P8 PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 23 PTB0/TPM3CH0/AD1P0 22 PTA1 44-Pin LQFP Figure 2-3. MC9S08AC60 Series in 44-Pin LQFP Package MC9S08AC60 Series Data Sheet, Rev. 2 28 Freescale Semiconductor VREFH 28 27 26 25 24 VREFL VSS Chapter 2 Pins and Connections Figure 2-4. shows the 32-pin LQFP pin assignments for the MC9S08AC60 Series device. PTC1/SDA1 PTC0/SCL1 PTG6/EXTAL PTG5/XTAL BKGD/MS 32 IRQ/TPMCLK 1 RESET PTF4/TPM2CH0 PTF5/TPM2CH1 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PTE3/TPM1CH1 2 3 4 5 6 7 8 10 9 PTE4/SS1 PTE7/SPSCK1 PTE5/MISO1 PTE6/MOSI1 VSS PTG0/KBI1P0 PTG1/KBI1P1 VDD 11 12 13 14 15 16 31 30 29 28 27 26 25 24 PTD3/KBI1P6/AD1P11 23 22 PTD2/KBI1P5/AD1P10 VSSAD VDDAD PTB3/AD1P3 PTB2/AD1P2 PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 VREFH 21 20 19 18 17 32-Pin LQFP Figure 2-4. MC9S08AC60 Series in 32-Pin LQFP Package 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08AC60 Series application systems. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 29 VREFL VSS Chapter 2 Pins and Connections VREFH CBYAD 0.1 μF SYSTEM POWER + 5V VDD VDDAD PTA0 VSSAD VREFL VDD CBY 0.1 μF VSS (x2) PTA1 PTA2 PORT A PTA3 PTA4 PTA5 PTA6 PTA7 NOTE 1 RF C1 C2 PTB0/AD1P0 XTAL NOTE 2 EXTAL NOTE 2 BACKGROUND HEADER VDD 1 BKGD/MS VDD 4.7 kΩ–10 kΩ 0.1 μF VDD RESET PORT C PORT B PTB1/AD1P1 PTB2/AD1P2 PTB3/AD1P3 PTB4/AD1P4 PTB5/AD1P5 PTB6/AD1P6 PTB7/AD1P7 PTC0/SCL1 PTC1/SDA1 PTC2/MCLK PTC3/TxD2 PTC4 PTC5/RxD2 PTC6 IRQ NOTE 1 PTD0/AD1P8 PTG0/KBI1P0 PTG1/KBI1P1 PTG2/KBI1P2 PTG3/KBI1P3 PTG4/KBI1P4 PTG5/XTAL PTG6/EXTAL PORT G PORT D PTD1/AD1P9 PTD2/KBI1P5/AD1P10 PTD3/KBI1P6/AD1P11 PTD4/TPM2CLK/AD1P12 PTD5/AD1P13 PTD6/TPM1CLK/AD1P14 PTD7/KBI1P7/AD1P15 PTE0/TxD1 PTE1/RxD1 PTE2/TPM1CH0 PORT F PORT E PTE3/TPM1CH1 PTE4/SS1 PTE5/MISO1 PTE6/MOSI1 PTE7/SPSCK1 I/O AND PERIPHERAL INTERFACE TO APPLICATION SYSTEM MC9S08AC60 CBLK + 10 μF RS X1 OPTIONAL MANUAL RESET ASYNCHRONOUS INTERRUPT INPUT 4.7 kΩ– 10 kΩ 0.1 μF NOTES: 1. Not required if using the internal clock option. 2. These are the same pins as PTG5 and PTG6 3. RC filters on RESET and IRQ are recommended for EMC-sensitive applications. PTF0/TPM1CH2 PTF1/TPM1CH3 PTF2/TPM1CH4 PTF3/TPM1CH5 PTF4/TPM2CH0 PTF5/TPM2CH1 PTF6 PTF7 Figure 2-5. Basic System Connections MC9S08AC60 Series Data Sheet, Rev. 2 30 Freescale Semiconductor Chapter 2 Pins and Connections 2.3.1 Power (VDD, VSS, VDDAD, VSSAD) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the paired VDD and VSS power pins as practical to suppress high-frequency noise. The MC9S08AC60 has a second VSS pin. This pin should be connected to the system ground plane or to the primary VSS pin through a low-impedance connection. VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to the ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the analog power pins as practical to suppress high-frequency noise. 2.3.2 Oscillator (XTAL, EXTAL) Out of reset the MCU uses an internally generated clock (self-clocked mode — fSelf_reset) equivalent to about 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, see Chapter 10, “Internal Clock Generator (S08ICGV4).” The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin. Refer to Figure 2-5 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 which are usually the same size. As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.3.3 RESET Pin RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 31 Chapter 2 Pins and Connections external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 cycles of fSelf_reset. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS). In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-5 for an example. 2.3.4 Background/Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, and no output slew rate control. When the pin functions as a background pin, it includes a high current output driver. When the pin functions as a mode select pin it is input only, and therefore does not include a standard output driver. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset which forces the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.3.5 ADC Reference Pins (VREFH, VREFL) The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs respectively for the ADC module. 2.3.6 External Interrupt Pin (IRQ) The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin can still be configured as the TPMCLK (see the TPM chapter). In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for an example. MC9S08AC60 Series Data Sheet, Rev. 2 32 Freescale Semiconductor Chapter 2 Pins and Connections 2.3.7 General-Purpose I/O and Peripheral Ports The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user’s reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unconnected pins to outputs so the pins do not float. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output.” When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. See the Chapter 6, “Parallel Input/Output” chapter for more details. Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTD7, PTD3, PTD2, and PTG4 pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device rather than a pullup device. NOTE When an alternative function is first enabled it is possible to get a spurious edge to the module, user software should clear out any associated flags before interrupts are enabled. Table 2-1 illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. It is recommended that all modules that share a pin be disabled before enabling another module. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 33 Chapter 2 Pins and Connections Table 2-1. Pin Availability by Package Pin-Count Pin Number Highest Alt 2 Pin Number Highest Alt 2 64 48 44 32 Port Pin 1 2 3 4 5 6 7 8 9 11 12 13 1 2 3 4 5 1 2 3 4 5 — PTC4 1 IRQ 2 RESET — PTF0 — PTF1 64 48 44 32 Port Pin 33 25 — — PTA7 TPMCLK 34 26 23 17 PTB0 35 27 24 18 PTB1 36 28 25 19 PTB2 37 29 26 20 PTB3 38 — — — PTB4 39 — — — PTB5 40 — — — PTB6 41 — — — PTB7 42 30 27 — PTD0 43 31 28 — PTD1 44 32 29 21 VDDAD 45 33 30 22 VSSAD 46 34 31 23 PTD2 47 35 32 24 PTD3 48 36 33 — PTG3 49 37 — — PTG4 50 — — — PTD4 51 — — — PTD5 52 — — — PTD6 53 — — — PTD7 54 38 34 25 VREFH 55 39 35 26 VREFL 56 40 36 27 BKGD 57 41 37 28 PTG5 58 42 38 29 PTG6 59 43 39 30 VSS 60 44 40 31 PTC0 61 45 41 32 PTC1 62 46 42 — PTC2 63 47 43 — PTC3 64 48 44 — PTC5 TPM3CH0 AD1P0 TPM3CH1 AD1P1 AD1P2 AD1P3 AD1P4 AD1P5 AD1P6 AD1P7 AD1P8 AD1P9 TPM1CH2 TPM1CH3 TPM1CH4 TPM1CH5 TPM2CH0 — — — PTF2 — — — PTF3 6 6 3 PTF4 — — — PTC6 7 8 9 7 8 9 4 PTF5 5 PTE0 6 PTE1 7 PTE2 8 PTE3 9 PTE4 10 — — — PTF7 TPM2CH1 TxD1 RxD1 TPM1CH0 TPM1CH1 SS1 MISO1 MOSI1 SPSCK1 — — PTF6 14 10 KBI1P5 KBI1P6 KBI1P3 KBI1P4 AD1P10 AD1P11 15 11 10 16 12 11 17 13 12 18 14 13 10 PTE5 19 15 14 11 PTE6 20 16 15 12 PTE7 21 17 16 13 VSS 22 18 17 14 VDD 23 19 18 15 PTG0 24 20 19 16 PTG1 25 21 20 — PTG2 26 22 21 — PTA0 27 23 22 — PTA1 28 24 — — PTA2 29 — — — PTA3 30 — — — PTA4 31 — — — PTA5 32 — — — PTA6 TPM2CLK AD1P12 AD1P13 TPM1CLK AD1P14 KBI1P7 AD1P15 KBI1P0 KBI1P1 KBI1P2 MS XTAL EXTAL SCL1 SDA1 MCLK TxD2 RxD2 1. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. MC9S08AC60 Series Data Sheet, Rev. 2 34 Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08AC60 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • Features Active background mode for code development Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained Stop modes: — System clocks stopped; voltage regulator in standby — Stop2 — Partial power down of internal circuits, RAM contents retained — Stop3 — All internal circuits powered for fast recovery • 3.3 Run Mode This is the normal operating mode for the MC9S08AC60 Series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip ICE debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 35 Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In both stop modes, all internal clocks are halted. If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. Some HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08AC60 Series of devices operates at 2.7 V to 5.5 V and does not include stop1 mode. MC9S08AC60 Series Data Sheet, Rev. 2 36 Freescale Semiconductor Chapter 3 Modes of Operation Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1. Stop Mode Behavior CPU, Digital Peripherals, FLASH Off Standby Mode PPDC RAM ICG ADC Regulator I/O Pins RTI Stop2 Stop3 1 1 0 Standby Standby Off Off1 Disabled Optionally on Standby Standby States held States held Optionally on Optionally on Crystal oscillator can be configured to run in stop3. Please see the ICG registers. 3.6.1 Stop2 Mode The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. To enter stop2, the user must execute a STOP instruction with stop2 selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to operate in stop (LVDSE = LVDE = 1). If the LVD is enabled in stop, then the MCU enters stop3 upon the execution of the STOP instruction regardless of the state of PPDC. Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by user software before pin latches are opened. When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ADC. Upon entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a logic 1 is written to PPDACK in SPMSC2. Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before entering stop2. Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 37 Chapter 3 Modes of Operation For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. 3.6.2 Stop3 Mode To enter stop3, the user must execute a STOP instruction with stop3 selected (PPDC = 0) and stop mode enabled (STOPE = 1). Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The ICG enters its standby state, as does the voltage regulator and the ADC. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exit from stop3 is done by asserting RESET, an asynchronous interrupt pin, or through the real-time interrupt (RTI). The asynchronous interrupt pins are the IRQ or KBI pins. Exit from stop3 can also facilitated by the SCI reciever interrupt, the ADC, and LVI. If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector. A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3 mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. 3.6.3 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in Chapter 16, “Development Support” of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background MC9S08AC60 Series Data Sheet, Rev. 2 38 Freescale Semiconductor Chapter 3 Modes of Operation commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the background debug mode is enabled. Table 3-2. BDM Enabled Stop Mode Behavior CPU, Digital Peripherals, FLASH Standby Mode PPDC RAM ICG ADC Regulator I/O Pins RTI Stop3 x Standby Active Optionally on Active States held Optionally on 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the LVD is enabled. Table 3-3. LVD Enabled Stop Mode Behavior CPU, Digital Peripherals, FLASH Standby Mode PPDC RAM ICG ADC Regulator I/O Pins RTI Stop3 x Standby Off Optionally on Active States held Optionally on 3.6.5 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2 Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes. Table 3-4. Stop Mode Behavior Mode Peripheral Stop2 CPU RAM FLASH Parallel Port Registers ADC ICG IIC RTI Off Standby Off Off Off Off Off Optionally on 3 Stop3 Standby Standby Standby Standby Optionally On1 Optionally On2 Standby Optionally on3 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 39 Chapter 3 Modes of Operation Table 3-4. Stop Mode Behavior (continued) Mode Peripheral Stop2 SCI SPI TPM System Voltage Regulator I/O Pins 1 2 Stop3 Standby Standby Standby Standby States Held Off Off Off Standby States Held Requires the asynchronous ADC clock and LVD to be enabled, else in standby. OSCSTEN set in ICGC1, else in standby. 3 RTIS[2:0] in SRTISC does not equal 0 before entering stop, else off. MC9S08AC60 Series Data Sheet, Rev. 2 40 Freescale Semiconductor Chapter 4 Memory 4.1 MC9S08AC60 Series Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08AC60 Series series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers ($0000 through $006F) • High-page registers ($1800 through $185F) • Nonvolatile registers ($FFB0 through $FFBF) MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 41 Chapter 4 Memory $0000 $006F $0070 DIRECT PAGE REGISTERS RAM 2048 BYTES $0000 $006F $0070 DIRECT PAGE REGISTERS RAM 2048 BYTES $0000 $006F $0070 DIRECT PAGE REGISTERS RAM 2048 BYTES $086F $0870 $17FF $1800 FLASH 3984 BYTES $086F $0870 $17FF $1800 RESERVED 3984 BYTES $086F $0870 $17FF $1800 RESERVED 3984 BYTES HIGH PAGE REGISTERS $185F $1860 $185F $1860 HIGH PAGE REGISTERS $185F $1860 RESERVED 10,144 BYTES $3FFF $4000 $7FFF $8000 HIGH PAGE REGISTERS RESERVED 26,528 BYTES FLASH 59,296 BYTES FLASH 49,152 BYTES FLASH 32,768 BYTES $FFFF $FFFF $FFFF MC9S08AC60 MC9S08AC48 MC9S08AC32 Figure 4-1. MC9S08AC60 Series Memory Map MC9S08AC60 Series Data Sheet, Rev. 2 42 Freescale Semiconductor Chapter 4 Memory 4.1.1 Reset and Interrupt Vector Assignments Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08AC60 Series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1. Reset and Interrupt Vectors Address (High/Low) 0xFFC0:FFC1 through 0xFFC4:FFC5 0xFFC6:FFC7 0xFFC8:FFC9 0xFFCA:FFCB 0xFFCC:FFCD 0xFFCE:FFCF 0xFFD0:FFD1 0xFFD2:FFD3 0xFFD4:FFD5 0xFFD6:FFD7 0xFFD8:FFD9 0xFFDA:FFDB 0xFFDC:FFDD 0xFFDE:FFDF 0xFFE0:FFE1 0xFFE2:FFE3 0xFFE4:FFE5 0xFFE6:FFE7 0xFFE8:FFE9 0xFFEA:FFEB 0xFFEC:FFED 0xFFEE:FFEF 0xFFF0:FFF1 0xFFF2:FFF3 0xFFF4:FFF5 0xFFF6:FFF7 0xFFF8:FFF9 0xFFFA:FFFB 0xFFFC:FFFD 0xFFFE:FFFF Vector Unused Vector Space (available for user program) TPM3 overflow TPM3 channel 1 TPM3 channel 0 RTI IIC1 ADC1 conversion KBI1 SCI2 transmit SCI2 receive SCI2 error SCI1 transmit SCI1 receive SCI1 error SPI1 TPM2 overflow TPM2 channel 1 TPM2 channel 0 TPM1 overflow TPM1 channel 5 TPM1 channel 4 TPM1 channel 3 TPM1 channel 2 TPM1 channel 1 TPM1 channel 0 ICG Low voltage detect IRQ SWI Reset Vector Name — Vtpm3ovf Vtpm3ch1 Vtpm3ch0 Vrti Viic1 Vadc1 Vkeyboard1 Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi1 Vtpm2ovf Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch5 Vtpm1ch4 Vtpm1ch3 Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vswi Vreset MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 43 Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08AC60 Series are divided into these three groups: • Direct-page registers are located in the first 112 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0–$FFBF. Nonvolatile register locations include: — Three values which are loaded into working registers at reset — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08AC60 Series Data Sheet, Rev. 2 44 Freescale Semiconductor Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 PTAD7 PTADD7 PTBD7 PTBDD7 0 0 PTDD7 PTDDD7 PTED7 PTEDD7 PTFD7 PTFDD7 0 0 — — COCO ADACT 0 ADR7 0 ADCV7 ADLPC ADPC7 ADPC15 — — 0 — KBEDG7 KBIPE7 TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F 6 PTAD6 PTADD6 PTBD6 PTBDD6 PTCD6 PTCDD6 PTDD6 PTDDD6 PTED6 PTEDD6 PTFD6 PTFDD6 PTGD6 PTGDD6 — — AIEN ADTRG 0 ADR6 0 ADCV6 ADPC6 ADPC14 — — IRQPDD — KBEDG6 KBIPE6 TOIE 14 6 14 6 CH0IE 14 6 CH1IE ADIV ADPC5 ADPC13 — — IRQEDG — KBEDG5 KBIPE5 CPWMS 13 5 13 5 MS0B 13 5 MS1B 5 PTAD5 PTADD5 PTBD5 PTBDD5 PTCD5 PTCDD5 PTDD5 PTDDD5 PTED5 PTEDD5 PTFD5 PTFDD5 PTGD5 PTGDD5 — — ADCO ACFE 0 ADR5 0 ADCV5 ACFGT 0 ADR4 0 ADCV4 ADLSMP ADPC4 ADPC12 — — IRQPE — KBEDG4 KBIPE4 CLKSB 12 4 12 4 MS0A 12 4 MS1A 0 0 ADR3 0 ADCV3 ADPC3 ADPC11 — — IRQF — KBF KBIPE3 CLKSA 11 3 11 3 ELS0B 11 3 ELS1B MODE ADPC2 ADPC10 — — IRQACK — KBACK KBIPE2 PS2 10 2 10 2 ELS0A 10 2 ELS1A 4 PTAD4 PTADD4 PTBD4 PTBDD4 PTCD4 PTCDD4 PTDD4 PTDDD4 PTED4 PTEDD4 PTFD4 PTFDD4 PTGD4 PTGDD4 — — 3 PTAD3 PTADD3 PTBD3 PTBDD3 PTCD3 PTCDD3 PTDD3 PTDDD3 PTED3 PTEDD3 PTFD3 PTFDD3 PTGD3 PTGDD3 — — 2 PTAD2 PTADD2 PTBD2 PTBDD2 PTCD2 PTCDD2 PTDD2 PTDDD2 PTED2 PTEDD2 PTFD2 PTFDD2 PTGD2 PTGDD2 — — ADCH 0 0 ADR2 0 ADCV2 R ADR9 ADR1 ADCV9 ADCV1 ADPC1 ADPC9 — — IRQIE — KBIE KBIPE1 PS1 9 1 9 1 0 9 1 0 R ADR8 ADR0 ADCV8 ADCV0 ADPC0 ADPC8 — — IRQMOD — KBIMOD KBIPE0 PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 1 PTAD1 PTADD1 PTBD1 PTBDD1 PTCD1 PTCDD1 PTDD1 PTDDD1 PTED1 PTEDD1 PTFD1 PTFDD1 PTGD1 PTGDD1 — — Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 PTDD0 PTDDD0 PTED0 PTEDD0 PTFD0 PTFDD0 PTGD0 PTGDD0 — — 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E– 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019– 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 PTAD PTADD PTBD PTBDD PTCD PTCDD PTDD PTDDD PTED PTEDD PTFD PTFDD PTGD PTGDD Reserved ADC1SC1 ADC1SC2 ADC1RH ADC1RL ADC1CVH ADC1CVL ADC1CFG APCTL1 APCTL2 Reserved IRQSC Reserved KBISC KBIPE TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL TPM1C1SC ADICLK MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 45 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 Bit 15 Bit 7 CH2F Bit 15 Bit 7 CH3F Bit 15 Bit 7 CH4F Bit 15 Bit 7 CH3F Bit 15 Bit 7 — LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 LBKDIE SBR7 LOOPS TIE TDRE LBKDIF R8 Bit 7 HGO LOLRE CLKST 0 0 0 0 6 14 6 CH2IE 14 6 CH3IE 14 6 CH4IE 14 6 CH5IE 14 6 — RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 RXEDGIE SBR6 SCISWAI TCIE TC RXEDGIF T8 6 RANGE 5 13 5 MS2B 13 5 MS3B 13 5 MS4B 13 5 MS5B 13 5 — 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 0 SBR5 RSRC RIE RDRF 0 TXDIR 5 REFS MFD REFST 0 0 LOLS 0 0 FLT TRIM — SPIE — SPE — SPTIE — MSTR — CPOL — CPHA — SSOE — LSBFE 4 12 4 MS2A 12 4 MS3A 12 4 MS4A 12 4 MS5A 12 4 — SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 SBR12 SBR4 M ILIE IDLE RXINV TXINV 4 CLKS LOCRE LOCK 0 LOCS 0 FLT 3 11 3 ELS2B 11 3 ELS3B 11 3 ELS4B 11 3 ELS5B 11 3 — SBR11 SBR3 WAKE TE OR RWUID ORIE 3 SBR11 SBR3 WAKE TE OR RWUID ORIE 3 2 10 2 ELS2A 10 2 ELS3A 10 2 ELS4A 10 2 ELS5A 10 2 — SBR10 SBR2 ILT RE NF BRK13 NEIE 2 SBR10 SBR2 ILT RE NF BRK13 NEIE 2 OSCSTEN 1 9 1 0 9 1 0 9 1 0 9 1 0 9 1 — SBR9 SBR1 PE RWU FE LBKDE FEIE 1 SBR9 SBR1 PE RWU FE LBKDE FEIE 1 LOCD RFD ERCS 0 ICGIF DCOS Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 0 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 TPM1C1VH TPM1C1VL TPM1C2SC TPM1C2VH TPM1C2VL TPM1C3SC TPM1C3VH TPM1C3VL TPM1C4SC TPM1C4VH TPM1C4VL TPM1C5SC TPM1C5VH TPM1C5VL Reserved SCI1BDH SCI1BDL SCI1C1 SCI1C2 SCI1S1 SCI1S2 SCI1C3 SCI1D SCI2BDH SCI2BDL SCI2C1 SCI2C2 SCI2S1 SCI2S2 SCI2C3 SCI2D ICGC1 ICGC2 ICGS1 ICGS2 ICGFLTU ICGFLTL ICGTRM Reserved SPI1C1 MC9S08AC60 Series Data Sheet, Rev. 2 46 Freescale Semiconductor Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 0 0 SPRF 0 Bit 7 Bit 15 Bit 7 MULT IICEN TCF GCAEN — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 — — IICIE IAAS ADEXT — — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 — — MST BUSY 0 — — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 — — TX ARBL DATA 0 — — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 — — 0 — — CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 — — AD10 — — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 — — AD9 — — PS1 9 1 9 1 0 9 1 0 9 1 — — AD8 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — TXAK 0 6 0 SPPR2 0 0 6 14 6 5 0 SPPR1 SPTEF 0 5 13 5 4 MODFEN SPPR0 MODF 0 4 12 4 ADDR ICR RSTA SRW 0 IICIF 0 RXAK 3 BIDIROE 0 0 0 3 11 3 2 0 SPR2 0 0 2 10 2 1 SPISWAI SPR1 0 0 1 9 1 Bit 0 SPC0 SPR0 0 0 Bit 0 Bit 8 Bit 0 0 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E– 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B– 0x006F SPI1C2 SPI1BR SPI1S Reserved SPI1D CRCH CRCL IIC1A IIC1F IIC1C1 IIC1S IIC1D IIC1C2 Reserved TPM2SC TPM2CNTH TPM2CNTL TPM2MODH TPM2MODL TPM2C0SC TPM2C0VH TPM2C0VL TPM2C1SC TPM2C1VH TPM2C1VL Reserved High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table 4-3. High-Page Register Summary (Sheet 1 of 3) Address Register Name Bit 7 POR 0 COPE 0 — — REV3 6 PIN 0 COPT 0 — — REV2 5 COP 0 STOPE 0 — — REV1 4 ILOP 0 — MPE — — REV0 3 0 0 0 0 — — ID11 — — ID10 2 ICG 0 0 1 LVD 0 — MCSEL — — ID9 — — ID8 Bit 0 0 BDFR — 0x1800 0x1801 0x1802 0x1803 0x1804 – 0x1805 0x1806 SRS SBDFR SOPT SMCLK Reserved SDIDH MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 47 Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 ID7 RTIF LVDF LVWF — COPCLKS — — Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 DBGEN TRGSEL AF — — DIVLD KEYEN — 0 FPS7 FCBEF FCMD7 — — TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7 6 ID6 RTIACK LVDACK LVWACK — — — — 14 6 14 6 14 6 ARM BEGIN BF — — PRDIV8 FNORED — 0 FPS6 FCCF FCMD6 — — TOIE 14 6 14 6 CH0IE 14 6 CH1IE 14 6 5 ID5 RTICLKS LVDIE LVDV — — — — 13 5 13 5 13 5 TAG 0 ARMF — — DIV5 0 — KEYACC FPS5 FPVIOL FCMD5 — — CPWMS 13 5 13 5 MS0B 13 5 MS1B 13 5 4 ID4 RTIE LVDRE LVWV — — — — 12 4 12 4 12 4 BRKEN 0 0 — — DIV4 0 — 0 FPS4 FACCERR FCMD4 — — CLKSB 12 4 12 4 MS0A 12 4 MS1A 12 4 3 ID3 0 LVDSE PPDF — TPMCCFG 2 ID2 RTIS2 LVDE PPDACK — — — — 10 2 10 2 10 2 RWAEN TRG2 CNT2 — — DIV2 0 — 0 FPS2 FBLANK FCMD2 — — PS2 10 2 10 2 ELS0A 10 2 ELS1A 10 2 1 ID1 RTIS1 0 1 Bit 0 ID0 RTIS0 BGBE PPDC — — — — Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 RWBEN TRG0 CNT0 — — DIV0 SEC00 — 0 FPDIS 0 FCMD0 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0x1807 0x1808 0x1809 0x180A 0x180B 0x180C 0x180D– 0x180F 0x1810 0x1811 0x1812 0x1813 0x1814 0x1815 0x1816 0x1817 0x1818 0x1819– 0x181F 0x1820 0x1821 0x1822 0x1823 0x1824 0x1825 0x1826 0x1827– 0x182F 0x1830 0x1831 0x1832 0x1833 0x1834 0x1835 0x1836 0x1837 0x1838 0x1839 0x183A SDIDL SRTISC SPMSC1 SPMSC2 Reserved SOPT2 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL DBGC DBGT DBGS Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Reserved TPM3SC TPM3CNTH TPM3CNTL TPM3MODH TPM3MODL TPM3C0SC TPM3C0VH TPM3C0VL TPM3C1SC TPM3C1VH TPM3C1VL — — — — — 9 1 9 1 9 1 RWB TRG1 CNT1 — — DIV1 SEC01 — 0 FPS1 0 FCMD1 — — PS1 9 1 9 1 0 9 1 0 9 1 — — 11 3 11 3 11 3 RWA TRG3 CNT3 — — DIV3 0 — 0 FPS3 0 FCMD3 — — CLKSA 11 3 11 3 ELS0B 11 3 ELS1B 11 3 MC9S08AC60 Series Data Sheet, Rev. 2 48 Freescale Semiconductor Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 3 of 3) Address Register Name Bit 7 — — PTAPE7 PTASE7 PTADS7 — PTBPE7 PTBSE7 PTBDS7 — 0 0 0 — PTDPE7 PTDSE7 PTDDS7 — PTEPE7 PTESE7 PTEDS7 — PTFPE7 PTFSE7 PTFDS7 — 0 0 0 — — 6 — — PTAPE6 PTASE6 PTADS6 — PTBPE6 PTBSE6 PTBDS6 — PTCPE6 PTCSE6 PTCDS6 — PTDPE6 PTDSE6 PTDDS6 — PTEPE6 PTESE6 PTEDS6 — PTFPE6 PTFSE6 PTFDS6 — PTGPE6 PTGSE6 PTGDS6 — — 5 — — PTAPE5 PTASE5 PTADS5 — PTBPE5 PTBSE5 PTBDS5 — PTCPE5 PTCSE5 PTCDS5 — PTDPE5 PTDSE5 PTDDS5 — PTEPE5 PTESE5 PTEDS5 — PTFPE5 PTFSE5 PTFDS5 — PTGPE5 PTGSE5 PTGDS5 — — 4 — — PTAPE4 PTASE4 PTADS4 — PTBPE4 PTBSE4 PTBDS4 — PTCPE4 PTCSE4 PTCDS4 — PTDPE4 PTDSE4 PTDDS4 — PTEPE4 PTESE4 PTEDS4 — PTFPE4 PTFSE4 PTFDS4 — PTGPE4 PTGSE4 PTGDS4 — — 3 — — PTAPE3 PTASE3 PTADS3 — PTBPE3 PTBSE3 PTBDS3 — PTCPE3 PTCSE3 PTCDS3 — PTDPE3 PTDSE3 PTDDS3 — PTEPE3 PTESE3 PTEDS3 — PTFPE3 PTFSE3 PTFDS3 — PTGPE3 PTGSE3 PTGDS3 — — 2 — — PTAPE2 PTASE2 PTADS2 — PTBPE2 PTBSE2 PTBDS2 — PTCPE2 PTCSE2 PTCDS2 — PTDPE2 PTDSE2 PTDDS2 — PTEPE2 PTESE2 PTEDS2 — PTFPE2 PTFSE2 PTFDS2 — PTGPE2 PTGSE2 PTGDS2 — — 1 — — PTAPE1 PTASE1 PTADS1 — PTBPE1 PTBSE1 PTBDS1 — PTCPE1 PTCSE1 PTCDS1 — PTDPE1 PTDSE1 PTDDS1 — PTEPE1 PTESE1 PTEDS1 — PTFPE1 PTFSE1 PTFDS1 — PTGPE1 PTGSE1 PTGDS1 — — Bit 0 — — PTAPE0 PTASE0 PTADS0 — PTBPE0 PTBSE0 PTBDS0 — PTCPE0 PTCSE0 PTCDS0 — PTDPE0 PTDSE0 PTDDS0 — PTEPE0 PTESE0 PTEDS0 — PTFPE0 PTFSE0 PTFDS0 — PTGPE0 PTGSE0 PTGDS0 — — 0x183B 0x183F 0x1840 0x1841 0x1842 0x1843 0x1844 0x1845 0x1846 0x1847 0x1848 0x1849 0x184A 0x184B 0x184C 0x184D 0x184E 0x184F 0x1850 0x1851 0x1852 0x1853 0x1854 0x1855 0x1856 0x1857 0x1858 0x1859 0x185A 0x185B– 0x185F 1 Reserved PTAPE PTASE PTADS Reserved PTBPE PTBSE PTBDS Reserved PTCPE PTCSE PTCDS Reserved PTDPE PTDSE PTDDS Reserved PTEPE PTESE PTEDS Reserved PTFPE PTFSE PTFDS Reserved PTGPE PTGSE PTGDS Reserved This reserved bit must always be written to 0. Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 49 Chapter 4 Memory Table 4-4. Nonvolatile Register Summary Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 $FFB0 – $FFB7 $FFB8 – $FFBB $FFBC NVBACKKEY Reserved Reserved for storage of 250 kHz ICGTRM value NVPROT Reserved for storage of 243 kHz ICGTRM value NVOPT — — — 8-Byte Comparison Key — — — — — — FPS7 — KEYEN — FPS6 — FNORED — FPS5 — 0 — FPS4 — 0 — FPS3 — 0 — FPS2 — 0 — FPS1 — SEC01 — FPDIS — SEC00 $FFBD $FFBE $FFBF Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08AC60 Series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the MC9S08AC60 Series, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP fADCK Subsequent continuous 10-bit; fBUS > fADCK Subsequent continuous 8-bit; fBUS > fADCK/11 Subsequent continuous 10-bit; fBUS > fADCK/11 ADICLK 0x, 10 0x, 10 0x, 10 0x, 10 11 11 11 11 xx xx xx xx ADLSMP 0 0 1 1 0 0 1 1 0 0 1 1 Max Total Conversion Time 20 ADCK cycles + 5 bus clock cycles 23 ADCK cycles + 5 bus clock cycles 40 ADCK cycles + 5 bus clock cycles 43 ADCK cycles + 5 bus clock cycles 5 μs + 20 ADCK + 5 bus clock cycles 5 μs + 23 ADCK + 5 bus clock cycles 5 μs + 40 ADCK + 5 bus clock cycles 5 μs + 43 ADCK + 5 bus clock cycles 17 ADCK cycles 20 ADCK cycles 37 ADCK cycles 40 ADCK cycles The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is: Conversion time = 23 ADCK cyc 8 MHz/1 + 5 bus cyc 8 MHz = 3.5 μs Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications. MC9S08AC60 Series Data Sheet, Rev. 2 152 Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.5.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than the compare value, COCO is set. The value generated by the addition of the conversion result and the two’s complement of the compare value is transferred to ADCRH and ADCRL. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon the setting of COCO if the ADC interrupt is enabled (AIEN = 1). NOTE The compare function can be used to monitor the voltage on a channel while the MCU is in either wait or stop3 mode. The ADC interrupt will wake the MCU when the compare condition is met. 9.5.6 MCU Wait Mode Operation The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled. The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait mode if the ADC interrupt is enabled (AIEN = 1). 9.5.7 MCU Stop3 Mode Operation The STOP instruction is used to put the MCU in a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 9.5.7.1 Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 153 Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.5.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3 mode if the ADC interrupt is enabled (AIEN = 1). NOTE It is possible for the ADC module to wake the system from low power stop and cause the MCU to begin consuming run-level currents without generating a system level interrupt. To prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in Section 9.5.4.2, “Completing Conversions) is cleared when entering stop3 and continuing ADC conversions. 9.5.8 MCU Stop1 and Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode. All module registers contain their reset values following exit from stop1 or stop2. Therefore the module must be re-enabled and re-configured following exit from stop1 or stop2. 9.6 Initialization Information This section gives an example which provides some basic direction on how a user would initialize and configure the ADC module. The user has the flexibility of choosing between configuring the module for 8-bit or 10-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 9-6, Table 9-7, and Table 9-8 for information used in this example. NOTE Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 9.6.1 9.6.1.1 ADC Module Initialization Example Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. MC9S08AC60 Series Data Sheet, Rev. 2 154 Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 9.6.1.2 Pseudo — Code Example In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will be derived from the bus clock divided by 1. ADCCFG = 0x98 (%10011000) Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed) Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1 Bit 4 ADLSMP 1 Configures for long sample time Bit 3:2 MODE 10 Sets mode at 10-bit conversions Bit 1:0 ADICLK 00 Selects bus clock as input clock source ADCSC2 = 0x00 (%00000000) Bit 7 ADACT 0 Bit 6 ADTRG 0 Bit 5 ACFE 0 Bit 4 ACFGT 0 Bit 3:2 00 Bit 1:0 00 ADCSC1 = 0x41 (%01000001) Bit 7 COCO 0 Bit 6 AIEN 1 Bit 5 ADCO 0 Bit 4:0 ADCH 00001 Flag indicates if a conversion is in progress Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel ADCRH/L = 0xxx Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion data cannot be overwritten with data from the next conversion. ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 155 Chapter 9 Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT NO CONTINUE Figure 9-13. Initialization Flowchart for Example 9.7 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 9.7.1 External Pins and Routing The following sections discuss the external pins associated with the ADC module and how they should be used for best results. 9.7.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (VDDAD and VSSAD) which are available as separate pins on some devices. On other devices, VSSAD is shared on the same pin as the MCU digital VSS, and on others, both VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. MC9S08AC60 Series Data Sheet, Rev. 2 156 Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 9.7.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The high reference is VREFH, which may be shared on the same pin as VDDAD on some devices. The low reference is VREFL, which may be shared on the same pin as VSSAD on some devices. When available on a separate pin, VREFH may be connected to the same potential as VDDAD, or may be driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH must never exceed VDDAD). When available on a separate pin, VREFL must be connected to the same voltage potential as VSSAD. Both VREFH and VREFL must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. Inductance in this path must be minimum (parasitic only). 9.7.1.3 Analog Input Pins The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin control register bit always be set when using a pin as an analog input. This avoids problems with contention because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input buffer draws dc current when its input is not at either VDD or VSS. Setting the pin control register bits for all pins used as analog inputs should be done to achieve lowest operating current. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to VSSA. For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to $3FF (full scale 10-bit representation) or $FF (full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. There will be a brief current associated with VREFL when the sampling capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 157 Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.7.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 9.7.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept below 5 kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 9.7.2.2 Pin Leakage Error Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high. If this error cannot be tolerated by the application, keep RAS lower than VDDAD / (2N*ILEAK) for less than 1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode). 9.7.2.3 Noise-Induced Errors System noise which occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1 μF low-ESR capacitor from VREFH to VREFL. • There is a 0.1 μF low-ESR capacitor from VDDAD to VSSAD. • If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from VDDAD to VSSAD. • VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane. • Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion. — For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT instruction or STOP instruction. — For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: • Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSAD (this will improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08AC60 Series Data Sheet, Rev. 2 158 Freescale Semiconductor Chapter 9 Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 9.7.2.4 Code Width and Quantization Error The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH - VREFL) / 2N Eqn. 9-2 There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB. 9.7.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. These errors are: • Zero-scale error (EZS) (sometimes called offset) — This error is defined as the difference between the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is used. • Full-scale error (EFS) — This error is defined as the difference between the actual code width of the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the difference between the actual $3FE code width and its ideal (1LSB) is used. • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. • Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. • Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 9.7.2.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 159 Chapter 9 Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around 1/2LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 9.7.2.3 will reduce this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08AC60 Series Data Sheet, Rev. 2 160 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) 10.1 Introduction The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. As seen in Figure 10-2, the ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator. Two frequency ranges are software selectable to allow optimal startup and stability. Alternatively, the oscillator block can be used to route an external square wave to the system clock. External sources can provide a very precise clock source. The oscillator is capable of being configured for low power mode or high amplitude mode as selected by HGO. • Internal reference generator — The internal reference generator consists of two controlled clock sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller. The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU. This provides a highly reliable, low-cost clock source. • Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or external clock source and multiplies it to a higher frequency. Status bits provide information when the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. • Clock select block — The clock select block provides several switch options for connecting different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source, and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC). The internal clock generation (ICG) module is used to generate the system clocks for the MC9S08AC60 Series MCU. A diagram of the System Clock Distribution is provide in the figure below. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 161 Chapter 10 Internal Clock Generator (S08ICGV4) ICGERCLK FFE SYSTEM CONTROL LOGIC RTI TPM1 TPM2 IIC1 SCI1 SCI2 SPI1 ÷2 ICG XCLK** **** 1 kHz ICGOUT ICGLCLK* ÷2 BUSCLK CPU COP BDC TPM3*** ADC1 RAM ROM * ICGLCLK is the alternate BDC clock source for the MC9S08AC60 Series. ** Fixed frequency clock. *** TPM3 not available on the MC9S08AW60/48/32/16 **** Optional 1-kHz clock not available on MC9S08AW60/48/32/16 Figure 10-1. System Clock Distribution Diagram MC9S08AC60 Series Data Sheet, Rev. 2 162 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) PORT A HCS08 CORE ICE DEBUG MODULE (DBG) 8 PTA[7:0] BKGD/MS BDC CPU CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT B 6 HCS08 SYSTEM CONTROL RESET IRQ/TPMCLK RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD TPMCLK VDDAD VSSAD VREFL VREFH USER FLASH 63,280 BYTES 49,152 BYTES 32,768 BYTES 2-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CH1 TPM3CH0 RxD2 TxD2 SDA1 PTB[7:2]/AD1P[7:2] PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 IIC MODULE (IIC1) SCL1 8 AD1P[7:0] PORT D 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) 8 AD1P[15:8] SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USER RAM 2048 BYTES 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CLK TPM1CH[5:2] RxD1 TxD1 TPM2CH1 TPM2CH0 TPM2CLK 3 5 KBI1P[7:5] KBI1P[4:0] PORT E PORT C SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VDD VSS SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) 2-CHANNEL TIMER/PWM MODULE (TPM2) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VOLTAGE REGULATOR EXTAL XTAL PORT G Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. Pin contains integrated pullup device. 4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). 5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 10-2. Block Diagram Highlighting ICG Module MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 163 PORT F Chapter 10 Internal Clock Generator (S08ICGV4) 10.2 Introduction The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. As seen in Figure 10-3, the ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator. Two frequency ranges are software selectable to allow optimal startup and stability. Alternatively, the oscillator block can be used to route an external square wave to the system clock. External sources can provide a very precise clock source. The oscillator is capable of being configured for low power mode or high amplitude mode as selected by HGO. • Internal reference generator — The internal reference generator consists of two controlled clock sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller. The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU. This provides a highly reliable, low-cost clock source. • Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or external clock source and multiplies it to a higher frequency. Status bits provide information when the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the external reference clock and signals whether the clock is valid or not. • Clock select block — The clock select block provides several switch options for connecting different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source, and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC). 10.2.1 Features The module is intended to be very user friendly with many of the features occurring automatically without user intervention. To quickly configure the module, go to Section 10.6, “Initialization/Application Information” and pick an example that best suits the application needs. Features of the ICG and clock distribution system: • Several options for the primary clock source allow a wide range of cost, frequency, and precision choices: — 32 kHz–100 kHz crystal or resonator — 1 MHz–16 MHz crystal or resonator — External clock — Internal reference generator • Defaults to self-clocked mode to minimize startup delays • Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz) — Uses external or internal clock as reference frequency • Automatic lockout of non-running clock sources • Reset or interrupt on loss of clock or loss of FLL lock MC9S08AC60 Series Data Sheet, Rev. 2 164 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) • • • • • • • Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast frequency lock when recovering from stop3 mode DCO will maintain operating frequency during a loss or removal of reference clock Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128) Separate self-clocked source for real-time interrupt Trimmable internal clock source supports SCI communications without additional external components Automatic FLL engagement after lock is acquired External oscillator selectable for low power or high gain 10.2.2 Modes of Operation This is a high-level description only. Detailed descriptions of operating modes are contained in Section 10.5, “Functional Description.” • Mode 1 — Off The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is executed. • Mode 2 — Self-clocked (SCM) Default mode of operation that is entered immediately after reset. The ICG’s FLL is open loop and the digitally controlled oscillator (DCO) is free running at a frequency set by the filter bits. • Mode 3 — FLL engaged internal (FEI) In this mode, the ICG’s FLL is used to create frequencies that are programmable multiples of the internal reference clock. — FLL engaged internal unlocked is a transition state that occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged internal locked is a state that occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. • Mode 4 — FLL bypassed external (FBE) In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source. • Mode 5 — FLL engaged external (FEE) The ICG’s FLL is used to generate frequencies that are programmable multiples of the external clock reference. — FLL engaged external unlocked is a transition state that occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. — FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 165 Chapter 10 Internal Clock Generator (S08ICGV4) 10.2.3 Block Diagram Figure 10-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list. EXTAL OSCILLATOR (OSC) WITH EXTERNAL REF SELECT XTAL ICGDCLK FREQUENCY LOCKED LOOP (FLL) DCO ICG CLOCK SELECT ICGERCLK OUTPUT CLOCK SELECT /R ICGOUT REF SELECT VDDA (SEE NOTE 2) V SSA (SEE NOTE 2) LOSS OF LOCK AND CLOCK DETECTOR FIXED CLOCK SELECT IRG INTERNAL TYP 243 kHz REFERENCE 8 MHz GENERATORS RG ICGIRCLK FFE LOCAL CLOCK FOR OPTIONAL USE WITH BDC ICGLCLK NOTES: 1. See Table 10-1 for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK 2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments. Figure 10-3. ICG Block Diagram 10.3 External Signal Description The oscillator pins are used to provide an external clock source for the MCU. The oscillator pins are gain controlled in low-power mode (default). Oscillator amplitudes in low-power mode are limited to approximately 1 V, peak-to-peak. 10.3.1 EXTAL — External Reference Clock / Oscillator Input If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as either the external clock input or the input of the oscillator circuit as determined by REFS. If upon the first write to ICGC1, either the FEI mode or SCM mode is selected, this pin is not used by the ICG. 10.3.2 XTAL — Oscillator Output If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as the output of the oscillator circuit. If upon the first write to ICGC1, either the FEI mode or SCM mode is MC9S08AC60 Series Data Sheet, Rev. 2 166 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) selected, this pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. 10.3.3 External Clock Connections If an external clock is used, then the pins are connected as shown Figure 10-4. ICG EXTAL VSS XTAL NOT CONNECTED CLOCK INPUT Figure 10-4. External Clock Connections 10.3.4 External Crystal/Resonator Connections If an external crystal/resonator frequency reference is used, then the pins are connected as shown in Figure 10-5. Recommended component values are listed in the Electrical Characteristics chapter. ICG EXTAL VSS XTAL RS C1 C2 RF CRYSTAL OR RESONATOR Figure 10-5. External Frequency Reference Connection MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 167 Chapter 10 Internal Clock Generator (S08ICGV4) 10.4 Register Definition Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 10.4.1 ICG Control Register 1 (ICGC1) 7 6 5 4 3 2 1 0 R W Reset HGO1 0 0 RANGE 1 REFS 0 0 CLKS 0 OSCSTEN 1 LOCD 0 0 = Unimplemented or Reserved Figure 10-6. ICG Control Register 1 (ICGC1) 1 This bit can be written only once after reset. Additional writes are ignored. Table 10-1. ICGC1 Register Field Descriptions Field 7 HGO Description High Gain Oscillator Select — The HGO bit is used to select between low power operation and high gain operation for improved noise immunity. This bit is write-once after reset. 0 Oscillator configured for low power operation. 1 Oscillator configured for high gain operation. Frequency Range Select — The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler multiplication factor (P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is write-once after a reset. The RANGE bit only has an effect in FLL engaged external and FLL bypassed external modes. 0 Oscillator configured for low frequency range. FLL loop prescale factor P is 64. 1 Oscillator configured for high frequency range. FLL loop prescale factor P is 1. External Reference Select — The REFS bit controls the external reference clock source for ICGERCLK. The REFS bit is write-once after a reset. 0 External clock requested. 1 Oscillator using crystal or resonator requested. Clock Mode Select — The CLKS bits control the clock mode as described below. If FLL bypassed external is requested, it will not be selected until ERCS = 1. If the ICG enters off mode, the CLKS bits will remain unchanged. Writes to the CLKS bits will not take effect if a previous write is not complete. 00 Self-clocked 01 FLL engaged, internal reference 10 FLL bypassed, external reference 11 FLL engaged, external reference The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits cannot be written to 1X until after the next reset (because the EXTAL pin was not reserved). 6 RANGE 5 REFS 4:3 CLKS MC9S08AC60 Series Data Sheet, Rev. 2 168 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) Table 10-1. ICGC1 Register Field Descriptions (continued) Field 2 OSCSTEN Description Enable Oscillator in Off Mode — The OSCSTEN bit controls whether or not the oscillator circuit remains enabled when the ICG enters off mode. This bit has no effect if HGO = 1 and RANGE = 1. 0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1. Loss of Clock Disable 0 Loss of clock detection enabled. 1 Loss of clock detection disabled. 1 LOCD MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 169 Chapter 10 Internal Clock Generator (S08ICGV4) 10.4.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE W Reset 0 0 0 0 0 0 0 0 MFD LOCRE RFD Figure 10-7. ICG Control Register 2 (ICGC2) Table 10-2. ICGC2 Register Field Descriptions Field 7 LOLRE Description Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a loss of lock indication. The LOLRE bit only has an effect when LOLS is set. 0 Generate an interrupt request on loss of lock. 1 Generate a reset request on loss of lock. Multiplication Factor — The MFD bits control the programmable multiplication factor in the FLL loop. The value specified by the MFD bits establishes the multiplication factor (N) applied to the reference frequency. Writes to the MFD bits will not take effect if a previous write is not complete. Select a low enough value for N such that fICGDCLK does not exceed its maximum specified value. 000 Multiplication factor = 4 001 Multiplication factor = 6 010 Multiplication factor = 8 011 Multiplication factor = 10 100 Multiplication factor = 12 101 Multiplication factor = 14 110 Multiplication factor = 16 111 Multiplication factor = 18 Loss of Clock Reset Enable — The LOCRE bit determines how the system manages a loss of clock condition. 0 Generate an interrupt request on loss of clock. 1 Generate a reset request on loss of clock. Reduced Frequency Divider — The RFD bits control the value of the divider following the clock select circuitry. The value specified by the RFD bits establishes the division factor (R) applied to the selected output clock source. Writes to the RFD bits will not take effect if a previous write is not complete. 000 Division factor = 1 001 Division factor = 2 010 Division factor = 4 011 Division factor = 8 100 Division factor = 16 101 Division factor = 32 110 Division factor = 64 111 Division factor = 128 6:4 MFD 3 LOCRE 2:0 RFD MC9S08AC60 Series Data Sheet, Rev. 2 170 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) 10.4.3 ICG Status Register 1 (ICGS1) 7 6 5 4 3 2 1 0 R W Reset 0 CLKST REFST LOLS LOCK LOCS ERCS ICGIF 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-8. ICG Status Register 1 (ICGS1) Table 10-3. ICGS1 Register Field Descriptions Field 7:6 CLKST Description Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Self-clocked 01 FLL engaged, internal reference 10 FLL bypassed, external reference 11 FLL engaged, external reference Reference Clock Status — The REFST bit indicates which clock reference is currently selected by the Reference Select circuit. 0 External Clock selected. 1 Crystal/Resonator selected. FLL Loss of Lock Status — The LOLS bit is a sticky indication of FLL lock status. 0 FLL has not unexpectedly lost lock since LOLS was last cleared. 1 FLL has unexpectedly lost lock since LOLS was last cleared, LOLRE determines action taken.FLL has unexpectedly lost lock since LOLS was last cleared, LOLRE determines action taken. FLL Lock Status — The LOCK bit indicates whether the FLL has acquired lock. The LOCK bit is cleared in off, self-clocked, and FLL bypassed modes. 0 FLL is currently unlocked. 1 FLL is currently locked. Loss Of Clock Status — The LOCS bit is an indication of ICG loss of clock status. 0 ICG has not lost clock since LOCS was last cleared. 1 ICG has lost clock since LOCS was last cleared, LOCRE determines action taken. External Reference Clock Status — The ERCS bit is an indication of whether or not the external reference clock (ICGERCLK) meets the minimum frequency requirement. 0 External reference clock is not stable, frequency requirement is not met. 1 External reference clock is stable, frequency requirement is met. ICG Interrupt Flag — The ICGIF read/write flag is set when an ICG interrupt request is pending. It is cleared by a reset or by reading the ICG status register when ICGIF is set and then writing a logic 1 to ICGIF. If another ICG interrupt occurs before the clearing sequence is complete, the sequence is reset so ICGIF would remain set after the clear sequence was completed for the earlier interrupt. Writing a logic 0 to ICGIF has no effect. 0 No ICG interrupt request is pending. 1 An ICG interrupt request is pending. 5 REFST 4 LOLS 3 LOCK 2 LOCS 1 ERCS 0 ICGIF MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 171 Chapter 10 Internal Clock Generator (S08ICGV4) 10.4.4 ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 DCOS 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-9. ICG Status Register 2 (ICGS2) Table 10-4. ICGS2 Register Field Descriptions Field 0 DCOS Description DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error has not changed by more than nunlock for two consecutive samples and the DCO clock is not static. This bit is used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It is also used in self-clocked mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the off state. 0 DCO clock is unstable. 1 DCO clock is stable. 10.4.5 ICG Filter Registers (ICGFLTU, ICGFLTL) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FLT 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-10. ICG Upper Filter Register (ICGFLTU) Table 10-5. ICGFLTU Register Field Descriptions Field 3:0 FLT Description Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. MC9S08AC60 Series Data Sheet, Rev. 2 172 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) 7 6 5 4 3 2 1 0 R FLT W Reset 1 1 0 0 0 0 0 0 Figure 10-11. ICG Lower Filter Register (ICGFLTL) Table 10-6. ICGFLTL Register Field Descriptions Field 7:0 FLT Description Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete. The filter registers show the filter value (FLT). 10.4.6 ICG Trim Register (ICGTRM) 7 6 5 4 3 2 1 0 R TRIM W POR Reset: 1 0 0 0 0 0 0 0 U U U U U U U U U = Unaffected by MCU reset Figure 10-12. ICG Trim Register (ICGTRM) Table 10-7. ICGTRM Register Field Descriptions Field 7 TRIM Description ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a ±25% adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value will decrease the period. 10.5 Functional Description This section provides a functional description of each of the five operating modes of the ICG. Also discussed are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG is very flexible, and in some configurations, it is possible to exceed certain clock specifications. When using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 173 Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.1 Off Mode (Off) Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state. However there are two cases to consider when clock activity continues while the CPU is in stop mode, 10.5.1.1 BDM Active When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to memory and control registers via the BDC controller. 10.5.1.2 OSCSTEN Bit Set When the oscillator is enabled in stop mode (OSCSTEN = 1), the individual clock generators are enabled but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator startup times if necessary, or to run the RTI from the oscillator during stop3. 10.5.1.3 Stop/Off Mode Recovery Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT. Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096 clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time. 10.5.2 Self-Clocked Mode (SCM) Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following conditions occur: • After any reset. • Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state temporarily until the DCO is stable (DCOS = 1). • CLKS bits are written from X1 to 00. • CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1). In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given by fICGDCLK / R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value into the filter registers (ICGFLTH and ICGFLTL). This is the only mode in which the filter registers can be written. If this mode is entered due to a reset, fICGDCLK will default to fSelf_reset which is nominally 8 MHz. If this mode is entered from FLL engaged internal, fICGDCLK will maintain the previous frequency.If this mode is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference clock), fICGDCLK will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked. If this mode is entered from off mode, fICGDCLK will be equal to the frequency of ICGDCLK before MC9S08AC60 Series Data Sheet, Rev. 2 174 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS bits. CLKST CLKS RFD REFERENCE DIVIDER (/7) ICGIRCLK CLOCK SELECT CIRCUIT REDUCED FREQUENCY DIVIDER (R) ICGOUT RANGE FLT MFD ICGDCLK SUBTRACTOR DIGITAL LOOP FILTER 1x DIGITALLY CONTROLLED OSCILLATOR 2x FLL ANALOG FREQUENCYLOCKED LOOP (FLL) ICGERCLK CLKST OVERFLOW COUNTER ENABLE RANGE PULSE COUNTER ICG2DCLK LOCK AND LOSS OF CLOCK DETECTOR RESET AND INTERRUPT CONTROL IRQ RESET DCOS LOCK LOLS LOCS ERCS LOCD ICGIF LOLRE LOCRE Figure 10-13. Detailed Frequency-Locked Loop Block Diagram 10.5.3 FLL Engaged, Internal Clock (FEI) Mode FLL engaged internal (FEI) is entered when any of the following conditions occur: • CLKS bits are written to 01 • The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01 In FLL engaged internal mode, the reference clock is derived from the internal reference clock ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 175 Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.4 FLL Engaged Internal Unlocked FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition. The ICG will remain in this state while the count error (Δn) is greater than the maximum nlock or less than the minimum nlock, as required by the lock detector to detect the lock condition. In this state the output clock signal ICGOUT frequency is given by fICGDCLK / R. 10.5.5 FLL Engaged Internal Locked FLL engaged internal locked is entered from FEI unlocked when the count error (Δn), which comes from the subtractor, is less than nlock (max) and greater than nlock (min) for a given number of samples, as required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is given by fICGDCLK / R. In FEI locked, the filter value is updated only once every four comparison cycles. The update made is an average of the error measurements taken in the four previous comparisons. 10.5.6 FLL Bypassed, External Clock (FBE) Mode FLL bypassed external (FBE) is entered when any of the following conditions occur: • From SCM when CLKS = 10 and ERCS is high • When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited • From FLL engaged external mode if a loss of DCO clock occurs and the external reference remains valid (both LOCS = 1 and ERCS = 1) In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock, ICGERCLK. The output clock signal ICGOUT frequency is given by fICGERCLK / R. If an external clock source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range 0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for RANGE = 0 or high for RANGE = 1. 10.5.7 FLL Engaged, External Clock (FEE) Mode The FLL engaged external (FEE) mode is entered when any of the following conditions occur: • CLKS = 11 and ERCS and DCOS are both high. • The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11. In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO. The minimum multiplier for the FLL, from Table 10-12 is 4. Because 4 X 10 MHz is 40MHz, which is the operational limit of the DCO, the reference clock cannot be any faster than 10 MHz. MC9S08AC60 Series Data Sheet, Rev. 2 176 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.7.1 FLL Engaged External Unlocked FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition. The ICG will remain in this state while the count error (Δn) is greater than the maximum nlock or less than the minimum nlock, as required by the lock detector to detect the lock condition. In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to lock it according to their operational descriptions later in this section. Upon entering this state and until the FLL becomes locked, the output clock signal ICGOUT frequency is given by fICGDCLK / (2×R) This extra divide by two prevents frequency overshoots during the initial locking process from exceeding chip-level maximum frequency specifications. After the FLL has locked, if an unexpected loss of lock causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal ICGOUT frequency is given by fICGDCLK / R. 10.5.7.2 FLL Engaged External Locked FEE locked is entered from FEE unlocked when the count error (Δn) is less than nlock (max) and greater than nlock (min) for a given number of samples, as required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is given by fICGDCLK/R. In FLL engaged external locked, the filter value is updated only once every four comparison cycles. The update made is an average of the error measurements taken in the four previous comparisons. 10.5.8 FLL Lock and Loss-of-Lock Detection To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO for one comparison cycle (see Table 10-9 for explanation of a comparison cycle) and passes this number to the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn. To achieve locked status, Δn must be between nlock (min) and nlock (max). After the FLL has locked, Δn must stay between nunlock (min) and nunlock (max) to remain locked. If Δn goes outside this range unexpectedly, the LOLS status bit is set and remains set until cleared by software or until the MCU is reset. LOLS is cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset (LOLRE = 1), or by any MCU reset. If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up from stop. Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the LOLS will not be set. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 177 Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.9 FLL Loss-of-Clock Detection The reference clock and the DCO clock are monitored under different conditions (see Table 10-8). Provided the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error. LOCS will remain set until it is acknowledged or until the MCU is reset. LOCS is cleared by reading ICGS1 then writing 1 to ICGIF (LOCRE = 0), or by a loss-of-clock induced reset (LOCRE = 1), or by any MCU reset. If the ICG is in FEE, a loss of reference clock causes the ICG to enter SCM, and a loss of DCO clock causes the ICG to enter FBE mode. If the ICG is in FBE mode, a loss of reference clock will cause the ICG to enter SCM. In each case, the CLKST and CLKS bits will be automatically changed to reflect the new state. If the ICG is in FEE mode when a loss of clock occurs and the ERCS is still set to 1, then the CLKST bits are set to 10 and the ICG reverts to FBE mode. A loss of clock will also cause a loss of lock when in FEE or FEI modes. Because the method of clearing the LOCS and LOLS bits is the same, this would only be an issue in the unlikely case that LOLRE = 1 and LOCRE = 0. In this case, the interrupt would be overridden by the reset for the loss of lock. Table 10-8. Clock Monitoring (When LOCD = 0) Mode Off CLKS 0X or 11 10 10 SCM (CLKST = 00) 0X 10 10 11 FEI (CLKST = 01) FBE (CLKST = 10) FEE (CLKST = 11) 1 2 REFST X 0 1 X 0 1 X X X 0 1 X ERCS Forced Low Forced Low Real-Time1 Forced Low Forced High Real-Time Real-Time Forced Low Real-Time Forced High Real-Time Real-Time External Reference Clock Monitored? No No Yes(1) No No Yes Yes No Yes No Yes Yes DCO Clock Monitored? No No No Yes2 Yes(2) Yes(2) Yes(2) Yes Yes No No Yes 0X 11 10 10 11 If ENABLE is high (waiting for external crystal start-up after exiting stop). DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode. MC9S08AC60 Series Data Sheet, Rev. 2 178 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.10 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should be the same as the requested mode in CLKS1:CLKS0. Table 10-9 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST. NOTE If a crystal will be used before the next reset, then be sure to set REFS = 1 and CLKS = 1x on the first write to the ICGC1 register. Failure to do so will result in “locking” REFS = 0 which will prevent the oscillator amplifier from being enabled until the next reset occurs. Table 10-9. ICG State Table Actual Mode (CLKST) Off (XX) Desired Mode (CLKS) Off (XX) FBE (10) SCM (00) SCM (00) FEI (01) FBE (10) FEE (11) FEI (01) FEI (01) FEE (11) FBE (10) FEE (11) FEE (11) Range Reference Frequency (fREFERENCE) 0 0 fICGIRCLK/72 fICGIRCLK/7(1) fICGIRCLK/7(1) fICGIRCLK/7(1) fICGIRCLK/7 fICGIRCLK/7 0 0 fICGERCLK fICGERCLK Comparison Cycle Time — — 8/fICGIRCLK 8/fICGIRCLK 8/fICGIRCLK 8/fICGIRCLK 8/fICGIRCLK 8/fICGIRCLK — — 2/fICGERCLK 128/fICGERCLK ICGOUT Conditions1 for CLKS = CLKST — — Not switching from FBE to SCM — — — DCOS = 1 — ERCS = 1 — ERCS = 1 and DCOS = 1 ERCS = 1 and DCOS = 1 Reason CLKS1 ≠ CLKST — ERCS = 0 X X 0 0 X ICGDCLK/R — 0 X X 0 X X X 0 1 ICGDCLK/R ICGDCLK/R ICGDCLK/R ICGDCLK/R ICGDCLK/R ICGERCLK/R ICGERCLK/R ICGDCLK/R3 ICGDCLK/R(2) DCOS = 0 ERCS = 0 DCOS = 0 or ERCS = 0 — ERCS = 0 — LOCS = 1 & ERCS = 1 — — FBE (10) FEE (11) 1 CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new value. 2 The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons that determine the DCOS bit 3 After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are changed. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 179 Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.11 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in all modes except FEE. In FEE mode, XCLK is equal to ICGERCLK ÷ 2 when the following conditions are met: • (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 10-11), N and R are determined by MFD and RFD respectively (see Table 10-12). • LOCK = 1. If the above conditions are not true, then XCLK is equal to BUSCLK. When the ICG is in either FEI or SCM mode, XCLK is turned off. Any peripherals which can use XCLK as a clock source must not do so when the ICG is in FEI or SCM mode. 10.5.12 High Gain Oscillator The oscillator has the option of running in a high gain oscillator (HGO) mode, which improves the oscillator's resistance to EMC noise when running in FBE or FEE modes. This option is selected by writing a 1 to the HGO bit in the ICGC1 register. HGO is used with both the high and low range oscillators but is only valid when REFS = 1 in the ICGC1 register. When HGO = 0, the standard low-power oscillator is selected. This bit is writable only once after any reset. 10.6 10.6.1 Initialization/Application Information Introduction The section is intended to give some basic direction on which configuration a user would want to select when initializing the ICG. For some applications, the serial communication link may dictate the accuracy of the clock reference. For other applications, lowest power consumption may be the chief clock consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in choosing which is best for any application. MC9S08AC60 Series Data Sheet, Rev. 2 180 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) Table 10-10. ICG Configuration Consideration Clock Reference Source = Internal FEI 4 MHz < fBus < 20 MHz.1 Medium power (will be less than FEE if oscillator range = high) Good clock accuracy (After IRG is trimmed) Lowest system cost (no external components required) IRG is on. DCO is on. 2 SCM This mode is mainly provided for quick and reliable system startup. 3 MHz < fBus < 5 MHz (default).1 3 MHz < fBus < 20 MHz (via filter bits).1 Medium power Poor accuracy. IRG is off. DCO is on and open loop. Clock Reference Source = External FEE 4 MHz < fBus < 20 MHz.1 Medium power (will be less than FEI if oscillator range = low) High clock accuracy Medium/High system cost (crystal, resonator or external clock source required) IRG is off. DCO is on. FBE fBus range ≤ 8 MHz when crystal or resonator is used. Lowest power Highest clock accuracy Medium/High system cost (Crystal, resonator or external clock source required) IRG is off. DCO is off. FLL Engaged FLL Bypassed 1 2 Range values are given for an assumed RFD = 1. Changing the RFD allows for a lower minimum frequency. The IRG typically consumes 100 μA. The FLL and DCO typically consumes 0.5 to 2.5 mA, depending upon output frequency. For minimum power consumption and minimum jitter, choose N and R to be as small as possible. The following sections contain initialization examples for various configurations. NOTE Hexadecimal values designated by a preceding $, binary values designated by a preceding %, and decimal values have no preceding character. Important configuration information is repeated here for reference. Table 10-11. ICGOUT Frequency Calculation Options Clock Scheme SCM — self-clocked mode (FLL bypassed internal) FBE — FLL bypassed external FEI — FLL engaged internal FEE — FLL engaged external 1 fICGOUT1 fICGDCLK / R fext / R (fIRG / 7)* 64 * N / R fext * P * N / R P NA NA 64 Range = 0 ; P = 64 Range = 1; P = 1 Note Typical fICGOUT = 8 MHz immediately after reset Typical fIRG = 243 kHz Ensure that fICGDCLK, which is equal to fICGOUT * R, does not exceed fICGDCLKmax. Table 10-12. MFD and RFD Decode Table MFD Value 000 001 010 Multiplication Factor (N) 4 6 8 RFD 000 001 010 Division Factor (R) ÷1 ÷2 ÷4 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 181 Chapter 10 Internal Clock Generator (S08ICGV4) Table 10-12. MFD and RFD Decode Table 011 100 101 110 111 10 12 14 16 18 011 100 101 110 111 ÷8 ÷16 ÷32 ÷64 ÷128 10.6.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38 MHz to achieve 4.19 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (fBus). The clock scheme will be FLL engaged, external (FEE). So fICGOUT = fext * P * N / R ; P = 64, fext = 32 kHz Eqn. 10-1 Solving for N / R gives: N / R = 8.38 MHz /(32 kHz * 64) = 4 ; we can choose N = 4 and R =1 Eqn. 10-2 The values needed in each register to set up the desired operation are: ICGC1 = $38 (%00111000) Bit 7 Bit 6 Bit 5 Bits 4:3 Bit 2 Bit 1 Bit 0 HGO RANGE REFS CLKS OSCSTEN LOCD 0 0 1 11 0 0 0 Configures oscillator for low power Configures oscillator for low-frequency range; FLL prescale factor is 64 Oscillator using crystal or resonator is requested FLL engaged, external reference clock mode Oscillator disabled Loss-of-clock detection enabled Unimplemented or reserved, always reads zero ICGC2 = $00 (%00000000) Bit 7 Bits 6:4 Bit 3 Bits 2:0 LOLRE MFD LOCRE RFD 0 Generates an interrupt request on loss of lock 000 Sets the MFD multiplication factor to 4 0 Generates an interrupt request on loss of clock 000 Sets the RFD division factor to ÷1 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; should read DCOS = 1 before performing any time critical tasks ICGFLTLU/L = $xx MC9S08AC60 Series Data Sheet, Rev. 2 182 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock Bits 15:12 unused 0000 Bits 11:0 FLT No need for user initialization ICGTRM = $xx Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external crystal is clock source Figure 10-14 shows flow charts for three conditions requiring ICG initialization. RESET QUICK RECOVERY FROM STOP RECOVERY FROM STOP OSCSTEN = 1 INITIALIZE ICG ICGC1 = $38 ICGC2 = $00 MINIMUM CURRENT DRAW IN STOP RECOVERY FROM STOP OSCSTEN = 0 CHECK FLL LOCK STATUS. LOCK = 1? YES NO CONTINUE NO CHECK FLL LOCK STATUS. LOCK = 1? YES NO CHECK FLL LOCK STATUS. LOCK = 1? YES CONTINUE CONTINUE NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR AND EXTERNAL CIRCUITRY. Figure 10-14. ICG Initialization for FEE in Example #1 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 183 Chapter 10 Internal Clock Generator (S08ICGV4) 10.6.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to 40-MHz to achieve 20 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus). During reset initialization software, the clock scheme will be set to FLL engaged, external (FEE). So fICGOUT = fext * P * N / R ; P = 1, fext = 4.00 MHz Eqn. 10-3 Solving for N / R gives: N / R = 40 MHz /(4 MHz * 1) = 10 ; We can choose N = 10 and R = 1 Eqn. 10-4 The values needed in each register to set up the desired operation are: ICGC1 = $78 Bit 7 Bit 6 Bit 5 Bits 4:3 Bit 2 Bit 1 Bit 0 (%01111000) 0 1 1 11 0 0 0 Configures oscillator for low power Configures oscillator for high-frequency range; FLL prescale factor is 1 Requests an oscillator FLL engaged, external reference clock mode Disables the oscillator Loss-of-clock detection enabled Unimplemented or reserved, always reads zero HGO RANGE REFS CLKS OSCSTEN LOCD ICGC2 = $30 Bit 7 Bit 6:4 Bit 3 Bit 2:0 (%00110000) 0 Generates an interrupt request on loss of lock 011 Sets the MFD multiplication factor to 10 0 Generates an interrupt request on loss of clock 000 Sets the RFD division factor to ÷1 LOLRE MFD LOCRE RFD ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only. Should read DCOS before performing any time critical tasks ICGFLTLU/L = $xx Not used in this example ICGTRM Not used in this example MC9S08AC60 Series Data Sheet, Rev. 2 184 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) RESET RECOVERY FROM STOP INITIALIZE ICG ICGC1 = $7A ICGC2 = $30 SERVICE INTERRUPT SOURCE (fBus = 4 MHz) CHECK FLL LOCK STATUS LOCK = 1? YES NO CHECK FLL LOCK STATUS LOCK = 1? YES NO CONTINUE CONTINUE Figure 10-15. ICG Initialization and Stop Recovery for Example #2 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 185 Chapter 10 Internal Clock Generator (S08ICGV4) 10.6.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus). The clock scheme will be FLL engaged, internal (FEI). So fICGOUT = (fIRG / 7) * P * N / R ; P = 64, fIRG = 243 kHz Eqn. 10-5 Solving for N / R gives: N / R = 10.8 MHz /(243/7 kHz * 64) = 4.86 ; We can choose N = 10 and R = 2. Eqn. 10-6 A trim procedure will be required to hone the frequency to exactly 5.4 MHz. An example of the trim procedure is shown in example #4. The values needed in each register to set up the desired operation are: ICGC1 = $28 (%00101000) Bit 7 HGO 0 Bit 6 RANGE 0 Bit 5 REFS 1 Bits 4:3 CLKS 01 Bit 2 OSCSTEN 0 Bit 1 LOCD 0 Bit 0 0 Configures oscillator for low power Configures oscillator for low-frequency range; FLL prescale factor is 64 Oscillator using crystal or resonator requested (bit is really a don’t care) FLL engaged, internal reference clock mode Disables the oscillator Loss-of-clock enabled Unimplemented or reserved, always reads zero ICGC2 = $31 (%00110001) Bit 7 LOLRE 0 Generates an interrupt request on loss of lock Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10 Bit 3 LOCRE 0 Generates an interrupt request on loss of clock Bit 2:0 RFD 001 Sets the RFD division factor to ÷2 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only; good idea to read this before performing time critical operations ICGFLTLU/L = $xx Not used in this example MC9S08AC60 Series Data Sheet, Rev. 2 186 Freescale Semiconductor Chapter 10 Internal Clock Generator (S08ICGV4) ICGTRM = $xx Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate operation (see example #4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $28 ICGC2 = $31 CHECK FLL LOCK STATUS. LOCK = 1? YES NO CONTINUE NO CHECK FLL LOCK STATUS. LOCK = 1? YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure 10-16. ICG Initialization and Stop Recovery for Example #3 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 187 Chapter 10 Internal Clock Generator (S08ICGV4) 10.6.5 Example #4: Internal Clock Generator Trim The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. This section outlines one example of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used. Initial conditions: 1) Clock supplied from ATE has 500 μsec duty period 2) ICG configured for internal reference with 4 MHz bus START TRIM PROCEDURE ICGTRM = $80, n = 1 MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 4) COUNT < EXPECTED = 500 (RUNNING TOO SLOW) . CASE STATEMENT COUNT = EXPECTED = 500 COUNT > EXPECTED = 500 (RUNNING TOO FAST) ICGTRM = ICGTRM - 128 / (2**n) (DECREASING ICGTRM INCREASES THE FREQUENCY) ICGTRM = ICGTRM + 128 / (2**n) (INCREASING ICGTRM DECREASES THE FREQUENCY) STORE ICGTRM VALUE IN NON-VOLATILE MEMORY CONTINUE n = n+1 YES IS n > 8? NO Figure 10-17. Trim Procedure In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final test with automated test equipment. A separate signal or message is provided to the MCU operating under user provided software control. The MCU initiates a trim procedure as outlined in Figure 10-17 while the tester supplies a precision reference signal. If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using a reduction divisor (R) twice the final value. After the trim procedure is complete, the reduction divisor can be restored. This will prevent accidental overshoot of the maximum clock frequency. MC9S08AC60 Series Data Sheet, Rev. 2 188 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. For additional detail, please refer to volume 1 of the HCS08 Reference Manual, (Freescale Semiconductor document order number HCS08RMv1/D). The MC9S08AC60 series of microcontrollers has an inter-integrated circuit (IIC) module for communication with other integrated circuits. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 189 Chapter 11 Inter-Integrated Circuit (S08IICV2) PORT A HCS08 CORE ICE DEBUG MODULE (DBG) 8 PTA[7:0] BKGD/MS BDC CPU CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT B 6 HCS08 SYSTEM CONTROL RESET IRQ/TPMCLK RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD TPMCLK VDDAD VSSAD VREFL VREFH USER FLASH 63,280 BYTES 49,152 BYTES 32,768 BYTES 2-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CH1 TPM3CH0 RxD2 TxD2 SDA1 PTB[7:2]/AD1P[7:2] PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 IIC MODULE (IIC1) SCL1 8 AD1P[7:0] PORT D 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) 8 AD1P[15:8] SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USER RAM 2048 BYTES 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CLK TPM1CH[5:2] RxD1 TxD1 TPM2CH1 TPM2CH0 TPM2CLK 3 5 KBI1P[7:5] KBI1P[4:0] PORT E PORT C SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VDD VSS SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) 2-CHANNEL TIMER/PWM MODULE (TPM2) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VOLTAGE REGULATOR EXTAL XTAL PORT G Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. Pin contains integrated pullup device. 4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). 5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 11-1. Block Diagram Highlighting the IIC Module MC9S08AC60 Series Data Sheet, Rev. 2 190 Freescale Semiconductor PORT F Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.1 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection • General call recognition • 10-bit address extension 11.1.2 Modes of Operation A brief description of the IIC in the various MCU modes is given here. • Run mode — This is the basic mode of operation. To conserve power in this mode, disable the module. • Wait mode — The module continues to operate while the MCU is in wait mode and can provide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 191 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1.3 Block Diagram Address Interrupt ADDR_DECODE DATA_MUX Data Bus Figure 11-2 is a block diagram of the IIC. CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 11.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. 11.3 Register Definition This section consists of the IIC register descriptions in address order. MC9S08AC60 Series Data Sheet, Rev. 2 192 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 0 R AD7 W Reset 0 0 0 0 0 0 0 AD6 AD5 AD4 AD3 AD2 AD1 0 0 = Unimplemented or Reserved Figure 11-3. IIC Address Register (IICA) Table 11-1. IICA Field Descriptions Field 7–1 AD[7:1] Description Slave Address. The AD[7:1] field contains the slave address to be used by the IIC module. This field is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 11.3.2 IIC Frequency Divider Register (IICF) 7 6 5 4 3 2 1 0 R MULT W Reset 0 0 0 0 0 0 0 0 ICR Figure 11-4. IIC Frequency Divider Register (IICF) MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 193 Chapter 11 Inter-Integrated Circuit (S08IICV2) Table 11-2. IICF Field Descriptions Field 7–6 MULT Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time. Table 11-4 provides the SCL divider and hold values for corresponding values of the ICR. The SCL divider multiplied by multiplier factor mul generates IIC baud rate. bus speed (Hz) IIC baud rate = -------------------------------------------mul × SCLdivider 5–0 ICR Eqn. 11-1 SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data). SDA hold time = bus period (s) × mul × SDA hold value Eqn. 11-2 SCL start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the falling edge of SCL (IIC clock). SCL Start hold time = bus period (s) × mul × SCL Start hold value SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA SDA (IIC data) while SCL is high (Stop condition). SCL Stop hold time = bus period (s) × mul × SCL Stop hold value Eqn. 11-3 Eqn. 11-4 For example, if the bus speed is 8 MHz, the table below shows the possible hold time values with different ICR and MULT selections to achieve an IIC baud rate of 100kbps. Table 11-3. Hold Time Values for 8 MHz Bus Speed Hold Times (μs) MULT ICR SDA 0x2 0x1 0x1 0x0 0x0 0x00 0x07 0x0B 0x14 0x18 3.500 2.500 2.250 2.125 1.125 SCL Start 3.000 4.000 4.000 4.250 4.750 SCL Stop 5.500 5.250 5.250 5.125 5.125 MC9S08AC60 Series Data Sheet, Rev. 2 194 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) Table 11-4. IIC Divider and Hold Values ICR (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F SCL Divider 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 SDA Hold Value 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 SCL Hold (Start) Value 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 SDA Hold (Stop) Value 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 ICR (hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F SCL Divider 160 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 SDA Hold Value 17 17 33 33 49 49 65 65 33 33 65 65 97 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 SCL Hold (Start) Value 78 94 110 126 142 158 190 238 158 190 222 254 286 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 SCL Hold (Stop) Value 81 97 113 129 145 161 193 241 161 193 225 257 289 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 195 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.3 IIC Control Register (IICC1) 7 6 5 4 3 2 1 0 R IICEN W Reset 0 0 0 0 0 IICIE MST TX TXAK 0 RSTA 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. IIC Control Register (IICC1) Table 11-5. IICC1 Field Descriptions Field 7 IICEN 6 IICIE 5 MST Description IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested. 0 IIC interrupt request not enabled 1 IIC interrupt request enabled Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0 Slave mode 1 Master mode Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high. When addressed as a slave, this bit should be set by software according to the SRW bit in the status register. 0 Receive 1 Transmit Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA during data acknowledge cycles for master and slave receivers. 0 An acknowledge signal is sent out to the bus after receiving one data byte 1 No acknowledge signal response is sent Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. 4 TX 3 TXAK 2 RSTA MC9S08AC60 Series Data Sheet, Rev. 2 196 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.4 IIC Status Register (IICS) 7 6 5 4 3 2 1 0 R W Reset TCF IAAS 1 0 BUSY ARBL 0 0 0 SRW IICIF RXAK 0 0 0 0 = Unimplemented or Reserved Figure 11-6. IIC Status Register (IICS) Table 11-6. IICS Field Descriptions Field 7 TCF Description Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress 1 Transfer complete Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address or when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit. 0 Not addressed 1 Addressed as a slave Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set when a start signal is detected and cleared when a stop signal is detected. 0 Bus is idle 1 Bus is busy Arbitration Lost. This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software by writing a 1 to it. 0 Standard bus operation 1 Loss of arbitration Slave Read/Write. When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the calling address sent to the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit: • One byte transfer completes • Match of slave address to calling address • Arbitration lost 0 No interrupt pending 1 Interrupt pending Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received 6 IAAS 5 BUSY 4 ARBL 2 SRW 1 IICIF 0 RXAK MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 197 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure 11-7. IIC Data I/O Register (IICD) Table 11-7. IICD Field Descriptions Field 7–0 DATA Description Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transitioning out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, reading the IICD does not initiate the receive. Reading the IICD returns the last byte received while the IIC is configured in master receive or slave receive modes. The IICD does not reflect every byte transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back. In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required R/W bit (in position bit 0). 11.3.6 IIC Control Register 2 (IICC2) 7 6 5 4 3 2 1 0 R GCAEN W Reset 0 0 ADEXT 0 0 0 AD10 AD9 0 AD8 0 0 0 0 0 = Unimplemented or Reserved Figure 11-8. IIC Control Register (IICC2) MC9S08AC60 Series Data Sheet, Rev. 2 198 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) Table 11-8. IICC2 Field Descriptions Field 7 GCAEN 6 ADEXT 2–0 AD[10:8] Description General Call Address Enable. The GCAEN bit enables or disables general call address. 0 General call address is disabled 1 General call address is enabled Address Extension. The ADEXT bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address scheme. This field is only valid when the ADEXT bit is set. 11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • Start signal • Slave address transmission • Data transfer • Stop signal The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Figure 11-9. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 199 Chapter 11 Inter-Integrated Circuit (S08IICV2) msb SCL 1 2 3 4 5 6 7 lsb 8 9 msb 1 2 3 4 5 6 7 lsb 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Start Signal Calling Address Read/ Ack Write Bit Data Byte No Ack Bit lsb Stop Signal msb SCL 1 2 3 4 5 6 7 lsb 8 9 msb 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal Calling Address Read/ Ack Write Bit Repeated Start Signal New Calling Address Read/ Write No Ack Bit Stop Signal Figure 11-9. IIC Bus Transmission Signals 11.4.1.1 Start Signal When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a master may initiate communication by sending a start signal. As shown in Figure 11-9, a start signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 11.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure 11-9). No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit an address equal to its own slave address. The IIC cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the IIC reverts to slave mode and operates correctly even if it is being addressed by another master. MC9S08AC60 Series Data Sheet, Rev. 2 200 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 11-9. There is one clock pulse on SCL for each data bit, the msb being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the ninth bit time, the SDA line must be left high by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a stop signal. • Commences a new calling by generating a repeated start signal. 11.4.1.4 Stop Signal The master can terminate the communication by generating a stop signal to free the bus. However, the master may generate a start signal followed by a calling command without generating a stop signal first. This is called repeated start. A stop signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 11-9). The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. 11.4.1.5 Repeated Start Signal As shown in Figure 11-9, a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 201 Chapter 11 Inter-Integrated Circuit (S08IICV2) the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 Clock Synchronization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus. The devices start counting their low period and after a device’s clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 11-10). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. Delay SCL1 Start Counting High Period SCL2 SCL Internal Counter Reset Figure 11-10. IIC Clock Synchronization 11.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 11.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. MC9S08AC60 Series Data Sheet, Rev. 2 202 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.2 10-bit Address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (see Table 11-9). When a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the second byte of the slave address with its own address. Only one slave finds a match and generates an acknowledge (A2). The matching slave remains addressed by the master until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address. S Slave Address 1st 7 bits 11110 + AD10 + AD9 R/W 0 A1 Slave Address 2nd byte AD[8:1] A2 Data A ... Data A/A P Table 11-9. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. 11.4.2.2 Master-Receiver Addresses a Slave-Transmitter The transfer direction is changed after the second R/W bit (see Table 11-10). Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the first seven bits of the first byte of the slave address following Sr are the same as they were after the start condition (S) and tests whether the eighth (R/W) bit is 1. If there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3. The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address. After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not match. S Slave Address 1st 7 bits 11110 + AD10 + AD9 R/W 0 A1 Slave Address 2nd byte AD[8:1] A2 Sr Slave Address 1st 7 bits 11110 + AD10 + AD9 R/W 1 A3 Data A ... Data A P Table 11-10. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 203 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.4.3 General Call Address General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches the general call address as well as its own slave address. When the IIC responds to a general call, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after the first byte transfer to determine whether the address matches is its own slave address or a general call. If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied from a general call address by not issuing an acknowledgement. 11.5 Resets The IIC is disabled after reset. The IIC cannot cause an MCU reset. 11.6 Interrupts The IIC generates a single interrupt. An interrupt from the IIC is generated when any of the events in Table 11-11 occur, provided the IICIE bit is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You can determine the interrupt type by reading the status register. Table 11-11. Interrupt Summary Interrupt Source Complete 1-byte transfer Match of received calling address Arbitration Lost Status TCF IAAS ARBL Flag IICIF IICIF IICIF Local Enable IICIE IICIE IICIE 11.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. 11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 11.6.3 Arbitration Lost Interrupt The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. MC9S08AC60 Series Data Sheet, Rev. 2 204 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing a 1 to it. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 205 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.7 1. Initialization/Application Information Module Initialization (Slave) Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode Write: IICA — to set the slave address Write: IICC1 — to enable IIC and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in Figure 11-12 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7. Module Initialization (Master) Write: IICF — to set the IIC baud rate (example provided in this chapter) Write: IICC1 — to enable IIC and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in Figure 11-12 Write: IICC1 — to enable TX Write: IICC1 — to enable MST (master mode) Write: IICD — with the address of the target slave. (The lsb of this byte determines whether the communication is master receive or transmit.) Module Use The routine shown in Figure 11-12 can handle both master and slave IIC operations. For slave operation, an incoming IIC message that contains the proper address begins IIC communication. For master operation, communication must be initiated by writing to the IICD register. Register Model IICA MULT AD[7:1] 0 When addressed as a slave (in slave mode), the module responds to this address IICF ICR Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER)) IICC1 IICS IICD IICEN TCF IICIE IAAS MST BUSY TX ARBL DATA Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT Address configuration 0 0 0 AD10 AD9 AD8 TXAK 0 RSTA SRW 0 IICIF 0 RXAK Module configuration Module status flags Figure 11-11. IIC Module Quick Start MC9S08AC60 Series Data Sheet, Rev. 2 206 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) Clear IICIF Y Master Mode ? N TX Tx/Rx ? RX Y Arbitration Lost ? N Last Byte Transmitted ? N Y Clear ARBL RXAK=0 ? Y N Last Byte to Be Read ? N N Y IAAS=1 ? Y Y IAAS=1 ? N Data Transfer See Note 2 TX/RX ? TX RX Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? N Y 2nd Last Byte to Be Read ? N Y (Read) SRW=1 ? N (Write) Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) Set TX Mode Y ACK from Receiver ? N Read Data from IICD and Store Write Data to IICD Tx Next Byte Switch to Rx Mode Set RX Mode Switch to Rx Mode Dummy Read from IICD Generate Stop Signal (MST = 0) Read Data from IICD and Store Dummy Read from IICD Dummy Read from IICD RTI NOTES: 1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a general call address, then the general call must be handled by user software. 2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Figure 11-12. Typical IIC Interrupt Routine MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 207 Chapter 11 Inter-Integrated Circuit (S08IICV2) MC9S08AC60 Series Data Sheet, Rev. 2 208 Freescale Semiconductor Chapter 12 Keyboard Interrupt (S08KBIV1) 12.1 Introduction The MC9S08AC60 Series has one KBI module with upto eight keyboard interrupt inputs available depending on package. 12.1.1 Features The keyboard interrupt (KBI) module features include: • Four falling edge/low level sensitive • Four falling edge/low level or rising edge/high level sensitive • Choice of edge-only or edge-and-level sensitivity • Common interrupt flag and interrupt enable control • Capable of waking up the MCU from stop3 or wait mode MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 209 Chapter 12 Keyboard Interrupt (S08KBIV1) PORT A HCS08 CORE ICE DEBUG MODULE (DBG) 8 PTA[7:0] BKGD/MS BDC CPU CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT B 6 HCS08 SYSTEM CONTROL RESET IRQ/TPMCLK RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD TPMCLK VDDAD VSSAD VREFL VREFH USER FLASH 63,280 BYTES 49,152 BYTES 32,768 BYTES 2-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CH1 TPM3CH0 RxD2 TxD2 SDA1 PTB[7:2]/AD1P[7:2] PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 IIC MODULE (IIC1) SCL1 8 AD1P[7:0] PORT D 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) 8 AD1P[15:8] SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USER RAM 2048 BYTES 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CLK TPM1CH[5:2] RxD1 TxD1 TPM2CH1 TPM2CH0 TPM2CLK 3 5 KBI1P[7:5] KBI1P[4:0] PORT E PORT C SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VDD VSS SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) 2-CHANNEL TIMER/PWM MODULE (TPM2) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VOLTAGE REGULATOR EXTAL XTAL PORT G Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. Pin contains integrated pullup device. 4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). 5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 12-1. Block Diagram Highlighting KBI Module MC9S08AC60 Series Data Sheet, Rev. 2 210 Freescale Semiconductor PORT F Chapter 12 Keyboard Interrupt (S08KBIV1) 12.1.2 KBIP0 KBI Block Diagram Figure 12-2 shows the block diagram for a KBI module. KBIPE0 KBIP3 KBIPE3 1 KBIP4 0 S KBIPE4 KEYBOARD INTERRUPT FF KBIMOD KBIE S KBIPEn STOP STOP BYPASS KEYBOARD INTERRUPT REQUEST VDD D CLR Q CK KBACK RESET SYNCHRONIZER BUSCLK KBF KBEDG4 1 KBIPn 0 KBEDGn Figure 12-2. KBI Block Diagram 12.2 Register Definition This section provides information about all registers and control bits associated with the KBI module. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 211 Chapter 12 Keyboard Interrupt (S08KBIV1) 12.2.1 R KBI Status and Control Register (KBISC) 7 6 5 4 3 2 1 0 KBF KBEDG7 KBEDG6 0 KBEDG5 0 KBEDG4 0 KBIE KBACK KBIMOD 0 W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 12-3. KBI Status and Control Register (KBISC) Table 12-1. KBISC Register Field Descriptions Field Description 7:4 Keyboard Edge Select for KBI Port Bits — Each of these read/write bits selects the polarity of the edges and/or KBEDG[7:4] levels that are recognized as trigger events on the corresponding KBI port pin when it is configured as a keyboard interrupt input (KBIPEn = 1). Also see the KBIMOD control bit, which determines whether the pin is sensitive to edges-only or edges and levels. 0 Falling edges/low levels 1 Rising edges/high levels 3 KBF Keyboard Interrupt Flag — This read-only status flag is set whenever the selected edge event has been detected on any of the enabled KBI port pins. This flag is cleared by writing a 1 to the KBACK control bit. The flag will remain set if KBIMOD = 1 to select edge-and-level operation and any enabled KBI port pin remains at the asserted level. KBF can be used as a software pollable flag (KBIE = 0) or it can generate a hardware interrupt request to the CPU (KBIE = 1). 0 No KBI interrupt pending 1 KBI interrupt pending Keyboard Interrupt Acknowledge — This write-only bit (reads always return 0) is used to clear the KBF status flag by writing a 1 to KBACK. When KBIMOD = 1 to select edge-and-level operation and any enabled KBI port pin remains at the asserted level, KBF is being continuously set so writing 1 to KBACK does not clear the KBF flag. Keyboard Interrupt Enable — This read/write control bit determines whether hardware interrupts are generated when the KBF status flag equals 1. When KBIE = 0, no hardware interrupts are generated, but KBF can still be used for software polling. 0 KBF does not generate hardware interrupts (use polling) 1 KBI hardware interrupt requested when KBF = 1 Keyboard Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level detection. KBI port bits 3 through 0 can detect falling edges-only or falling edges and low levels. KBI port bits 7 through 4 can be configured to detect either: • Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = 0) 0 Edge-only detection 1 Edge-and-level detection 2 KBACK 1 KBIE KBIMOD MC9S08AC60 Series Data Sheet, Rev. 2 212 Freescale Semiconductor Chapter 12 Keyboard Interrupt (S08KBIV1) 12.2.2 R KBI Pin Enable Register (KBIPE) 7 6 5 4 3 2 1 0 KBIPE7 W Reset 0 KBIPE6 0 KBIPE5 0 KBIPE4 0 KBIPE3 0 KBIPE2 0 KBIPE1 0 KBIPE0 0 = Unimplemented or Reserved Figure 12-4. KBI Pin Enable Register (KBIPE) Table 12-2. KBIPE Register Field Descriptions Field 7:0 KBIPE[7:0] Description Keyboard Pin Enable for KBI Port Bits — Each of these read/write bits selects whether the associated KBI port pin is enabled as a keyboard interrupt input or functions as a general-purpose I/O pin. 0 Bit n of KBI port is a general-purpose I/O pin not associated with the KBI 1 Bit n of KBI port enabled as a keyboard interrupt input 12.3 12.3.1 Functional Description Pin Enables The KBIPEn control bits in the KBIPE register allow a user to enable (KBIPEn = 1) any combination of KBI-related port pins to be connected to the KBI module. Pins corresponding to 0s in KBIPE are general-purpose I/O pins that are not associated with the KBI module. 12.3.2 Edge and Level Sensitivity Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI module must be at the deasserted logic level. A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. The KBIMOD control bit can be set to reconfigure the detection logic so that it detects edges and levels. In KBIMOD = 1 mode, the KBF status flag becomes set when an edge is detected (when one or more enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their deasserted levels), but the flag is continuously set (and cannot be cleared) as long as any enabled keyboard input pin remains at the asserted level. When the MCU enters stop mode, the synchronous edge-detection logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous level-sensitive inputs so they can wake the MCU from stop mode. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 213 Chapter 12 Keyboard Interrupt (S08KBIV1) 12.3.3 KBI Interrupt Controls The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If KBIE = 1 in the KBISC register, a hardware interrupt will be requested whenever KBF = 1. The KBF flag is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit. When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK. When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard input is at its asserted level. MC9S08AC60 Series Data Sheet, Rev. 2 214 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) 13.1 Introduction The MC9S08AC60 Series includes up to two independent serial communications interface (SCI) modules depending on package. An SCI is sometimes called universal asynchronous receiver/transmitters (UARTs). For the MC9S08AC60 Series, stop1 is not a valid mode, so ignore these references. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 215 Chapter 13 Serial Communications Interface (S08SCIV4) PORT A HCS08 CORE ICE DEBUG MODULE (DBG) 8 PTA[7:0] BKGD/MS BDC CPU CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT B 6 HCS08 SYSTEM CONTROL RESET IRQ/TPMCLK RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD TPMCLK VDDAD VSSAD VREFL VREFH USER FLASH 63,280 BYTES 49,152 BYTES 32,768 BYTES 2-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CH1 TPM3CH0 RxD2 TxD2 SDA1 PTB[7:2]/AD1P[7:2] PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 IIC MODULE (IIC1) SCL1 8 AD1P[7:0] PORT D 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) 8 AD1P[15:8] SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USER RAM 2048 BYTES 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CLK TPM1CH[5:2] RxD1 TxD1 TPM2CH1 TPM2CH0 TPM2CLK 3 5 KBI1P[7:5] KBI1P[4:0] PORT E PORT C SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VDD VSS SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) 2-CHANNEL TIMER/PWM MODULE (TPM2) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VOLTAGE REGULATOR EXTAL XTAL PORT G Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. Pin contains integrated pullup device. 4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). 5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 13-1. Block Diagram Highlighting the SCI Modules MC9S08AC60 Series Data Sheet, Rev. 2 216 Freescale Semiconductor PORT F Chapter 13 Serial Communications Interface (S08SCIV4) 13.1.1 Features Features of SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect — Active edge on receive pin — Break detect supporting LIN • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wakeup by idle-line or address-mark • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity 13.1.2 Modes of Operation See Section 13.3, “Functional Description,” For details concerning SCI operation in these modes: • 8- and 9-bit data modes • Stop mode operation • Loop mode • Single-wire mode MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 217 Chapter 13 Serial Communications Interface (S08SCIV4) 13.1.3 Block Diagram INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER RSRC LOOP CONTROL Figure 13-2 shows the transmitter portion of the SCI. 11-BIT TRANSMIT SHIFT REGISTER START STOP M TO RECEIVE DATA IN SHIFT DIRECTION LSB 1 × BAUD RATE CLOCK H 8 7 6 5 4 3 2 1 0 L TO TxD PIN TXINV PREAMBLE (ALL 1s) LOAD FROM SCIxD T8 PE PT PARITY GENERATION BREAK (ALL 0s) SCI CONTROLS TxD TE SBK TXDIR BRK13 TRANSMIT CONTROL SHIFT ENABLE TxD DIRECTION TO TxD PIN LOGIC TDRE TIE TC TCIE Tx INTERRUPT REQUEST Figure 13-2. SCI Transmitter Block Diagram MC9S08AC60 Series Data Sheet, Rev. 2 218 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) Figure 13-3 shows the receiver portion of the SCI. INTERNAL BUS (READ-ONLY) 16 × BAUD RATE CLOCK FROM TRANSMITTER SINGLE-WIRE LOOP CONTROL STOP M LBKDE ALL 1s DATA RECOVERY MSB LSB 8 7 6 5 4 3 2 1 0 SHIFT DIRECTION RWU RWUID RDRF RIE IDLE ILIE LBKDIF LBKDIE RXEDGIF RXEDGIE OR ORIE FE FEIE NF NEIE PE PT PARITY CHECKING PF PEIE ERROR INTERRUPT REQUEST Rx INTERRUPT REQUEST LOOPS RSRC FROM RxD PIN RXINV START L 11-BIT RECEIVE SHIFT REGISTER DIVIDE BY 16 SCID – Rx BUFFER H WAKE ILT ACTIVE EDGE DETECT WAKEUP LOGIC Figure 13-3. SCI Receiver Block Diagram MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 219 Chapter 13 Serial Communications Interface (S08SCIV4) 13.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written. SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1). 7 6 5 4 3 2 1 0 R LBKDIE W Reset 0 0 RXEDGIE 0 SBR12 0 0 SBR11 0 SBR10 0 SBR9 0 SBR8 0 = Unimplemented or Reserved Figure 13-4. SCI Baud Rate Register (SCIxBDH) Table 13-1. SCIxBDH Field Descriptions Field 7 LBKDIE 6 RXEDGIE 4:0 SBR[12:8] Description LIN Break Detect Interrupt Enable (for LBKDIF) 0 Hardware interrupts from LBKDIF disabled (use polling). 1 Hardware interrupt requested when LBKDIF flag is 1. RxD Input Active Edge Interrupt Enable (for RXEDGIF) 0 Hardware interrupts from RXEDGIF disabled (use polling). 1 Hardware interrupt requested when RXEDGIF flag is 1. Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 13-2. MC9S08AC60 Series Data Sheet, Rev. 2 220 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) 7 6 5 4 3 2 1 0 R SBR7 W Reset 0 0 0 0 0 1 0 0 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Figure 13-5. SCI Baud Rate Register (SCIxBDL) Table 13-2. SCIxBDL Field Descriptions Field 7:0 SBR[7:0] Description Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 13-1. 13.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 R LOOPS W Reset 0 0 0 0 0 0 0 0 SCISWAI RSRC M WAKE ILT PE PT Figure 13-6. SCI Control Register 1 (SCIxC1) Table 13-3. SCIxC1 Field Descriptions Field 7 LOOPS Description Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. SCI Stops in Wait Mode 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU. 1 SCI clocks freeze while CPU is in wait mode. Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins. 1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. 9-Bit or 8-Bit Mode Select 0 Normal — start + 8 data bits (LSB first) + stop. 1 Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop. 6 SCISWAI 5 RSRC 4 M MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 221 Chapter 13 Serial Communications Interface (S08SCIV4) Table 13-3. SCIxC1 Field Descriptions (continued) Field 3 WAKE Description Receiver Wakeup Method Select — Refer to Section 13.3.3.2, “Receiver Wakeup Operation” for more information. 0 Idle-line wakeup. 1 Address-mark wakeup. Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section 13.3.3.2.1, “Idle-Line Wakeup” for more information. 0 Idle character bit count starts after start bit. 1 Idle character bit count starts after stop bit. Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. 2 ILT 1 PE 0 PT 13.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R TIE W Reset 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK Figure 13-7. SCI Control Register 2 (SCIxC2) Table 13-4. SCIxC2 Field Descriptions Field 7 TIE 6 TCIE 5 RIE 4 ILIE Description Transmit Interrupt Enable (for TDRE) 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1. Transmission Complete Interrupt Enable (for TC) 0 Hardware interrupts from TC disabled (use polling). 1 Hardware interrupt requested when TC flag is 1. Receiver Interrupt Enable (for RDRF) 0 Hardware interrupts from RDRF disabled (use polling). 1 Hardware interrupt requested when RDRF flag is 1. Idle Line Interrupt Enable (for IDLE) 0 Hardware interrupts from IDLE disabled (use polling). 1 Hardware interrupt requested when IDLE flag is 1. MC9S08AC60 Series Data Sheet, Rev. 2 222 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) Table 13-4. SCIxC2 Field Descriptions (continued) Field 3 TE Description Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress. Refer to Section 13.3.2.1, “Send Break and Queued Idle” for more details. When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. 0 Receiver off. 1 Receiver on. Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer to Section 13.3.3.2, “Receiver Wakeup Operation” for more details. 0 Normal SCI receiver operation. 1 SCI receiver in standby waiting for wakeup condition. Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Refer to Section 13.3.2.1, “Send Break and Queued Idle” for more details. 0 Normal transmitter operation. 1 Queue break character(s) to be sent. 2 RE 1 RWU 0 SBK 13.2.4 SCI Status Register 1 (SCIxS1) This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status flags. 7 6 5 4 3 2 1 0 R W Reset TDRE TC RDRF IDLE OR NF FE PF 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-8. SCI Status Register 1 (SCIxS1) MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 223 Chapter 13 Serial Communications Interface (S08SCIV4) Table 13-5. SCIxS1 Field Descriptions Field 7 TDRE Description Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty. Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being transmitted. 0 Transmitter active (sending data, a preamble, or a break). 1 Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIxS1 with TC = 1 and then doing one of the following three things: • Write to the SCI data register (SCIxD) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SBK in SCIxC2 Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full. Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. To clear IDLE, read SCIxS1 with IDLE = 1 and then read the SCI data register (SCIxD). After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if the receive line remains idle for an extended period. 0 No idle line detected. 1 Idle line was detected. Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from SCIxD yet. In this case, the new character (and all associated error information) is lost because there is no room to move it into SCIxD. To clear OR, read SCIxS1 with OR = 1 and then read the SCI data register (SCIxD). 0 No overrun. 1 Receive overrun (new SCI data lost). Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No noise detected. 1 Noise detected in the received character in SCIxD. 6 TC 5 RDRF 4 IDLE 3 OR 2 NF MC9S08AC60 Series Data Sheet, Rev. 2 224 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) Table 13-5. SCIxS1 Field Descriptions (continued) Field 1 FE Description Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE = 1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error. Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, read SCIxS1 and then read the SCI data register (SCIxD). 0 No parity error. 1 Parity error. 0 PF 13.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. 7 6 5 4 3 2 1 0 R LBKDIF W Reset 0 0 RXEDGIF 0 RXINV 0 0 RWUID 0 BRK13 0 LBKDE 0 RAF 0 = Unimplemented or Reserved Figure 13-9. SCI Status Register 2 (SCIxS2) Table 13-6. SCIxS2 Field Descriptions Field 7 LBKDIF Description LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected. LBKDIF is cleared by writing a “1” to it. 0 No LIN break character has been detected. 1 LIN break character has been detected. RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it. 0 No active edge on the receive pin has occurred. 1 An active edge on the receive pin has occurred. Receive Data Inversion — Setting this bit reverses the polarity of the received data input. 0 Receive data not inverted 1 Receive data inverted Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit. 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. Break Character Generation Length — BRK13 is used to select a longer transmitted break character length. Detection of a framing error is not affected by the state of this bit. 0 Break character is transmitted with length of 10 bit times (11 if M = 1) 1 Break character is transmitted with length of 13 bit times (14 if M = 1) 6 RXEDGIF 4 RXINV1 3 RWUID 2 BRK13 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 225 Chapter 13 Serial Communications Interface (S08SCIV4) Table 13-6. SCIxS2 Field Descriptions (continued) Field 1 LBKDE Description LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1). Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an SCI character is being received before instructing the MCU to go to stop mode. 0 SCI receiver idle waiting for a start bit. 1 SCI receiver active (RxD input not idle). 0 RAF 1 Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle. When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol. 13.2.6 SCI Control Register 3 (SCIxC3) 7 6 5 4 3 2 1 0 R W Reset R8 T8 0 0 TXDIR 0 TXINV 0 ORIE 0 NEIE 0 FEIE 0 PEIE 0 = Unimplemented or Reserved Figure 13-10. SCI Control Register 3 (SCIxC3) Table 13-7. SCIxC3 Field Descriptions Field 7 R8 Description Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the MSB of the buffered data in the SCIxD register. When reading 9-bit data, read R8 before reading SCIxD because reading SCIxD completes automatic flag clearing sequences which could allow R8 and SCIxD to be overwritten with new data. Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the left of the MSB of the data in the SCIxD register. When writing 9-bit data, the entire 9-bit value is transferred to the SCI shift register after SCIxD is written so T8 should be written (if it needs to change from its previous value) before SCIxD is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCIxD is written. TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. 6 T8 5 TXDIR MC9S08AC60 Series Data Sheet, Rev. 2 226 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) Table 13-7. SCIxC3 Field Descriptions (continued) Field 4 TXINV1 3 ORIE 2 NEIE 1 FEIE Description Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1. Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. 0 NF interrupts disabled (use polling). 1 Hardware interrupt requested when NF = 1. Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt requests. 0 FE interrupts disabled (use polling). 1 Hardware interrupt requested when FE = 1. Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests. 0 PF interrupts disabled (use polling). 1 Hardware interrupt requested when PF = 1. 0 PEIE 1 Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle. 13.2.7 SCI Data Register (SCIxD) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. 7 6 5 4 3 2 1 0 R W Reset R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 0 Figure 13-11. SCI Data Register (SCIxD) 13.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI. 13.3.1 Baud Rate Generation As shown in Figure 13-12, the clock source for the SCI baud rate generator is the bus-rate clock. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 227 Chapter 13 Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY 16 Tx BAUD RATE BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] × 16 Figure 13-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5percent for 8-bit data format and about 4 percent for 9-bit data format. Although baud rate modulo di ider settings do not always v produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 13.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown in Figure 13-2. The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIxC2. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the SCI data register (SCIxD). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0, selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCIxD. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. MC9S08AC60 Series Data Sheet, Rev. 2 228 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 13.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE = 1) occurs. When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below. Table 13-8. Break Character Length BRK13 0 0 1 1 M 0 1 0 1 Break Character Length 10 bit times 11 bit times 13 bit times 14 bit times 13.3.3 Receiver Functional Description In this section, the receiver block diagram (Figure 13-3) is used as a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained. The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to Section 13.3.5.1, “8- and 9-Bit Data Modes.” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 229 Chapter 13 Serial Communications Interface (S08SCIV4) flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section 13.3.4, “Interrupts and Status Flags” for more details about flag clearing. 13.3.3.1 Data Sampling Technique The SCI receiver uses a 16× baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 13.3.3.2 Receiver Wakeup Operation Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU bit is set, the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant MC9S08AC60 Series Data Sheet, Rev. 2 230 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 13.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE flag. The receiver wakes up and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether RWU is zero or one. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 13.3.3.2.2 Address-Mark Wakeup When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is received and sets the RDRF flag. In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time. 13.3.4 Interrupts and Status Flags The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 231 Chapter 13 Serial Communications Interface (S08SCIV4) Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD. When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains idle for an extended period of time. IDLE is cleared by reading SCIxS1 while IDLE = 1 and then reading SCIxD. After IDLE has been cleared, it cannot become set again until the receiver has received at least one new character and has set RDRF. If the associated error was detected in the received character that caused RDRF to be set, the error flags — noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF. These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE, or PF condition is lost. At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled (RE = 1). 13.3.5 Additional SCI Functions The following sections describe additional SCI functions. 13.3.5.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is held in R8 in SCIxC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD. If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. MC9S08AC60 Series Data Sheet, Rev. 2 232 Freescale Semiconductor Chapter 13 Serial Communications Interface (S08SCIV4) 13.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. . An active edge on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1). Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module. 13.3.5.3 Loop Mode When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 13.3.5.4 Single-Wire Operation When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used and reverts to a general-purpose port I/O pin. In single-wire mode, the TXDIR bit in SCIxC3 controls the direction of serial data on the TxD pin. When TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 233 Chapter 13 Serial Communications Interface (S08SCIV4) MC9S08AC60 Series Data Sheet, Rev. 2 234 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (S08SPIV3) 14.1 Introduction The MC9S08AC60 Series has one serial peripheral interface (SPI) module. See Appendix A, “Electrical Characteristics and Timing Specifications,” for SPI electrical parametric information. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 235 Chapter 14 Serial Peripheral Interface (S08SPIV3) PORT A HCS08 CORE ICE DEBUG MODULE (DBG) 8 PTA[7:0] BKGD/MS BDC CPU CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT B 6 HCS08 SYSTEM CONTROL RESET IRQ/TPMCLK RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD TPMCLK VDDAD VSSAD VREFL VREFH USER FLASH 63,280 BYTES 49,152 BYTES 32,768 BYTES 2-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CH1 TPM3CH0 RxD2 TxD2 SDA1 PTB[7:2]/AD1P[7:2] PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 IIC MODULE (IIC1) SCL1 8 AD1P[7:0] PORT D 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) 8 AD1P[15:8] SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USER RAM 2048 BYTES 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CLK TPM1CH[5:2] RxD1 TxD1 TPM2CH1 TPM2CH0 TPM2CLK 3 5 KBI1P[7:5] KBI1P[4:0] PORT E PORT C SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VDD VSS SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) 2-CHANNEL TIMER/PWM MODULE (TPM2) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VOLTAGE REGULATOR EXTAL XTAL PORT G Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. Pin contains integrated pullup device. 4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). 5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 14-1. Block Diagram Highlighting the SPI Module MC9S08AC60 Series Data Sheet, Rev. 2 236 Freescale Semiconductor PORT F Chapter 14 Serial Peripheral Interface (S08SPIV3) 14.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 14.1.2 Block Diagrams This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate. 14.1.2.1 SPI System Block Diagram Figure 14-2 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave select output. MASTER MOSI SPI SHIFTER 7 6 5 4 3 2 1 0 MISO MISO 7 MOSI SLAVE SPI SHIFTER 6 5 4 3 2 1 0 SPSCK SPSCK CLOCK GENERATOR SS SS Figure 14-2. SPI System Connections MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 237 Chapter 14 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 14-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 14.1.2.2 SPI Module Block Diagram Figure 14-3 is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls connections between MCU pins and the SPI module. When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. MC9S08AC60 Series Data Sheet, Rev. 2 238 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM SHIFT OUT SPI SHIFT REGISTER SHIFT IN SPC0 BIDIROE LSBFE SHIFT DIRECTION SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY M S MISO (SISO) S MOSI (MOMI) Rx BUFFER (READ SPID) MASTER CLOCK BUS RATE CLOCK MSTR SPIBR CLOCK GENERATOR MASTER/SLAVE MODE SELECT MODFEN MODE FAULT DETECTION SSOE CLOCK LOGIC SLAVE CLOCK M SPSCK S MASTER/ SLAVE SS SPRF SPTEF SPTIE SPI INTERRUPT REQUEST MODF SPIE Figure 14-3. SPI Module Block Diagram 14.1.3 SPI Baud Rate Generation As shown in Figure 14-4, the clock source for the SPI baud rate generator is the bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal SPI master mode bit-rate clock. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 239 Chapter 14 Serial Peripheral Interface (S08SPIV3) PRESCALER BUS CLOCK DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 CLOCK RATE DIVIDER DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 MASTER SPI BIT RATE SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure 14-4. SPI Baud Rate Generation 14.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that are not controlled by the SPI. 14.2.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 14.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 14.2.3 MISO — Master Data In, Slave Data Out When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. 14.2.4 SS — Slave Select When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select output (SSOE = 1). MC9S08AC60 Series Data Sheet, Rev. 2 240 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (S08SPIV3) 14.3 14.3.1 Modes of Operation SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected. If stop3 is exited with a reset, the SPI will be put into its reset state. If stop3 is exited with an interrupt, the SPI continues from the state it was in when stop3 was entered. 14.4 Register Definition The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SPI registers. This section refers to registers and control bits only by their names, and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.4.1 SPI Control Register 1 (SPIC1) This read/write register includes the SPI enable control, interrupt enables, and configuration options. 7 6 5 4 3 2 1 0 R SPIE W Reset 0 0 0 0 0 1 0 0 SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Figure 14-5. SPI Control Register 1 (SPIC1) Table 14-1. SPIC1 Field Descriptions Field 7 SPIE Description SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF) and mode fault (MODF) events. 0 Interrupts from SPRF and MODF inhibited (use polling) 1 When SPRF or MODF is 1, request a hardware interrupt SPI System Enable — Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty. 0 SPI system inactive 1 SPI system enabled SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). 0 Interrupts from SPTEF inhibited (use polling) 1 When SPTEF is 1, hardware interrupt requested 6 SPE 5 SPTIE MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 241 Chapter 14 Serial Peripheral Interface (S08SPIV3) Table 14-1. SPIC1 Field Descriptions (continued) Field 4 MSTR 3 CPOL Description Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 14.5.1, “SPI Clock Formats” for more details. 0 Active-high SPI clock (idles low) 1 Active-low SPI clock (idles high) Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer to Section 14.5.1, “SPI Clock Formats” for more details. 0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer 1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in SPCR2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 14-2. LSB First (Shifter Direction) 0 SPI serial data transfers start with most significant bit 1 SPI serial data transfers start with least significant bit 2 CPHA 1 SSOE 0 LSBFE Table 14-2. SS Pin Function MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode General-purpose I/O (not SPI) General-purpose I/O (not SPI) SS input for mode fault Automatic SS output Slave Mode Slave select input Slave select input Slave select input Slave select input NOTE Ensure that the SPI should not be disabled (SPE=0) at the same time as a bit change to the CPHA bit. These changes should be performed as separate operations or unexpected behavior may occur. 14.4.2 SPI Control Register 2 (SPIC2) This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not implemented and always read 0. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 MODFEN BIDIROE 0 0 SPISWAI 0 0 SPC0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-6. SPI Control Register 2 (SPIC2) MC9S08AC60 Series Data Sheet, Rev. 2 242 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (S08SPIV3) Table 14-3. SPIC2 Register Field Descriptions Field 4 MODFEN Description Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 14-2 for more details). 0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1, BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO (SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect. 0 Output driver disabled so SPI data I/O pin acts as an input 1 SPI I/O pin enabled as an output SPI Stop in Wait Mode 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the output driver for the single bidirectional SPI I/O pin. 0 SPI uses separate pins for data input and data output 1 SPI configured for single-wire bidirectional operation 3 BIDIROE 1 SPISWAI 0 SPC0 14.4.3 SPI Baud Rate Register (SPIBR) This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time. 7 6 5 4 3 2 1 0 R W Reset 0 SPPR2 0 0 SPPR1 0 SPPR0 0 0 SPR2 0 0 SPR1 0 SPR0 0 = Unimplemented or Reserved Figure 14-7. SPI Baud Rate Register (SPIBR) Table 14-4. SPIBR Register Field Descriptions Field 6:4 SPPR[2:0] 2:0 SPR[2:0] Description SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler as shown in Table 14-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider (see Figure 14-4). SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in Table 14-6. The input to this divider comes from the SPI baud rate prescaler (see Figure 14-4). The output of this divider is the SPI bit rate clock for master mode. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 243 Chapter 14 Serial Peripheral Interface (S08SPIV3) Table 14-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Prescaler Divisor 1 2 3 4 5 6 7 8 Table 14-6. SPI Baud Rate Divisor SPR2:SPR1:SPR0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Rate Divisor 2 4 8 16 32 64 128 256 14.4.4 SPI Status Register (SPIS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0. Writes have no meaning or effect. 7 6 5 4 3 2 1 0 R W Reset SPRF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure 14-8. SPI Status Register (SPIS) MC9S08AC60 Series Data Sheet, Rev. 2 244 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (S08SPIV3) Table 14-7. SPIS Register Field Descriptions Field 7 SPRF Description SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register. 0 No data available in the receive data buffer 1 Data available in the receive data buffer SPI Transmit Buffer Empty Flag — This bit is set when there is room in the transmit data buffer. It is cleared by reading SPIS with SPTEF set, followed by writing a data value to the transmit buffer at SPID. SPIS must be read with SPTEF = 1 before writing data to SPID or the SPID write will be ignored. SPTEF generates an SPTEF CPU interrupt request if the SPTIE bit in the SPIC1 is also set. SPTEF is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift register and no transfer in progress), data written to SPID is transferred to the shifter almost immediately so SPTEF is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and SPTEF will be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter. 0 SPI transmit buffer not empty 1 SPI transmit buffer empty Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading MODF while it is 1, then writing to SPI control register 1 (SPIC1). 0 No mode fault error 1 Mode fault error detected 5 SPTEF 4 MODF 14.4.5 R SPI Data Register (SPID) 7 6 5 4 3 2 1 0 Bit 7 W Reset 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Figure 14-9. SPI Data Register (SPID) Reads of this register return the data read from the receive data buffer. Writes to this register write data to the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer initiates an SPI transfer. Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag (SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte. Data may be read from SPID any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 245 Chapter 14 Serial Peripheral Interface (S08SPIV3) 14.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts. During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, SPTEF is set, and a new transfer is started. Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable (LSBFE) bit is set, SPI data is shifted LSB first. When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See Section 14.5.1, “SPI Clock Formats” for more details. Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the transmit buffer has room for a new character. The SPRF flag indicates when a received character is available in the receive data buffer. The received character must be read out of the receive buffer (read SPID) before the next transfer is finished or a receive overrun error results. In the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 14.5.1 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. Figure 14-10 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle after the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output MC9S08AC60 Series Data Sheet, Rev. 2 246 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (S08SPIV3) pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SS OUT (MASTER) SS IN (SLAVE) Figure 14-10. SPI Clock Formats (CPHA = 1) When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive high level between transfers. Figure 14-11 shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 247 Chapter 14 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low at the start of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) SPSCK (CPOL = 0) 1 2 ... 6 7 8 SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 SS OUT (MASTER) SS IN (SLAVE) Figure 14-11. SPI Clock Formats (CPHA = 0) When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CPHA = 0, the slave’s SS input must go to its inactive high level between transfers. MC9S08AC60 Series Data Sheet, Rev. 2 248 Freescale Semiconductor Chapter 14 Serial Peripheral Interface (S08SPIV3) 14.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should check the flag bits to determine what event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 14.5.3 Mode Fault Detection A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1), and slave select output enable is clear (SSOE = 0). The mode fault detection feature can be used in a system where more than one SPI device might become a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected. When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled. MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User software should verify the error condition has been corrected before changing the SPI back to master mode. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 249 Chapter 14 Serial Peripheral Interface (S08SPIV3) MC9S08AC60 Series Data Sheet, Rev. 2 250 Freescale Semiconductor Chapter 15 Timer/PWM (S08TPMV3) 15.1 Introduction The MC9S08AC60 Series includes three independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. The timer system in the MC9S08AC60 Series includes a 6-channel TPM1, a separate 2-channel TPM2 and a separate 2-channel TPM3. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions. In each TPM, timing functions are based on a separate 16-bit counter with prescaler and modulo features to control frequency and range (period between overflows) of the time reference. The use of the fixed system clock, XCLK, as the clock source for any of the TPM modules allows the TPM prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This option is only available if the ICG is configured in FEE mode and the proper conditions are met (see Chapter 10, “Internal Clock Generator (S08ICGV4)”). In all other ICG modes this selection is redundant because XCLK is the same as BUSCLK. An external clock source can be connected to the TPMxCLK pin. The maximum frequency for TPMxCLK is the bus clock frequency divided by 4. For the MC9S08AC60 Series, TPMCLK, TPM1CLK, and TPM2CLK options are configured via software using the TPMCCFG bit in the SOPT2 register; out of reset, TPM1CLK, and TPM2CLK, and TPMCLK is connected to TPM1, TPM2, and TPM3 respectively. (TPMCCFG = 1). 15.2 Features Timer system features include: • Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system clock, or an external pin. • 16-bit free-running or up/down (CPWM) count operation • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus a terminal count interrupt for each TPM module • Each channel may be input capture, output compare, or buffered edge-aligned PWM • Rising-edge, falling-edge, or any-edge input capture trigger • Set, clear, or toggle output compare action • Selectable polarity on PWM outputs • Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all channels MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 251 Chapter 15 Timer/PWM (S08TPMV3) PORT A HCS08 CORE ICE DEBUG MODULE (DBG) 8 PTA[7:0] BKGD/MS BDC CPU CYCLIC REDUNDANCY CHECK MODULE (CRC) PORT B 6 HCS08 SYSTEM CONTROL RESET RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI IRQ COP LVD TPMCLK VDDAD VSSAD VREFL VREFH USER FLASH 63,280 BYTES 49,152 BYTES 32,768 BYTES 2-CHANNEL TIMER/PWM MODULE (TPM3) TPM3CH1 TPM3CH0 PTB[7:2]/AD1P[7:2] PTB1/TPM3CH1/AD1P1 PTB0/TPM3CH0/AD1P0 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTD3/KBI1P6/AD1P11 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 IRQ/TPMCLK TxD2 SDA1 IIC MODULE (IIC1) SCL1 8 AD1P[7:0] PORT D 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) 8 AD1P[15:8] SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USER RAM 2048 BYTES 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 MISO1 SS1 TPM1CH1 TPM1CH0 TPM1CLK TPM1CH[5:2] RxD1 TxD1 TPM2CH1 TPM2CH0 TPM2CLK 3 5 KBI1P[7:5] KBI1P[4:0] PORT E PORT C SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) RxD2 INTERNAL CLOCK GENERATOR (ICG) LOW-POWER OSCILLATOR VDD VSS SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) 2-CHANNEL TIMER/PWM MODULE (TPM2) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) PTE1/RxD1 PTE0/TxD1 PTF[7:6] PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VOLTAGE REGULATOR EXTAL XTAL PORT G Notes: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. Pin contains integrated pullup device. 4. PTD3, PTD2, PTD7, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). 5. TPMCLK, TPM1CLK, and TPM2CLK options are configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Figure 15-1. Block Diagram Highlighting the TPM Module MC9S08AC60 Series Data Sheet, Rev. 2 252 Freescale Semiconductor PORT F Chapter 15 Timer/PWM (S08TPMV3) 15.3 TPMV3 Differences from Previous Versions The TPMV3 is the latest version of the Timer/PWM module that addresses errata found in previous versions. The following section outlines the differences between TPMV3 and TPMV2 modules, and any considerations that should be taken when porting code. Table 15-1. TPMV2 and TPMV3 Porting Considerations Action Write to TPMxCnTH:L registers1 Any write to TPMxCNTH or TPMxCNTL registers Clears the TPM counter (TPMxCNTH:L) and the prescaler counter. Clears the TPM counter (TPMxCNTH:L) only. TPMV3 TPMV2 Read of TPMxCNTH:L registers1 In BDM mode, any read of TPMxCNTH:L registers Returns the value of the TPM If only one byte of the counter that is frozen. TPMxCNTH:L registers was read before the BDM mode became active, returns the latched value of TPMxCNTH:L from the read buffer (instead of the frozen TPM counter value). Does not clear this read coherency mechanism. In BDM mode, a write to TPMxSC, TPMxCNTH or TPMxCNTL Clears this read coherency mechanism. Read of TPMxCnVH:L registers2 In BDM mode, any read of TPMxCnVH:L registers Returns the value of the TPMxCnVH:L register. If only one byte of the TPMxCnVH:L registers was read before the BDM mode became active, returns the latched value of TPMxCNTH:L from the read buffer (instead of the value in the TPMxCnVH:L registers). Does not clear this read coherency mechanism. In BDM mode, a write to TPMxCnSC Write to TPMxCnVH:L registers In Input Capture mode, writes to TPMxCnVH:L registers3 In Output Compare mode, when (CLKSB:CLKSA not = 0:0), writes to TPMxCnVH:L registers3 Clears this read coherency mechanism. Not allowed. Update the TPMxCnVH:L registers with the value of their write buffer at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. Allowed. Always update these registers when their second byte is written. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 253 Chapter 15 Timer/PWM (S08TPMV3) Table 15-1. TPMV2 and TPMV3 Porting Considerations (continued) Action TPMV3 TPMV2 Update after both bytes are written and when the TPM counter changes from TPMxMODH:L to $0000. In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00), Update the TPMxCnVH:L writes to TPMxCnVH:L registers registers with the value of their write buffer after both bytes were written and when the TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). Note: If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. In Center-Aligned PWM mode when (CLKSB:CLKSA not = 00), writes to TPMxCnVH:L registers4 Update the TPMxCnVH:L registers with the value of their write buffer after both bytes are written and when the TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). Note: If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Update after both bytes are written and when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1). Center-Aligned PWM When TPMxCnVH:L = TPMxMODH:L5 When TPMxCnVH:L = (TPMxMODH:L 1)6 Produces 100% duty cycle. Produces a near 100% duty cycle. Waits for the start of a new PWM period to begin using the new duty cycle setting. Finishes the current PWM period using the old duty cycle setting. Produces 0% duty cycle. Produces 0% duty cycle. Changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). Finishes the current PWM period using the new duty cycle setting. TPMxCnVH:L is changed from 0x0000 to a non-zero value7 TPMxCnVH:L is changed from a non-zero value to 0x00008 Write to TPMxMODH:L registers in BDM mode In BDM mode, a write to TPMxSC register Clears the write coherency Does not clear the write mechanism of TPMxMODH:L coherency mechanism. registers. 1 2 3 4 5 6 7 For more information, refer to Section 15.5.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL).” [SE110-TPM case 7] For more information, refer to Section 15.5.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL).” For more information, refer to Section 15.6.2.1, “Input Capture Mode.” For more information, refer to Section 15.6.2.4, “Center-Aligned PWM Mode.” For more information, refer to Section 15.6.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 1] For more information, refer to Section 15.6.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 2] For more information, refer to Section 15.6.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 3 and 5] MC9S08AC60 Series Data Sheet, Rev. 2 254 Freescale Semiconductor Chapter 15 Timer/PWM (S08TPMV3) 8 For more information, refer to Section 15.6.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 4] 15.3.1 Migrating from TPMV1 In addition to Section 15.3, “TPMV3 Differences from Previous Versions,” keep in mind the following considerations when migrating from a device that uses TPMV1. • You can write to the Channel Value register (TPMxCnV) when the timer is not in input capture mode for TPMV2, not TPMV3. • In edge- or center- aligned modes, the Channel Value register (TPMxCnV) registers only update when the timer changes from TPMMOD-1 to TPMMOD, or in the case of a free running timer from 0xFFFE to 0xFFFF. • Also, when configuring the TPM modules, it is best to write to TPMxSC before TPMxCnV as a write to TPMxSC resets the coherency mechanism on the TPMxCnV registers. Table 15-2. Migrating to TPMV3 Considerations When... Writing to the Channel Value Register (TPMxCnV) register... Action / Best Practice Timer must be in Input Capture mode. Updating the Channel Value Register (TPMxCnV) Only occurs when the timer changes from register in edge-aligned or center-aligned modes... TPMMOD-1 to TPMMOD (or in the case of a free running timer, from 0xFFFE to 0xFFFF). Reseting the coherency mechanism for the Channel Value Register (TPMxCnV) register... Configuring the TPM modules... Write to TPMxSC. Write first to TPMxSC and then to TPMxCnV register. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 255 Chapter 15 Timer/PWM Module (S08TPMV3) 15.3.2 Features The TPM includes these distinctive features: • One to eight channels: — Each channel may be input capture, output compare, or edge-aligned PWM — Rising-Edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs • Module may be configured for buffered, center-aligned pulse-width-modulation (CPWM) on all channels • Timer clock source selectable as prescaled bus clock, fixed system clock, or an external clock pin — Prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 — Fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit — External clock pin may be shared with any timer channel pin or a separated input pin • 16-bit free-running or modulo up/down count operation • Timer system enable • One interrupt per channel plus terminal count interrupt 15.3.3 Modes of Operation In general, TPM channels may be independently configured to operate in input capture, output compare, or edge-aligned PWM modes. A control bit allows the whole TPM (all channels) to switch to center-aligned PWM mode. When center-aligned PWM mode is selected, input capture, output compare, and edge-aligned PWM functions are not available on any channels of this TPM module. When the microcontroller is in active BDM background or BDM foreground mode, the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode. During stop mode, all system clocks, including the main oscillator, are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. Provided the TPM does not need to produce a real time reference or provide the interrupt source(s) needed to wake the MCU from wait mode, the user can save power by disabling TPM functions before entering wait mode. • Input capture mode When a selected edge event occurs on the associated MCU pin, the current value of the 16-bit timer counter is captured into the channel value register and an interrupt flag bit is set. Rising edges, falling edges, any edge, or no edge (disable channel) may be selected as the active edge which triggers the input capture. • Output compare mode When the value in the timer counter register matches the channel value register, an interrupt flag bit is set, and a selected output action is forced on the associated MCU pin. The output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). MC9S08AC60 Series Data Sheet, Rev. 2 256 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point. This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned with the beginning of the period, which is the same for all channels within a TPM. Center-aligned PWM mode Twice the value of a 16-bit modulo register sets the period of the PWM output, and the channel-value register sets the half-duty-cycle duration. The timer counter counts up until it reaches the modulo value and then counts down until it reaches zero. As the count matches the channel value register while counting down, the PWM output becomes active. When the count matches the channel value register while counting up, the PWM output becomes inactive. This type of PWM signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. This type of PWM is required for types of motors used in small appliances. This is a high-level description only. Detailed descriptions of operating modes are in later sections. 15.3.4 Block Diagram The TPM uses one input/output (I/O) pin per channel, TPMxCHn (timer channel n) where n is the channel number (1-8). The TPM shares its I/O pins with general purpose I/O port pins (refer to I/O pin descriptions in full-chip specification for the specific chip implementation). Figure 15-2 shows the TPM structure. The central component of the TPM is the 16-bit counter that can operate as a free-running counter or a modulo up/down counter. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter (the values 0x0000 or 0xFFFF effectively make the counter free running). Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 257 Chapter 15 Timer/PWM Module (S08TPMV3) BUS CLOCK FIXED SYSTEM CLOCK EXTERNAL CLOCK SYNC CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT PRESCALE AND SELECT 1, 2, 4, 8, 16, 32, 64, or 128 CLKSB:CLKSA CPWMS 16-BIT COUNTER COUNTER RESET 16-BIT COMPARATOR TPMxMODH:TPMxMODL ELS0B ELS0A PS2:PS1:PS0 TOF TOIE INTERRUPT LOGIC CHANNEL 0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL 16-BIT LATCH PORT LOGIC CH0F INTERRUPT LOGIC TPMxCH0 MS0B MS0A CH0IE INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TPMxC1VH:TPMxC1VL 16-BIT LATCH ELS1B ELS1A PORT LOGIC CH1F INTERRUPT LOGIC TPMxCH1 MS1B MS1A CH1IE Up to 8 channels CHANNEL 7 16-BIT COMPARATOR TPMxC7VH:TPMxC7VL 16-BIT LATCH ELS7B ELS7A PORT LOGIC CH7F INTERRUPT LOGIC TPMxCH7 MS7B MS7A CH7IE Figure 15-2. TPM Block Diagram MC9S08AC60 Series Data Sheet, Rev. 2 258 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel. The details of how a module interacts with pin controls depends upon the chip implementation because the I/O pins and associated general purpose I/O controls are not part of the module. Refer to the discussion of the I/O port logic in a full-chip specification. Because center-aligned PWMs are usually used to drive 3-phase AC-induction motors and brushless DC motors, they are typically used in sets of three or six channels. 15.4 Signal Description Table 15-3 shows the user-accessible signals for the TPM. The number of channels may be varied from one to eight. When an external clock is included, it can be shared with the same pin as any TPM channel; however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip specification for the specific chip implementation. Table 15-3. Signal Properties Name EXTCLK1 TPMxCHn 1 2 Function External clock source which may be selected to drive the TPM counter. I/O pin associated with TPM channel n When preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. 2 n=channel number (1 to 8) Refer to documentation for the full-chip for details about reset states, port connections, and whether there is any pullup device on these pins. TPM channel pins can be associated with general purpose I/O pins and have passive pullup devices which can be enabled with a control bit when the TPM or general purpose I/O controls have configured the associated pin as an input. When no TPM function is enabled to use a corresponding pin, the pin reverts to being controlled by general purpose I/O controls, including the port-data and data-direction registers. Immediately after reset, no TPM functions are enabled, so all associated pins revert to general purpose I/O control. 15.4.1 Detailed Signal Descriptions This section describes each user-accessible pin signal in detail. Although Table 15-3 grouped all channel pins together, any TPM pin can be shared with the external clock source signal. Since I/O pin logic is not part of the TPM, refer to full-chip documentation for a specific derivative for more details about the interaction of TPM pin functions and general purpose I/O controls including port data, data direction, and pullup controls. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 259 Chapter 15 Timer/PWM Module (S08TPMV3) 15.4.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM. The bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the frequency of the bus-rate clock, to meet Nyquist criteria and allowing for jitter. The external clock signal shares the same pin as a channel I/O pin, so the channel pin will not be usable for channel I/O function when selected as the external clock source. It is the user’s responsibility to avoid such settings. If this pin is used as an external clock source (CLKSB:CLKSA = 1:1), the channel can still be used in output compare mode as a software timer (ELSnB:ELSnA = 0:0). 15.4.1.2 TPMxCHn — TPM Channel n I/O Pin(s) Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the channel configuration. The TPM pins share with general purpose I/O pins, where each pin has a port data register bit, and a data direction control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. The TPM channel does not control the I/O pin when (ELSnB:ELSnA = 0:0) or when (CLKSB:CLKSA = 0:0) so it normally reverts to general purpose I/O control. When CPWMS = 1 (and ELSnB:ELSnA not = 0:0), all channels within the TPM are configured for center-aligned PWM and the TPMxCHn pins are all controlled by the TPM system. When CPWMS=0, the MSnB:MSnA control bits determine whether the channel is configured for input capture, output compare, or edge-aligned PWM. When a channel is configured for input capture (CPWMS=0, MSnB:MSnA = 0:0 and ELSnB:ELSnA not = 0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control bits determine what polarity edge or edges will trigger input-capture events. A synchronizer based on the bus clock is used to synchronize input edges to the bus clock. This implies the minimum pulse width—that can be reliably detected—on an input capture pin is four bus clock periods (with ideal clock pulses as near as two bus clocks can be detected). TPM uses this pin as an input capture input to override the port data and data direction controls for the same pin. When a channel is configured for output compare (CPWMS=0, MSnB:MSnA = 0:1 and ELSnB:ELSnA not = 0:0), the associated data direction control is overridden, the TPMxCHn pin is considered an output controlled by the TPM, and the ELSnB:ELSnA control bits determine how the pin is controlled. The remaining three combinations of ELSnB:ELSnA determine whether the TPMxCHn pin is toggled, cleared, or set each time the 16-bit channel value register matches the timer counter. When the output compare toggle mode is initially selected, the previous value on the pin is driven out until the next output compare event—then the pin is toggled. MC9S08AC60 Series Data Sheet, Rev. 2 260 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the channel value register matches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT ... 0 1 2 3 4 5 6 7 8 0 1 2 ... Figure 15-3. High-True Pulse of an Edge-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT ... 0 1 2 3 4 5 6 7 8 0 1 2 ... Figure 15-4. Low-True Pulse of an Edge-Aligned PWM MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 261 Chapter 15 Timer/PWM Module (S08TPMV3) When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB:ELSnA=1:0, the corresponding TPMxCHn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the TPMxCHn pin is set when the timer counter is counting down, and the channel value register matches the timer counter. If ELSnA=1, the corresponding TPMxCHn pin is set when the timer counter is counting up and the channel value register matches the timer counter; the TPMxCHn pin is cleared when the timer counter is counting down and the channel value register matches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... Figure 15-5. High-True Pulse of a Center-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL TPMxCHn CHnF BIT TOF BIT ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... Figure 15-6. Low-True Pulse of a Center-Aligned PWM MC9S08AC60 Series Data Sheet, Rev. 2 262 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) 15.5 Register Definition This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 15.5.1 TPM Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM configuration, clock source, and prescale factor. These controls relate to all channels within this timer module. 7 6 5 4 3 2 1 0 R W Reset TOF TOIE 0 0 0 0 0 0 0 0 0 CPWMS CLKSB CLKSA PS2 PS1 PS0 Figure 15-7. TPM Status and Control Register (TPMxSC) Table 15-4. TPMxSC Field Descriptions Field 7 TOF Description Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is generated when TOF equals one. Reset clears TOIE. 0 TOF interrupts inhibited (use for software polling) 1 TOF interrupts enabled Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS. 0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register. 1 All channels operate in center-aligned PWM mode. 6 TOIE 5 CPWMS MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 263 Chapter 15 Timer/PWM Module (S08TPMV3) Table 15-4. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown in Table 15-5, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the fixed-system clock source is the same as the bus rate clock. The external source is synchronized to the bus clock by TPM module, and the fixed system clock source (when a PLL or FLL is present) is synchronized to the bus clock by an on-chip synchronization circuit. When a PLL or FLL is present but not enabled, the fixed-system clock source is the same as the bus-rate clock. 2–0 PS[2:0] Prescale factor select. This 3-bit field selects one of 8 division factors for the TPM clock input as shown in Table 15-6. This prescaler is located after any clock source synchronization or clock source selection so it affects the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. Table 15-5. TPM-Clock-Source Selection CLKSB:CLKSA 00 01 10 11 TPM Clock Source to Prescaler Input No clock selected (TPM counter disable) Bus rate clock Fixed system clock External source Table 15-6. Prescale Factor Selection PS2:PS1:PS0 000 001 010 011 100 101 110 111 TPM Clock Source Divided-by 1 2 4 8 16 32 64 128 15.5.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or little-endian order which makes this more friendly to various compiler implementations. The coherency mechanism is automatically restarted by an MCU reset or any write to the timer status/control register (TPMxSC). MC9S08AC60 Series Data Sheet, Rev. 2 264 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. 7 6 5 4 3 2 1 0 R W Reset Bit 15 14 13 12 11 10 9 Bit 8 Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 0 0 Figure 15-8. TPM Counter Register High (TPMxCNTH) 7 6 5 4 3 2 1 0 R W Reset Bit 7 6 5 4 3 2 1 Bit 0 Any write to TPMxCNTL clears the 16-bit counter 0 0 0 0 0 0 0 0 Figure 15-9. TPM Counter Register Low (TPMxCNTL) When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active, even if one or both counter halves are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write. 15.5.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is active or not). MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 265 Chapter 15 Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active. 7 6 5 4 3 2 1 0 R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 Figure 15-10. TPM Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 15-11. TPM Counter Modulo Register Low (TPMxMODL) Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. 15.5.4 TPM Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 1 0 R W Reset CHnF CHnIE 0 0 0 0 0 0 0 MSnB MSnA ELSnB ELSnA 0 0 0 0 = Unimplemented or Reserved Figure 15-12. TPM Channel n Status and Control Register (TPMxCnSC) MC9S08AC60 Series Data Sheet, Rev. 2 266 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) Table 15-7. TPMxCnSC Field Descriptions Field 7 CHnF Description Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous CHnF. Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event on channel n Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE. 0 Channel n interrupt requests disabled (use for software polling) 1 Channel n interrupt requests enabled Mode select B for TPM channel n. When CPWMS=0, MSnB=1 configures TPM channel n for edge-aligned PWM mode. Refer to the summary of channel mode and setup controls in Table 15-8. Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for input-capture mode or output compare mode. Refer to Table 15-8 for a summary of channel mode and setup controls. Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown in Table 15-8, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin. 6 CHnIE 5 MSnB 4 MSnA 3–2 ELSnB ELSnA Table 15-8. Mode, Edge, and Level Selection CPWMS X MSnB:MSnA XX ELSnB:ELSnA 00 Mode Configuration Pin not used for TPM - revert to general purpose I/O or other peripheral control MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 267 Chapter 15 Timer/PWM Module (S08TPMV3) Table 15-8. Mode, Edge, and Level Selection CPWMS 0 MSnB:MSnA 00 ELSnB:ELSnA 01 10 11 01 01 10 11 1X 10 X1 1 XX 10 X1 Center-aligned PWM Edge-aligned PWM Output compare Mode Input capture Configuration Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare High-true pulses (clear output on compare) Low-true pulses (set output on compare) High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up) 15.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel registers are cleared by reset. 7 6 5 4 3 2 1 0 R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 Figure 15-13. TPM Channel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 Figure 15-14. TPM Channel Value Register Low (TPMxCnVL) In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other half is read. This latching mechanism also resets MC9S08AC60 Series Data Sheet, Rev. 2 268 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode. When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read buffer. In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written. • If (CLKSB:CLKSA not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the TPM counter (end of the prescaler counting). • If (CLKSB:CLKSA not = 0:0 and in EPWM or CPWM modes), then the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active even if one or both halves of the channel register are written while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to the channel register while BDM is active. The values written to the channel register while BDM is active are used for PWM & output compare operation once normal execution resumes. Writes to the channel registers while BDM is active do not interfere with partial completion of a coherency sequence. After the coherency mechanism has been fully exercised, the channel registers are updated using the buffered values written (while BDM was not active) by the user. 15.6 Functional Description All TPM functions are associated with a central 16-bit counter which allows flexible selection of the clock source and prescale factor. There is also a 16-bit modulo register associated with the main counter. The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM (CPWMS=1) or general purpose timing functions (CPWMS=0) where each channel can independently be configured to operate in input capture, output compare, or edge-aligned PWM mode. The CPWMS control bit is located in the main TPM status and control register because it affects all channels within the TPM and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.) MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 269 Chapter 15 Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 15.6.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, end-of-count overflow, up-counting vs. up/down counting, and manual counter reset. 15.6.1.1 Counter Clock Source The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three possible clock sources or OFF (which effectively disables the TPM). See Table 15-5. After any MCU reset, CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These control bits may be read or written at any time and disabling the timer (writing 00 to the CLKSB:CLKSA field) does not affect the values in the counter or other timer registers. MC9S08AC60 Series Data Sheet, Rev. 2 270 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) Table 15-9. TPM Clock Source Selection CLKSB:CLKSA 00 01 10 11 TPM Clock Source to Prescaler Input No clock selected (TPM counter disabled) Bus rate clock Fixed system clock External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses. In MCUs that have no PLL and FLL or the PLL and FLL are not engaged, the fixed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. When a PLL or FLL is present and engaged, a synchronizer is required between the crystal divided-by two clock source and the timer counter so counter transitions will be properly aligned to bus-clock transitions. A synchronizer will be used at chip level to synchronize the crystal-related source clock to the bus clock. The external clock source may be connected to any TPM channel pin. This clock source always has to pass through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. The bus-rate clock drives the synchronizer; therefore, to meet Nyquist criteria even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by four. With ideal clocks the external clock can be as fast as bus clock divided by four. When the external clock source shares the TPM channel pin, this pin should not be used for other channel timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility to avoid such settings.) The TPM channel could still be used in output compare mode for software timing functions (pin controls set not to affect the TPM channel pin). 15.6.1.2 Counter Overflow and Modulo Reset An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one. The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1 mode. In this case, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes direction at the end of the count value set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). This corresponds to the end of a PWM period (the 0x0000 count value corresponds to the center of a period). MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 271 Chapter 15 Timer/PWM Module (S08TPMV3) 15.6.1.3 Counting Modes The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. When center-aligned PWM operation is specified, the counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up counting. Both 0x0000 and the terminal count value are normal length counts (one timer clock period long). In this mode, the timer overflow flag (TOF) becomes set at the end of the terminal-count period (as the count changes to the next lower count value). 15.6.1.4 Manual Counter Reset The main timer counter can be manually reset at any time by writing any value to either half of TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only half of the counter was read before resetting the count. 15.6.2 Channel Mode Selection Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and edge-aligned PWM. 15.6.2.1 Input Capture Mode With the input-capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM counter into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only. When either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) which may optionally generate a CPU interrupt request. While in BDM, the input capture function works as configured by the user. When an external event occurs, the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the channel value registers and sets the flag bit. 15.6.2.2 Output Compare Mode With the output-compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel-value registers of an output-compare channel, the TPM can set, clear, or toggle the channel pin. MC9S08AC60 Series Data Sheet, Rev. 2 272 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) In output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request. 15.6.2.3 Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the value of the modulus register (TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. 0% and 100% duty cycle cases are possible. The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal (Figure 15-15). The time between the modulus overflow and the output compare is the pulse width. If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare forces the PWM signal high. OVERFLOW PERIOD PULSE WIDTH TPMxCHn OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OVERFLOW OVERFLOW Figure 15-15. PWM Period and Pulse Width (ELSnA=0) When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle. Because the TPM may be used in an 8-bit MCU, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxCnVH and TPMxCnVL, actually write to buffer registers. In edge-aligned PWM mode, values are transferred to the corresponding timer-channel registers according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 273 Chapter 15 Timer/PWM Module (S08TPMV3) the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. 15.6.2.4 Center-Aligned PWM Mode This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal while the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width = 2 x (TPMxCnVH:TPMxCnVL) period = 2 x (TPMxMODH:TPMxMODL); TPMxMODH:TPMxMODL=0x0001-0x7FFF If the channel-value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if you do not need to generate 100% duty cycle). This is not a significant limitation. The resulting period would be much longer than required for normal applications. TPMxMODH:TPMxMODL=0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle) of the CPWM signal (Figure 15-16). If ELSnA=0, a compare occurred while counting up forces the CPWM output signal low and a compare occurred while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. COUNT= 0 OUTPUT COUNT= COMPARE TPMxMODH:TPMxMODL (COUNT DOWN) OUTPUT COMPARE (COUNT UP) COUNT= TPMxMODH:TPMxMODL TPMxCHn PULSE WIDTH 2 x TPMxCnVH:TPMxCnVL PERIOD 2 x TPMxMODH:TPMxMODL Figure 15-16. CPWM Period and Pulse Width (ELSnA=0) Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. MC9S08AC60 Series Data Sheet, Rev. 2 274 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS=1. The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. In center-aligned PWM mode, the TPMxCnVH:L registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. When TPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF interrupt (at the end of this count). Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 15.7 15.7.1 Reset Overview General The TPM is reset whenever any MCU reset occurs. 15.7.2 Description of Reset Operation Reset clears the TPMxSC register which disables clocks to the TPM and disables timer overflow interrupts (TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM channels for input-capture operation with the associated pins disconnected from I/O pin logic (so all MCU pins related to the TPM revert to general purpose I/O pins). 15.8 15.8.1 Interrupts General The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 275 Chapter 15 Timer/PWM Module (S08TPMV3) All TPM interrupts are listed in Table 15-10 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic. Table 15-10. Interrupt Summary Interrupt TOF Local Enable TOIE Source Counter overflow Description Set each time the timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) An input capture or output compare event took place on channel n CHnF CHnIE Channel event The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip integration time in the interrupt module so refer to the user’s guide for the interrupt module or to the chip’s complete documentation for details. 15.8.2 Description of Interrupt Operation For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps to clear the interrupt flag before returning from the interrupt-service routine. TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1) followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 15.8.2.1 Timer Overflow Interrupt (TOF) Description The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system (general purpose timing functions versus center-aligned PWM operation). The flag is cleared by the two step sequence described above. 15.8.2.1.1 Normal Case Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not configured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning of counter overflow. MC9S08AC60 Series Data Sheet, Rev. 2 276 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) 15.8.2.1.2 Center-Aligned PWM Case When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period. 15.8.2.2 Channel Event Interrupt Description The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare, edge-aligned PWM, or center-aligned PWM). 15.8.2.2.1 Input Capture Events When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select no edge (off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described in Section 15.8.2, “Description of Interrupt Operation.” 15.8.2.2.2 Output Compare Events When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step sequence described Section 15.8.2, “Description of Interrupt Operation.” 15.8.2.2.3 PWM End-of-Duty-Cycle Events For channels configured for PWM operation there are two possibilities. When the channel is configured for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. The flag is cleared by the two-step sequence described Section 15.8.2, “Description of Interrupt Operation.” 15.9 The Differences from TPM v2 to TPM v3 1. Write to TPMxCnTH:L registers (Section 15.5.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7] Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter (TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared in this case. 2. Read of TPMxCNTH:L registers (Section 15.5.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) — In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was read before the BDM mode became active, then any read of TPMxCNTH:L registers during MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 277 Chapter 15 Timer/PWM Module (S08TPMV3) BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section 15.5.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)) — In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in the TPMxCnVH:L registers. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency mechanism. 4. Write to TPMxCnVH:L registers — Input Capture Mode (Section 15.6.2.1, “Input Capture Mode) In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the TPM v2 allows these writes. — Output Compare Mode (Section 15.6.2.2, “Output Compare Mode) In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. Instead, the TPM v2 always updates these registers when their second byte is written. — Edge-Aligned PWM (Section 15.6.2.3, “Edge-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer after that the both bytes were written and when the TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to $0000. — Center-Aligned PWM (Section 15.6.2.4, “Center-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer after that the both bytes were written and when the TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1). 5. Center-Aligned PWM (Section 15.6.2.4, “Center-Aligned PWM Mode) — TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1] In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. MC9S08AC60 Series Data Sheet, Rev. 2 278 Freescale Semiconductor Chapter 15 Timer/PWM Module (S08TPMV3) — TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2] In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. — TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5] In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). — TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4] In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting. Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting. 6. Write to TPMxMODH:L registers in BDM mode (Section 15.5.3, “TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)) In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when there is a write to TPMxSC register. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 279 Chapter 15 Timer/PWM Module (S08TPMV3) MC9S08AC60 Series Data Sheet, Rev. 2 280 Freescale Semiconductor Chapter 16 Development Support 16.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes). Debug is done through commands fed into the target MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. The alternate BDC clock source for MC9S08AC60 Series is the ICGLCLK. See Chapter 10, “Internal Clock Generator (S08ICGV4)” for more information about ICGCLK and how to select clock sources. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 281 Chapter 16 Development Support 16.1.1 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode Features of the ICE system include: • • Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access Nine trigger modes: — Basic: A-only, A OR B — Sequence: A then B — Full: A AND B data, A AND NOT B data — Event (store data): Event-only B, A then event-only B — Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B) • • 16.2 Background Debug Controller (BDC) All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • Active background mode commands require that the target MCU is in active background mode (the user program is not running). Active background mode commands allow the CPU registers to be read or written, and allow the user to trace one user instruction at a time, or GO to the user program from active background mode. MC9S08AC60 Series Data Sheet, Rev. 2 282 Freescale Semiconductor Chapter 16 Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET, and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. BKGD 1 NO CONNECT 3 NO CONNECT 5 2 GND 4 RESET 6 VDD Figure 16-1. BDM Tool Connector 16.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the user’s application program. This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer to Section 16.2.2, “Communication Details.” If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 16.2.2, “Communication Details,” for more detail. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 283 Chapter 16 Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface. 16.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles. MC9S08AC60 Series Data Sheet, Rev. 2 284 Freescale Semiconductor Chapter 16 Development Support Figure 16-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES EARLIEST START OF NEXT BIT SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT TIME TARGET SENSES BIT LEVEL Figure 16-2. BDC Host-to-Target Serial Bit Timing MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 285 Chapter 16 Development Support Figure 16-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN HIGH-IMPEDANCE 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN EARLIEST START OF NEXT BIT Figure 16-3. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08AC60 Series Data Sheet, Rev. 2 286 Freescale Semiconductor Chapter 16 Development Support Figure 16-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME SPEEDUP PULSE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 16-4. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 287 Chapter 16 Development Support 16.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program. Table 16-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 16-1 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / = separates parts of the command d = delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS = the contents of BDCSCR in the target-to-host direction (STATUS) CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08AC60 Series Data Sheet, Rev. 2 288 Freescale Semiconductor Chapter 16 Development Support Table 16-1. BDC Command Summary Command Mnemonic SYNC ACK_ENABLE ACK_DISABLE BACKGROUND READ_STATUS WRITE_CONTROL READ_BYTE READ_BYTE_WS READ_LAST WRITE_BYTE WRITE_BYTE_WS READ_BKPT WRITE_BKPT GO TRACE1 TAGGO READ_A READ_CCR READ_PC READ_HX READ_SP READ_NEXT READ_NEXT_WS WRITE_A WRITE_CCR WRITE_PC WRITE_HX WRITE_SP WRITE_NEXT WRITE_NEXT_WS 1 Active BDM/ Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Non-intrusive Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM Active BDM n/a1 D5/d D6/d 90/d E4/SS C4/CC Coding Structure Description Request a timed reference pulse to determine target BDC communication speed Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. Enter active background mode if enabled (ignore if ENBDM bit equals 0) Read BDC status from BDCSCR Write BDC controls in BDCSCR Read a byte from target memory Read a byte and report status Re-read byte from address just read and report status Write a byte to target memory Write a byte and report status Read BDCBKPT breakpoint register Write BDCBKPT breakpoint register Go to execute the user application program starting at the address currently in the PC Trace 1 user instruction at the address in the PC, then return to active background mode Same as GO but enable external tagging (HCS08 devices have no external tagging pin) Read accumulator (A) Read condition code register (CCR) Read program counter (PC) Read H and X register pair (H:X) Read stack pointer (SP) Increment H:X by one then read memory byte located at H:X Increment H:X by one then read memory byte located at H:X. Report status and data. Write accumulator (A) Write condition code register (CCR) Write program counter (PC) Write H and X register pair (H:X) Write stack pointer (SP) Increment H:X by one, then write memory byte located at H:X Increment H:X by one, then write memory byte located at H:X. Also report status. E0/AAAA/d/RD E1/AAAA/d/SS/RD E8/SS/RD C0/AAAA/WD/d C1/AAAA/WD/d/SS E2/RBKP C2/WBKP 08/d 10/d 18/d 68/d/RD 69/d/RD 6B/d/RD16 6C/d/RD16 6F/d/RD16 70/d/RD 71/d/SS/RD 48/WD/d 49/WD/d 4B/WD16/d 4C/WD16/d 4F/WD16/d 50/WD/d 51/WD/d/SS The SYNC command is a special operation that does not have a command code. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 289 Chapter 16 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16 cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128 BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 16.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the BDC module. MC9S08AC60 Series Data Sheet, Rev. 2 290 Freescale Semiconductor Chapter 16 Development Support 16.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. The system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user’s memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Most of the debug module’s functions are used during development, and user programs rarely access any of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section 16.3.6, “Hardware Breakpoints.” 16.3.1 Comparators A and B Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actually executed as opposed to only being read from memory into the instruction queue. The comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s write data bus is used. Otherwise, the CPU’s read data bus is used. The currently selected trigger mode determines what the debugger logic does when a comparator detects a qualified match condition. A match can cause: • Generation of a breakpoint to the CPU • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) 16.3.2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 291 Chapter 16 Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port. In the event-only trigger modes (see Section 16.3.5, “Trigger Modes”), 8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-flow address or a change-of-flow address appears during the next two bus cycles after a trigger event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is not armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 16.3.3 Change-of-Flow Information To minimize the amount of information stored in the FIFO, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. With knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-flow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are not conditional, these events do not cause change-of-flow information to be stored in the FIFO. Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow information. 16.3.4 Tag vs. Force Breakpoints and Triggers Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed. MC9S08AC60 Series Data Sheet, Rev. 2 292 Freescale Semiconductor Chapter 16 Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 16.3.5 Trigger Modes The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace), or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected (end trigger). A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally known at a particular address. The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines whether the CPU request will be a tag request or a force request. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 293 Chapter 16 Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of comparator B is not used. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within the same bus cycle to cause a trigger. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger event occurs each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. Inside Range (A ≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. MC9S08AC60 Series Data Sheet, Rev. 2 294 Freescale Semiconductor Chapter 16 Development Support 16.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 16.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 16.4 Register Definition This section contains the descriptions of the BDC and DBG registers and control bits. Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 16.4.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For example, the ENBDM control bit may not be written while the MCU is in active background mode. (This prevents the ambiguous condition of the control bit forbidding active background mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 295 Chapter 16 Development Support 16.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 5 4 3 2 1 0 R ENBDM W Normal Reset Reset in Active BDM: 0 1 BDMACT BKPTEN 0 1 0 0 FTS 0 0 CLKSW 0 1 WS WSF DVF 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-5. BDC Status and Control Register (BDCSCR) Table 16-2. BDCSCR Register Field Descriptions Field 7 ENBDM Description Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands Background Mode Active Status — This is a read-only status bit. 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock source. 0 Alternate BDC clock source 1 MCU bus clock 6 BDMACT 5 BKPTEN 4 FTS 3 CLKSW MC9S08AC60 Series Data Sheet, Rev. 2 296 Freescale Semiconductor Chapter 16 Development Support Table 16-2. BDCSCR Register Field Descriptions (continued) Field 2 WS Description Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. 0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to active background mode Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode Data Valid Failure Status — This status bit is not used in the MC9S08AC60 Series because it does not have any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 1 WSF 0 DVF 16.4.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. Breakpoints are normally set while the target MCU is in active background mode before running the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section 16.2.4, “BDC Hardware Breakpoint.” 16.4.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 297 Chapter 16 Development Support 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 BDFR1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 16-6. System Background Debug Force Reset Register (SBDFR) Table 16-3. SBDFR Register Field Description Field 0 BDFR Description Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 16.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so they are accessible to normal application programs. These registers are rarely if ever accessed by normal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic. 16.4.3.1 Debug Comparator A High Register (DBGCAH) This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 16.4.3.2 Debug Comparator A Low Register (DBGCAL) This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 16.4.3.3 Debug Comparator B High Register (DBGCBH) This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 16.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. MC9S08AC60 Series Data Sheet, Rev. 2 298 Freescale Semiconductor Chapter 16 Development Support 16.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information. 16.4.3.6 Debug FIFO Low Register (DBGFL) This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case. Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 299 Chapter 16 Development Support 16.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 R DBGEN W Reset 0 0 0 0 0 0 0 0 ARM TAG BRKEN RWA RWAEN RWB RWBEN Figure 16-7. Debug Control Register (DBGC) Table 16-4. DBGC Register Field Descriptions Field 7 DBGEN 6 ARM Description Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. 0 DBG disabled 1 DBG enabled Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match. 0 R/W is not used in comparison A 1 R/W is used in comparison A R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match. 0 R/W is not used in comparison B 1 R/W is used in comparison B 5 TAG 4 BRKEN 3 RWA 2 RWAEN 1 RWB 0 RWBEN MC9S08AC60 Series Data Sheet, Rev. 2 300 Freescale Semiconductor Chapter 16 Development Support 16.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 5 4 3 2 1 0 R TRGSEL W Reset 0 0 BEGIN 0 0 TRG3 TRG2 0 TRG1 0 TRG0 0 0 0 0 = Unimplemented or Reserved Figure 16-8. Debug Trigger Register (DBGT) Table 16-5. DBGT Register Field Descriptions Field 7 TRGSEL Description Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) Select Trigger Mode — Selects one of nine triggering modes, as described below. 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A ≤ address ≤ B 1000 Outside range: address < A or address > B 1001 – 1111 (No trigger) 6 BEGIN 3:0 TRG[3:0] MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 301 Chapter 16 Development Support 16.4.3.9 Debug Status Register (DBGS) This is a read-only status register. 7 6 5 4 3 2 1 0 R W Reset AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-9. Debug Status Register (DBGS) Table 16-6. DBGS Register Field Descriptions Field 7 AF Description Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming. 0 Comparator A has not matched 1 Comparator A match Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B condition was met since arming. 0 Comparator B has not matched 1 Comparator B match Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1 to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8 6 BF 5 ARMF 3:0 CNT[3:0] MC9S08AC60 Series Data Sheet, Rev. 2 302 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications A.1 Introduction This section contains electrical and timing specifications. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1. Parameter Classifications P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. T D MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 303 Appendix A Electrical Characteristics and Timing Specifications A.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). Table A-2. Absolute Maximum Ratings Rating Supply voltage Input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature Maximum junction temperature 1 Symbol VDD VIn ID IDD Tstg TJ Value – 0.3 to + 5.8 – 0.3 to VDD + 0.3 ± 25 120 – 55 to +150 150 Unit V V mA mA °C °C Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. MC9S08AC60 Series Data Sheet, Rev. 2 304 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications A.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table A-3. Thermal Characteristics Rating Operating temperature range (packaged) Thermal resistance 1,2,3,4 64-pin QFP 1s 2s2p 64-pin LQFP 1s 2s2p 48-pin QFN 1s 2s2p 44-pin LQFP 1s 2s2p 32-pin LQFP 1s 2s2p 85 56 73 56 θJA 84 27 °C/W 69 54 57 43 Symbol TA Value TL to TH –40 to 125 Unit °C 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s - Single Layer Board, one signal layer 4 2s2p - Four Layer Board, 2 signal and 2 power layers MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 305 Appendix A Electrical Characteristics and Timing Specifications The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. A-1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 4MHz fADCK < 4MHz 8-bit mode (all valid fADCK) RAS — — — fADCK 0.4 0.4 m — Min 2.7 –100 –100 2.7 VSSAD — VREFL — — Typ1 — 0 0 VDDAD VSSAD 0.011 — 4.5 3 — — — — — 3.266 3.638 Max 5.5 +100 +100 VDDAD VSSAD 1 VREFH 5.5 5 5 10 10 8.0 4.0 — — — Unit V mV mV V V μA V pF kΩ kΩ Supply voltage Ground voltage Ref voltage high Ref voltage low Supply current Input Voltage Input capacitance Input resistance Analog source resistance External to MCU Delta to VSS (VSS–VSSAD)2 ADC conversion clock frequency High speed (ADLPC = 0) Low power (ADLPC = 1) MHz Temp Sensor Slope Temp Sensor Voltage 1 −40°C– 25°C 25°C– 125°C 25°C mV/°C VTEMP25 — 1.396 V Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK = 1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 dc potential difference. MC9S08AC60 Series Data Sheet, Rev. 2 314 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS Pad leakage due to input protection ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + – CAS – RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure A-8. ADC Input Impedance Equivalency Diagram MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 315 Appendix A Electrical Characteristics and Timing Specifications Table A-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 ADC asynchronous clock source tADACK = 1/fADACK Conversion time (Including sample time) Sample time Conditions C T Symb IDDAD Min — Typ1 133 Max — Unit μA T IDDAD — 218 — μA T IDDAD — 327 — μA T VDDAD < 5.5 V P IDDAD — — 582 — — 1 μA mA High speed (ADLPC = 0) Low power (ADLPC = 1) Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) Short sample (ADLSMP = 0) Long sample (ADLSMP = 1) P fADACK 2 1.25 3.3 2 20 40 3.5 23.5 ±1 ±0.5 ±0.5 ±0.3 5 3.3 — — — — ±2.5 ±1.0 ±1.0 ±0.5 MHz P tADC — — ADCK cycles ADCK cycles LSB2 P tADS — — Total unadjusted error Includes quantization Differential non-linearity 10-bit mode 8-bit mode 10-bit mode 8-bit mode P ETUE — — P DNL — — LSB2 Monotonicity and no-missing-codes guaranteed Integral non-linearity 10-bit mode 8-bit mode Zero-scale error VADIN = VSSA Full-scale error VADIN = VDDA Quantization error 10-bit mode 8-bit mode 10-bit mode 8-bit mode 10-bit mode 8-bit mode D EQ P P C INL — — ±0.5 ±0.3 ±0.5 ±0.5 ±0.5 ±0.5 — — ±1.0 ±0.5 ±1.5 ±0.5 ±1.5 ±0.5 ±0.5 ±0.5 LSB2 EZS — — LSB2 EFS — — — — LSB2 LSB2 MC9S08AC60 Series Data Sheet, Rev. 2 316 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications Table A-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Input leakage error Pad leakage3 * RAS 1 Conditions 10-bit mode 8-bit mode C D Symb EIL Min — — Typ1 ±0.2 ±0.1 Max ±2.5 ±1 Unit LSB2 Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH – VREFL)/2N 3 Based on input pad leakage current. Refer to pad electricals. A.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RS RF C1 Crystal or Resonator C2 Table A-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Load capacitors Feedback resistor Low range (32k to 100 kHz) High range (1M – 16 MHz) Series resistor Low range Low Gain (HGO = 0) High Gain (HGO = 1) High range Low Gain (HGO = 0) High Gain (HGO = 1) ≥ 8 MHz 4 MHz 1 MHz 1 2 Symbol C1 C2 RF Min Typ1 Max Unit See Note 2 10 1 MΩ MΩ — — RS — — — — 0 100 0 0 10 20 — — — — — — kΩ Typical values are based on characterization data at VDD = 5.0V, 25°C or is typical recommended value. See crystal or resonator manufacturer’s recommendation. MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 317 Appendix A Electrical Characteristics and Timing Specifications A.9.1 ICG Frequency Specifications Table A-11. ICG Frequency Specifications (VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient) Num C Characteristic Oscillator crystal or resonator (REFS = 1) (Fundamental mode crystal or ceramic resonator) Low range High range High Gain, FBE (HGO = 1,CLKS = 10) High Gain, FEE (HGO = 1,CLKS = 11) Low Power, FBE (HGO = 0, CLKS = 10) Low Power, FEE (HGO = 0, CLKS = 11) Input clock frequency (CLKS = 11, REFS = 0) Low range High range Symbol Min Typ1 Max Unit flo fhi_byp fhi_eng flp_byp flp_eng flo fhi_eng fExtal fICGIRCLK tdc 32 1 2 1 2 32 2 0 182.25 40 — — — 100 16 10 8 8 100 10 40 303.75 60 fExtal (max) fICGDCLKmax( max) 40 fICGDCLKmax kHz MHz MHz MHz MHz kHz MHz MHz kHz % 1 T 2 3 4 5 T T T T — — — 243 — Input clock frequency (CLKS = 10, REFS = 0) Internal reference frequency (untrimmed) Duty cycle of input clock (REFS = 0) Output clock ICGOUT frequency CLKS = 10, REFS = 0 All other cases Minimum DCO clock (ICGDCLK) frequency Maximum DCO clock (ICGDCLK) frequency Self-clock mode (ICGOUT) frequency 3 2 6 P fICGOUT fExtal (min) flo (min) 8 fICGDCLKmin 5.5 5 50 0.5 — — — — –4*N –2*N — — — — — MHz MHz MHz MHz MHz 7 8 9 10 11 12 13 T T P T T T T fICGDCLKmin fICGDCLKmax fSelf fSelf_reset fLOR fLOD t t CSTL Self-clock mode reset (ICGOUT) frequency Loss of reference frequency Low range High range Loss of DCO frequency 4 Crystal start-up time Low range High range FLL lock time , 7 Low range High range FLL frequency unlock range FLL frequency lock range at fICGOUT Max ICGOUT period jitter, Long term jitter (averaged over 2 ms interval) Internal oscillator deviation from trimmed frequency9 VDD = 2.7 – 5.5 V, (constant temperature) VDD = 5.0 V ±10%, –40° C to 125°C , 8 measured 5, 6 8 10.5 25 500 1.5 kHz MHz CSTH 430 4 — — 2 2 4*N 2*N 0.2 ms ms counts counts % fICG 14 15 16 17 T T T T tLockl tLockh nUnlock nLock CJitter 18 1 2 P ACCint — — ± 0.5 ± 0.5 ±2 ±2 % Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. MC9S08AC60 Series Data Sheet, Rev. 2 318 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications 3 4 5 6 7 8 9 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range. This parameter is characterized before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. See Figure A-9. Average of Percentage Error Variable 3V 5V Figure A-9. Internal Oscillator Deviation from Trimmed Frequency MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 319 Appendix A Electrical Characteristics and Timing Specifications A.10 AC Characteristics This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the bus are generated, see Chapter 10, “Internal Clock Generator (S08ICGV4).” A.10.1 Num 1 2 3 4 5 Control Timing Table A-12. Control Timing C Parameter Bus frequency (tcyc = 1/fBus) Real-time interrupt internal oscillator period External reset pulse width2 (tcyc = 1/fSelf_reset) Reset low drive3 Active background debug mode latch setup time Active background debug mode latch hold time IRQ pulse width Asynchronous path2 Synchronous path4 KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time — High output drive (PTxDS) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Symbol fBus tRTI textrst trstdrv tMSSU tMSH tILIH, tIHIL Min dc 700 1.5 x tSelf_reset 34 x tcyc 25 25 100 1.5 x tcyc 100 1.5 x tcyc — Typ1 — Max 20 1300 — — — — — Unit MHz μs ns ns ns ns ns 6 7 8 tILIH, tIHIL — — ns 9 tRise, tFall — — 3 30 ns Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 125°C. 2 1 textrst RESET PIN Figure A-10. Reset Timing MC9S08AC60 Series Data Sheet, Rev. 2 320 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications BKGD/MS RESET tMSH tMSSU Figure A-11. Active Background Debug Mode Latch Timing tIHIL IRQ/KBIP7-KBIP4 IRQ/KBIPx tILIH Figure A-12. IRQ/KBIPx Timing A.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-13. TPM Input Timing Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTPMext tTPMext tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 — — — — Unit MHz tcyc tcyc tcyc tcyc MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 321 Appendix A Electrical Characteristics and Timing Specifications tTPMext tclkh TPMxCLK tclkl Figure A-13. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure A-14. Timer Input Capture Pulse MC9S08AC60 Series Data Sheet, Rev. 2 322 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications A.11 SPI Characteristics Table A-14. SPI Electrical Characteristic Num1 C Characteristic2 Operating frequency3 Master Slave 1 Cycle time Master Slave 2 Enable lead time Master Slave 3 Enable lag time Master Slave 4 5 6 Clock (SPSCK) high time Master and Slave Clock (SPSCK) low time Master and Slave Data setup time (inputs) Master Slave 7 Data hold time (inputs) Master Slave 8 9 10 Access time, slave4 Disable time, slave5 Data setup time (outputs) Master Slave Data hold time (outputs) Master Slave 1 Table A-14 and Figure A-15 through Figure A-18 describe the timing requirements for the SPI system. Symbol Min Max Unit Hz fop fop tSCK tSCK fBus/2048 dc 2 4 — 1/2 fBus/2 fBus/4 2048 — 1/2 — 1/2 — — — — — tcyc tcyc tLead tLead tLag tLag tSCKH tSCKL tSI(M) tSI(S) tHI(M) tHI(S) tA tdis tSO tSO tHO tHO tSCK tSCK tSCK tSCK ns ns ns ns — 1/2 1/2 tSCK – 25 1/2 tSCK – 25 30 30 30 30 0 — 25 25 — — 40 40 — — ns ns ns ns ns ns 11 –10 –10 — — ns ns Refer to Figure A-15 through Figure A-18. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Maximum baud rate must be limited to 5 MHz due to pad input characteristics. 4 Time to data active from high-impedance state. 5 Hold time to high-impedance state. 2 MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 323 Appendix A Electrical Characteristics and Timing Specifications SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 10 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 10 BIT 6 . . . 1 LSB OUT LSB IN 11 1 5 4 3 5 4 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-15. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 10 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 3 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-16. SPI Master Timing (CPHA = 1) MC9S08AC60 Series Data Sheet, Rev. 2 324 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) NOTE: 3 5 4 5 4 10 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 11 SLAVE LSB OUT SEE NOTE 9 1. Not defined but normally MSB of character just received Figure A-17. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 10 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 11 BIT 6 . . . 1 SLAVE LSB OUT 9 3 NOTE: 1. Not defined but normally LSB of character just received Figure A-18. SPI Slave Timing (CPHA = 1) MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 325 Appendix A Electrical Characteristics and Timing Specifications A.12 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table A-15. FLASH Characteristics Num 1 2 3 4 5 C P P P P P Characteristic Supply voltage for program/erase Supply voltage for read operation Internal FCLK frequency2 Internal FCLK period (1/FCLK) Byte program time (random location)(2) Byte program time (burst mode)(2) Page erase time3 Mass erase time(2) Program/erase endurance4 TL to TH = –40°C to + 125°C T = 25°C Data retention5 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass Min 2.7 2.7 150 5 Typ1 Max 5.5 5.5 200 6.67 Unit V V kHz μs tFcyc tFcyc tFcyc tFcyc 9 4 4000 20,000 6 7 C P 8 P 9 C 10,000 — tD_ret 15 — 100,000 100 — — — cyces 10 1 C years Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated. The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 2 MC9S08AC60 Series Data Sheet, Rev. 2 326 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications A.13 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. A.13.1 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below the table. Table A-16. Conducted Transient Susceptibility Parameter Symbol Conditions fOSC/fBUS 32.768kHz crystal 2MHz Bus Result A B C D 1 2 Amplitude1 (Min) ± 2.82 ± 2.8 Unit Conducted susceptibility, electrical fast transient/burst (EFT/B) VCS_EFT VDD = 5.0V TA = +25oC package type 64 QFP kV ± 2.8 ± 3.8 Data based on qualification test results. Not tested in production. The RESET pin is susceptible to the minimum applied transient of 220V. However, adding the recommended 0.1μF decoupling capacitor should prevent failures below the minimum amplitude. The susceptibility performance classification is described in Table A-17. Table A-17. Susceptibility Performance Classification Result A B No failure Self-recovering failure Soft failure Performance Criteria The MCU performs as designed during and after exposure. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. C MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 327 Appendix A Electrical Characteristics and Timing Specifications Table A-17. Susceptibility Performance Classification Result D Hard failure Performance Criteria The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation. E Damage MC9S08AC60 Series Data Sheet, Rev. 2 328 Freescale Semiconductor Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering numbers for MC9S08AC60 Series devices. See below for an example of the device numbering system. Table B-1. Device Numbering System Device Number1 Flash MC9S08AC60 MC9S08AC48 MC9S08AC32 1 2 Memory RAM Available Packages2 Type 64 LQFP, 64 QFP 48 QFN, 44 LQFP, 32 LQFP 2048 64 LQFP, 64 QFP 48 QFN, 44 LQFP, 32 LQFP 64 LQFP, 64 QFP 48 QFN, 44 LQFP, 32 LQFP 63,280 49,152 32,768 See Table 1-1 for a complete description of modules included on each device. See Table B-2 for package information. B.2 Orderable Part Numbering System MC 9 S08 AC 60 C XX E Status (MC = Fully Qualified) Memory (9 = FLASH-based) Core Family Pb free indicator Package designator (See Table B-2) Temperature range (C = –40°C to 85°C) (M = –40°C to 125°C) Approximate memory size (in KB) B.3 Mechanical Drawings This following pages contain mechanical specifications for MC9S08AC60 Series package options. See Table B-2 for the document numbers that correspond to each package type. Table B-2. Package Information Pin Count 64 64 48 Type LQFP QFP QFN Designator PU FU FD Document No. 98ASS23234W 98ASB42844B 98ARH99048A MC9S08AC60 Series Data Sheet, Rev. 2 Freescale Semiconductor 329 Appendix B Ordering Information and Mechanical Drawings Table B-2. Package Information Pin Count 44 32 Type LQFP LQFP Designator FG FJ Document No. 98ASS23225W 98ASH70029A MC9S08AC60 Series Data Sheet, Rev. 2 330 Freescale Semiconductor How to Reach Us: USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor H.K. Ltd. 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 Learn More: For more information about Freescale Semiconductor products, please visit http://www.freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. MC9S08AC60, Rev. 2 3/2008 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008.