MCF51QM128

Freescale Semiconductor Data Sheet: Advance Information Document Number: MCF51QM128 Rev. 2, 05/2011 Supports the MCF51QM128VLH, MCF51QM128VHX, MCF51QM128VHS, MCF51QM64VLF, MCF51QM64VHS, MCF51QM32VHS, MCF51QM32VFM Features • Operating characteristics – Voltage range: 1.71 V to 3.6 V – Flash write voltage range: 1.71 V to 3.6 V – Temperature range (ambient): -40°C to 105°C • Core – Up to 50 MHz V1 ColdFire CPU – Dhrystone 2.1 performance: 1.10 DMIPS per MHz when executing from internal RAM, 0.99 DMIPS per MHz when executing from flash memory • System – DMA controller with four programmable channels – Integrated ColdFire DEBUG_Rev_B+ interface with single-wire BDM connection • Power management – 10 low power modes to provide power optimization based on application requirements – Low-leakage wakeup unit (LLWU) – Voltage regulator (VREG) • Clocks – Crystal oscillators (two, each with range options): 1 kHz to 32 kHz (low), 1 MHz to 8 MHz (medium), 8 MHz to 32 MHz (high) – Multipurpose clock generator (MCG) • Memories and memory interfaces – Flash memory, FlexNVM, FlexRAM, and RAM – Serial programming interface (EzPort) – Mini-FlexBus external bus interface • Security and integrity – Hardware CRC module to support fast cyclic redundancy checks – Hardware random number generator (RNGB) – Hardware cryptographic acceleration unit (CAU) – 128-bit unique identification (ID) number per chip • Analog – 16-bit SAR ADC – 12-bit DAC – Analog comparator (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference (VREF) • Timers – Programmable delay block (PDB) – Motor control/general purpose/PWM timers (FTM) – 16-bit low-power timers (LPTMRs) – 16-bit modulo timer (MTIM) – Carrier modulator transmitter (CMT) • Communication interfaces – UARTs with Smart Card support and FIFO – SPI modules, one with FIFO – Inter-Integrated Circuit (I2C) modules • Human-machine interface – Up to 48 EGPIO pins – Up to 16 rapid general purpose I/O (RGPIO) pins – Low-power hardware touch sensor interface (TSI) – Interrupt request pin (IRQ) MCF51QM128 Advance Information MCF51QM128 This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2010–2011 Freescale Semiconductor, Inc. Preliminary Table of Contents 1 Ordering parts...........................................................................3 1.1 Determining valid orderable parts......................................3 2 Part identification......................................................................3 2.1 Description.........................................................................3 2.2 Format...............................................................................3 2.3 Fields.................................................................................3 2.4 Example............................................................................4 3 Terminology and guidelines......................................................4 3.1 Definition: Operating requirement......................................4 3.2 Definition: Operating behavior...........................................5 3.3 Definition: Attribute............................................................5 3.4 Definition: Rating...............................................................5 3.5 Result of exceeding a rating..............................................6 3.6 Relationship between ratings and operating requirements......................................................................6 3.7 Guidelines for ratings and operating requirements............6 3.8 Definition: Typical value.....................................................7 4 Ratings......................................................................................8 4.1 Thermal handling ratings...................................................8 4.2 Moisture handling ratings..................................................8 4.3 ESD handling ratings.........................................................9 4.4 Voltage and current operating ratings...............................9 5 General.....................................................................................9 5.1 Typical Value Conditions...................................................9 5.2 Nonswitching electrical specifications...............................10 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 Voltage and Current Operating Requirements......10 LVD and POR operating requirements.................11 Voltage and current operating behaviors..............12 Power mode transition operating behaviors..........12 Power consumption operating behaviors..............13 EMC radiated emissions operating behaviors.......16 Designing with radiated emissions in mind...........16 Capacitance attributes..........................................16 5.3.1 General Switching Specifications..........................17 5.4 Thermal specifications.......................................................19 5.4.1 5.4.2 Thermal operating requirements...........................19 Thermal attributes.................................................19 6 Peripheral operating requirements and behaviors....................20 6.1 Core modules....................................................................20 6.1.1 Debug specifications.............................................20 6.2 System modules................................................................21 6.2.1 VREG electrical specifications..............................21 6.3 Clock modules...................................................................21 6.3.1 6.3.2 MCG specifications...............................................21 Oscillator electrical specifications.........................24 6.4 Memories and memory interfaces.....................................26 6.4.1 6.4.2 6.4.3 Flash (FTFL) electrical specifications....................26 EzPort Switching Specifications............................31 Mini-Flexbus Switching Specifications..................32 6.5 Security and integrity modules..........................................34 6.6 Analog...............................................................................35 6.6.1 6.6.2 6.6.3 6.6.4 ADC electrical specifications.................................35 CMP and 6-bit DAC electrical specifications.........39 12-bit DAC electrical characteristics.....................41 Voltage reference electrical specifications............44 6.7 Timers................................................................................45 6.8 Communication interfaces.................................................46 6.8.1 SPI switching specifications..................................46 6.9 Human-machine interfaces (HMI)......................................49 6.9.1 TSI electrical specifications...................................49 7 Dimensions...............................................................................50 7.1 Obtaining package dimensions.........................................50 8 Pinout........................................................................................51 8.1 Signal Multiplexing and Pin Assignments..........................51 8.2 Pinout diagrams.................................................................53 8.3 Module-by-module signals.................................................57 9 Revision History........................................................................67 5.3 Switching electrical specifications.....................................17 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 2 Preliminary Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device: 1. Go to http://www.freescale.com. 2. Perform a part number search for the following partial device numbers: PCF51QM and MCF51QM. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q CCCC DD MMM T PP 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Q Description Qualification status Values • M = Fully qualified, general market flow • P = Prequalification CF51 = ColdFire V1 JF, JU, QF, QH, QM, QU CCCC DD Core code Device number Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 3 Terminology and guidelines Field MMM Description Memory size (program flash memory)1 Values • 32 = 32 KB • 64 = 64 KB • 128 = 128 KB V = –40 to 105 • FM = 32 QFN (5 mm x 5 mm) • HS = 44 Laminate QFN (5 mm x 5 mm) • LF = 48 LQFP (7 mm x 7 mm) • HX = 64 Laminate QFN (9 mm x 9 mm) • LH = 64 LQFP (10 mm x 10 mm) T PP Temperature range, ambient (°C) Package identifier 1. All parts also have FlexNVM, FlexRAM, and RAM. 2.4 Example This is an example part number: MCF51QM128VLH 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage 0.9 Min. 1.1 Max. V Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 4 Preliminary Freescale Semiconductor, Inc. Terminology and guidelines 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Digital I/O weak pullup/ 10 pulldown current Min. 130 Max. µA Unit 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins — Min. 7 Max. pF Unit 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 5 Terminology and guidelines 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage –0.3 Min. 1.2 Max. V Unit 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 20 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 10 0 Operating rating Measured characteristic 3.6 Relationship between ratings and operating requirements go r n ha dli ng ra g tin (m in. ) em en t( n. mi ) ir qu em en t( x ma .) r n ha dli ng ra g tin .) ax (m gr e ir qu gr e go O ra pe tin O ra pe tin O ra pe tin O ra pe tin Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Normal operating range - No permanent failure - Correct operation Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Handling range - No permanent failure –ȡ ȡ 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 6 Preliminary Freescale Semiconductor, Inc. Terminology and guidelines • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Description Digital I/O weak pullup/pulldown current 10 Min. 70 Typ. 130 Max. µA Unit 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 7 Ratings 5000 4500 4000 3500 IDD_STOP (μA) 3000 2500 2000 1500 1000 500 0 0.90 0.95 1.00 VDD (V) 1.05 1.10 TJ 150 °C 105 °C 25 °C –40 °C 4 Ratings 4.1 Thermal handling ratings Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Solder temperature, leaded Min. –55 — — Max. 150 260 245 Unit °C °C Notes 1 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. — Max. 3 Unit — Notes 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 8 Preliminary Freescale Semiconductor, Inc. General 4.3 ESD handling ratings Symbol VHBM VCDM ILAT Description Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 105°C Min. -2000 -500 -100 Max. +2000 +500 +100 Unit V V mA Notes 1 2 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol VDD IDD VDIO VAIO ID VDDA IDDA VREGIN Description Digital supply voltage Digital supply current Digital input voltage (except RESET, EXTAL, and XTAL) Analog, RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage Analog supply current Regulator input Min. –0.3 — –0.3 –0.3 –25 VDD – 0.3 — –0.3 Max. 3.8 120 VDD + 0.3 VDD + 0.3 25 VDD + 0.3 TBD 6.0 Unit V mA V V mA V mA V 5 General 5.1 Typical Value Conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol TA VDD Description Ambient temperature 3.3 V supply voltage 25 3.3 Value °C V Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 9 Nonswitching electrical specifications 5.2 Nonswitching electrical specifications 5.2.1 Voltage and Current Operating Requirements Table 1. Voltage and current operating requirements Symbol VDD VDDA Description Supply voltage Analog supply voltage Min. 1.71 1.71 –0.1 –0.1 Max. 3.6 3.6 0.1 0.1 Unit V V V V 1 0.7 × VDD 0.75 × VDD — — V V 2 — — 0.35 × VDD 0.3 × VDD V V 3 0 0 2 –0.2 mA mA 3 0 0 1.2 25 –5 — mA mA V Notes VDD – VDDA VDD-to-VDDA differential voltage VSS – VSSA VSS-to-VSSA differential voltage VIH Input high voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VIL Input low voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V IIC DC injection current — single pin • VIN > VDD • VIN < VSS DC injection current — total MCU limit, includes sum of all stressed pins • VIN > VDD • VIN < VSS VRAM VDD voltage required to retain RAM 1. The device always interprets an input as a 1 when the input is greater than or equal to VIH (min.) and less than or equal to VIH (max.), regardless of whether input hysteresis is turned on. 2. The device always interprets an input as a 0 when the input is less than or equal to VIL (max.) and greater than or equal to VIL (min.), regardless of whether input hysteresis is turned on. 3. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 10 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications 5.2.2 LVD and POR operating requirements Table 2. LVD and POR operating requirements Symbol VPOR VLVDH Description Falling VDD POR detect voltage Falling low-voltage detect threshold — high range (LVDV=01) Low-voltage warning thresholds — high range VLVW1H VLVW2H VLVW3H VLVW4H VHYSH VLVDL • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis — high range Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range VLVW1L VLVW2L VLVW3L VLVW4L VHYSL VBG tLPO • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) Low-voltage inhibit reset/recover hysteresis — low range Bandgap voltage reference Internal low power oscillator period factory trimmed 1. Rising thresholds are falling threshold + hysteresis voltage TBD TBD TBD TBD TBD TBD 1.80 1.90 2.00 2.10 40 1.00 1000 TBD TBD TBD TBD TBD TBD TBD V V V V mV V μs TBD TBD TBD TBD TBD 2.70 2.80 2.90 3.00 60 1.60 TBD TBD TBD TBD TBD TBD V V V V mV V 1 Min. TBD TBD Typ. 1.1 2.56 Max. TBD TBD Unit V V 1 Notes MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 11 Nonswitching electrical specifications 5.2.3 Voltage and current operating behaviors Table 3. Voltage and current operating behaviors Symbol VOH Description Output high voltage — high drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA Output high voltage — low drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA IOHT VOL Output high current total for all ports Output low voltage — high drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA Output low voltage — low drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA IOLT IIN Output low current total for all ports Input leakage current (per pin) • @ full temperature range • @ 25 °C IOZ RPU RPD Hi-Z (off-state) leakage current (per pin) Internal pullup resistors Internal pulldown resistors — — — 20 20 TBD TBD TBD 50 50 μA μA μA kΩ kΩ 1 2 — — — 0.5 0.5 100 V V mA — — 0.5 0.5 V V VDD – 0.5 VDD – 0.5 — — — 100 V V mA VDD – 0.5 VDD – 0.5 — — V V Min. Max. Unit Notes 1. Measured at Vinput = VSS 2. Measured at Vinput = VDD 5.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx-RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 50 MHz • Bus clock (and flash and Mini-FlexBus clocks) = 25 MHz MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 12 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 4. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. RUN → VLLS1 → RUN • RUN → VLLS1 • VLLS1 → RUN RUN → VLLS2 → RUN • RUN → VLLS2 • VLLS2 → RUN RUN → VLLS3 → RUN • RUN → VLLS3 • VLLS3 → RUN RUN → LLS → RUN • RUN → LLS • LLS → RUN RUN → VLPS → RUN • RUN → VLPS • VLPS → RUN RUN → STOP → RUN • RUN → STOP • STOP → RUN 1. Normal boot (FTFL_FOPT[LPBOOT] is 1) — — 4.4 4.6 μs μs — — 4.4 4.6 μs μs — — 4.4 6.5 μs μs — — 4.4 TBD μs μs — — 4.6 TBD μs μs 1 — — 4.4 TBD μs μs 1 Min. — Max. 300 Unit μs Notes 1 1 5.2.5 Power consumption operating behaviors Table 5. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Run mode current — all peripheral clocks disabled, code executing from RAM • @ 1.8 V • @ 3.0 V — — Table continues on the next page... 13.5 14 TBD TBD mA mA Min. — Typ. — Max. TBD Unit mA Notes 1 2 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 13 Nonswitching electrical specifications Table 5. Power consumption operating behaviors (continued) Symbol IDD_RUN Description Run mode current — all peripheral clocks disabled, code executing from flash memory with page buffering disabled • @ 1.8 V • @ 3.0 V IDD_RUN Run mode current — all peripheral clocks enabled, code executing from RAM, exercising flash memory • @ 1.8 V • @ 3.0 V IDD_RUN_MAX Run mode current — all peripheral clocks enabled and peripherals active, code executing from flash memory • @ 1.8 V • @ 3.0 V IDD_WAIT IDD_WAIT IDD_STOP IDD_VLPR IDD_VLPR IDD_VLPW IDD_VLPS IDD_LLS Wait mode current at 3.0 V — all peripheral clocks disabled Wait mode current at 3.0 V — all peripheral clocks disabled Stop mode current at 3.0 V Very-low-power run mode current at 3.0 V — all peripheral clocks disabled Very-low-power run mode current at 3.0 V — all peripheral clocks enabled Very-low-power wait mode current at 3.0 V Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V • @ –40 to 25 °C • @ 70 °C • @ 105 °C IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V • @ –40 to 25 °C • @ 70 °C • @ 105 °C IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V • @ –40 to 25 °C • @ 70 °C • @ 105 °C — — — Table continues on the next page... 1.5 TBD TBD TBD TBD TBD μA μA μA — — — 2.0 TBD TBD TBD TBD TBD μA μA μA 10,11 — — — 3.0 TBD TBD TBD TBD TBD μA μA μA 10,11,12 — — 20 20 TBD TBD mA mA 4 — — — — — — — — — TBD TBD 6.6 TBD 0.34 0.63 0.78 0.15 12 TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA μA 7 8 9 10 10,11,12 5 6 — — 16.6 17 TBD TBD mA mA 3 Min. Typ. Max. Unit Notes 2 MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 14 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 5. Power consumption operating behaviors (continued) Symbol IDD_VLLS1 Description Very low-leakage stop mode 1 current at 3.0 V • @ –40 to 25 °C • @ 70 °C • @ 105 °C IDD_OSC Average current for OSC enabled with 32 kHz crystal at 3.0 V • @ –40 to 25 °C • @ 70 °C • @ 105 °C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled. 3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 5. 25 MHz core and system clocks, and 12.5 MHz bus clock. MCG configured for FEI mode. 6. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. 7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash memory. 8. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled, but peripherals are not in active operation. Code executing from flash memory. 9. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. 10. OSC clocks disabled. 11. All pads disabled. 12. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For devices with 8 KB of RAM, power consumption is reduced by 750 nA. — — — 1.3 TBD TBD TBD TBD TBD μA μA μA Min. Typ. Max. Unit Notes 10,11 — — — 0.7 TBD TBD — — — μA μA μA 5.2.5.1 • • • • • Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks disabled except FTFL LVD disabled, voltage regulator disabled No GPIOs toggled Code execution from flash memory DIAGRAM TBD Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled The following data was measured under these conditions: • MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) • All peripheral clocks enabled, but peripherals are not in active operation MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 15 Nonswitching electrical specifications • LVD disabled, voltage regulator disabled • No GPIOs toggled • Code execution from flash memory DIAGRAM TBD Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled 5.2.6 EMC radiated emissions operating behaviors Table 6. EMC radiated emissions operating behaviors Symbol VRE1 VRE2 VRE3 VRE4 Description Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 0.15–1000 Typ. TBD TBD TBD TBD TBD — 2, 3 Unit dBμV Notes 1, 2 VRE_IEC_SAE IEC and SAE level 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/ Wideband TEM (GTEM) Cell Method. 2. VDD = 3 V, TA = 25 °C, fOSC = 16 MHz (crystal), fBUS = 25 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to http://www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 7. Capacitance attributes Symbol CIN_A CIN_D Description Input capacitance: analog pins Input capacitance: digital pins Min. — — Max. 7 7 Unit pF pF MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 16 Preliminary Freescale Semiconductor, Inc. Nonswitching electrical specifications 5.3 Switching electrical specifications Table 8. Device clock specifications Symbol Description Normal run mode fSYS fBUS FB_CLK fLPTMR System and core clock Bus clock Mini-FlexBus clock LPTMR clock VLPR mode fSYS fBUS FB_CLK fLPTMR System and core clock Bus clock Mini-FlexBus clock LPTMR clock — — — — 2 1 1 25 MHz MHz MHz MHz — — — — 50 25 25 25 MHz MHz MHz MHz Min. Max. Unit Notes 5.3.1 General Switching Specifications These general purpose specifications apply to all signals configured for EGPIO, MTIM, CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V, and full temperature range. The GPIO are set for high drive, no slew rate control, and no input filter, digital or analog, unless otherwise specified. Table 9. EGPIO General Control Timing Symbol G1 G2 G3 G4 Description Bus clock from CLK_OUT pin high to GPIO output valid Bus clock from CLK_OUT pin high to GPIO output invalid (output hold) GPIO input valid to bus clock high Bus clock from CLK_OUT pin high to GPIO input invalid GPIO pin interrupt pulse width (digital glitch filter disabled) Synchronous path1 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) Asynchronous path2 Table continues on the next page... 100 — — 1 28 — 1.5 Min. 32 — — 4 — Max. ns ns ns ns Bus clock cycles ns Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 17 Nonswitching electrical specifications Table 9. EGPIO General Control Timing (continued) Symbol Description GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) Asynchronous path2 External reset pulse width (digital glitch filter disabled) Mode select (MS) hold time after reset deassertion 100 2 — — ns Bus clock cycles 50 Min. — Max. ns Unit 1. The greater synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. Bus clock G1 G2 Data outputs G3 G4 Data inputs Figure 3. EGPIO timing diagram The following general purpose specifications apply to all signals configured for RGPIO, FTM, and UART. The conditions are 25 pf load, VDD = 3.6 V to 1.71 V, and full temperature range. The GPIO are set for high drive, no slew rate control, and no input filter, digital or analog, unless otherwise specified. Table 10. RGPIO General Control Timing Symbol R1 R2 R3 R4 Description CPUCLK from CLK_OUT pin high to GPIO output valid CPUCLK from CLK_OUT pin high to GPIO output invalid (output hold) GPIO input valid to bus clock high CPUCLK from CLK_OUT pin high to GPIO input invalid — 1 17 — Min. 16 — — 2 Max. ns ns ns ns Unit MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 18 Preliminary Freescale Semiconductor, Inc. Thermal specifications Bus clock R1 R2 Data outputs R3 R4 Data inputs Figure 4. RGPIO timing diagram 5.4 Thermal specifications 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol TJ TA Description Die junction temperature Ambient temperature Min. –40 –40 Max. 125 105 Unit °C °C 5.4.2 Thermal attributes Board type Symbol Description 64 LQFP 64 Laminate QFN 108 48 LQFP 44 Laminate QFN 108 32 QFN Unit Notes Single-layer RθJA (1s) Four-layer (2s2p) RθJA Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (natural convection) Thermal resistance, junction to ambient (200 ft./min. air speed) Thermal resistance, junction to ambient (200 ft./min. air speed) 73 79 98 °C/W 1 54 69 55 69 33 °C/W 1 Single-layer RθJMA (1s) Four-layer (2s2p) RθJMA 61 91 66 91 81 °C/W 1 48 63 48 63 28 °C/W 1 Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 19 Peripheral operating requirements and behaviors Board type Symbol Description 64 LQFP 64 Laminate QFN 44 31 6.0 48 LQFP 44 Laminate QFN 44 31 6.0 32 QFN Unit Notes — — — RθJB RθJC ΨJT Thermal resistance, junction to board Thermal resistance, junction to case Thermal characterization parameter, junction to package top outside center (natural convection) 37 20 5.0 34 20 4.0 13 2.2 6.0 °C/W °C/W °C/W 2 3 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions —Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions —Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions —Natural Convection (Still Air). 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug specifications Table 12. Background debug mode (BDM) timing Number 1 2 Symbol tMSSU tMSH Description BKGD/MS setup time after issuing background debug force reset to enter user mode or BDM BKGD/MS hold time after issuing background debug force reset to enter user mode or BDM1 Min. 500 100 — — Max. ns µs Unit 1. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 20 Preliminary Freescale Semiconductor, Inc. System modules 6.2 System modules 6.2.1 VREG electrical specifications Table 13. VREG electrical specifications Symbol VREGIN IDDon IDDstby IDDoff Description Input supply voltage Quiescent current — Run mode, load current equal zero, input supply (VREGIN) > 3.6 V Quiescent current — Standby mode, load current equal zero Quiescent current — Shutdown mode • VREGIN = 5.0 V and temperature=25C • Across operating voltage and temperature ILOADrun ILOADstby VReg33out Maximum load current — Run mode Maximum load current — Standby mode Regulator output voltage — Input supply (VREGIN) > 3.6 V • Run mode • Standby mode VReg33out COUT ESR ILIM Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode External output capacitor External output capacitor equivalent series resistance Short circuit current 3 TBD TBD 1.76 1 TBD 3.3 2.8 — 2.2 — 290 3.6 3.6 3.6 8.16 100 TBD V V V μF mΩ mA 1 — — — — 500 — — — — TBD 120 1 nA μA mA mA Min. 2.7 — — Typ. — 120 1.1 Max. 5.5 TBD TBD Unit V μA μA Notes 1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. 6.3 Clock modules 6.3.1 MCG specifications Table 14. MCG specifications Symbol fints_ft Description Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25°C Min. — Typ. 32.768 Max. — Unit kHz Notes Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 21 Clock modules Table 14. MCG specifications (continued) Symbol fints_t Iints tirefsts Δfdco_res_t Description Internal reference frequency (slow clock) — user trimmed Internal reference (slow clock) current Internal reference (slow clock) startup time Resolution of trimmed DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM Resolution of trimmed DCO output frequency at fixed voltage and temperature — using SCTRIM only Total deviation of trimmed average DCO output frequency over voltage and temperature Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C Internal reference frequency (fast clock) — user trimmed Internal reference (fast clock) current Internal reference startup time (fast clock) Loss of external clock minimum frequency — RANGE = 00 Loss of external clock minimum frequency — RANGE = 01, 10, or 11 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 640 × ffll_ref Mid range (DRS=01) 1280 × ffll_ref Mid-high range (DRS=10) 1920 × ffll_ref High range (DRS=11) 2560 × ffll_ref Table continues on the next page... 80 83.89 100 MHz 60 62.91 75 MHz 40 41.94 50 MHz 31.25 20 — 20.97 39.0625 25 kHz MHz 2, 3 Min. 31.25 — — — Typ. — TBD TBD ± 0.1 Max. 39.0625 — 4 ± 0.3 Unit kHz µA µs %fdco 1 Notes Δfdco_res_t — ± 0.2 ± 0.5 %fdco 1 Δfdco_t Δfdco_t — + 0.5 - 1.0 ± 3.5 %fdco %fdco 1 — ± 0.5 ± TBD 1 fintf_ft fintf_t Iintf tirefstf floc_low floc_high 3.4 3 — — (3/5) x fints_t (16/5) x fints_t — — TBD TBD — — 4 5 — TBD — — MHz MHz µA µs kHz kHz MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 22 Preliminary Freescale Semiconductor, Inc. Clock modules Table 14. MCG specifications (continued) Symbol Description Low range (DRS=00) 732 × ffll_ref Mid range (DRS=01) 1464 × ffll_ref Mid-high range (DRS=10) 2197 × ffll_ref High range (DRS=11) 2929 × ffll_ref Jcyc_fll Jacc_fll tfll_acquire FLL period jitter FLL accumulated jitter of DCO output over a 1µs time window FLL target frequency acquisition time PLL fvco Ipll VCO operating frequency PLL operating current • PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) PLL operating current • PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) PLL reference frequency range PLL period jitter • fvco = 48 MHz • fvco = 100 MHz Jacc_pll PLL accumulated jitter over 1µs window • fvco = 48 MHz • fvco = 100 MHz Dlock Dunl tpll_lock Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time — — ± 1.49 ± 4.47 — 1350 600 — — — — — ± 2.98 ± 5.97 0.15 + 1075(1/ fpll_ref) ps ps % % ms 11 — — 120 50 — — ps ps 9, 10 48.0 — — 1060 100 — MHz µA 8 — — — TBD TBD — TBD TBD 1 ps ps ms 6 6 7 — 95.98 — MHz — 71.99 — MHz — 47.97 — MHz Min. — Typ. 23.99 Max. — Unit MHz Notes 4, 5 fdco_t_DMX3 DCO output frequency 2 Ipll — 600 — µA 8 fpll_ref Jcyc_pll 2.0 — 4.0 MHz 9, 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 23 Clock modules 6. This specification was obtained at TBD frequency. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. PLL period jitter is measured in RMS. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 Oscillator electrical specifications This section provides the electrical characteristics of the module. 6.3.2.1 Symbol VDD IDDOSC Oscillator DC electrical specifications Description Supply voltage Supply current — low-power mode (HGO=0) • 32 kHz • 1 MHz • 4 MHz • 8 MHz (only RANGE=01) • 16 MHz • 24 MHz • 32 MHz — — — — — — — Min. 1.71 Table 15. Oscillator DC electrical specifications Typ. — Max. 3.6 Unit V 1 500 100 200 300 950 1.2 1.5 — — — — — — — nA μA μA μA μA mA mA 1 — — — — — — — — — Table continues on the next page... 25 200 400 500 2.5 3 4 — — — — — — — — — — — μA μA μA μA mA mA mA 2, 3 2, 3 Notes IDDOSC Supply current — high gain mode (HGO=1) • 32 kHz • 1 MHz • 4 MHz • 8 MHz (only RANGE=01) • 16 MHz • 24 MHz • 32 MHz Cx Cy EXTAL load capacitance XTAL load capacitance MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 24 Preliminary Freescale Semiconductor, Inc. Clock modules Table 15. Oscillator DC electrical specifications (continued) Symbol RF Description Feedback resistor — low-frequency, low-power mode (HGO=0) Feedback resistor — low-frequency, high-gain mode (HGO=1) Feedback resistor — high-frequency, low-power mode (HGO=0) Feedback resistor — high-frequency, high-gain mode (HGO=1) RS Series resistor — low-frequency, low-power mode (HGO=0) Series resistor — low-frequency, high-gain mode (HGO=1) Series resistor — high-frequency, low-power mode (HGO=0) Series resistor — high-frequency, high-gain mode (HGO=1) • 1 MHz resonator • 2 MHz resonator • 4 MHz resonator • 8 MHz resonator • 16 MHz resonator • 20 MHz resonator • 32 MHz resonator Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) 1. 2. 3. 4. 5. — — — — — — — — 6.6 3.3 0 0 0 0 0 0.6 — — — — — — — — kΩ kΩ kΩ kΩ kΩ kΩ kΩ V Min. — — — — — — — Typ. — 10 — 1 — 200 — Max. — — — — — — — Unit MΩ MΩ MΩ MΩ kΩ kΩ kΩ Notes 2, 4 — VDD — V — 0.6 — V — VDD — V VDD=3.3 V, Temperature =25 °C See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 25 Memories and memory interfaces 6.3.2.2 Symbol fosc_lo fosc_hi_1 Oscillator frequency specifications Description Oscillator crystal or resonator frequency — low frequency mode (MCG_C2[RANGE]=00) Oscillator crystal or resonator frequency — high frequency mode (low range) (MCG_C2[RANGE]=01) Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) Input clock frequency (external clock mode) Input clock duty cycle (external clock mode) Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) Min. 32 1 Table 16. Oscillator frequency specifications Typ. — — Max. 40 8 Unit kHz MHz Notes fosc_hi_2 8 — 32 MHz fec_extal tdc_extal tcst — 40 — — — — 50 750 250 0.6 50 60 — — — MHz % ms ms ms 1 2, 3 — 1 — ms 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL 2. Proper PC board layout procedures must be followed to achieve specifications. 3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.4 Memories and memory interfaces 6.4.1 Flash (FTFL) electrical specifications This section describes the electrical characteristics of the FTFL module. 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 17. NVM program/erase timing specifications Symbol thvpgm4 Description Longword Program high-voltage time Min. — Typ. 20 Max. TBD Unit μs Notes Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 26 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces Table 17. NVM program/erase timing specifications (continued) Symbol thversscr thversblk32k Description Sector Erase high-voltage time Erase Block high-voltage time for 32 KB Min. — — — Typ. 20 20 80 Max. 100 100 400 Unit ms ms ms Notes 1 1 1 thversblk128k Erase Block high-voltage time for 128 KB 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Symbol Flash timing specifications — commands Description Read 1s Block execution time Min. Table 18. Flash command timing specifications Typ. Max. Unit Notes trd1blk32k trd1blk128k trd1sec1k tpgmchk trdrsrc tpgm4 • 32 KB data flash • 128 KB data flash Read 1s Section execution time (flash sector) Program Check execution time Read Resource execution time Program Longword execution time Erase Flash Block execution time — — — — — — — — — — — 50 0.4 1.4 40 35 35 TBD ms ms μs μs μs μs 2 1 1 1 tersblk32k tersblk128k tersscr • 32 KB data flash • 128 KB data flash Erase Flash Sector execution time Program Section execution time — — — 20 80 20 100 400 100 ms ms ms 2 tpgmsec512 tpgmsec1k trd1all trdonce tpgmonce tersall tvfykey • 512 B flash • 1 KB flash Read 1s All Blocks execution time Read Once execution time Program Once execution time Erase All Blocks execution time Verify Backdoor Access Key execution time Program Partition for EEPROM execution time — — — — — — — TBD TBD — — 50 100 — TBD TBD 1.8 35 TBD 500 35 ms ms ms μs μs ms μs 2 1 1 tpgmpart32k • 32 KB FlexNVM Set FlexRAM Function execution time: — 25 TBD ms tsetram8k tsetram32k • 8 KB EEPROM backup • 32 KB EEPROM backup — — TBD TBD TBD TBD ms ms Byte-write to FlexRAM for EEPROM operation Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 27 Memories and memory interfaces Table 18. Flash command timing specifications (continued) Symbol teewr8bers Description Byte-write to erased FlexRAM location execution time Byte-write to FlexRAM execution time: teewr8b8k teewr8b16k teewr8b32k • 8 KB EEPROM backup • 16 KB EEPROM backup • 32 KB EEPROM backup — — — TBD TBD TBD TBD TBD 1.5 ms ms ms Min. — Typ. 100 Max. TBD Unit μs Notes 3 Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time Word-write to FlexRAM execution time: teewr16b8k teewr16b16k teewr16b32k • 8 KB EEPROM backup • 16 KB EEPROM backup • 32 KB EEPROM backup — — — TBD TBD TBD TBD TBD 1.5 ms ms ms — 100 TBD μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time Longword-write to FlexRAM execution time: teewr32b8k teewr32b16k teewr32b32k • 8 KB EEPROM backup • 16 KB EEPROM backup • 32 KB EEPROM backup — — — TBD TBD TBD TBD TBD 2.7 ms ms ms — 200 TBD μs 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 6.4.1.3 Flash (FTFL) current and power specfications Description Worst case programming current in program flash Table 19. Flash (FTFL) current and power specfications Typ. 10 Unit mA Symbol IDD_PGM 6.4.1.4 Symbol Reliability specifications Description Table 20. NVM reliability specifications Min. Program Flash Typ.1 Max. Unit Notes tnvmretp10k tnvmretp1k Data retention after up to 10 K cycles Data retention after up to 1 K cycles 5 10 TBD TBD — — years years 2 2 Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 28 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces Table 20. NVM reliability specifications (continued) Symbol tnvmretp100 nnvmcycp Description Data retention after up to 100 cycles Cycling endurance Min. 15 10 K Data Flash tnvmretd10k tnvmretd1k tnvmretd100 nnvmcycd Data retention after up to 10 K cycles Data retention after up to 1 K cycles Data retention after up to 100 cycles Cycling endurance 5 10 15 10 K FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance tnvmretee10 tnvmretee1 Data retention up to 10% of write endurance Data retention up to 1% of write endurance Write endurance nnvmwree16 nnvmwree128 nnvmwree512 nnvmwree4k nnvmwree8k • EEPROM backup to FlexRAM ratio = 16 • EEPROM backup to FlexRAM ratio = 128 • EEPROM backup to FlexRAM ratio = 512 • EEPROM backup to FlexRAM ratio = 4096 • EEPROM backup to FlexRAM ratio = 8192 35 K 315 K 1.27 M 10 M 20 M TBD TBD TBD TBD TBD — — — — — writes writes writes writes writes 5 10 15 TBD TBD TBD — — — years years years 2 2 2 4 TBD TBD TBD TBD — — — — years years years cycles 2 2 2 3 Typ.1 TBD TBD Max. — — Unit years cycles Notes 2 3 1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618. 2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum value assumes all byte-writes to FlexRAM. 6.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFL to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 29 Memories and memory interfaces While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_FlexRAM = EEPROM – 2 × EEESIZE EEESIZE × Write_efficiency × nnvmcycd where • Writes_FlexRAM — minimum number of writes to each FlexRAM location • EEPROM — allocated FlexNVM based on DEPART; entered with Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycd — data flash cycling endurance MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 30 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces Figure 5. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 21. EzPort switching specifications Num Description Operating voltage EP1 EP1a EP2 EP3 EP4 EP5 EP6 EP7 EP8 EZP_CK frequency of operation (all commands except READ) EZP_CK frequency of operation (READ command) EZP_CS negation to next EZP_CS assertion EZP_CS input valid to EZP_CK high (setup) EZP_CK high to EZP_CS input invalid (hold) EZP_D input valid to EZP_CK high (setup) EZP_CK high to EZP_D input invalid (hold) EZP_CK low to EZP_Q output valid (setup) EZP_CK low to EZP_Q output invalid (hold) Table continues on the next page... Min. 2.7 — — 2 x tEZP_CK 15 0.0 15 0.0 — 0.0 Max. 3.6 fSYS/2 fSYS/8 — — — — — 25 — Unit V MHz MHz ns ns ns ns ns ns ns MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 31 Memories and memory interfaces Table 21. EzPort switching specifications (continued) Num EP9 Description EZP_CS negation to EZP_Q tri-state Min. — Max. 12 Unit ns EZP_CK EP3 EP4 EP2 EZP_CS EP7 EP8 EP9 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 6. EzPort Timing Diagram 6.4.3 Mini-Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 22. Flexbus switching specifications Num Description Operating voltage Frequency of operation FB1 FB2 FB3 FB4 FB5 Clock period Address, data, and control output valid Address, data, and control output hold Data and FB_TA input setup Data and FB_TA input hold Min. 2.7 — 20 TBD 1 20 10 Max. 3.6 25 — 20 — — — Unit V MHz ns ns ns ns ns 1 1 2 2 Notes MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 32 Preliminary Freescale Semiconductor, Inc. Memories and memory interfaces 1. Specification is valid for all FB_AD[31:0], FB_CSn, FB_OE, FB_R/W, and FB_TS. 2. Specification is valid for all FB_AD[31:0]. Note The following diagrams refer to signal names that may not be included on your particular device. Ignore these extraneous signals. Also, ignore the AA=0 portions of the diagrams because this setting is not supported in the Mini-FlexBus. FB1 FB_CLK FB3 FB5 FB_A[Y] FB2 Address FB4 Data FB_D[X] FB_RW FB_TS FB_ALE Address AA=1 FB_CSn FB_OEn FB4 AA=0 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 7. Mini-FlexBus read timing diagram MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 33 Memories and memory interfaces FB1 FB_CLK FB2 FB3 Address FB_A[Y] FB_D[X] FB_RW FB_TS FB_ALE Address Data AA=1 FB_CSn FB_OEn FB4 AA=0 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 8. Mini-FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. 34 Preliminary Freescale Semiconductor, Inc. Analog 6.6 Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 Symbol VDDA ΔVDDA ΔVSSA VREFH VREFL VADIN CADIN 16-bit ADC operating conditions Description Supply voltage Supply voltage Ground voltage ADC reference voltage high Reference voltage low Input voltage Input capacitance • 16 bit modes • 8/10/12 bit modes Conditions Absolute Delta to VDD (VDDVDDA) Delta to VSS (VSSVSSA) Min. 1.71 -100 -100 1.13 VSSA VREFL — — Table 23. 16-bit ADC operating conditions Typ.1 — 0 0 VDDA VSSA — 8 4 Max. 3.6 +100 +100 VDDA VSSA VREFH 10 5 Unit V mV mV V V V pF 2 2 Notes RADIN RAS Input resistance Analog source resistance 13/12 bit modes fADCK < 4MHz ≤ 13 bit modes — 2 5 kΩ 3 — — 5 kΩ fADCK fADCK ADC conversion clock frequency ADC conversion clock frequency 4 1.0 — 18.0 MHz 5 2.0 — 12.0 MHz 16 bit modes Table continues on the next page... MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 35 Analog Table 23. 16-bit ADC operating conditions (continued) Symbol Crate Description ADC conversion rate Conditions ≤ 13 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16 bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the best results. The results in this datasheet were derived from a system which has