MM912G634CM1AE

Freescale Semiconductor Advance Information Document Number: MM912_634D1 Rev. 4.0, 5/2011 Integrated S12 Based Relay Driver with LIN The MM912G634 (48 kB) and MM912H634 (64 kB) are integrated single package solutions that integrates an HCS12 microcontroller with a SMARTMOS analog control IC. The Die to Die Interface (D2D) controlled analog die combines system base chip and application specific functions, including a LIN transceiver. Features • • • • • • • • • • 16-Bit S12 CPU, 64/48 kByte P-FLASH, 6.0 kByte RAM; 4/2 kByte D-FLASH Background debug (BDM) & debug module (DBG) Die to Die bus interface for transparent memory mapping On-chip oscillator & two independent watchdogs LIN 2.1 Physical Layer Interface with integrated SCI 10 digital MCU GPIOs shared with SPI (PA7…0, PE1…0) 10-Bit, 15 Channel - Analog to Digital Converter (ADC) 16-Bit, 4 Channel - Timer Module (TIM16B4C) 8-Bit, 2 Channel - Pulse width modulation module (PWM) • • • • • • • • • MM912_634 48-PIN LQFP, 7.0 mm x 7.0 mm AE SUFFIX: Exposed Pad Option AP SUFFIX: Non Exposed Pad Option ORDERING INFORMATION See Page 2. Six high voltage / Wake-up inputs (L5…0) Three low voltage GPIOs (PB2…0) Low power modes with cyclic sense & forced wake-up Current sense module with selectable gain Reverse battery protected voltage sense module Two protected low side outputs to drive inductive loads Two protected high side outputs Chip temperature sensor Hall sensor supply & integrated voltage regulator(s) Battery Sense Power Supply LIN Interface ADC Supply 2.5 V Suppy 5.0 V Supply Digital Ground Reset VSENSE VS1 MM912_634 VS2 LS1 5.0 V Digital I/O Debug and External Oscillator MCU Test PGND LIN LGND LS2 ADC25 AGND ISENSEH* VDD ISENSEL* VDDD2D HSUP VDDX VDDRX DGND VSSD2D PTB0/AD0/RX/TIM0CH0 VSSRX PTB1/AD1/TX/TIM0CH1 RESET PTB2/AD2/PWM/TIM0CH2 RESET_A HS1 PA0/MISO PA1/MOSI HS2* PA2/SCK PA3/SS PA4 L0 PA5 L1 PA6 L2 PA7 L3 BKGD/MODC L4* PE0/EXTAL L5* PE1/XTAL TCLK TEST TEST_A * Feature not availablre in all Analog Options M Low Side Drivers Current Sense Moe Hall Sensor Hall Sensor Hall Sensor Supply 5.0 V GPI/O with optional pull-up (shared with ADC, PWM, Timer, and SCI) 12 V Light/LED and Switch Supply Analog/Digita inputs (High Voltage and Wake-up capable) Analog Test Figure 1. Simplified Application Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010-2011. All rights reserved. Ordering Information 1 Ordering Information Table 1. ORDERING INFORMATION Temperature Range (TA) -40°C to 125°C -40°C to 105°C -40°C to 105°C -40°C to 125°C -40°C to 105°C Max. Bus Frequency in MHz (fBUSMAX) 20 20 16 20 20 Analog Option(1) A1 A1 A2 A1 A1 Device (Add an R2 suffix for Tape and Reel orders) MM912G634CM1AE MM912G634CV1AE MM912G634CV2AP MM912H634CM1AE MM912H634CV1AE Package LQFP48-EP LQFP48-EP LQFP48 LQFP48-EP LQFP48-EP Flash (kB) 48(2) 48 48 (2) (2) Data Flash (kB) 2(3) 2 2 (3) (3) RAM (kB) 2(4) 2(4) 2 (4) 64 64 4 4 6 6 Note: 1. See Table 2. 2. The 48 kB Flash option (MM912G634) using the same S12I64 MCU with the tested FLASHSIZE reduced to 48 kB. This will limit the usable Flash area to the first 48 kB (0x3_4000-0x3_FFFF). 3. The 48 kB Flash option (MM912G634) using the same S12I64 MCU with the tested Data - FLASHSIZE reduced to 2.0 kB. This will limit the usable Data Flash area to the first 2.0 kB (0x0_4400-0x0_4BFF). 4. The 48 kB Flash option (MM912G634) using the same S12I64 MCU with the tested RAMSIZE reduced to 2.0 kB. This will limit the usable RAM area to the first 2.0 kB (0x0_2800-0x0_2FFF). Table 2. Analog Options(5) Feature Battery Sense Module Current Sense Module 2nd High Side Output (HS2) Wake-up Inputs (Lx) Hall Supply Output (HSUP) LIN Module A1 YES YES YES L0…L5 YES YES A2 YES NO YES L0…L3 YES YES Note: 5. This table only highlights the analog die differences between the derivatives. Features highlighted as “NO” or the Lx Inputs not mentioned are not available in the specific option and not bonded out and/or not tested. See Section 4.3.3, “Analog Die Options for detailed information. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 2 Ordering Information The device part number is following the standard scheme in Table 3: Table 3. Part Numbering Scheme MM 9 cc f xxx r t v PPP RR Product Category MM- Qualified Standard SM- Custom Device PM- Prototype Device Memory Type 9 = Flash, OTP Blank = ROM Core 08 = HC08 12 = HC12 Memory Size A 1k B2k C4k D8k E 16 k F 32 k G 48 k H 64 k I 96 k J 128 k Analog Core/Target Revision (default A) Temperature Range I = 0 °C to 85 °C C = -40 °C to 85 °C V = -40 °C to 105 °C M = -40 °C to 125 °C Variation (default blank) Package Designator Tape and Reel Indicator MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 3 Table of Contents 1 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 MM912_634 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2 MCU Die Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.3 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.4 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.5 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.6 Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.7 Thermal Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.8 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.9 Additional Test Information ISO7637-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.2 Device Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.3 MM912_634 - Analog Die Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.6 Die to Die Interface - Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 4.9 Wake-up / Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.10 Window Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 4.11 Hall Sensor Supply Output - HSUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.12 High Side Drivers - HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 4.13 Low Side Drivers - LSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 4.14 PWM Control Module (PWM8B2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.15 LIN Physical Layer Interface - LIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 4.16 Serial Communication Interface (S08SCIV4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.17 High Voltage Inputs - Lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.18 General Purpose I/O - PTB[0…2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.19 Basic Timer Module - TIM (TIM16B4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 4.20 Analog Digital Converter - ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 4.21 Current Sense Module - ISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 4.22 Temperature Sensor - TSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 4.23 Supply Voltage Sense - VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 4.24 Internal Supply Voltage Sense - VS1SENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 4.25 Internal Bandgap Reference Voltage Sense - BANDGAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 4.26 MM912_634 - Analog Die Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 4.27 MM912_634 - MCU Die Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 4.28 Port Integration Module (S12IPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 4.29 Memory Map Control (S12PMMCV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.30 Interrupt Module (S12SINTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 4.31 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 4.32 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 4.33 Security (S12X9SECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 4.34 Impact on MCU modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 4.35 Secure firmware Code Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 4.36 Initialization of a Virgin Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 4.37 Impact of Security on Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 4.38 S12 Clock, Reset and Power Management Unit (S12CPMU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 4.39 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 4.40 64 KByte Flash Module (S12FTMRC64K1V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 4.41 Die-to-Die Initiator (D2DIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 3 4 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 4 5 6 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 5.1 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 5 BKGD/MODC RESET_A ISENSEH ISENSEL TEST_A RESET PGND TCLK PA7 LS2 Test Interface Internal Bus Current Sense Module Low Side Control Module LS1 L5 Reset Control Module 2 Channel PWM Module L4 L3 Lx Input Module Internal Bus PE0/EXTAL PORTE[0:1] Amplitude Contr. Low Power Pierce OSC Single-Wire Background Debug Module COP Watchdog Periodic Interrupt Interrupt Module L1 OSC (trimmable) Chip Temp Sense Module PE1/XTAL Reset Generation and Test Entry PLL with Freq. Modulation option OSC Clock Monitor L0 TEST CPU 12-V1 PA5 CPU Register ALU Interrupt Control Module Debug Module include 64 byte Trace Buffer RAM AGND D2DCLK Analog Multiplexer ADC 10bit PA4 Data Flash 4k Bytes with ECC RAM 6k Byte Flash 64k Bytes with ECC D2DDAT0 ADC2p5 D2DDAT1 D2DI Die To Die Interface PA3 D2DDAT2 PTB2/AD2/PWM/TIMCH2 PA2 PORTA DDRA SS SCK MOSI MISO D2DDAT3 SPI VREG 1.8V Core 2.7V Flash PA1 4 Channel Timer Module GPIO PTB1/AD1/TX/TIMCH1 D2DINT PA0 MCU Die SCI Cascaded Voltage Regulators VDD = 2.5V VDDX = 5V High Side Control Module 18V clamped Output Module VBAT Sense Module LIN Physical Layer PTB0/AD0/RX/TIMCH0 LGND VSSRX Figure 2. Device Block Diagram Wake Up Module L2 MM912_634 Advance Information, Rev. 4.0 Analog Die PA6 Window Watchdog Module VDDRX Freescale Semiconductor VSENSE DGND HSUP VDDX VS1 VS2 HS1 HS2 VSSD2D VDDD2D VDD LIN 6 Pin Assignment 2 Pin Assignment RESET_A ISENSEH ISENSEL TEST_A RESET PGND BKGD TCLK PA7 LS2 LS1 NC 48 47 46 45 44 43 42 41 40 39 38 37 PA6 PE0/EXTAL PE1/XTAL TEST PA5 PA4 PA3 PA2 PA1 PA0 VSSRX VDDRX 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 L5 L4 L3 L2 L1 L0 AGND ADC2p5 PTB2 PTB1 PTB0 LGND NOTE The device exposed pad (package option AE only) is recommended to be connected to GND. Not all pins are available for analog die option 2. See Section 4.3.3, “Analog Die Options for details. 13 VSSD2D 14 VDDD2D MM912_634 Advance Information, Rev. 4.0 15 VDD Figure 3. MM912_634 Pin Out 16 VDDX 17 DGND 18 VSENSE 19 VS1 20 VS2 21 HS1 22 HS2 23 HSUP 24 LIN Freescale Semiconductor 7 Pin Assignment 2.1 MM912_634 Pin Description The following table gives a brief description of all available pins on the MM912_634 package. Refer to the highlighted chapter for detailed information. Table 4. MM912_634 Pin Description Pin # 1 Pin Name PA6 Formal Name MCU PA6 Description General purpose port A input or output pin 6. See Section 4.28, “Port Integration Module (S12IPIMV1) EXTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock and port PE may be used for general purpose I/O. See Section 4.38.2.2, “EXTAL and XTAL and Section 4.28, “Port Integration Module (S12IPIMV1). XTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock and port PE may be used for general purpose I/O. See Section 4.38.2.2, “EXTAL and XTAL and Section 4.28, “Port Integration Module (S12IPIMV1). This input only pin is reserved for test. This pin has a pull-down device. The TEST pin must be tied to EVSS in user mode. General purpose port A input or output pin 5. See Section 4.28, “Port Integration Module (S12IPIMV1) General purpose port A input or output pin 4. See Section 4.28, “Port Integration Module (S12IPIMV1). General purpose port A input or output pin 3, shared with the SS signal of the integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1). General purpose port A input or output pin 2, shared with the SCLK signal of the integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1). General purpose port A input or output pin 1, shared with the MOSI signal of the integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1). General-purpose port A input or output pin 0, shared with the MISO signal of the integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1). Ground for the MCU 5.0 V power supply. MCU 5.0 V - Core- and Flash Voltage Regulator supply. See Section 4.27, “MM912_634 - MCU Die Overview. Ground for the MCU 2.5 V power supply. MCU 2.5 V - MCU Die-to-Die Interface power supply. See Section 4.27, “MM912_634 - MCU Die Overview. +2.5 V main voltage regulator output pin. External capacitor (CVDD) needed. See Section 4.5, “Power Supply. 2 PE0/EXTAL MCU Oscillator 3 PE1/XTAL MCU Oscillator 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TEST PA5 PA4 PA3 PA2 PA1 PA0 VSSRX VDDRX VSSD2D VDDD2D VDD VDDX DGND MCU Test MCU PA5 MCU PA4 MCU PA3 / SS MCU PA2 / SCK MCU PA1 / MOSI MCU PA0 / MISO MCU 5.0 V Ground MCU 5.0 V Supply MCU 2.5 V Ground MCU 2.5 V Supply Voltage Regulator Output 2.5 V Voltage Regulator Output +5.0 V main voltage regulator output pin. External capacitor (CVDDX) needed. See 5.0 V Section 4.5, “Power Supply. Digital Ground This pin is the device digital ground connection for the 5.0 V and 2.5V logic. DGND, LGND, and AGND are internally connected to PGND via a back to back diode. Battery voltage sense input. This pin can be connected directly to the battery line for voltage measurements. The voltage present at this input is scaled down by an internal voltage divider, and can be routed to the internal ADC via the analog multiplexer.The pin is self-protected against reverse battery connections. An external resistor (RVSENXSE) is needed for protection(6). See Section 4.23, “Supply Voltage Sense - VSENSE. Note: This pin function is not available on all device configurations. 18 VSENSE Voltage Sense Note: 6. An optional filter capacitor CVSENSE is recommended to be placed between the board connector and DVSENSE to GND for increased ESD performance. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 8 Pin Assignment Table 4. MM912_634 Pin Description Pin # Pin Name Formal Name Description This pin is the device power supply pin 1. VS1 is primarily supplying the VDDX Voltage regulator and the Hall Sensor Supply Regulator (HSUP). VS1 can be sensed via a voltage divider through the AD converter. Reverse battery protection diode is required. See Section 4.5, “Power Supply This pin is the device power supply pin 2. VS2 supplies the High Side Drivers (HSx). Reverse battery protection diode required. See Section 4.5, “Power Supply This pin is the first High Side output. It is supplied through the VS2 pin. It is designed to drive small resistive loads with optional PWM. In cyclic sense mode, this output will activate periodically during low power mode. See Section 4.12, “High Side Drivers - HS. This pin is the second High Side output. It is supplied through the VS2 pin. It is designed to drive small resistive loads with optional PWM. In cyclic sense mode, this output will activate periodically during low power mode. See Section 4.12, “High Side Drivers - HS. Note: This pin function is not available on all device configurations. This pin is designed as an 18 V Regulator to drive Hall Sensor Elements. It is supplied through the VS1 pin. An external capacitor (CHSUP) is needed. See Section 4.11, “Hall Sensor Supply Output - HSUP. Note: This pin function is not available on all device configurations. This pin represents the single-wire bus transmitter and receiver. See Section 4.15, “LIN Physical Layer Interface - LIN. Note: This pin function is not available on all device configurations. This pin is the device LIN Ground connection. DGND, LGND, and AGND are internally connected to PGND via a back to back diode. This is the General Purpose I/O pin 0 based on VDDX with the following shared functions: • PTB0 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD0 - Analog Input Channel 0, 0…2.5V (ADC2p5) analog input • TIM0CH0 - Timer Channel 0 Input/Output • Rx - Selectable connection to LIN / SCI See Section 4.18, “General Purpose I/O - PTB[0…2]. This is the General Purpose I/O pin 1 based on VDDX with the following shared functions: • PTB1 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD1 - Analog Input Channel 1, 0…2.5 V (ADC2p5) analog input • TIM0CH1 - Timer Channel 1 Input/Output • Tx - Selectable connection to LIN / SCI See Section 4.18, “General Purpose I/O - PTB[0…2]. This is the General Purpose I/O pin 2 based on VDDX with the following shared functions: • PTB2 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up resistor. • AD2 - Analog Input Channel 2, 0…2.5V (ADC2p5) analog input • TIM0CH2 - Timer Channel 2 Input/Output • PWM - Selectable connection to PWM Channel 0 or 1 See Section 4.18, “General Purpose I/O - PTB[0…2]. This pin represents the ADC reference voltage and has to be connected to a filter capacitor. See Section 4.20, “Analog Digital Converter - ADC This pin is the device Analog to Digital converter ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode. 19 VS1 Power Supply Pin 1 20 VS2 Power Supply Pin 2 21 HS1 High Side Output 1 22 HS2 High Side Output 2 23 HSUP Hall Sensor Supply Output 24 LIN LIN Bus I/O 25 LGND LIN Ground Pin 26 PTB0 General Purpose I/O 0 27 PTB1 General Purpose I/O 1 28 PTB2 General Purpose I/O 2 29 30 ADC2p5 AGND ADC Reference Voltage Analog Ground Pin MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 9 Pin Assignment Table 4. MM912_634 Pin Description Pin # Pin Name Formal Name Description This pins is the High Voltage Input 0 with the following shared functions: • L0 - Digital High Voltage Input 0. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7) • AD3 - Analog Input 3 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU0 - Selectable Wake-up input 0 for wake up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx This pins is the High Voltage Input 1 with the following shared functions: • L1 - Digital High Voltage Input 1. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7) • AD4 - Analog Input 4 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU1 - Selectable Wake-up input 1 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx This pins is the High Voltage Input 2 with the following shared functions: • L2 - Digital High Voltage Input 2. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7) • AD5 - Analog Input 5 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU2 - Selectable Wake-up input 2 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations. This pins is the High Voltage Input 3 with the following shared functions: • L3 - Digital High Voltage Input 3. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7) • AD6 - Analog Input 6 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU3 - Selectable Wake-up input 3 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations. This pins is the High Voltage Input 4 with the following shared functions: • L4 - Digital High Voltage Input 4. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7) • AD7 - Analog Input 7 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU4 - Selectable Wake-up input 4 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations. This pins is the High Voltage Input 5 with the following shared functions: • L5 - Digital High Voltage Input 5. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients.(7) • AD8 - Analog Input 8 with selectable divider for 0…5.0 V and 0…18 V measurement range. • WU5 - Selectable Wake-up input 5 for wake-up and cyclic sense during low power mode. See Section 4.17, “High Voltage Inputs - Lx. Note: This pin function is not available on all device configurations. 31 L0 High Voltage Input 0 32 L1 High Voltage Input 1 33 L2 High Voltage Input 2 34 L3 High Voltage Input 3 35 L4 High Voltage Input 4 36 L5 High Voltage Input 5 Note: 7. An optional filter capacitor CLX is recommended to be placed between the board connector and RLX to GND for increased ESD performance. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 10 Pin Assignment Table 4. MM912_634 Pin Description Pin # Pin Name Formal Name Description Low Side output 1 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.13, “Low Side Drivers - LSx This pin is the device Low Side Ground connection. DGND, LGND and AGND are internally connected to PGND via a back to back diode. Low Side output 2 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.13, “Low Side Drivers - LSx Current Sense differential input “Low”. This pin is used in combination with ISENSEH to measure the voltage drop across a shunt resistor. See Section 4.21, “Current Sense Module - ISENSE. Note: This pin function is not available on all device configurations. Current Sense differential input “High”. This pin is used in combination with ISENSEL to measure the voltage drop across a shunt resistor. Section 4.21, “Current Sense Module - ISENSE. Note: This pin function is not available on all device configurations. This pin is reserved for alternative function and should be left floating. Analog die Test Mode pin for Test Mode only. This pin must be grounded in user mode! Test Mode Clock Input pin for Test Mode only. The pin can be used to disable the internal watchdog for development purpose in user mode. See Section 4.10, “Window Watchdog. The pin is recommended to be grounded in user mode. Bidirectional Reset I/O pin of the analog die. Active low signal. Internal pull-up. VDDX based. See Section 4.8, “Resets. To be externally connected to the RESET pin. The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device to EVDDX. The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pull-up device. General purpose port A input or output pin 7. See Section 4.28, “Port Integration Module (S12IPIMV1) 37 LS1 Low Side Output 1 38 PGND Power Ground Pin 39 LS2 Low Side Output 2 40 ISENSEL Current Sense Pin L 41 ISENSEH Current Sense Pin H 42 43 NC TEST_A Not connected Test Mode 44 TCLK Test Clock Input 45 RESET_A Reset I/O 46 RESET MCU Reset 47 BKGD MCU Background Debug and Mode 48 PA7 MCU PA7 2.2 MCU Die Signal Properties Table 5. Signal Properties Summary This section describes the external MCU signals. It includes a table of signal properties. Pin Name Function 1 Pin Name Function 2 Power Supply Internal Pull Resistor Description CTRL Reset State DOWN DOWN Port E I/O, Oscillator pin Port E I/O, Oscillator pin External reset DOWN UP NA Test input Background debug Port A I/O PE0 PE1 RESET TEST BKGD PA7 EXTAL XTAL — — MODC — VDDRX VDDRX VDDRX N.A. VDDRX VDDRX PUPEE/ OSCPINS_EN PUPBE/ OSCPINS_EN PULLUP RESET pin BKPUE NA MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 11 Pin Assignment Table 5. Signal Properties Summary Pin Name Function 1 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PC1 PC0 PD7-0 Pin Name Function 2 — — — SS SCK MOSI MISO D2DINT D2DCLK D2DDAT7-0 Internal Pull Resistor Description CTRL VDDRX VDDRX VDDRX VDDRX VDDRX VDDRX VDDRX VDDD2D VDDD2D VDDD2D NA NA NA NA NA NA NA PUPCE/ D2DEN NA PUPDE/ D2DEN Reset State NA NA NA NA NA NA NA Disabled NA Disabled Port A I/O Port A I/O Port A I/O Port A I/O, SPI Port A I/O, SPI Port A I/O, SPI Port A I/O, SPI Port C I/O, D2DI Port C I/O, D2DI Port D I/O, D2DI Power Supply MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 12 General 3 3.1 Electrical Characteristics General This section contains electrical information for the embedded MC9S12I64 microcontroller die, as well as the MM912_634 analog die. 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. All voltages are with respect to ground, unless otherwise noted. Table 6. Absolute Maximum Electrical Ratings - Analog Die Ratings Supply Voltage at VS1 and VS2 Normal operation (DC) Transient conditions (load dump) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) L0…L5 - Pin Voltage Normal operation with a series RLX resistor (DC) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) LIN Pin Voltage Normal operation (DC) Transient input voltage with external component (according to LIN Conformance Test Specification / ISO7637-2) Supply Voltage at VDDX Supply Voltage at VDD VDD Output Current VDDX Output Current TCLK Pin Voltage RESET_A Pin Voltage Input / Output Pins PTB[0:2] Voltage HS1 and HS2 Pin Voltage (DC) LS1 and LS2 Pin Voltage (DC) ISENSEH and ISENSEL Pin Voltage (DC) HSUP Pin Voltage (DC) VSENSE Pin Voltage (DC) Note: 8. See Section 3.9, “Additional Test Information ISO7637-2 VBUSDC VBUSTR VDDX VDD IVDD IVDDX VTCLK VIN VIN VHS VLS VISENSE VHSUP VVSENSE -33 to 40 (8) Symbol Value Unit VSUP(SS) VSUP(PK) VSUP(TR) -0.3 to 27 -0.3 to 40 (8) V VLxDC VLxTR 27 to 40 (8) V V -0.3 to 5.5 -0.3 to 2.75 Internally Limited Internally Limited -0.3 to 10 -0.3 to VDDx+0.3 -0.3 to VDDx+0.3 -0.3 to VS2+0.3 -0.3 to 45 -0.3 to 40 -0.3 to VS1+0.3 -27 to 40 V V A A V V V V V V V V MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 13 Operating Conditions Table 7. Maximum Electrical Ratings - MCU Die(9) Ratings 5.0 V Supply Voltage (Supplying the MCU internal regulator for core and flash) 2.5 V D2D - Supply Voltage Digital I/O input voltage (PA0...PA7, PE0, PE1) EXTAL, XTAL (PE0 and PE1 in alternative configuration) TEST Input Instantaneous Maximum Current Single pin limit for all digital I/O pins Instantaneous Maximum Current Single pin limit for EXTAL, XTAL Note: 9. All digital I/O pins are internally clamped to VSSRX and VDDRX. Symbol VDDRX VDDD2D VIN VILV VTEST ID IDL Value -0.3 to 6.0 -0.3 to 3.6 -0.3 to 6.0 -0.3 to 2.16 -0.3 to 10.0 -25 to 25 -25 to 25 Unit V V V V V mA mA Table 8. Maximum Thermal Ratings Ratings Storage Temperature Package (LQFP48), Thermal Resistance Peak Package Reflow Temperature During Reflow(10), (11) Symbol TSTG RJA TPPRT Value -55 to 150 max. 48 Note 11 Unit C k °C Notes 10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 11. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 3.3 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. Table 9. Operating Conditions Ratings Analog Die Nominal Operating Voltage Analog Die Functional Operating Voltage - Device is fully functional. All features are operating. MCU I/O and Supply Voltage(12) MCU Digital Logic Supply Voltage(12) MCU Oscillator MM912x634xxxAE MM912x634xxxAP MCU Bus frequency MM912x634xxxAE MM912x634xxxAP Note: 12. During power up and power down sequence always VDDD2D < VDDRX 13. fBUSMAX frequency ratings differ by device and is specified in Table 1 fBUS fBUSMAX(13) MHz fOSC 4.0 to 16 4.0 to 16 MHz Symbol VSUP VSUPOP VDDRX VDDD2D Value 5.5 to 18 5.5 to 27 4.75 to 5.25 2.25 to 2.75 Unit V V V V MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 14 Supply Currents Table 9. Operating Conditions Ratings Operating Ambient Temperature MM912x634xMxxx MM912x634xVxxx Operating Junction Temperature - Analog Die Operating Junction Temperature - MCU Die TJ_A TJ_M TA -40 to 125 -40 to 105 -40 to 150 -40 to 150 C C C Symbol Value Unit 3.4 3.4.1 Supply Currents Measurement Conditions This section describes the current consumption characteristics of the device as well as the conditions for the measurements. All measurements are without output loads. Currents are measured in MCU special single chip mode and the CPU code is executed from RAM, unless otherwise noted. Table 10. Supply Currents Ratings Normal Mode analog die only, excluding external loads, LIN Recessive State (5.5 V  VSUP  18 V, 2.25 V  VDD  2.75 V, 4.5 V  VDDX  5.5 V, -40 °C  TJ_A  150 °C). Normal Mode MCU die only (TJ_M=150 °C; VDDD2D = 2.75 V, VDDRX = 5.5 V, fOSC = 4.0 MHz, fBUS= fBUSMAX(15)(16) Stop Mode internal analog die only, excluding external loads, LIN Recessive State, Lx enabled, measured at VS1+VS2 (5.5 V  VSUP  18 V, 2.25 V  VDD  2.75 V, 4.5 V  VDDX  5.5 V) -40 °C  TJ_A  125 °C Stop Mode MCU die only (VDDD2D = 2.75 V, VDDRX = 5.5 V, fOSC= 4.0 MHz; MCU in STOP; RTI and COP off)(17) TJ_M=150°C TJ_M=-40°C TJ_M=25°C Sleep Mode (VDD = VDDX = OFF; 5.5 V  VSUP  18 V; -40 °C  TJ_A  125 °C; 3.0 V  LX  1.0 V). Cyclic Sense Supply Current Adder (5.0 ms Cycle) Note: 14. 15. 16. 17. Typical values noted reflect the approximate parameter mean at TA = 25 °C fBUSMAX frequency ratings differ by device and is specified in Table 1 IRUN_M denotes the sum of the currents flowing into VDD and VDDX. ISTOP_M denotes the sum of the currents flowing into VDD and VDDX. ISLEEP ICS ISTOP_M 85 31 31 15 15 150 50 50 28 20 µA µA µA Symbol IRUN_A Min Typ(14) 5.0 Max 8.0 Unit mA IRUN_M - 18 20 mA ISTOP_A 20 40 µA 3.5 Static Electrical Characteristics All characteristics noted under the following conditions: • 5.5 V  VSUP  18 V • -40 °C  TA  125 °C (MM912x634xMxxx) • -40 °C  TA  105 °C (MM912x634xVxxx) Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 15 Electrical Characteristics 3.5.1 Static Electrical Characteristics Analog Die Table 11. Static Electrical Characteristics - Power Supply Ratings Symbol VPOR VLVI VLVI_H VHVI VHVI_H VLBI VLBI_H VJ2602UV VLVRX VLVR VLVRS VVDDOV VVDDXOV Min 1.5 5.55 18 5.55 5.5 2.7 2.30 1.6 2.575 5.25 Typ 6.0 1.0 19.25 1.0 6.0 1.0 5.7 3.0 2.35 1.85 2.7875 5.675 Max 3.5 6.6 20.5 6.6 6.2 3.3 2.4 2.1 3.0 6.1 V V V V V V V V Unit V V Power-On Reset (POR) Threshold (measured on VS1) Low Voltage Warning (LVI) Threshold (measured on VS1, falling edge) Hysteresis (measured on VS1) High Voltage Warning (HVI) Threshold (measured on VS2, rising edge) Hysteresis (measured on VS2) Low Battery Warning (LBI) Threshold (measured on VSENSE, falling edge) Hysteresis (measured on VSENSE) J2602 Under-voltage threshold Low VDDX Voltage (LVRX) Threshold Low VDD Voltage Reset (LVR) Threshold Normal Mode Low VDD Voltage Reset (LVR) Threshold Stop Mode VDD Over-voltage Threshold (VROV) VDDX Over-voltage Threshold (VROVX) Table 12. Static Electrical Characteristics - Resets Ratings Low-state Output Voltage IOUT = 2.0 mA Pull-up Resistor Low-state Input Voltage High-state Input Voltage Reset Release Voltage (VDDX) RESET_A pin Current Limitation Symbol VOL RRPU VIL VIH VRSTRV Min 25 0.7VDDX 5.0 Typ 1.5 7.5 Max 0.8 50 0.3VDDX 10 Unit V kOhm V V V mA Table 13. Static Electrical Characteristics - Window Watchdog Ratings Watchdog Disable Voltage (fixed voltage) Watchdog Enable Voltage (fixed voltage) Symbol VTST VTSTEN Min 7.0 Typ Max 10 5.5 Unit V V Table 14. Static Electrical Characteristics - Voltage Regulator 5.0 V (VDDX) Ratings Normal Mode Output Voltage 1.0 mA < IVDDX + IVDDXinternal < 80 mA; 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation (IVDDX) Stop Mode Output Voltage (IVDDX < 500 µA) Stop Mode Output Current Limitation (IVDDX) Line Regulation Normal Mode, IVDDX = 80 mA Stop Mode, IVDDX = 500 µA LRXRUN LRXSTOP 20 25 200 mV Symbol VDDXRUN IVDDXRUN VDDXSTOP IVDDXSTOP Min Typ Max Unit V mA V mA 4.75 80 1.0 5.00 130 5.0 - 5.25 200 5.5 20 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 16 Electrical Characteristics Table 14. Static Electrical Characteristics - Voltage Regulator 5.0 V (VDDX) Ratings Load Regulation Normal Mode, 1.0 mA < IVDDX < 80 mA Normal Mode, VSUP = 3.6 V, 1.0 mA < IVDDX < 40 mA Stop Mode, 0.1 mA < IVDDX < 500 µA External Capacitor External Capacitor ESR LDXRUN LDXCRK LDXSTOP CVDDX CVDDX_R 1.0 15 80 200 250 10 10 µF Ohm mV Symbol Min Typ Max Unit Table 15. Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD) Ratings Normal Mode Output Voltage 1.0 mA < IVDD 18 V) Hall Supply Capacitor Range External Capacitor ESR VHSUPMAX LDHSUP CHSUP CHSUP_R RDS(ON) 16 0.22 17.5 10 12 18 500 10 10 V mV µF Ohm Ohm Symbol IHSUP Min 40 Typ 70 Max 90 Unit mA MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 17 Electrical Characteristics Table 17. Static Electrical Characteristics - High Side Drivers - HS Ratings Output Drain-to-Source On resistance TJ = 25 °C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150 °C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150 °C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V Output Current Limitation (0 V < VOUT < VSUP - 2.0 V) Open Load Current Detection Leakage Current (-0.2 V < VHSx < VS2 + 0.2 V) Current Limitation Flag Threshold (5.5 V < VSUP < 27 V) ILIMHSX IOLHSX ILEAK VTHSC RDS(ON) 60 VSUP -2 110 5.0 7.0 10 14 250 7.5 10 mA mA µA V Ohm Symbol Min Typ Max Unit Table 18. Static Electrical Characteristics - Low Side Drivers - LS Ratings Output Drain-to-Source On resistance TJ = 25 °C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 150 °C, ILOAD = 150 mA, VSUP > 9.0 V TJ = 150 °C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V Output Current Limitation (2.0 V < VOUT < VSUP) Open Load Current Detection Leakage Current (-0.2 V < VOUT < VS1) Active Output Energy Clamp (IOUT = 150 mA) Coil Series Resistance (IOUT = 150 mA) Coil Inductance (IOUT = 150 mA) Current Limitation Flag Threshold (5.5 V < VSUP < 27 V) ILIMLSX IOLLSX ILEAK VCLAMP RCOIL RCOIL VTHSC RDS(ON) – – – 180 40 120 2.0 – – – 275 8.0 400 2.5 4.5 10 380 12 10 45 mA mA µA V Ohm m V Ohm Symbol Min Typ Max Unit Table 19. Static Electrical Characteristics - LIN Physical Layer Interface - LIN Ratings Current Limitation for Driver dominant state. VBUS = 18 V Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE; Driver OFF; VBUS = 0 V; VBAT = 12 V Input Leakage Current at the Receiver incl. Pull-up Resistor RSLAVE; Driver OFF; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS  VBAT Input Leakage Current; GND Disconnected; GNDDEVICE = VSUP; 0 < VBUS < 18 V; VBAT = 12 V Input Leakage Current; VBAT disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V Receiver Input Voltage; Receiver Dominant State Receiver Input Voltage; Receiver Recessive State Receiver Threshold Center (VTH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) Voltage Drop at the serial Diode LIN Pull-up Resistor Bus Wake-up Threshold from Stop or Sleep Bus Dominant Voltage Symbol IBUSLIM IBUS_PAS_DOM Min 40 -1.0 Typ 120 Max 200 Unit mA mA IBUS_PAS_REC - - 20 µA IBUS_NO_GND IBUS_NO_BAT VBUSdom VBUSrec VBUS_CNT VBUS_HYS Dser_int Rslave VWUP VDOM -1.0 0.6 0.475 0.4 20 4.0 - 0.5 0.7 30 5.0 - 1.0 100 0.4 0.525 0.175 1.0 60 6.0 2.5 mA µA VSUP VSUP VSUP VSUP V kOhm V V MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 18 Electrical Characteristics Table 20. Static Electrical Characteristics - High Voltage Inputs - Lx Ratings Low Detection Threshold (7.0 V  VSUP  27 V) (5.5 V  VSUP  7.0 V) High Detection Threshold (7.0 V  VSUP  27 V) (5.5 V  VSUP  7.0 V) Hysteresis (5.5 V < VSUP < 27 V) Input Current Lx (-0.2 V < VIN < VS1) Analog Input Impedance Lx Lx Series Resistor Lx Capacitor (optional)(18) Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0) LXDS (Lx Divider Select) = 0 LXDS (Lx Divider Select) = 1 Analog Input Divider Ratio Accuracy Analog Inputs Channel Ratio - Mismatch LXDS (Lx Divider Select) = 0 LXDS (Lx Divider Select) = 1 LxMATCH 5.0 5.0 % RATIOLX RATIOLx -5.5 2.0 7.2 5.5 % IIN RLxIN RLX CLX VHYS 0.25 -10 9.5 0.45 10 100 1.0 10 1.2 10.5 µA MOhm kOhm nF VTHH 2.6 2.0 3.0 3.0 3.7 4.5 V Symbol VTHL 2.2 1.5 2.5 2.5 3.4 4.0 V Min Typ Max Unit V Note: 18. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity are guaranteed without the optional capacitor. Table 21. Static Electrical Characteristics - General Purpose I/O - PTB[0…2] Ratings Input High Voltage Input Low Voltage Input Hysteresis Input High Voltage (VS1 = 3.7 V) Input Low Voltage (VS1 = 3.7 V) Input Hysteresis (VS1 = 3.7 V) Input Leakage Current (pins in high-impedance input mode) (VIN = VDDX or VSSX) Output High Voltage (pins in output mode) Full drive IOH = -10 mA Output Low Voltage (pins in output mode) Full drive IOL = 10 mA Internal Pull-up Resistance (VIH min > Input voltage > VIL max) Input Capacitance Clamp Voltage when selected as analog input Analog Input impedance = 10 kOhm max, Capacitance = 12 pF Analog Input Capacitance = 12 pF Maximum current all PTB combined (VDDX capability!) Output Drive strength at 10 MHz Symbol VIH VIL VHYS VIH3.7 VIL3.7 VHYS3.7 IIN VOH VOL RPUL CIN VCL_AIN RAIN CAIN IBMAX COUT Min 0.7VDDX VSS-0.3 2.1 VSS-0.3 100 -1.0 VDDX-0.8 26.25 VDD -15 Typ 140 200 37.5 6.0 12 Max VDDX+0.3 0.35VDDX VDDX+0.3 1.4 300 1.0 0.8 48.75 10 15 100 Unit V V mV V V mV µA V V kOhm pF V kOhm pF mA pF MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 19 Electrical Characteristics Table 22. Static Electrical Characteristics - Analog Digital Converter - ADC(19) Ratings ADC2p5 Reference Voltage 5.5 V < VSUP < 27 V ADC2p5 Reference Stop Mode Output Voltage Line Regulation, Normal Mode External Capacitor External Capacitor ESR Scale Factor Error Differential Linearity Error Integral Linearity Error Zero Offset Error Quantization Error Total Error with offset compensation Bandgap measurement Channel (CH14) Valid Result Range (including ±7.0% bg1p25sleep accuracy + high-impedance measurement error of ±5.0% at fADC)(20) Note: 19. No external load allowed on the ADC2p5 pin. 20. Reduced ADC frequency will lower measurement error. Symbol VADC2p5RU N Min Typ Max Unit V mV mV µF Ohm LSB LSB LSB LSB LSB LSB V 2,45 0.1 -1 -1.5 -1.5 -2.0 -0.5 -5.0 1.1 2.5 10 1.25 2.55 100 12.5 1.0 10 1 1.5 1.5 2.0 0.5 5.0 1.4 VADC2p5ST OP LRRUNA CADC2p5 CVDD_R ESCALE EDNL EINL EOFF EQ TE ADCH14 Table 23. Static Electrical Characteristics - Current Sense Module - ISENSE Ratings Gain CSGS (Current Sense Gain Select) = 000 CSGS (Current Sense Gain Select) = 001 CSGS (Current Sense Gain Select) = 010 CSGS (Current Sense Gain Select) = 011 CSGS (Current Sense Gain Select) = 100 CSGS (Current Sense Gain Select) = 101 CSGS (Current Sense Gain Select) = 110 CSGS (Current Sense Gain Select) = 111 Gain Accuracy Offset Resolution(21) ISENSEH, ISENSEL Input Common Mode Voltage Range Current Sense Module - Normal Mode Current Consumption Adder (CSE = 1) Note: 21. RES = 2.44 mV/(GAIN*RSHUNT) RES VIN IISENSE G -3.0 -1.5 -0.2 7 9 10 12 14 18 24 36 51 600 3.0 1.5 3.0 % % mA/LSB V µA Symbol Min Typ Max Unit Table 24. Static Electrical Characteristics - Temperature Sensor - TSENSE Ratings Internal Chip Temperature Sense Gain(22) (22) Symbol TSG TSErr T0.15V Min –5.0 -55 Typ 9.17 -50 Max 5.0 -45 Unit mV/k °C °C Internal Chip Temperature Sense Error at the end of conversion(22) Temperature represented by a ADCIN Voltage of 0.150 V MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 20 Electrical Characteristics Table 24. Static Electrical Characteristics - Temperature Sensor - TSENSE Ratings Temperature represented by a ADCIN Voltage of 1.984 V Note: 22. Guaranteed by design and characterization. (22) Symbol T1.984V Min 145 Typ 150 Max 155 Unit °C Table 25. Static Electrical Characteristics - Supply Voltage Sense - VSENSE and VS1SENSE Ratings VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / ADCIN) 5.5 V < VSUP < 27 V VSENSE error - whole path (VSENSE pad to Digital value) VS1SENSE Input Divider Ratio (RATIOVS1SENSE = VVS1SENSE / ADCIN) 5.5 V < VSUP < 27 V VS1SENSE error - whole path (VS1 pad to Digital value) VSENSE Series Resistor VSENSE Capacitor (optional)(23) Symbol RATIOVSENS E Min 9.5 - Typ 10.8 10.8 10 100 Max 5.0% 5.0 5.0% 5.0 10.5 - Unit ErVSENSE RATIOVS1SE NSE % ErVS1SENSE RVSENSE CVSENSE % kOhm nF Note: 23. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity is guaranteed without the optional capacitor. 3.5.2 3.5.2.1 Static Electrical Characteristics MCU Die I/O Characteristics Table 26. 5.0 V I/O Characteristics for PTA, PTE, RESET and BKGD Pins Ratings Symbol V IH This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. Min 0.65*VDDRX VSSRX - 0.3 -1.0 VDDRX – 0.8 25 25 -2.5 -25 Typ 250 6.0 - Max VDDRX + 0.3 0.35*VDDR X Unit V V V V mV A V V k k pF mA Input high voltage Input high voltage Input low voltage Input low voltage Input hysteresis Input leakage current (pins in high-impedance input mode) VIN = VDDRX or VSSRX Output high voltage (pins in output mode) IOH = -4.0 mA Output low voltage (pins in output mode) IOL = +4.0 mA Internal pull-up resistance (VIHmin > input voltage > VILmax) Internal pull-down resistance (VIHmin > input voltage > VILmax) Input capacitance Injection current (24) VIH VIL VIL VHYS I V IN 1.0 0.8 50 50 2.5 25 OH VOL RPUL RPDH Cin IICS IICP Single pin limit Total device Limit, sum of all injected currents Note: 24. Refer to Section 3.8, “ESD Protection and Latch-up Immunity” for more details. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 21 Electrical Characteristics 3.5.2.2 Electrical Specification for MCU internal Voltage Regulator Table 27. IVREG Characteristics Characteristic Symbol Min Typical Max Unit VDDRX Low Voltage Reset (25)(26)(27) Assert Level Deassert Level Power-on Reset(28) Assert Level Deassert Level Note: 25. 26. 27. 28. VPORA VPORD 0.6 — 0.9 0.95 — 1.60 V V VLVRXA VLVRXD 2.97 — 3.06 3.09 — 3.3 V V Device functionality is guaranteed on power down to the LVR assert level. Monitors VDDRX, active only in Full Performance mode. MCU is monitored by the POR in RPM (see Figure ). Monitors VDDRX, active only in Full Performance mode. VLVRA and VPORD. Monitors MCU_CORE_VDD. Active in all modes. NOTE The LVR monitors the voltages VDD_CORE, VDDFLASH and VDDRX. As soon as voltage drops on these supplies which would prohibit the correct function of the microcontroller, the LVR is triggering a reset. 3.5.2.3 Chip Power-up and Voltage Drops LVI (low voltage interrupt), POR (power-on reset) and LVRs (low voltage reset) handle chip power-up or drops of the supply voltage. V VLVID VLVIA VDDRX VDD_Core VLVRD VLVRA VPORD t LVI LVI enabled POR LVI disabled due to LVR LVR Figure 4. MC9S12I32 - Chip Power-up and Voltage Drops (not scaled) MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 22 Electrical Characteristics 3.6 Dynamic Electrical Characteristics Dynamic characteristics noted under conditions 5.5 V  VSUP  18 V, -40 °C  TA 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. 3.6.1 Dynamic Electrical Characteristics Analog Die Table 28. Dynamic Electrical Characteristics - Modes of Operation Ratings Symbol tVTO fBASE tRST Min 110 140 Typ 150 100 200 Max 205 280 Unit ms kHz µs VDD Short Timeout Analog Base Clock Reset Delay Table 29. Dynamic Electrical Characteristics - Power Supply(29) Ratings Glitch Filter Low Battery Warning (LBI) Glitch Filter Low Voltage Warning (LVI) Glitch Filter High Voltage Warning (HVI) Note: 29. Guaranteed by design. Symbol tLB tLV tHV Min Typ 2.0 2.0 2.0 Max Unit µs µs µs Table 30. Dynamic Electrical Characteristics - Die to Die Interface - D2D Ratings Operating Frequency (D2DCLK, D2D[0:3]) Note: 30. fBUSMAX frequency ratings differ by device and is specified in Table 1 Symbol fD2D Min Typ Max fBUSMAX ) (30 Unit MHz Table 31. Dynamic Electrical Characteristics - Resets Ratings Reset Deglitch Filter Time Reset Low Level Duration Symbol tRSTDF tRSTLOW Min 1.2 140 Typ 2.0 200 Max 3.0 280 Unit µs µs Table 32. Dynamic Electrical Characteristics - Wake-up / Cyclic Sense Ratings Lx Wake-up Filter Time Cyclic Sense / Forced Wake-up Timing Accuracy - not trimmed Cyclic Sense / Forced Wake-up Timing Accuracy - trimmed(31) Time between HSx on and Lx sense during cyclic sense HSx ON duration during Cyclic Sense HSx ON duration during Cyclic Sense - trimmed(31) Note: 31. No trimming possible in Sleep mode. Symbol tWUF CSAC CSACT tS tHSON tHSONT Min -35 -5.0 Typ 20 35 5.0 Max Unit s % % s s same as tHSON / tHSONT 140 180 200 200 280 220 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 23 Electrical Characteristics Table 33. Dynamic Electrical Characteristics - Window Watchdog Ratings Initial Non-window Watchdog Timeout Watchdog Timeout Accuracy - not trimmed Watchdog Timeout Accuracy - trimmed Symbol tIWDTO WDAC WDACT Min 110 -35 -5.0 Typ 150 Max 190 35 5.0 Unit ms % % Table 34. Dynamic Electrical Characteristics - High Side Drivers - HS Ratings High Side Operating Frequency(32) Load Condition: CLOAD2.2 nF; RLOAD500  Note: 32. Guaranteed by design. Symbol fHS Min Typ Max Unit kHz - - 50 Table 35. Dynamic Electrical Characteristics - Low Side Drivers - LS Ratings Low Side Operating Frequency Symbol fLS Min Typ Max 10 Unit kHz Table 36. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN Ratings Bus Wake-up Deglitcher (Sleep and Stop mode) Fast Bit Rate (Programming mode) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)(33) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR Symbol tPROPWL BRFAST tREC_PD tREC_SYM Min 60 -2.0 Typ 80 Max 100 100 6.0 2.0 Unit µs kBit/s µs µs LIN Driver - 20.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660  / 10 nF;500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 6. Duty Cycle 1: THREC(MAX) = 0.744 x VSUP THDOM(MAX) = 0.581 x VSUP 7.0 V VSUP18 V; tBit = 50 µs; D1 = tBUS_REC(MIN)/(2 x tBit) Note: 33. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 8. Duty Cycle 2: THREC(MIN) = 0.422 x VSUP THDOM(MIN) = 0.284 x VSUP 7.6 V VSUP18 V; tBIT = 50 µs D2 = tBUS_REC(MAX)/(2 x tBIT) LIN Driver - 10.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 k / 6,8 nF;660  / 10 nF;500  Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 7. Duty Cycle 3: THREC(MAX) = 0.778 x VSUP THDOM(MAX) = 0.616 x VSUP 7.0 V VSUP18 V; tBIT = 96 µs D3 = TBUS_REC(MIN)/(2 x tBIT) D3 0.417 D2 0.581 D1 0.396 - MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 24 Electrical Characteristics Table 36. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN Ratings Duty Cycle 4: THREC(MIN) = 0.389 x VSUP THDOM(MIN) = 0.251 x VSUP 7.6 V VSUP18 V; tBIT = 96 µs D4 = tBUS_REC(MAX)/(2 x tBIT) LIN Transmitter Timing, (VSUP from 7.0 to 18 V) - See Figure 9 Transmitter Symmetry ttran_sym < MAX(ttran_sym60%, ttran_sym40%) tran_sym60% = ttran_pdf60% - ttran_pdr60% tran_sym40% = ttran_pdf40% - ttran_pdr40% ttran_sym -7.25 0 7.25 µs D4 0.590 Symbol Min Typ Max Unit Figure 5. Test Circuit for Timing Measurements Figure 6. LIN Timing Measurements for Normal Baud Rate MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 25 Electrical Characteristics Figure 7. LIN Timing Measurements for Slow Baud Rate Figure 8. LIN Receiver Timing TX BUS 60% 40% ttran_pdf60% ttran_pdf40% ttran_pdr40% ttran_pdr60% Figure 9. LIN Transmitter Timing MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 26 Electrical Characteristics Table 37. Dynamic Electrical Characteristics - General Purpose I/O - PTB[0…2](34) Ratings GPIO Digital Frequency Propagation Delay - Rising Edge(35) Rise Time - Rising Edge (34) Symbol fPTB tPDR tRISE tPDF tFALL Min - Typ - Max 10 20 17.5 20 17.5 Unit MHz ns ns ns ns Propagation Delay - Falling Edge(34) Rise Time - Falling Edge(34) Note: 34. Guaranteed by design. 35. Load PTBx = 100 pF. Table 38. Dynamic Electrical Characteristics - Analog Digital Converter - ADC(36) Ratings ADC Operating Frequency Conversion Time (from ACCR write to CC Flag) Sample Frequency Channel 14 (Bandgap) Note: 36. Guaranteed by design. Symbol fADC tCONV fCH14 Min 1.6 Typ 2.0 26 2.5 Max 2.4 Unit MHz clk kHz 3.6.2 3.6.2.1 3.6.2.1.1 Dynamic Electrical Characteristics MCU Die NVM Timing Parameters The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV register. The frequency of this derived clock must be set within the limits specified as fNVMOP. The NVM module does not have any means to monitor the frequency and will not prevent program or erase operations at frequencies above or below the specified minimum. When attempting to program or erase the NVM module at a lower frequency, a full program or erase transition is not assured. The following sections provide equations which can be used to determine the time required to execute specific flash commands. All timing parameters are a function of the bus clock frequency, fNVMBUS. All program and erase times are also a function of the NVM operating frequency, fNVMOP. A summary of key timing parameters can be found in Table . 3.6.2.1.1.1 Erase Verify All Blocks (Blank Check) (FCMD=0x01) The time required to perform a blank check on all blocks is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify all blocks is given by: 1 t check = 19200  ------------------f NVMBUS 3.6.2.1.1.2 Erase Verify Block (Blank Check) (FCMD=0x02) The time required to perform a blank check is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by: 1 t pcheck = 17200  ------------------f NVMBUS Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by: MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 27 Electrical Characteristics 1 t dcheck = 2800  ------------------f NVMBUS 3.6.2.1.1.3 Erase Verify P-Flash Section (FCMD=0x03) The maximum time to erase verify a section of P-Flash depends on the number of phrases being verified (NVP) and is given by: 1 t   450 + N VP   ------------------f NVMBUS 3.6.2.1.1.4 Read Once (FCMD=0x04) The maximum read once time is given by: 1 t = 400  ------------------f NVMBUS 3.6.2.1.1.5 Program P-Flash (FCMD=0x06) The programming time for a single phrase of four P-Flash words and the two seven-bit ECC fields is dependent on the bus frequency, fNVMBUS, as well as on the NVM operating frequency, fNVMOP. The typical phrase programming time is given by: 1 1 t ppgm  164  ---------------- + 2000  ------------------f NVMOP f NVMBUS The maximum phrase programming time is given by: 1 1 t ppgm  164  ---------------- + 2500  ------------------f NVMBUS f NVMOP 3.6.2.1.1.6 Program Once (FCMD=0x07) The maximum time required to program a P-Flash Program Once field is given by: 1 1 t  164  ---------------- + 2150  ------------------f NVMOP f NVMBUS 3.6.2.1.1.7 Erase All Blocks (FCMD=0x08) The time required to erase all blocks is given by: 1 1 t mass  100100  ---------------- + 38000  ------------------f NVMBUS f NVMOP 3.6.2.1.1.8 Erase P-Flash Block (FCMD=0x09) The time required to erase the P-Flash block is given by: 1 1 t pmass  100100  ---------------- + 35000  ------------------f NVMBUS f NVMOP MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 28 Electrical Characteristics 3.6.2.1.1.9 Erase P-Flash Sector (FCMD=0x0A) The typical time to erase a 512-byte P-Flash sector is given by: 1 1 t pera  20020  ---------------- + 700  ------------------f NVMBUS f NVMOP The maximum time to erase a 512-byte P-Flash sector is given by: 1 1 t pera  20020  ---------------- + 1400  ------------------f NVMOP f NVMBUS 3.6.2.1.1.10 Unsecure Flash (FCMD=0x0B) The maximum time required to erase and unsecure the Flash is given by: 1 1 t uns  100100  ---------------- + 38000  ------------------f NVMOP f NVMBUS 3.6.2.1.1.11 Verify Backdoor Access Key (FCMD=0x0C) The maximum verify back door access key time is given by: 1 t = 400  ------------------f NVMBUS 3.6.2.1.1.12 Set User Margin Level (FCMD=0x0D) The maximum set user margin level time is given by: 1 t = 350  ------------------f NVMBUS 3.6.2.1.1.13 Set Field Margin Level (FCMD=0x0E) The maximum set field margin level time is given by: 1 t = 350  ------------------f NVMBUS 3.6.2.1.1.14 Erase Verify D-Flash Section (FCMD=0x10) The time required to Erase Verify D-Flash for a given number of words NW is given by: 1 t dcheck   450 + N W   ------------------f NVMBUS 3.6.2.1.1.15 Program D-Flash (FCMD=0x11) D-Flash programming time is dependent on the number of words being programmed and their location with respect to a row boundary, since programming across a row boundary requires extra steps. The D-Flash programming time is specified for different cases: 1,2,3,4 words and 4 words across a row boundary. The typical D-Flash programming time is given by the following equation, where NW denotes the number of words; BC=0 if no row boundary is crossed and BC=1 if a row boundary is crossed: 1 1 t dpgm    14 +  54  N W  +  14  BC    ----------------  +   500 +  525  N W  +  100  BC    -------------------   f NVMOP   f NVMBUS  MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 29 Electrical Characteristics The maximum D-Flash programming time is given by: 1 1 t dpgm    14 +  54  N W  +  14  BC    ----------------  +   500 +  750  N W  +  100  BC    -------------------   f NVMOP   f NVMBUS  3.6.2.1.1.16 Erase D-Flash Sector (FCMD=0x12) Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given by: 1 1 t dera  5025  ---------------- + 700  ------------------f NVMBUS f NVMOP Maximum D-Flash sector erase times is given by: 1 1 t dera  20100  ---------------- + 3400  ------------------f NVMOP f NVMBUS The D-Flash sector erase time is ~5.0 ms on a new device and can extend to ~20 ms as the flash is cycled. Table 39. NVM Timing Characteristics (FTMRC) C Bus frequency(40) Operating frequency D Erase all blocks (mass erase) time D Erase verify all blocks (blank check) time D Unsecure Flash time D P-Flash block erase time D P-Flash erase verify (blank check) time D P-Flash sector erase time D P-Flash phrase programming time D D-Flash sector erase time D D-Flash erase verify (blank check) time D D-Flash one word programming time D D-Flash two word programming time D D-Flash three word programming time D D-Flash four word programming time D D-Flash four word programming time crossing row boundary Note: 37. 38. 39. 40. 41. Rating Symbol fNVMBUS fNVMOP tmass tCHECK tUNS tPMASS tPCHECK tPERA tPPGM tDERA tDCHECK tDPGM1 tDPGM2 tDPGM3 tDPGM4 tDPGM4C Min 1 0.8 — — — — — — — — — — — — — — Typ(37) — 1.0 100 — 100 100 — 20 226 5 (41) Max(38) 32 1.05 130 19200 130 130 17200 26 285 26 2800 107 185 262 339 357 Unit(39) MHz MHz ms tCYC ms ms tCYC ms s ms tCYC s s s s s — 100 170 241 311 328 Typical program and erase times are based on typical fNVMOP and maximum fNVMBUS. Maximum program and erase times are based on minimum fNVMOP and maximum fNVMBUS. tCYC = 1 / fNVMBUS The maximum device bus clock is specified as fBUS. Typical value for a new device. 3.6.2.1.2 NVM Reliability Parameters The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors, and burn-in to screen early life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE All values shown in Table 40 are preliminary and subject to further characterization. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 30 Electrical Characteristics Table 40. NVM Reliability Characteristics Rating Program Flash Arrays Data retention at an average junction temperature of TJAVG = 85 C(42) after up to 10,000 program/erase cycles Program Flash number of program/erase cycles (-40 C  TJ  150 C Data Flash Array Data retention at an average junction temperature of TJAVG = 85 C(42) after up to 50,000 program/erase cycles Data retention at an average junction temperature of TJAVG = 85 C(42) after up to 10,000 program/erase cycles Data retention at an average junction temperature of TJAVG = 85 C(42) after less than 100 program/erase cycles Data Flash number of program/erase cycles (-40 C  TJ  150 C tNVMRET tNVMRET tNVMRET nFLPE 5 10 20 50K 100(43) 100(43) 100(43) 500K(44) — — — — Years Years Years Cycles tNVMRET nFLPE 20 10K 100(43) 100K(44) — — Years Cycles Symbol Min Typ Max Unit Note: 42. TJAVG does not exceed 85 C in a typical temperature profile over the lifetime of a consumer, industrial or automotive application. 43. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618 44. Spec table quotes typical endurance evaluated at 25 C for this product family. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. 3.6.2.2 3.6.2.2.1 Phase Locked Loop Jitter Definitions With each transition of the feedback clock, the deviation from the reference clock is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency. Noise, voltage, temperature, and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods, as illustrated in Figure 10. 0 tMIN1 tNOM tMAX1 1 2 3 N-1 N tMINN tMAXN Figure 10. Jitter Definitions The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Jitter is defined as: t N t N   max min J  N  = max  1 – ---------------------- , 1 – ----------------------  Nt Nt  nom nom  MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 31 Electrical Characteristics For N < 100, the following equation is a good fit for the maximum jitter: j 1 J  N  = ------N J(N) 1 5 10 20 Figure 11. Maximum Bus Clock Jitter Approximation N NOTE On timers and serial modules a prescaler will eliminate the effect of the jitter to a large extent. 3.6.2.2.2 Electrical Characteristics for the PLL(45) Table 41. PLL Characteristics Rating VCO Frequency During System Reset VCO Locking Range Reference Clock Lock Detection Un-Lock Detection Time to Lock Jitter Fit Parameter 1(47) Symbol fVCORST fVCO fREF Lock| unl| tlock j1 Min 8.0 32 1.0 0 0.5 — — Typ — — — — — — — Max 32 64 — 1.5 2.5 150 + 256/fREF 1.2 Unit MHz MHz MHz %(46) %(46) s % Note: 45. the maximum device bus clock is specified as fBUS. 46. % deviation from target frequency. 47. fREF = 1.0 MHz, fBUS = 32 MHz equivalent fPLL = 64 MHz, REFRQ=00, SYNDIV=$1F, VCOFRQ=01, POSTDIV=$00. 3.6.2.3 Electrical Characteristics for the IRC1M Table 42. IRC1M Characteristics Rating Symbol fIRC1M_TRIM Min Typ Max Unit MHz Internal Reference Frequency, Factory Trimmed -40 °C  TJ  150 °C 0.987 1.0 1.013 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 32 Electrical Characteristics 3.6.2.4 Electrical Characteristics for the Oscillator (OSCLCP) Table 43. OSCLCP Characteristics Rating Symbol fOSC iOSC tUPOSC tUPOSC tUPOSC fCMFA CIN VHYS,EXTAL VPP,EXTAL Min 4.0 100 — — — 200 — — — Typ — — 2.0 1.6 1.0 450 7.0 120 0.9 Max 16 — 10 8.0 5.0 1200 — — — Unit MHz A ms ms ms KHz pF mV V Crystal Oscillator Range Startup Current Oscillator Start-up time (LCP, 4MHz)(48) Oscillator Start-up time (LCP, 8MHz)(48) Oscillator Start-up time (LCP, 16MHz)(48) Clock Monitor Failure Assert Frequency Input Capacitance (EXTAL, XTAL pins) EXTAL Pin Input Hysteresis EXTAL Pin Oscillation Amplitude (loop controlled Pierce) Note: 48. These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements. 49. Only applies if EXTAL is externally driven. 3.6.2.5 Reset Characteristics Table 44. Reset and Stop Characteristics Rating Symbol PWRSTL nRST tSTP_REC Min 2.0 — — Typ — 768 50 Max — — — Unit tVCORST tVCORST s Reset Input Pulse Width, Minimum Input Time Startup from Reset STOP Recovery Time 3.6.2.6 SPI Timing Table 45. Measurement Conditions Description Value Full drive mode (50) , on This section provides electrical parametrics and ratings for the SPI. In Table 45 the measurement conditions are listed. Unit — pF V Drive mode Load capacitance CLOAD all outputs 50 (20% / 80%) VDDRX Thresholds for delay measurement points Note: 50. Timing specified for equal load on all SPI output pins. Avoid asymmetric load. 3.6.2.6.1 Master Mode In Figure 12 the timing diagram for master mode with transmission format CPHA = 0 is depicted. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 33 Electrical Characteristics SS (Output) 2 SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 5 MISO (Input) 6 Bit MSB-1… 1 9 Bit MSB-1…1 LSB OUT LSB IN 11 1 4 4 12 13 12 13 3 MSB IN2 10 MOSI (Output) MSB OUT2 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB. Figure 12. SPI Master Timing (CPHA = 0) In Figure 13 the timing diagram for master mode with transmission format CPHA=1 is depicted. SS (Output) 1 2 SCK (CPOL = 0) (Output) 4 SCK (CPOL = 1) (Output) 5 MISO (Input) 9 MOSI (Output) Port Data Master MSB OUT2 6 Bit MSB-1... 1 11 Bit MSB-1... 1 Master LSB OUT Port Data LSB IN MSB IN2 4 12 13 12 13 3 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB. Figure 13. SPI Master Timing (CPHA = 1) In Table 46 the timing characteristics for master mode are listed. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 34 Electrical Characteristics Table 46. SPI Master Mode Timing Characteristics Characteristic SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (inputs) Data Hold Time (inputs) Data Valid After SCK Edge Data Valid After SS Fall (CPHA = 0) Data Hold Time (outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs Symbol fSCK tSCK tLEAD tLAG tWSCK tSU tHI tVSCK tVSS tHO tRFI tRFO Min 1/2048 2.0 — — — 8.0 8.0 — — 20 — — Typ — — 1/2 1/2 1/2 — — — — — — — Max 1 2 2048 — — — — — 29 15 — 8.0 8.0 Unit fBUS tBUS tSCK tSCK tSCK ns ns ns ns ns ns ns 3.6.2.6.2 Slave Mode In Figure 14 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. SS (Input) 1 SCK (CPOL = 0) (Input) 2 SCK (CPOL = 1) (Input) 10 7 MISO (Output) See Note 5 MOSI (Input) NOTE: Not defined Figure 14. SPI Slave Timing (CPHA = 0) In Figure 15 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. MSB IN Slave MSB 6 Bit MSB-1... 1 LSB IN 9 Bit MSB-1... 1 4 4 12 13 8 11 11 See Note 12 13 3 Slave LSB OUT MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 35 Electrical Characteristics SS (Input) 1 2 SCK (CPOL = 0) (Input) 4 SCK (CPOL = 1) (Input) 9 MISO (Output) See Note 7 MOSI (Input) NOTE: Not defined Figure 15. SPI Slave Timing (CPHA = 1) In Table 47 the timing characteristics for slave mode are listed. Table 47. SPI Slave Mode Timing Characteristics Characteristic SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (inputs) Data Hold Time (inputs) Slave Access Time (time to data active) Slave MISO Disable Time Data Valid After SCK Edge Data Valid After SS Fall Data Hold Time (outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs Symbol fSCK tSCK tLEAD tLAG tWSCK tSU tHI tA tDIS tVSCK tVSS tHO tRFI tRFO Min DC 4 4 4.0 4.0 8.0 8.0 — — — — 20 — — Typ — — — — — — — — — — — — — — Max 1 4  — — — — — 20 22 29 + 0.5  tBUS 29 + 0.5  tBUS — 8.0 8.0 (51) (51) 3 12 13 4 12 13 11 MSB OUT 6 Bit MSB-1... 1 Slave LSB OUT 8 Slave 5 MSB IN Bit MSB-1… 1 LSB IN Unit fBUS tBUS tBUS tBUS tBUS ns ns ns ns ns ns ns ns ns Note: 51. 0.5 tBUS added due to internal synchronization delay 3.7 Thermal Protection Characteristics Characteristics noted under conditions 5.5 V  VSUP  18 V, -40 °C  TA 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 36 Electrical Characteristics Table 48. Thermal Characteristics - Voltage Regulators VDD (2.5 V) & VDDX (5.0 V)(52) Ratings VDD/VDDX High-temperature Warning (HTI) Threshold Hysteresis VDD/VDDX Over-temperature Shutdown Threshold Hysteresis HSUP Over-temperature Shutdown HSUP Over-temperature Shutdown Hysteresis HS Over-temperature Shutdown HS Over-temperature Shutdown Hysteresis LS Over-temperature Shutdown LS Over-temperature Shutdown Hysteresis LIN Over-temperature Shutdown LIN Over-temperature Shutdown Hysteresis Note: 52. Guaranteed by characterization. Functionality tested. TSD TSD_H THSUPSD THSUPSD_HYS THSSD THSSD_HYS TLSSD TLSSD_HYS TLINSD TLINSD_HYS 155 150 150 150 150 170 10 165 10 165 10 165 10 165 20 185 180 180 180 200 °C °C °C °C °C °C °C °C °C THTI THTI_H 110 125 10 140 °C Symbol Min Typ Max Unit 3.8 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification, ESD stresses were performed for the Human Body Model (HBM), Machine Model (MM), Charge Device Model (CDM), as well as LIN transceiver specific specifications. A device will be defined as a failure if after exposure to ESD pulses, the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature, followed by hot temperature, unless specified otherwise in the device specification. Table 49. ESD and Latch-up Protection Characteristics Ratings ESD - Human Body Model (HBM) following AEC-Q100 / JESD22-A114 (CZAP = 100 pF, RZAP = 1500 ) - LIN (DGND, PGND, AGND, and LGND shorted) - VS1, VS2, VSENSE, Lx - HSx - All other Pins ESD - Charged Device Model (CDM) following AEC-Q100, Corner Pins (1, 12, 13, 24, 25, 36, 37, and 48) All other Pins ESD - Machine Model (MM) following AEC-Q100 (CZAP = 200 pF, RZAP = 0 ), All Pins Latch-up current at TA = 125 C(53) ESD GUN - LIN Conformance Test Specification(55), unpowered, contact discharge, CZAP= 150 pF, RZAP = 330 . - LIN (with or without bus filter CBUS=220 pF) - VS1, VS2 with CVS - Lx with serial RLX ±15000 ±20000 ±6000 V VMM ILAT VCDM ±750 ±500 ±200 ±100 V mA V VHBM ±8000 ±4000 ±3000 ±2000 V Symbol Value Unit MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 37 Electrical Characteristics Table 49. ESD and Latch-up Protection Characteristics (continued) Ratings ESD GUN - following IEC 61000-4-2 Test Specification contact discharge, CZAP= 150 pF, RZAP = 330  - LIN (with or without bus filter CBUS=220 pF) - VSENSE with serial RVSENSE(54) - VS1, VS2 with CVS - Lx with serial RLX ESD GUN - following ISO10605 Test Specification(56), unpowered, contact discharge, CZAP= 150 pF, RZAP = 2.0 k - LIN (with or without bus filter CBUS=220pF) - VSENSE with serial RVSENSE(54) - VS1, VS2 with CVS - Lx with serial RLX ESD GUN - following ISO10605 Test Specification discharge, CZAP= 330 pF, RZAP = 2.0 k - LIN (with or without bus filter CBUS=220 pF) - VSENSE with serial RVSENSE(54) - VS1, VS2 with CVS - Lx with serial RLX Note: 53. 54. 55. 56. Input Voltage Limit = -2.5 to 7.5 V. With CVBAT (10…100 nF) as part of the battery path. Certification available on request Tested internally only; certification pending (56) (56), Symbol unpowered, Value Unit ±8000 ±8000 ±8000 ±8000 V ±6000 ±6000 ±6000 ±6000 , powered, contact V ±8000 ±8000 ±8000 ±8000 V MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 38 Electrical Characteristics 3.9 Additional Test Information ISO7637-2 Immunity against transients for the LIN, Lx, and VBAT, is specified according to the LIN Conformance Test Specification - Section LIN EMC Test Specification refer to the LIN Conformance Test Certification Report - available as separate document. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 39 Functional Description and Application Information 4 4.1 Functional Description and Application Information Introduction This chapter describes the MM912_634 dual die device functions on a block by block base. To distinguish between the module location being the MCU die or the analog die, the following symbols are shown on all module cover pages: The documented module is physically located on the Analog die. This applies to Section 4.3, “MM912_634 - Analog Die Overview through Section 4.26, “MM912_634 - Analog Die Trimming. MCU ANALOG The documented module is physically located on the Microcontroller die. This applies to Section 4.27, “MM912_634 - MCU Die Overview through Section 4.39, “Serial Peripheral Interface (S12SPIV5). MCU ANALOG Sections concerning both dies or the complete device will not have a specific indication. 4.2 Device Register Maps Table 50. Device Register Memory Map Overview Address 0x0000–0x0009 0x000A–0x000B 0x000C–0x000D 0x000E–0x000F 0x0010–0x0015 0x0016–0x0019 0x001A–0x001B 0x001C–0x001E 0x001F 0x0020–0x002F 0x0030–0x0033 0x0034–0x003F 0x0040–0x00D7 0x00D8–0x00DF 0x00E0–0x00E7 0x00E8–0x00EF 0x00F0–0x00FF 0x0100–0x0113 0x0114–0x011F 0x0120–0x017F 0x0180–0x01EF 0x01F0–0x01FC 0x01FD–0x01FF 0x0200-0x02FF 0x0300–0x03FF Module PIM (port integration module) MMC (memory map control) PIM (port integration module) Reserved MMC (memory map control) Reserved Device ID register Reserved INT (interrupt module) DBG (debug module) Reserved CPMU (clock and power management) Reserved D2DI (die 2 die initiator) Reserved SPI (serial peripheral interface) Reserved FTMRC control registers Reserved PIM (port integration module) Reserved CPMU (clock and power management) Reserved D2DI (die 2 die initiator, blocking access window) D2DI (die 2 die initiator, non-blocking write window) Size (Bytes) 10 2 2 2 8 2 2 4 1 16 4 12 152 8 32 8 32 20 12 96 112 13 3 256 256 Table 50 shows the device register memory map overview for the 64 kByte MCU die (MC9S12I64). MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 40 Functional Description and Application Information NOTE Reserved register space shown in Table 50 is not allocated to any module. This register space is reserved for future use, and will show as grayed areas in tables throughout this document. Writing to these locations has no effect. Read access to these locations returns zero. 4.2.1 Detailed Module Register Maps Table 51. 0x0000–0x0007 Port Integration Module (PIM) Map 1 of 3 Table 51 to Table 73 show the detailed module maps of the MC9S12I64 MCU die. Address 0x0000 Name PORTA R W R W R W R W R W Bit 7 PA7 0 Bit 6 PA6 0 Bit 5 PA5 0 Bit 4 PA4 0 Bit 3 PA3 0 Bit 2 PA2 0 Bit 1 PA1 Bit 0 PA 0 0x0001 PORTB PB1 PB0 0x0002 DDRA DDRA7 0 DDRA6 0 DDRA5 0 DDRA4 0 DDRA3 0 DDRA2 0 DDRA1 DDRA0 0x0003 0x00040x0009 DDRE DDRE1 0 DDRE0 0 Reserved 0 0 0 0 0 0 Table 52. 0x000A–0x000B Memory Map Control (MMC) Map 1 of 2 Address 0x000A Name Reserved R W R W MODC 0 0 0 0 0 0 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x000B MODE Table 53. 0x000C–0x000D Port Integration Module (PIM) Map 2 of 3 Address 0x000C Name PUCR R W R W 0 Bit 7 0 Bit 6 BKPUE 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 PDPEE 0 Bit 0 0 0x000D RDRIV 0 0 RDRD RDRC 0 Table 54. 0x000E–0x000F Reserved Address 0x000E0x000F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 55. 0x0010–0x001B Memory Map Control (MMC) Map 2 of 2 Address 0x0010 Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 41 Functional Description and Application Information Table 55. 0x0010–0x001B Memory Map Control (MMC) Map 2 of 2 Address 0x0011 Name DIRECT R W R W R W R W R W 0 0 0 0 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFRON 0 Bit 7 DP15 0 Bit 6 DP14 0 Bit 5 DP13 0 Bit 4 DP12 0 Bit 3 DP11 0 Bit 2 DP10 0 Bit 1 DP9 0 Bit 0 DP8 0 0x0012 Reserved 0x0013 MMCCTL1 0x0014 Reserved 0x0015 PPAGE Table 56. 0x0016–0x0019 Reserved Address 0x00160x0019 Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 57. 0x001A–0x001B Device ID Register (PARTIDH/PARTIDL) Address 0x001A Name PARTIDH R W R W PARTIDL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PARTIDH 0x001B PARTIDL Table 58. 0x001C–0x001E Reserved Address 0x001C0x001E Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 59. 0x001F Interrupt Module (INT) Address 0x001F Name IVBR R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IVB_ADDR[7:0] Table 60. 0x0020–0x002F Debug Module (DBG) Address 0x0020 Name DBGC1 R W R W R W 0 TSOURCE 0 0 TRCMOD 0 TALIGN Bit 7 ARM TBF Bit 6 0 TRIG 0 0 Bit 5 0 Bit 4 BDM 0 Bit 3 DBGBRK 0 Bit 2 0 Bit 1 COMRV SSF1 SSF0 Bit 0 0x0021 DBGSR SSF2 0x0022 DBGTCR MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 42 Functional Description and Application Information Table 60. 0x0020–0x002F Debug Module (DBG) Address 0x0023 Name DBGC2 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 0 0 SZE SZ TAG BRK RW RWE NDB 0 COMPE 0 0 0 0 0 0 0 0 SC3 0 SC2 MC2 SC1 MC1 SC0 MC0 TBF 0 CNT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 ABCM Bit 8 Bit 0 0x0024 DBGTBH 0x0025 DBGTBL 0x0026 DBGCNT DBGSCRX 0x0027 DBGMFR DBGACTL 0x0028 DBGBCTL SZE 0 SZ 0 TAG BRK RW RWE COMPE DBGCCTL TAG 0 BRK 0 RW 0 RWE 0 0 COMPE 0x0029 DBGXAH Bit 17 Bit 16 0x002A DBGXAM 9 Bit 8 0x002B DBGXAL Bit 7 6 5 4 3 2 1 Bit 0 0x002C DBGADH Bit 15 14 13 12 11 10 9 Bit 8 0x002D DBGADL Bit 7 6 5 4 3 2 1 Bit 0 0x002E DBGADHM Bit 15 14 13 12 11 10 9 Bit 8 0x002F DBGADLM Bit 7 6 5 4 3 2 1 Bit 0 Table 61. 0x0030–0x033 Reserved Address 0x00300x0033 Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 62. 0x0034–0x003F Clock and Power Management (CPMU) Map 1 of 2 Address 0x0034 Name CPMU SYNR R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCOFRQ[1:0] SYNDIV[5:0] MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 43 Functional Description and Application Information Table 62. 0x0034–0x003F Clock and Power Management (CPMU) Map 1 of 2 Address 0x0035 Name CPMU REFDIV CPMU POSTDIV CPMUFLG R W R W R W R W R W R W R W R W R W R W R W 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0 0 0 0 0 0 0 RTDEC RTR6 RTIF PORF 0 LVRF 0 LOCKIF LOCK Bit 7 Bit 6 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 REFFRQ[1:0] 0 0 REFDIV[3:0] 0x0036 0 POSTDIV[4:0] UPOSC 0x0037 ILAF 0 OSCIF 0x0038 CPMUINT RTIE LOCKIE 0 0 OSCIE RTI OSCSEL 0 0 0x0039 CPMUCLKS PLLSEL 0 PSTP 0 0 PRE 0 PCE 0 COP OSCSEL 0 0x003A CPMUPLL FM1 FM0 0x003B CPMURTI RTR5 0 WRTMASK 0 RTR4 0 RTR3 0 RTR2 RTR1 RTR0 0x003C CPMUCOP WCOP 0 RSBCK 0 CR2 0 CR1 0 CR0 0 0x003D Reserved 0 0 0x003E Reserved CPMU ARMCOP 0x003F Table 63. 0x0040–0x0D7 Reserved Address 0x00400x00D7 Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 64. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) Map 1 of 3 Address 0x00D8 Name D2DCTL0 R W R W R W R W R W R W ADR[7:0] Bit 7 D2DEN Bit 6 D2DCW 0 Bit 5 D2DSWAI 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 D2DCLKDIV[1:0] 0x00D9 D2DCTL1 D2DIE 0 TIMEOUT[3:0] TERRF PARF PAR1 PAR0 0x00DA D2DSTAT0 ERRIF ACKERF CNCLF TIMEF 0x00DB D2DSTAT1 D2DIF RWB D2DBSY 0 0 0 0 0 0 0x00DC D2DADRHI SZ8 0 NBLK 0 0 0 0 0x00DD D2DADRLO MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 44 Functional Description and Application Information Table 64. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) Map 1 of 3 0x00DE D2DDATAHI R W R W DATA[7:0] DATA[15:8] 0x00DF D2DDATALO Table 65. 0x00E0–0x0E7 Reserved Address 0x00E00x00E7 Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 66. 0x00E8–0x00EF Serial Peripheral Interface (SPI) Address 0x00E8 Name SPICR1 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 R15 T15 R7 T7 0 R14 T14 R6 T6 0 R13 T13 R5 T5 0 R12 T12 R4 T4 0 R11 T11 R3 T3 0 R10 T10 R2 T2 0 R9 T9 R1 T1 0 R8 T8 R0 T0 0 SPIF 0 Bit 7 SPIE 0 Bit 6 SPE Bit 5 SPTIE 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 Bit 1 SSOE Bit 0 LSBFE 0x00E9 SPICR2 XFRW MODFEN BIDIROE 0 SPISWAI SPC0 0x00EA SPIBR SPPR2 0 SPPR1 SPTEF SPPR0 MODF SPR2 0 SPR1 0 SPR0 0 0x00EB SPISR 0 0x00EC SPIDRH 0x00ED SPIDRL 0x00EE Reserved 0x00EF Reserved Table 67. 0x00F0–0x0FF Reserved Address 0x00E00x00FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 45 Functional Description and Application Information Table 68. 0x0100–0x011F Flash Module (FTMRC) Address 0x0100 Name FCLKDIV R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPOPEN RNV6 FPHDIS 0 FPHS1 0 FPHS0 FPLDIS CCIF 0 0 ACCERR 0 FPVIOL 0 MGBUSY RSVD CCIE 0 0 0 IGNSF 0 0 0 FDFD FSFD 0 0 0 0 0 0 0 0 0 0 CCOBIX2 0 CCOBIX1 0 CCOBIX0 0 KEYEN1 Bit 7 FDIVLD Bit 6 FDIVLCK KEYEN0 Bit 5 FDIV5 RNV5 Bit 4 FDIV4 RNV4 Bit 3 FDIV3 RNV3 Bit 2 FDIV2 RNV2 Bit 1 FDIV1 SEC1 Bit 0 FDIV0 SEC0 0x0101 FSEC 0x0102 FCCOBIX 0x0103 Reserved 0x0104 FCNFG 0x0105 FERCNFG 0 0 0 0 DFDIE MGSTAT1 SFDIE MGSTAT0 0x0106 FSTAT 0x0107 FERSTAT 0 0 0 DFDIF SFDIF 0x0108 FPROT FPLS1 FPLS0 0x0109 DFPROT DPOPEN 0 DPS3 DPS2 DPS1 DPS0 0x010A FCCOBHI CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 0x010B FCCOBLO CCOB7 0 CCOB6 0 CCOB5 0 CCOB4 0 CCOB3 0 CCOB2 0 CCOB1 0 CCOB0 0 0x010C Reserved 0x010D Reserved 0x010E Reserved 0x010F Reserved 0x0110 FOPT 0x0111 Reserved 0x0112 Reserved 0x0113 Reserved MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 46 Functional Description and Application Information Table 69. 0x0120 Port Integration Module (PIM) Map 3 of 3 Address 0x0120 Name PTIA R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTIB1 PTIB0 Bit 7 PTIA7 Bit 6 PTIA6 Bit 5 PTIA5 Bit 4 PTIA4 Bit 3 PTIA3 Bit 2 PTIA2 Bit 1 PTIA1 Bit 0 PTIA0 0x0121 0x01220x017F PTIB Reserved Table 70. 0x0180–0x1EF Reserved Address 0x01800x01EF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 71. 0x01F0–0x01FF Clock and Power Management (CPMU) Map 2 of 2 Address 0x01F0 Name Reserved CPMU LVCTL Reserved R W R W R W R W R W R W R W 0x01FB CPMUPROT R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROT 0 OSCE OSCBW OSCPINS_ EN TCTRIM[3:0] 0 0 IRCTRIM[9:8] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDS LVIE 0 LVIF 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x01F1 0x01F6 0x01F7 Reserved CPMU IRCTRIMH CPMU IRCTRIML 0x01F8 0x01F9 IRCTRIM[7:0] 0x01FA CPMUOSC OSCFILT[4:0] 0x01FC Reserved Table 72. 0x01FD–0x1FF Reserved Address 0x01FD0x01FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 73. 0x0200–0x03FF Die-To-Die Initiator Blocking and Non-Blocking Access Window Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 47 Functional Description and Application Information Table 73. 0x0200–0x03FF Die-To-Die Initiator Blocking and Non-Blocking Access Window 0x02000x02FF 0x03000x03FF Blocking Access R Window W Non-Blocking R Access Window W Table 74 shows the detailed module maps of the MM912_634 analog die. Table 74. Analog die Registers(57) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/ 0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 Offset 0x00 Name ISR (hi) Interrupt Source Register ISR (lo) Interrupt Source Register IVR Interrupt Vector Register VCR Voltage Control Register VSR Voltage Status Register LXR Lx Status Register LXCR Lx Control Register WDR Watchdog Register WDSR Watchdog Service Register WCR Wake Up Control Register TCR Timing Control Register WSR Wake Up Source Register RSR Reset Status Register MCR Mode Control Register LINR LIN Register PTBC1 Port B Configuration Register 1 PTBC2 Port B Config Register 2 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 LINOTIE 0 LINOTC RX TX LVSD 0 LINEN 0 0 0 0 0 0 MODE 0 0 WDR EXR WUR LVRX LVR POR FWU CSSEL L5WE WDSR WDOFF WDWO 0 0 L5DS 0 L4DS 0 L3DS 0 L2DS L1DS L0DS 0 0 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 VROVIE VROVC HTIE HTC HVIE HVC LVIE LVC LBIE LBC 0 0 IRQ TX ERR TOV CH3 CH2 CH1 CH0 VSI 7 0 6 0 5 HOT 4 LSOT 3 HSOT 2 LINOT 1 SCI 0 RX 0x01 0x02 0x04 0x05 0x08 0x09 0x10 WDTO 0x11 0x12 L4WE L3WE L2WE L1WE L0WE 0x13 FWM LINWU L5WU L4WU L3WU L2WU CST L1WU L0WU 0x14 0x15 0x16 0x18 LINSR 0x20 PUEB2 0 PUEB1 0 PUEB0 0 DDRB2 DDRB1 DDRB0 0x21 PWMCS PWMEN SERMOD MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 48 Functional Description and Application Information Table 74. Analog die Registers(57) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/ 0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 Offset 0x22 Name PTB Port B Data Register HSCR High Side Control Register HSSR High Side Status Register LSCR Low Side Control Register LSSR Low Side Status Register LSCEN 0x32 Low-Side Control Enable Register HSR Hall Supply Register CSR Current Sense Register SCIBD (hi) SCI Baud Rate Register SCIBD (lo) SCI Baud Rate Register SCIC1 SCI Control Register 1 SCIC2 SCI Control Register 2 SCIS1 SCI Status Register 1 SCIS2 SCI Status Register 2 SCIC3 SCI Control Register 3 SCID SCI Data Register PWMCTL PWM Control Register PWMPRCLK PWM Presc. Clk Select Reg PWMSCLA PWM Scale A Register PWMSCLB PWM Scale B Register R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 R7 T7 CAE1 0 LBKDIF R8 RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF HOTIE HOTC 0 0 0 0 0 0 0 0 LSCEN 0 LSOTIE LSOTC 0 PWMCS2 PWMCS1 PWMLS2 0 0 LS2CL PWMLS1 LS1CL LS2 LS2OL LS1 LS1OL HSOTIE HSOTC 7 0 6 0 5 0 4 0 3 0 2 PTB2 1 PTB1 0 PTB0 0x28 HSHVSD PWMCS2 PWMCS1 PWMHS2 PWMHS1 E 0 0 0 HS2CL HS1CL HS2 HS2OL HS1 HS1OL 0x29 0x30 0x31 0 0x38 HSUPON 0x3C CSE 0 0 0 CCD CSGS 0x40 LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x41 SBR7 SBR6 0 SBR5 SBR4 SBR3 0 SBR2 SBR1 SBR0 0x42 LOOPS RSRC M ILT PE PT 0x43 TIE TDRE TCIE TC RIE RDRF ILIE IDLE TE OR RE NF RWU FE SBK PF 0x44 0x45 0x46 T8 R6 T6 CAE0 TXDIR R5 T5 PCLK1 TXINV R4 T4 PCLK0 ORIE R3 T3 PPOL1 0 NEIE R2 T2 PPOL0 FEIE R1 T1 PWME1 PEIE R0 T0 PWME0 0x47 0x60 0x61 PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 0x62 6 5 4 3 2 1 Bit 0 0x63 Bit 7 6 5 4 3 2 1 Bit 0 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 49 Functional Description and Application Information Table 74. Analog die Registers(57) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/ 0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 Offset 0x64 Name PWMCNT0 PWM Ch Counter Reg 0 PWMCNT1 PWM Ch Counter Reg 1 PWMPER0 PWM Ch Period Register 0 PWMPER1 PWM Ch Period Register 1 PWMDTY0 PWM Ch Duty Register 0 PWMDTY1 PWM Ch Duty Register 1 ACR ADC Config Register ASR ADC Status Register ACCR (hi) ADC Conversion Ctrl Reg ACCR (lo) ADC Conversion Ctrl Reg ACCSR (hi) ADC Conv Complete Reg ACCSR (lo) ADC Conv Complete Reg ADR0 (hi) ADC Data Result Register 0 ADR0 (lo) ADC Data Result Register 0 ADR1 (hi) ADC Data Result Register 1 ADR1 (lo) ADC Data Result Register 1 ADR2 (hi) ADC Data Result Register 2 ADR2 (lo) ADC Data Result Register 2 ADR3 (hi) ADC Data Result Register 3 ADR3 (lo) ADC Data Result Register 3 ADR4 (hi) ADC Data Result Register 4 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W adr4 9 adr4 8 adr4 7 adr4 6 adr4 5 adr4 4 adr4 3 adr4 2 adr3 1 adr3 0 0 0 0 0 0 0 adr3 9 adr3 8 adr3 7 adr3 6 adr3 5 adr3 4 adr3 3 adr3 2 adr2 1 adr2 0 0 0 0 0 0 0 adr2 9 adr2 8 adr2 7 adr2 6 adr2 5 adr2 4 adr2 3 adr2 2 adr1 1 adr1 0 0 0 0 0 0 0 adr1 9 adr1 8 adr1 7 adr1 6 adr1 5 adr1 4 adr1 3 adr1 2 adr0 1 adr0 0 0 0 0 0 0 0 adr0 9 adr0 8 adr0 7 adr0 6 adr0 5 adr0 4 adr0 3 adr0 2 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 CH15 CH14 0 CH12 CH11 CH10 CH9 CH8 7 Bit 7 0 Bit 7 0 Bit 7 6 6 0 6 0 6 5 5 0 5 0 5 4 4 0 4 0 4 3 3 0 3 0 3 2 2 0 2 0 2 1 1 0 1 0 1 0 Bit 0 0 Bit 0 0 Bit 0 0x65 0x66 0x67 Bit 7 6 5 4 3 2 1 Bit 0 0x68 Bit 7 6 5 4 3 2 1 Bit 0 0x69 Bit 7 6 5 4 3 0 2 1 Bit 0 0x80 SCIE SCF CCE 2p5CLF OCE 0 ADCRST 0 PS2 CCNT2 PS1 CCNT1 PS0 CCNT0 0x81 CCNT3 0x82 0x83 CH7 CC15 CH6 CC14 CH5 0 CH4 CC12 CH3 CC11 CH2 CC10 CH1 CC9 CH0 CC8 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 50 Functional Description and Application Information Table 74. Analog die Registers(57) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/ 0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 Offset 0x8F Name ADR4 (lo) ADC Data Result Register 4 ADR5 (hi) ADC Data Result Register 5 ADR5 (lo) ADC Data Result Register 5 ADR6 (hi) ADC Data Result Register 6 ADR6 (lo) ADC Data Result Register 6 ADR7 (hi) ADC Data Result Register 7 ADR7 (lo) ADC Data Result Register 7 ADR8 (hi) ADC Data Result Register 8 ADR8 (lo) ADC Data Result Register 8 ADR9 (hi) ADC Data Result Register 9 ADR9 (lo) ADC Data Result Register 9 ADR10 (hi) ADC Data Result Reg 10 ADR10 (lo) ADC Data Result Reg 10 ADR11 (hi) ADC Data Result Reg 11 ADR11 (lo) ADC Data Result Reg 11 ADR12 (hi) ADC Data Result Reg 12 ADR12 (lo) ADC Data Result Reg 12 ADR14 (hi) ADC Data Result Reg 14 ADR14 (lo) ADC Data Result Reg 14 ADR15 (hi) ADC Data Result Reg 15 ADR15 (lo) ADC Data Result Reg 15 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W adr15 1 adr15 0 0 0 0 0 0 0 adr15 9 adr15 8 adr15 7 adr15 6 adr15 5 adr15 4 adr15 3 adr15 2 adr14 1 adr14 0 0 0 0 0 0 0 adr14 9 adr14 8 adr14 7 adr14 6 adr14 5 adr14 4 adr14 3 adr14 2 adr12 1 adr12 0 0 0 0 0 0 0 adr12 9 adr12 8 adr12 7 adr12 6 adr12 5 adr12 4 adr12 3 adr12 2 adr11 1 adr11 0 0 0 0 0 0 0 adr11 9 adr11 8 adr11 7 adr11 6 adr11 5 adr11 4 adr11 3 adr11 2 adr10 1 adr10 0 0 0 0 0 0 0 adr10 9 adr10 8 adr10 7 adr10 6 adr10 5 adr10 4 adr10 3 adr10 2 adr9 1 adr9 0 0 0 0 0 0 0 adr9 9 adr9 8 adr9 7 adr9 6 adr9 5 adr9 4 adr9 3 adr9 2 adr8 1 adr8 0 0 0 0 0 0 0 adr8 9 adr8 8 adr8 7 adr8 6 adr8 5 adr8 4 adr8 3 adr8 2 adr7 1 adr7 0 0 0 0 0 0 0 adr7 9 adr7 8 adr7 7 adr7 6 adr7 5 adr7 4 adr7 3 adr7 2 adr6 1 adr6 0 0 0 0 0 0 0 adr6 9 adr6 8 adr6 7 adr6 6 adr6 5 adr6 4 adr6 3 adr6 2 adr5 1 adr5 0 0 0 0 0 0 0 adr5 9 adr5 8 adr5 7 adr5 6 adr5 5 adr5 4 adr5 3 adr5 2 7 adr4 1 6 adr4 0 5 0 4 0 3 0 2 0 1 0 0 0 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA2 0xA3 0xA4 0xA5 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 51 Functional Description and Application Information Table 74. Analog die Registers(57) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/ 0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 Offset 0xC0 Name TIOS TIM InCap/OutComp Select CFORC Timer Compare Force Reg OC3M Output Comp 3 Mask Reg OC3D Output Comp 3 Data Reg TCNT (hi) Timer Count Register TCNT (lo) Timer Count Register TSCR1 Timer System Control Reg 1 TTOV Timer Toggle Overflow Reg TCTL1 Timer Control Register 1 TCTL2 Timer Control Register 2 TIE Timer Interrupt Enable Reg TSCR2 Timer System Control Reg 2 TFLG1 Main Timer Interrupt Flag 1 TFLG2 Main Timer Interrupt Flag 2 TC0 (hi) TIM InCap/OutComp Reg 0 TC0 (lo) TIM InCap/OutComp Reg 0 TC1 (hi) TIM InCap/OutComp Reg 1 TC1 (lo) TIM InCap/OutComp Reg 1 TC2 (hi) TIM InCap/OutComp Reg 2 TC2 (lo) TIM InCap/OutComp Reg 2 TC3 (hi) TIM InCap/OutComp Reg 3 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TOF 0 0 0 TOI 0 0 0 0 OM3 OL3 OM2 OL2 tcnt 15 tcnt 14 tcnt 13 tcnt 12 0 0 0 0 0 0 0 0 0 0 0 0 7 0 6 0 5 0 4 0 3 IOS3 0 FOC3 OC3M3 2 IOS2 0 FOC2 OC3M2 1 IOS1 0 FOC1 OC3M1 0 IOS0 0 FOC0 OC3M0 0xC1 0xC2 0xC3 OC3D3 OC3D2 OC3D1 OC3D0 0xC4 tcnt 11 tcnt 10 tcnt 9 tcnt 8 0xC5 tcnt 7 tcnt 6 0 tcnt 5 0 tcnt 4 tcnt 3 0 tcnt 2 0 tcnt 1 0 tcnt 0 0 0xC6 TEN 0 TFFCA 0 0xC7 0 0 TOV3 TOV2 TOV1 TOV0 0xC8 OM1 OL1 OM0 OL0 0xC9 EDG3B 0 EDG3A 0 EDG2B 0 EDG2A 0 EDG1B EDG1A EDG0B EDG0A 0xCA C3I C2I C1I C0I 0xCB TCRE PR2 PR1 PR0 0xCC 0 0 0 C3F 0 C2F 0 C1F 0 C0F 0 0xCD 0xCE tc0 15 tc0 14 tc0 13 tc0 12 tc0 11 tc0 10 tc0 9 tc0 8 0xCF tc0 7 tc0 6 tc0 5 tc0 4 tc0 3 tc0 2 tc0 1 tc0 0 0xD0 tc1 15 tc1 14 tc1 13 tc1 12 tc1 11 tc1 10 tc1 9 tc1 8 0xD1 tc1 7 tc1 6 tc1 5 tc1 4 tc1 3 tc1 2 tc1 1 tc1 0 0xD2 tc2 15 tc2 14 tc2 13 tc2 12 tc2 11 tc2 10 tc2 9 tc2 8 0xD3 tc2 7 tc2 6 tc2 5 tc2 4 tc2 3 tc2 2 tc2 1 tc2 0 0xD4 tc3 15 tc3 14 tc3 13 tc3 12 tc3 11 tc3 10 tc3 9 tc3 8 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 52 Functional Description and Application Information Table 74. Analog die Registers(57) - 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/ 0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 Offset 0xD5 Name TC3 (lo) TIM InCap/OutComp Reg 3 CTR0 Trimming Reg 0 CTR1 Trimming Reg 1 CTR2 Trimming Reg 2 CTR3 Trimming Reg 3 SRR Silicon Revision Register R W R W R W R W R W R W 7 tc3 7 6 tc3 6 5 tc3 5 4 tc3 4 3 tc3 3 2 tc3 2 1 tc3 1 0 tc3 0 0xF0 LINTRE LINTR WDCTRE BGTRIM UP CTR2_0 OFFCTR 1 0 CTR0_4 BGTRIM DN SLPBGT RE OFFCTR 0 0 CTR0_3 WDCTR2 WDCTR1 WDCTR0 0xF1 BGTRE CTR1_6 IREFTRE SLPBG_L OCK CTR3_E IREFTR2 SLPBGT R2 CTR3_2 IREFTR1 SLPBGT R1 CTR3_1 IREFTR0 SLPBGT R0 CTR3_0 0xF2 CTR2_E OFFCTR E 0 CTR2_1 OFFCTR 2 0 0xF3 0xF4 FMREV MMREV Note: 57. Registers not shown are reserved and must not be accessed. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 53 MM912_634 - Analog Die Overview 4.3 4.3.1 MM912_634 - Analog Die Overview Introduction MCU ANALOG The MM912_634 analog die implements all system base functionality to operate the integrated microcontroller, and delivers application specific actuator control as well as input capturing. 4.3.2 4.3.2.1 System Registers Silicon Revision Register (SRR) Table 75. Silicon Revision Register (SRR) Offset (58) 0xF4 7 6 0 5 0 4 0 3 FMREV 2 1 Access: User read 0 MMREV R W 0 Note: 58. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 76. SRR - Register Field Descriptions Field 3-2 FMREV 1-0 MMREV Description MM912_634 analog die Silicon Revision Register Full Mask Revision - The three bits represent the revision count of full mask change. Read only, writing will have no effect. The first Full Mask will have the count 00. MM912_634 analog die Silicon Revision Register Metal Tweak Revision - The three bits represent the count of metal tweaks applied to the full mask.Read only, writing will have no effect. The first Full Mask will have the count 00. NOTE Please refer to the MM912F634ER - Mask set errata document for details on the analog die mask revisions. 4.3.3 Analog Die Options Table 77. Analog Die Options Feature Current Sense Module Wake Up Inputs (Lx) The following section describes the differences between analog die options 1 and 2. Option 1 YES L0…L5 Option 2 NO L0.L3 NOTE This document will describe the features and functions of option 1 (all modules available and tested). Beyond this chapter, there will be no additional note or differentiation between the different implementations. 4.3.3.1 Current Sense Module For device options with the current sense module not available, the following considerations are to be made. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 54 4.3.3.1.1 Pinout considerations Table 78. ISENSE - Pin Considerations PIN 40 41 PIN name for option 1 ISENSEL ISENSEH New PIN name NC NC Comment ISENSE feature not bonded and/or not tested. Connect PINs 40 and 41 (NC) to GND. 4.3.3.1.2 Register Considerations The Current Sense Register must remain in default (0x00) state. Offset 0x3C Name CSR Current Sense Register R W 7 CSE 6 0 5 0 4 0 3 CCD 2 1 CSGS 0 The Conversion Control Register - Bit 9 must always be written 0. 0x82 ACCR (hi) ADC Conversion Ctrl Reg R W CH15 CH14 0 CH12 CH11 CH10 CH9 CH8 The Conversion Complete Register - Bit 9 must be ignored. 0x84 ACCSR (hi) ADC Conv Complete Reg R W CC15 CC14 0 CC12 CC11 CC10 CC9 CC8 The ADC Data Result Reg 9 must be ignored. 0x98 ADR9 (hi) ADC Data Result Register 9 ADR9 (lo) ADC Data Result Register 9 R W R W adr9 1 adr9 0 0 0 0 0 0 0 adr9 9 adr9 8 adr9 7 adr9 6 adr9 5 adr9 4 adr9 3 adr9 2 0x99 4.3.3.1.3 • • Functional Considerations The complete Current Sense Module is not available. The ADC Channel 9 is not available. 4.3.3.2 Wake-up Inputs (Lx) For device options with reduced number of wake up inputs (Lx), the following considerations are to be made. 4.3.3.2.1 Pinout considerations Table 79. Lx - Pin Considerations PIN PIN Name for Option 1 Lx New PIN name NC Comment One or more Lx wake up inputs are not available based on the analog die option. Not available Lx inputs are not bonded and/or not tested. Connect not available Lx pins (NC) to GND. RLx is not required on those pins. 31…36 4.3.3.2.2 Register Considerations The Lx - Bit for the not available Lx input in the Lx Status Register must be ignored. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 55 Offset 0x08 Name LXR Lx Status Register R W 7 0 6 0 5 L5 4 L4 3 L3 2 L2 1 L1 0 L0 The Lx Control register for the not available Lx input must be written 0. 0x09 LXCR Lx Control Register R W 0 0 L5DS L4DS L3DS L2DS L1DS L0DS A not available Lx input can not be selected as Wake-up Source and must have its LxWE bit set to 0. 0x12 WCR Wake Up Control Register R W CSSEL L5WE L4WE L3WE L2WE L1WE L0WE The Wake-up Source Register for not available Lx inputs must be ignored. 0x14 WSR Wake Up Source Register R W FWU LINWU L5WU L4WU L3WU L2WU L1WU L0WU The Conversion Control Register for the not available Lx analog input (3…8) must always be written 0. 0x82 ACCR (hi) ADC Conversion Ctrl Reg ACCR (lo) ADC Conversion Ctrl Reg R W R W CH15 CH14 0 CH12 CH11 CH10 CH9 CH8 0x83 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 The Conversion Complete Register for the not available Lx analog input (3.8) must be ignored. 0x84 ACCSR (hi) ADC Conv Complete Reg ACCSR (lo) ADC Conv Complete Reg R W R W CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 CC15 CC14 0 CC12 CC11 CC10 CC9 CC8 0x85 The ADC Data Result Register for the not available Lx analog input (3.8) must be ignored. ADRx (hi) 0x8C-0 x97 ADC Data Result Register x ADRx (lo) ADC Data Result Register x R W R W adrx 1 adrx 0 0 0 0 0 0 0 adrx 9 adrx 8 adrx 7 adrx 6 adrx 5 adrx 4 adrx 3 adrx 2 4.3.3.2.3 Functional Considerations For the not available Lx inputs, the following functions are limited: • No Wake-up feature / Cyclic Sense • No Digital Input • No Analog Input and conversion via ADC MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 56 Modes of Operation 4.4 Modes of Operation MCU ANALOG The MM912_634 analog die offers three main operating modes: Normal (Run), Stop, and Sleep. In Normal mode, the device is active and is operating under normal application conditions. In Stop mode, the voltage regulator operates with limited current capability, the external load is expected to be reduced while in Stop mode. In Sleep mode both voltage regulators are turned off (VDD = VDDX = 0 V). Wake-up from Stop mode is indicated by an interrupt signal. Wake-up from Sleep mode will change the MM912_634 analog die into reset mode while the voltage regulator is turned back on. The selection of the different modes is controlled by the Mode Control Register (MCR). Figure 16 describes how transitions are done between the different operating modes. Power Down Power Up (POR = 1) Power Down (VSUPVLVR and VDDX>VLVRX the MM912_634 analog die enters in Normal mode. To avoid short-circuit conditions being present for a long time, a tVTO timeout is implemented. Once VDD < VLVR or VDDX < VLVRX with VS1 > (VLVI + VLVI_H) for more than tVTO, the MM912_634 analog die will transit directly to Sleep mode. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 57 Modes of Operation The Reset Status Register (RSR) will indicate the source of the reset by individual flags. • POR - Power On Reset • LVR - Low Voltage Reset VDD • LVRX - Low Voltage Reset VDDX • WDR - Watchdog Reset • EXR - External Reset • WUR - Wake-up Sleep Reset See also Section 4.8, “Resets. 4.4.3 Normal Mode In Normal mode, all MM912_634 analog die user functions are active and can be controlled by the D2D Interface. Both regulators (VDD and VDDX) are active and operate with full current capability. Once entered in Normal mode, the Watchdog will operate as a simple non-window watchdog with an initial timeout (tIWDTO) to be reset via the D2D Interface. After the initial reset, the watchdog will operate in standard window mode. See Section 4.10, “Window Watchdog for details. 4.4.4 Stop Mode The Stop mode will allow reduced current consumption with fast startup time. In this mode, both voltage regulators (VDD and VDDX) are active, with limited current drive capability. In this condition, the MCU is supposed to operate in Low Power mode (STOP). NOTE To avoid any pending analog die interrupts prevent the MCU from entering MCU stop resulting in unexpected system behavior, the analog die IRQ sources should be disabled and the corresponding flags be cleared before entering stop. The device can enter in Stop mode by configuring the Mode Control Register (MCR) via the D2D Interface. The MCU has to enter a Low Power mode immediately afterwards executing the STOP instruction. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. While in Stop mode, the MM912_634 analog die will wake up on the following sources: • Lx - Wake-up (maskable with selectable cyclic sense) • Forced Wake-up (configurable timeout) • LIN Wake-up • D2D Wake-up (special command) After Wake-up from the sources listed above, the device will transit to Normal mode. Reset will wake up the device directly to Reset mode. See Section 4.9, “Wake-up / Cyclic Sense for details. 4.4.5 Sleep Mode The Sleep mode will allow very low current consumption. In this mode, both voltage regulators (VDD and VDDX) are inactive. The device can enter into Sleep mode by configuring the Mode Control Register (MCR) via the D2D- Interface. During Sleep mode, all unused internal blocks are deactivated to allow the lowest possible consumption. Power consumption will decrease further if the Cyclic Sense or Forced Wake-up feature are disabled. While in Sleep mode, the MM912_634 analog die will wake up on the following sources: • Lx - Wake-up (maskable with selectable cyclic sense) • Forced Wake-up (configurable timeout) • LIN Wake-up After Wake-up from the sources listed above or a reset condition, the device will transit to Reset mode. See Section 4.9, “Wake-up / Cyclic Sense for details. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 58 Modes of Operation 4.4.6 Analog Die Functionality by Operation Mode Table 80. Operation Mode Overview Function VDD/VDDX HSUP LSx HSx ADC D2D Lx PTBx LIN Watchdog VSENSE CSENSE Cyclic Sense OFF Reset full Normal full full full full full full full full full full (60) Stop stop OFF OFF Cyclic Sense(59) OFF functional Wake-up(59) OFF Wake-up(59) OFF OFF OFF Cyclic Sense (59) Sleep OFF OFF OFF Cyclic Sense(59) OFF OFF Wake-up(59) OFF Wake-up(59) OFF OFF OFF Cyclic Sense(59) full full not active Note: 59. If configured. 60. Special init through non window watchdog. 4.4.7 4.4.7.1 Register Definition Mode Control Register (MCR) Table 81. Mode Control Register (MCR) Offset(61) 0x16 7 R W Reset 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 Access: User read/write 1 MODE 0 0 0 Note: 61. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 82. MCR - Register Field Descriptions Field Description Mode Select - These bits will issue a transition from to the selected Operating Mode. 1-0 MODE 00 - Normal Mode. Only with effect in Stop Mode. Will issue Wake Up and transition to Normal Mode. 01 - Stop Mode. Will initiate transition to Stop Mode.(62) 10 - Sleep Mode. Will initiate transition to Sleep Mode. 11 - Normal Mode. Note: 62. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 59 Power Supply 4.5 Power Supply MCU ANALOG The MM912_634 analog die supplies VDD (2.5 V), VDDX (5.0 V), and HSUP, based on the supply voltage applied to the VS1 pin. VDD is cascaded of the VDDX regulator. To separate the High Side outputs from the main power supply, the VS2 pin does only power the High Side drivers. Both supply pins have to be externally protected against reverse battery conditions. To supply external Hall Effect Sensors, the HSUP pin will supply a switchable regulated supply. See Section 4.11, “Hall Sensor Supply Output - HSUP. A reverse battery protected input (VSENSE) is implemented to measure the Battery Voltage directly. A serial resistor (RVSENSE) is required on this pin. See Section 4.23, “Supply Voltage Sense - VSENSE. In addition, the VS1 supply can be routed to the ADC (VS1SENSE) to measure the VS1 pin voltage directly. See Section 4.24, “Internal Supply Voltage Sense - VS1SENSE. To have an independent ADC verification, the internal sleep mode bandgap voltage can be routed to the ADC (BANDGAP). As this node is independent from the ADC reference, any out of range result would indicate malfunctioning ADC or Bandgap reference. See Section 4.25, “Internal Bandgap Reference Voltage Sense - BANDGAP. To stabilize the internal ADC reference voltage for higher precision measurements, the current limited ADC2p5 pin needs to be connected to an external filter capacitor (CADC2p5). It is not recommended to connect additional loads to this pin. See Section 4.20, “Analog Digital Converter - ADC. The following safety features are implemented: • LBI - Low Battery Interrupt, internally measured at VSENSE • LVI - Low Voltage Interrupt, internally measured at VS1 • HVI - High Voltage Interrupt, internally measured at VS2 • VROVI - Voltage Regulator Over-voltage Interrupt internally measured at VDD and VDDX • LVR - Low Voltage Reset, internally measured at VDD • LVRX - Low Voltage Reset, internally measured at VDDX • HTI - High Temperature Interrupt measured between the VDD and VDDX regulators • Over-temperature Shutdown measured between the VDD and VDDX regulators VSENSE LBI VS2 HVI HS1 VS1 HS1 & HS2 HS2 LVI ÷ ADC bg1p25sleep HSUP HSUP (18V) Regulator VDDX (5V) Regulator CHSUP VDDXINTERNAL VROV LVRX CVDDX VDDX ADC2p5 ADC 2.5V Reference VDD (2.5V) Regulator VDD VDDINTERNAL LVR CVDD CADC Figure 17. MM912_634 Power Supply MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 60 Power Supply 4.5.1 Voltage Regulators VDD (2.5 V) & VDDX (5.0 V) To supply the MCU die and minor additional loads two cascaded voltage regulators have been implemented, VDDX (5.0 V) and VDD (2.5 V). External capacitors (CVDD) and (CVDDX) are required for proper regulation. 4.5.2 Power Up Behavior / Power Down Behavior - I64 To guarantee safe power up and down behavior, special dependencies are implemented to prevent unwanted MCU execution. Figure 18 shows a standard power up and power down sequence. MCU_POR MCU_POR 6 MCU_LVR MCU_LVR 1 4 5 2 RESET_A Normal Operating Range (not to scale) VLBI / VLVI VROVX 5V VLVRX / VLVR_MCU VROX VLVR VPOR_A VPOR_MCU 3 VSUP VDDX VDD Figure 18. Power Up / Down Sequence To avoid any critical behavior, it is essential to have the MCU Power On Reset (POR) active when the analog die reset (RESET_A) is not fully active. As the RESET_A circuity is supplied by VDDX, VDD needs to be below the POR threshold when VDDX is to low to guarantee RESET_A active (3;6). This is achieved with the following implementation. Power Up: • The VDD regulator is enabled after VDDX has reached the VLVRX threshold (1). • Once VDD reaches VLRV, the RESET_A is released (2). • The MCU is also protected by the MCU_LVR. Power Down: • Once VDDX has reached the VLVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well. • The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. NOTE The behavior explained previously is essential for the MC9S12I64 MCU die used, as this MCU does have an internal regulator stage, but the LVR function only active in normal modeMC9S12I64. The shutdown behavior should be considered when sizing the external capacitors CVDD and CVDDX for extended low voltage operation. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 61 Power Supply 4.5.3 4.5.3.1 Register Definition Voltage Control Register (VCR) Table 83. Voltage Control Register (VCR) Offset(63) 0x04 7 6 0 5 0 4 VROVIE 0 3 HTIE 0 2 HVIE 0 Access: User read/write 1 LVIE 0 0 LBIE 0 R W Reset Note: 63. 0 0 0 0 Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 84. VCR - Register Field Descriptions Field 4 VROVIE 3 HTIE 2 HVIE 1 LVIE 0 LBIE Description Voltage Regulator Over-voltage Interrupt Enable — Enables the interrupt for the Regulator Over-voltage Condition. 0 - Voltage Regulator Over-voltage Interrupt is disabled 1 - Voltage Regulator Over-voltage Interrupt is enabled High Temperature Interrupt Enable — Enables the interrupt for the Voltage Regulator (VDD/VDDX) Temperature Warning. 0 - High Temperature Interrupt is disabled 1 - High Temperature Interrupt is enabled High Voltage Interrupt Enable — Enables the interrupt for the VS2 - High Voltage Warning. 0 - High Voltage Interrupt is disabled 1 - High Voltage Interrupt is enabled Low Voltage Interrupt Enable — Enables the interrupt for the VS1 - Low Voltage Warning. 0 - Low Voltage Interrupt is disabled 1 - Low Voltage Interrupt is enabled Low Battery Interrupt Enable — Enables the interrupt for the VSENSE - Low Battery Voltage Warning. 0 - Low Battery Interrupt is disabled 1 - Low Battery Interrupt is enabled 4.5.3.2 Voltage Status Register (VSR) Table 85. Voltage Status Register (VSR) Offset(64) 0x05 7 R W Reset 0 0 0 0 0 0 0 0 6 0 5 0 4 VROVC 3 HTC 2 HVC 1 LVC Access: User read 0 LBC 0 Note: 64. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 62 Power Supply Table 86. VSR - Register Field Descriptions Field Description Voltage Regulator Over-voltage Condition - This status bit indicates an over-voltage warning is present for at least one of the main voltage regulators (VDD or VDDX). Reading the register will clear the VROVI flag if present. See Section 4.7, “Interrupts for details. Note: This feature requires the trimming of Section 4.26.1.2.3, “Trimming Register 2 (CTR2) to be done to be effective. Untrimmed devices may issue the VROVC condition including the LS turn off at normal operation! 0 - No Voltage Regulator Over-voltage Condition present. 1 - Voltage Regulator Over-voltage Condition present. 3 HTC High Temperature Condition - This status bit indicates a high temperature warning is present for the Voltage regulators (VDD/VDDX). Reading the register will clear the HTI flag if present. See Section 4.7, “Interrupts for details. 0 - No High Temperature Condition present. 1 - High Temperature Condition present. 2 HVC High Voltage Condition - This status bit indicates a high voltage warning for VS2 is present. Reading the register will clear the HVI flag if present. See Section 4.7, “Interrupts for details. 0 - No High Voltage Condition present. 1 - High Voltage Condition present. 1 LVC Low Voltage Condition - This status bit indicates a low voltage warning for VS1 is present. Reading the register will clear the LVI flag if present. See Section 4.7, “Interrupts for details. 0 - No Low Voltage Condition present. 1 - Low Voltage Condition present. 0 LBC Low Battery Condition - This status bit indicates a low voltage warning for VSENSE is present. Reading the register will clear the LBI flag if present. See Section 4.7, “Interrupts for details. 0 - No Low Battery Condition present. 1 - Low Battery Condition present. 4 VROVC MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 63 Die to Die Interface - Target 4.6 Die to Die Interface - Target MCU ANALOG The D2D Interface is the bus interface to the Microcontroller. Access to the MM912_634 analog die is controlled by the D2D Interface module. This section describes the functionality of the die-to-die target block (D2D). 4.6.1 Overview The D2D is the target for a data transfer from the target to the initiator (MCU). The initiator provides a set of configuration registers and two memory mapped 256 Byte address windows. When writing to a window, a transaction is initiated sending a write command, followed by an 8-bit address, and the data byte or word is received from the initiator. When reading from a window, a transaction is received with the read command, followed by an 8-bit address. The target then responds with the data. The basic idea is that a peripheral located on the MM912_634 analog die, can be addressed like an on-chip peripheral. Features: • software transparent register access to peripherals on the MM912_634 analog die • 256 Byte address window • supports blocking read or write, as well as non-blocking write transactions • 4-bit physical bus width • automatic synchronization of the target when initiator starts driving the interface clock • generates transaction and error status as well as EOT acknowledge • providing single interrupt interface to D2D Initiator 4.6.2 Low Power Mode Operation The D2D module is disabled in SLEEP mode. In Stop mode, the D2DINT signal is used to wake-up a powered down MCU. As the MCU could wake-up without the MM912_634 analog die, a special command will be recognized as a wake-up event during Stop mode. See Section 4.4, “Modes of Operation. 4.6.2.1 Normal Mode / Stop Mode While in Normal or Stop mode, D2DCLK acts as input only with pull present. D2D[3:0] operates as an input/output with pull-down always present. D2DINT acts as output only. NOTE The maximum allowed clock speed of the interface is limited to fD2D. 4.6.2.2 Sleep Mode While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 64 Interrupts 4.7 Interrupts MCU ANALOG Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. While in Stop mode, the interrupt signal is used to signal Wake-up events. The interrupts are signaled by an active high level of the D2DINT pin, which will remain high until the interrupt is acknowledged via the D2D-Interface. Interrupts are only asserted while in Normal mode. 4.7.1 Interrupt Source Identification Once an Interrupt is signalized, there are two options to identify the corresponding source(s). 4.7.1.1 Interrupt Source Mirror All Interrupt sources in MM912_634 analog die are mirrored to a special Interrupt Source Register (ISR). This register is read only and will indicate all currently pending Interrupts. Reading this register will not acknowledge any interrupt. An additional D2D access is necessary to serve the specific module. NOTE The VSI - Voltage Status Interrupt combines the five status flags for the Low Battery Interrupt, Low Voltage Interrupt, High Voltage Interrupt, Voltage Regulator Over-voltage Interrupt, and the Voltage Regulator High Temperature Interrupt. The specific source can be identified by reading the Voltage Status Register - VSR. 4.7.1.1.1 Interrupt Source Register (ISR) Table 87. Interrupt Source Register (ISR) Offset(65) 0x00 (0x00 and 0x01 for 8Bit access) 15 R W Note: 65. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. 0 14 0 13 HOT 12 LSOT 11 HSOT 10 LINOT 9 SCI 8 RX 7 TX 6 ERR 5 TOV 4 CH3 3 CH2 2 CH1 Access: User read 1 CH0 0 VSI Table 88. ISR - Register Field Descriptions Field Description VSI - Voltage Status Interrupt combining the following sources: • Low Battery Interrupt • Low Voltage Interrupt • High Voltage Interrupt • Voltage Regulator Over-voltage Interrupt • Voltage Regulator High Temperature Interrupt CH0 - TIM Channel 0 Interrupt CH1 - TIM Channel 1 Interrupt CH2 - TIM Channel 2 Interrupt CH3 - TIM Channel 3 Interrupt TOV - Timer Overflow Interrupt ERR - SCI Error Interrupt TX - SCI Transmit Interrupt RX - SCI Receive Interrupt SCI - ADC Sequence Complete Interrupt LINOT - LIN Driver Over-temperature Interrupt HSOT - High Side Over-temperature Interrupt LSOT - Low Side Over-temperature Interrupt HOT - HSUP Over-temperature Interrupt MM912_634 Advance Information, Rev. 4.0 0 - VSI 1 - CH0 2 - CH1 3 - CH2 4 - CH3 5 - TOV 6 - ERR 7 - TX 8 - RX 9 - SCI 10 - LINOT 11 - HSOT 12 - LSOT 13 - HOT Freescale Semiconductor 65 Interrupts 4.7.1.2 Interrupt Vector Emulation by Priority To allow a vector based interrupt handling by the MCU, the number of the highest prioritized interrupt pending is returned in the Interrupt Vector Register. To allow an offset based vector table, the result is pre-shifted (multiple of 2). Reading this register will not acknowledge an interrupt. An additional D2D access is necessary to serve the specific module. 4.7.1.2.1 Interrupt Vector Register (IVR) Table 89. Interrupt Vector Register (IVR) Offset(66) 0x02 7 R W Note: 66. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. 0 6 0 5 4 3 IRQ 2 1 Access: User read 0 Table 90. IVR - Register Field Descriptions Field 5:0 IRQ Description Represents the highest prioritized interrupt pending. See Table 91 In case no interrupt is pending, the result will be 0. The following table is listing all MM912_634 analog die interrupt sources with the corresponding priority. Table 91. Interrupt Source Priority Interrupt Source no interrupt pending or wake-up from Stop mode LVI - Low Voltage Interrupt HTI - Voltage Regulator High Temperature Interrupt LBI - Low Battery Interrupt CH0 - TIM Channel 0 Interrupt CH1 - TIM Channel 1 Interrupt CH2 - TIM Channel 2 Interrupt CH3 - TIM Channel 3 Interrupt TOV - Timer Overflow Interrupt ERR - SCI Error Interrupt TX - SCI Transmit Interrupt RX - SCI Receive Interrupt SCI - ADC Sequence Complete Interrupt LINOT - LIN Driver Over-temperature Interrupt HSOT - High Side Over-temperature Interrupt LSOT - Low Side Over-temperature Interrupt HOT - HSUP Over-temperature Interrupt HVI - High Voltage Interrupt VROVI - Voltage Regulator Over-voltage Interrupt IRQ 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 Priority 1 (highest) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 (lowest) 4.7.2 4.7.2.1 Interrupt Sources Voltage Status Interrupt (VSI) The Voltage Status Interrupt - VSI combines the five interrupt sources of the Voltage Status Register. It is only available in the Interrupt Source Register (ISR). Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 66 Interrupts interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information. 4.7.2.2 Low Voltage Interrupt (LVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information. 4.7.2.3 Voltage Regulator High Temperature Interrupt (HTI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information. 4.7.2.4 Low Battery Interrupt (LBI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information. 4.7.2.5 TIM Channel 0 Interrupt (CH0) See Section 4.19, “Basic Timer Module - TIM (TIM16B4C). 4.7.2.6 TIM Channel 1 Interrupt (CH1) See Section 4.19, “Basic Timer Module - TIM (TIM16B4C). 4.7.2.7 TIM Channel 2 Interrupt (CH2) See Section 4.19, “Basic Timer Module - TIM (TIM16B4C). 4.7.2.8 TIM Channel 3 Interrupt (CH3) See Section 4.19, “Basic Timer Module - TIM (TIM16B4C). 4.7.2.9 TIM Timer Overflow Interrupt (TOV) See Section 4.19, “Basic Timer Module - TIM (TIM16B4C). 4.7.2.10 SCI Error Interrupt (ERR) See Section 4.16, “Serial Communication Interface (S08SCIV4). 4.7.2.11 SCI Transmit Interrupt (TX) See Section 4.16, “Serial Communication Interface (S08SCIV4). 4.7.2.12 SCI Receive Interrupt (RX) See Section 4.16, “Serial Communication Interface (S08SCIV4). 4.7.2.13 LIN Driver Over-temperature Interrupt (LINOT) Acknowledge the interrupt by reading the LIN Register - LINR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.15, “LIN Physical Layer Interface - LIN for details on the LIN Register including masking information. 4.7.2.14 High Side Over-temperature Interrupt (HSOT) Acknowledge the interrupt by reading the High Side Status Register - HSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.12, “High Side Drivers - HS for details on the High Side Status Register including masking information. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 67 Interrupts 4.7.2.15 Low Side Over-temperature Interrupt (LSOT) Acknowledge the interrupt by reading the Low Side Status Register - LSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.13, “Low Side Drivers - LSx for details on the Low Side Status Register including masking information. 4.7.2.16 HSUP Over-temperature Interrupt (HOT) Acknowledge the interrupt by reading the Hall Supply Register - HSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.11, “Hall Sensor Supply Output - HSUP for details on the Hall Supply Register including masking information. 4.7.2.17 High Voltage Interrupt (HVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information. 4.7.2.18 Voltage Regulator Over-voltage Interrupt (VROVI) Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply for details on the Voltage Status Register including masking information. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 68 Resets 4.8 Resets MCU ANALOG To protect the system during critical events, the MM912_634 analog die will drive the RESET_A pin low during the presence of the reset condition. In addition, the RESET_A pin is monitored for external reset events. To match the MCU, the RESET_A pin is based on the VDDX voltage level. After an internal reset condition has gone, the RESET_A will stay low for an additional time tRST before being released. Entering reset mode will cause all MM912_634 analog die registers to be initialized to their RESET default. The only registers with valid information are the Reset Status Register (RSR) and the Wake-up Source Register (WUS). 4.8.1 Reset Sources In the MM912_634 six reset sources exist. 4.8.1.1 POR - Analog Die Power On Reset To indicate the device power supply (VS1) was below VPOR or the MM912_634 analog die was powered up, the POR condition is set. See Section 4.4, “Modes of Operation. 4.8.1.2 LVR - Low Voltage Reset - VDD With the VDD voltage regulator output voltage falling below VLVR, the Low Voltage Reset condition becomes present. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. See Section 4.5, “Power Supply. 4.8.1.3 LVRX - Low Voltage Reset - VDDX With the VDDX voltage regulator output voltage falling below VLVRX, the Low Voltage Reset condition becomes present. See Section 4.5, “Power Supply. 4.8.1.4 WUR - Wake-up Reset While in Sleep mode, any active wake-up event will cause a MM912_634 analog die transition from Sleep to Reset Mode. To determine the wake-up source, refer to Section 4.9, “Wake-up / Cyclic Sense. 4.8.1.5 EXR - External Reset Any low level voltage at the RESET_A pin with a duration > tRSTDF will issue an External Reset event. This reset source is also active in Stop mode. 4.8.1.6 WDR - Watchdog Reset Any incorrect serving if the MM912_634 analog die Watchdog will result in a Watchdog Reset. Please refer to the Section 4.10, “Window Watchdog for details. 4.8.2 4.8.2.1 Register Definition Reset Status Register (RSR) Table 92. Reset Status Register (RSR) Offset(67) 0x15 7 R W Note: 67. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. 0 6 0 5 WDR 4 EXR 3 WUR 2 LVRX 1 LVR Access: User read 0 POR MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 69 Resets Table 93. RSR - Register Field Descriptions Field 5 - WDR 4 - EXR 3 - WUR 2 - LVRX 1 - LVR 0 - POR Description Watchdog Reset - Reset caused by an incorrect serving of the watchdog. External Reset - Reset caused by the RESET_A pin driven low externally for > tRSTDF. Wake-up Reset - Reset caused by a wake-up from Sleep mode. To determine the wake-up source, refer to Section 4.9, “Wake-up / Cyclic Sense. Low Voltage Reset VDDX - Reset caused by a low voltage condition monitored at the VDDX output. Low Voltage Reset VDD - Reset caused by a low voltage condition monitored at the VDD output.(68) Power On Reset - Supply Voltage was below VPOR. Note: 68. As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. Reading the Reset Status register will clear the information inside. Writing has no effect. LVR and LVRX are masked when POR or WUR are set. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 70 Wake-up / Cyclic Sense 4.9 Wake-up / Cyclic Sense MCU ANALOG To wake-up the MM912_634 analog die from Stop or Sleep mode, several wake-up sources are implemented. As described in Section 4.4, “Modes of Operation, a wake-up from Stop mode will result in an interrupt (D2DINT) to the MCU combined with a transition to Normal mode. A wake-up from Sleep mode will result in a transition to Reset mode. In any case, the source of the wake-up can be identified by reading the Wake-up Source Register (WSR). The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between the WSR read and MCR write. In general, there are the following seven main wake-up sources: • Wake-up by a state change of one of the Lx inputs • Wake-up by a state change of one of the Lx inputs during a cyclic sense • Wake-up due to a forced wake-up • Wake-up by the LIN module • Wake-up by D2D interface (Stop mode only) • Wake-up due to internal / external Reset (Stop mode only) • Wake-up due to loss of supply voltage (Sleep mode only) VSUP HS1 HS2 D2DINT D2DCLK D2D3 D2D2 D2D1 L3 D2D0 Cyclic Wake Up Lx – Wake Up L4 L5 D2D Wake Up Wake Up Module Forced Wake Up Cyclic Sense / Forced Wake Up Timer L0 L1 L2 LIN Wake Up LIN LIN Bus Figure 19. Wake-up Sources 4.9.1 4.9.1.1 Wake-up Sources Lx - Wake-up (Cyclic Sense Disabled) Any state digital change on a Wake-up Enabled Lx input will issue a wake-up. In order to select and activate a Wake-up Input (Lx), the Wake-up Control Register (WCR) must be configured with appropriate LxWE inputs enabled or disabled before entering low power mode. The Lx - Wake-up may be combined with the Forced Wake-up. Note: Selecting a Lx Input for wake-up will disable a selected analog input once entering low power mode. 4.9.1.2 Lx - Cyclic Sense Wake-up To reduce external power consumption during low power mode a cyclic wake-up has been implemented. Configuring the Timing Control Register (TCR) a specific cycle time can be selected to implement a periodic switching of the HS1 or HS2 output with the corresponding detection of an Lx state change. Any configuration of the HSx in the High Side Control Register (HSCR) will be ignored when entering low power mode. The Lx - Cyclic Sense Wake-up may be combined with the Forced Wake-up. In case both (forced and Lx change) events are present at the same time, the Forced Wake-up will be indicated as Wake-up source. NOTE Once Cyclic Sense is configured (CSSEL!=0), the state change is only recognized from one cyclic sense event to the next. The additional accuracy of the cyclic sense cycle by the WD clock trimming is only active during STOP mode. There is no trimmed clock available during SLEEP mode. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 71 Wake-up / Cyclic Sense 4.9.1.3 Forced Wake-up Configuring the Forced Wake-up Multiplier (FWM) in the Timing Control Register (TCR) will enable the forced wake-up based on the selected Cyclic Sense Timing (CST). Forced Wake-up can be combined with all other wake-up sources considering the timing dependencies. 4.9.1.4 LIN - Wake-up While in Low-Power mode the MM912_634 analog die monitors the activity on the LIN bus. A dominant pulse longer than tPROPWL followed by a dominant to recessive transition will cause a LIN Wake-up. This behavior protects the system from a short-to-ground bus condition. 4.9.1.5 D2D - Wake-up (Stop Mode only) Receiving a Normal mode request via the D2D interface (MODE=0, Mode Control Register (MCR)) will result in a wake-up from stop mode. As this condition is controlled by the MCU, no wake-up status bit does indicate this wake-up source. 4.9.1.6 Wake-up Due to Internal / External Reset (STOP Mode Only) While in Stop mode, a Reset due to a VDD low voltage condition or an external Reset applied on the RESET_A pin will result in a Wake-up with immediate transition to Reset mode. In this case, the LVR or EXR bits in the Reset Status Register will indicate the source of the event. 4.9.1.7 Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only) While in Sleep mode, a supply voltage VS1 < VPOR will result in a transition to Power On mode. 4.9.2 4.9.2.1 Register Definition Wake-up Control Register (WCR) Table 94. Wake-up Control Register (WCR) Offset(69) 0x12 7 R W Reset 0 CSSEL 0 6 5 L5WE 1 4 L4WE 1 3 L3WE 1 2 L2WE 1 Access: User read/write 1 L1WE 1 0 L0WE 1 Note: 69. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 95. WCR - Register Field Descriptions Field Description Cyclic Sense Select - Configures the HSx output for the cyclic sense event. Note, with no LxWE selected - only the selected HSx output will be switched periodically, no Lx state change would be detected. For all configurations, the Forced Wake-up can be activated in parallel in Section 4.9.2.2, “Timing Control Register (TCR) 7-6 CSSEL 00 - Cyclic Sense Off 01 - Cyclic Sense with periodic HS1on 10 - Cyclic Sense with periodic HS2 on 11 - Cyclic Sense with periodic HS1 and HS2 on. Wake-up Input 5 Enabled - L5 Wake-up Select Bit. 5 - L5WE 0 - L5 Wake-up Disabled 1 - L5 Wake-up Enabled Wake-up Input 4 Enabled - L4 Wake-up Select Bit. 4 - L4WE 0 - L4 Wake-up Disabled 1 - L4 Wake-up Enabled MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 72 Wake-up / Cyclic Sense Table 95. WCR - Register Field Descriptions Field Wake-up Input 3 Enabled - L3 Wake-up Select Bit. 3 - L3WE 0 - L3Wake-up Disabled 1 - L3 Wake-up Enabled Wake-up Input 2 Enabled - L2 Wake-up Select Bit. 2- L2WE 0 - L2 Wake-up Disabled 1 - L2 Wake-up Enabled Wake-up Input 1 Enabled - L1 Wake-up Select Bit. 1 - L1WE 0 - L1 Wake-up Disabled 1 - L1 Wake-up Enabled Wake-up Input 0 Enabled - L0 Wake-up Select Bit. 0 - L0WE 0 - L0 Wake-up Disabled 1 - L0 Wake-up Enabled Description 4.9.2.2 Timing Control Register (TCR) Table 96. Timing Control Register (TCR) Offset(70) 0x13 7 6 FWM 0 0 0 0 0 0 5 4 3 2 CST Access: User read/write 1 0 R W Reset 0 0 Note: 70. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 73 Wake-up / Cyclic Sense Table 97. TCR - Register Field Descriptions Field Description Forced Wake-up Multiplicator - Configures the multiplicator for the forced wake-up. The selected multiplicator (FWM!=0) will force a wake-up every FWM x CST ms. With this implementation, Forced and Cyclic wake-up can be performed in parallel with the cyclic sense period = PWMPERx Note: 89. Counter = $00 and does not count. PWMPERx >$00 >$00 $00(89) (indicates no period) $00(89) (indicates no period) XX PPOLx 1 0 1 0 1 PWMx Output Always low Always high Always high Always low Always high 4.14.5 Resets The reset state of each individual bit is listed within the Section 4.14.3, “Register Descriptions”, which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured as an up counter out of reset. • All the channels are disabled and all the counters do not count. 4.14.6 Interrupts The PWM module has no Interrupts. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 99 LIN Physical Layer Interface - LIN 4.15 LIN Physical Layer Interface - LIN MCU ANALOG The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer version 2.1 specification, and has the following features: • LIN physical layer 2.1 compliant • Slew rate selection 20 kBit, 10 kBit, and fast Mode (100 kBit) • Over-temperature Shutdown - HTI • Permanent Pull-up in Normal mode 30 k, 1.0 M in low power • Current limitation • External Rx / Tx access. See Section 4.18, “General Purpose I/O - PTB[0…2] • Slew Rate Trim Bit. See Section 4.26, “MM912_634 - Analog Die Trimming The LIN driver is a Low Side MOSFET with current limitation and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed. 4.15.1 LIN Pin The LIN pin offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. See Section 3.8, “ESD Protection and Latch-up Immunity. 4.15.2 Slew Rate Selection The slew rate can be selected for optimized operation at 10 kBit/s and 20 kBit/s as well as a fast baud rate (100 kBit) for test and programming. The slew rate can be adapted with the bits LINSR[1:0] in the LIN Register (LINR). The initial slew rate is 20 kBit/s. 4.15.3 Over-temperature Shutdown (LIN Interrupt) The output Low Side FET (transmitter) is protected against over-temperature conditions. In case of an over-temperature condition, the transmitter will be shut down and the bit LINOTC in the LIN Register (LINR) is set as long as the condition is present. If the LINOTIE bit is set in the LIN Register (LINR), an Interrupt IRQ will be generated. Acknowledge the interrupt by reading the LIN Register (LINR). To issue a new interrupt, the condition has to vanish and occur again. The transmitter is automatically re-enabled once the over-temperature condition is gone and TxD is High. 4.15.4 Low Power Mode and Wake-up Feature During Low Power mode operation the transmitter of the physical layer is disabled. The receiver is still active and able to detect Wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge, will generate a wake-up event and be reported in the Wake-up Source Register (WSR). 4.15.5 J2602 Compliance A Low Voltage Shutdown feature was implemented to allow controlled J2602 compliant LIN driver behavior under Low Voltage conditions (LVSD=0). When an under-voltage occurs on VS1 (LVI), the LIN stays in recessive mode if it was in recessive state. If it was in a dominant state, it waits until the next dominant to recessive transition, then it stays in the recessive state. When the under-voltage condition (LVI) is gone, the LIN will start operating when Tx is in a recessive state or on the next dominant to recessive transition. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 100 4.15.6 4.15.6.1 Register Definition LIN Register (LINR) Table 132. LIN Register (LINR) Offset(90) 0x18 7 6 LINOTC 5 RX 4 TX 0 3 LVSD 0 2 LINEN 0 0 1 Access: User read 0 LINSR 0 R W Reset LINOTIE 0 0 0 Note: 90. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 133. LINR - Register Field Descriptions Field 7 - LINOTIE 6 - LINOTC 5 - RX LIN - Over-temperature Interrupt Enable LIN - Over-temperature condition present. LIN driver is shut down. Reading this bit will clear the LINOT interrupt flag. LIN - Receiver (Rx) Status. 0 - LIN Bus Dominant 1 - LIN Bus Recessive LIN - Direct Transmitter Control. The inverted signal is OR 4 - TX 0 - Transmitter not controlled 1 - Transmitter Dominant LIN - Low Voltage Shutdown Disable (J2602 Compliance Control) 3 - LVSD 0 - LIN will be set to recessive state in case of VS1 under-voltage condition 1 - LIN will stay functional even with a VS1 under-voltage condition LIN Module Enable 2 - LINEN 0 - LIN Module Disabled 1 - LIN Module Enabled LIN - Slew Rate Select 00 - Normal Slew Rate (20 kBit) 1-0 - LINSR 01 - Slow Slew Rate (10.4 kBit) 10 - Fast Slew Rate (100 kBit) 11 - Normal Slew Rate (20 kBit) Description MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 101 Serial Communication Interface (S08SCIV4) 4.16 4.16.1 4.16.1.1 Serial Communication Interface (S08SCIV4) Introduction Features MCU ANALOG Features of the SCI module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Interrupt-driven or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect — Active edge on receive pin — Break detect supporting LIN • Hardware parity generation and checking • Programmable 8-bit or 9-bit character length • Receiver wake-up by idle-line or address-mark • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity 4.16.1.2 Modes of Operation See Section 4.16.3, “Functional Description,” for details concerning SCI operation in these modes: • 8 and 9-bit data modes • Loop mode • Single-wire mode 4.16.1.3 Block Diagram Figure 29 shows the transmitter portion of the SCI. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 102 Serial Communication Interface (S08SCIV4) INTERNAL BUS (WRITE-ONLY) LOOPS SCID – Tx BUFFER RSRC LOOP CONTROL STOP M START 11-BIT TRANSMIT SHIFT REGISTER TO RECEIVE DATA IN SHIFT DIRECTION LSB 1  BAUD RATE CLOCK H 8 7 6 5 4 3 2 1 0 L TO TxD TX- LOAD FROM SCID PREAMBLE (ALL 1s) T* PE PT PARITY GENERATION BREAK (ALL 0s) SCI CONTROLS TxD TE SBK TXDIR BRK13 TRANSMIT CONTROL SHIFT ENABLE TxD DIRECTION TO TxD LOGIC TDRE TIE TC TCIE Tx INTERRUPT REQUEST Figure 29. SCI Transmitter Block Diagram Figure 30 shows the receiver portion of the SCI. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 103 Serial Communication Interface (S08SCIV4) INTERNAL BUS (READ-ONLY) 16  BAUD RATE CLOCK FROM TRANSMITTER M LBKDE ALL 1s DATA RECOVERY MSB LSB 8 7 6 5 4 3 2 1 0 SHIFT DIRECTION RWU RWUID RDRF RIE IDLE ILIE LBKDIF LBKDIE RXEDGIF RXEDGIE OR ORIE FE FEIE NF NEIE PE PT PARITY CHECKING PF PEIE ERROR INTERRUPT REQUEST Rx INTERRUPT REQUEST LOOPS RSRC FROM RxD RXSINGLE-WIRE LOOP CONTROL START L STOP H 11-BIT RECEIVE SHIFT REGISTER DIVIDE BY 16 SCID – Rx BUFFER ILT WAKEUP LOGIC ACTIVE EDGE DETECT Figure 30. SCI Receiver Block Diagram MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 104 Serial Communication Interface (S08SCIV4) 4.16.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to Section 4.6, “Die to Die Interface - Target of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names. 4.16.2.1 SCI Baud Rate Registers (SCIBD (hi), SCIBD (lo)) This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting [SBR12:SBR0], first write to SCIBD (hi) to buffer the high half of the new value, and then write to SCIBD (lo). The working value in SCIBD (hi) does not change until SCIBD (lo) is written. SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled (RE or TE bits in SCIC2 are written to 1). Table 134. SCI Baud Rate Register (SCIBD (hi)) Offset(91) 0x40 7 R W Reset LBKDIE 0 6 RXEDGIE 0 5 0 4 SBR12 0 3 SBR11 0 2 SBR10 0 Access: User read/write 1 SBR9 0 0 SBR8 0 0 Note: 91. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 135. SCIBD (hi) Field Descriptions Field 7 LBKDIE 6 RXEDGIE 4:0 SBR[128] LIN Break Detect Interrupt Enable (for LBKDIF) 0 1 0 1 Hardware interrupts from LBKDIF disabled (use polling). Hardware interrupt requested when LBKDIF flag is 1. Hardware interrupts from RXEDGIF disabled (use polling). Hardware interrupt requested when RXEDGIF flag is 1. Description RxD Input Active Edge Interrupt Enable (for RXEDGIF) Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Table 137. Table 136. SCI Baud Rate Register (SCIBDL) Offset(92) 0x41 7 R W Reset SBR7 0 6 SBR6 0 5 SBR5 0 4 SBR4 0 3 SBR3 0 2 SBR2 1 Access: User read/write 1 SBR1 0 0 SBR0 0 Note: 92. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 137. SCIBDL Field Descriptions Field 7:0 SBR[7:0] Description Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Table 135. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 105 Serial Communication Interface (S08SCIV4) 4.16.2.2 SCI Control Register 1 (SCIC1) Table 138. SCI Control Register 1 (SCIC1) This read/write register is used to control various optional features of the SCI system. Offset(93) 0x42 7 6 0 5 RSRC 0 4 M 0 3 0 2 ILT 0 Access: User read/write 1 PE 0 0 PT 0 R W Reset LOOPS 0 0 0 Note: 93. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 139. SCIC1 Field Descriptions Field Description Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the transmitter output is internally connected to the receiver input. 0 Normal operation — RxD and TxD use separate pins. 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by SCI. Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter output. 0 1 4 M 0 1 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins. Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input. Normal — start + 8 data bits (LSB first) + stop. Receiver and transmitter use 9-bit data characters start + 8 data bits (LSB first) + 9th data bit + stop. 7 LOOPS 5 RSRC 9-Bit or 8-Bit Mode Select 2 ILT Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section 4.16.3.3.2.1, “Idle-line Wake-up” for more information. 0 1 Idle character bit count starts after start bit. Idle character bit count starts after stop bit. 1 PE Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 1 No hardware parity generation or checking. Parity enabled. 0 PT Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. 0 1 Even parity. Odd parity. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 106 Serial Communication Interface (S08SCIV4) 4.16.2.3 SCI Control Register 2 (SCIC2) Table 140. SCI Control Register 2 (SCIC2) This register can be read or written at any time. Offset(94) 0x43 7 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 Access: User read/write 1 RWU 0 0 SBK 0 R W Reset TIE 0 Note: 94. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 141. SCIC2 Field Descriptions Field 7 TIE 6 TCIE 5 RIE 4 LIE Transmit Interrupt Enable (for TDRE) 0 1 0 1 0 1 0 1 0 1 3 TE Hardware interrupts from TDRE disabled (use polling). Hardware interrupt requested when TDRE flag is 1. Hardware interrupts from TC disabled (use polling). Hardware interrupt requested when TC flag is 1. Hardware interrupts from RDRF disabled (use polling). Hardware interrupt requested when RDRF flag is 1. Hardware interrupts from IDLE disabled (use polling). Hardware interrupt requested when IDLE flag is 1. Transmitter off. Transmitter on. Description Transmission Complete Interrupt Enable (for TC) Receiver Interrupt Enable (for RDRF) Idle Line Interrupt Enable (for IDLE) Transmitter Enable TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress. Refer to Section 4.16.3.2.1, “Send Break and Queued Idle” for more details. When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. 0 1 Receiver off. Receiver on. 2 RE MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 107 Serial Communication Interface (S08SCIV4) Table 141. SCIC2 Field Descriptions (continued) Field Description Receiver Wake-up Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wake-up condition. The wake-up condition is either an idle line between messages (WAKE = 0, idle-line wake-up), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wake-up). Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer to Section 4.16.3.3.2, “Receiver Wake-up Operation” for more details. 0 1 Normal SCI receiver operation. SCI receiver in standby waiting for wake-up condition. 1 RWU 0 SBK Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Refer to Section 4.16.3.2.1, “Send Break and Queued Idle” for more details. 0 1 Normal transmitter operation. Queue break character(s) to be sent. 4.16.2.4 SCI Status Register 1 (SCIS1) This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to this register) are used to clear these status flags. Table 142. SCI Status Register 1 (SCIS1) Offset(95) 0x44 7 R W Reset 1 1 0 0 0 0 0 0 TDRE 6 TC 5 RDRF 4 IDLE 3 OR 2 NF Access: User read/write 1 FE 0 pF Note: 95. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 143. SCIS1 Field Descriptions Field Description Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIS1 with TDRE = 1 and then write to the SCI data register (SCID). 0 1 Transmit data register (buffer) full. Transmit data register (buffer) empty. 7 TDRE Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being transmitted. 0 6 TC 1 Transmitter active (sending data, a preamble, or a break). Transmitter idle (transmission activity complete). TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things: • Write to the SCI data register (SCID) to transmit new data • Queue a preamble by changing TE from 0 to 1 • Queue a break character by writing 1 to SBK in SCIC2 Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID). 0 1 Receive data register empty. Receive data register full. 5 RDRF MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 108 Serial Communication Interface (S08SCIV4) Table 143. SCIS1 Field Descriptions (continued) Field Description Idle Line Flag — IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if the receive line remains idle for an extended period. 0 1 No idle line detected. Idle line was detected. 4 IDLE 3 OR Receiver Overrun Flag — OR is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from SCID yet. In this case, the new character (and all associated error information) is lost because there is no room to move it into SCID. To clear OR, read SCIS1 with OR = 1 and then read the SCI data register (SCID). 0 1 No overrun. Receive overrun (new SCI data lost). 2 NF Noise Flag — The advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and then read the SCI data register (SCID). 0 1 No noise detected. Noise detected in the received character in SCID. 1 FE Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIS1 with FE = 1 and then read the SCI data register (SCID). 0 1 No framing error detected. This does not guarantee the framing is correct. Framing error. 0 PF Parity Error Flag — PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the SCI data register (SCID). 0 1 No parity error. Parity error. 4.16.2.5 SCI Status Register 2 (SCIS2) Table 144. SCI Status Register 2 (SCIS2) This register has one read-only status flag. Offset (96) 0x45 7 6 RXEDGIF 0 5 0 4 RXINV(97) 0 3 RWUID 0 2 BRK13 0 Access: User read/write 1 LBKDE 0 0 RAF R W Reset LBKDIF 0 0 0 Note: 96. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 109 Serial Communication Interface (S08SCIV4) Table 145. SCIS2 Field Descriptions Field Description LIN Break Detect Interrupt Flag — LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected. LBKDIF is cleared by writing a “1” to it. 0 1 6 RXEDGIF No LIN break character has been detected. LIN break character has been detected. 7 LBKDIF RxD Pin Active Edge Interrupt Flag — RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin occurs. RXEDGIF is cleared by writing a “1” to it. 0 1 No active edge on the receive pin has occurred. An active edge on the receive pin has occurred. Receive data not inverted Receive data inverted During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. 4 RXINV(97) 3 RWUID Receive Data Inversion — Setting this bit reverses the polarity of the received data input. 0 1 0 1 Receive Wake Up Idle Detect— RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit. 2 BRK13 Break Character Generation Length — BRK13 is used to select a longer transmitted break character length. Detection of a framing error is not affected by the state of this bit. 0 1 Break character is transmitted with length of 10 bit times (11 if M = 1) Break character is transmitted with length of 13 bit times (14 if M = 1) 1 LBKDE LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 1 Break character detection enabled. Break character detection disabled. Note: 97. Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle. When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol. 4.16.2.6 SCI Control Register 3 (SCIC3) Table 146. SCI Control Register 3 (SCIC3) Offset (98) 0x46 7 6 T8 0 5 TXDIR 0 4 TXINV(99) 0 3 ORIE 0 2 NEIE 0 Access: User read/write 1 FEIE 0 0 PEIE 0 R W Reset R8 0 Note: 98. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 110 Serial Communication Interface (S08SCIV4) Table 147. SCIC3 Field Descriptions Field 7 R8 Description Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the MSB of the buffered data in the SCID register. When reading 9-bit data, read R8 before reading SCID because reading SCID completes automatic flag clearing sequences which could allow R8 and SCID to be overwritten with new data. Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire 9-bit value is transferred to the SCI shift register after SCID is written so T8 should be written (if it needs to change from its previous value) before SCID is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time SCID is written. TxD Pin Direction in Single-wire Mode — When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 1 4 TXINV(99) 3 ORIE 2 NEIE 1 FEIE 0 PEIE 0 1 0 1 0 1 0 1 0 1 TxD pin is an input in single-wire mode. TxD pin is an output in single-wire mode. Transmit data not inverted Transmit data inverted OR interrupts disabled (use polling). Hardware interrupt requested when OR = 1. NF interrupts disabled (use polling). Hardware interrupt requested when NF = 1. FE interrupts disabled (use polling). Hardware interrupt requested when FE = 1. PF interrupts disabled (use polling). Hardware interrupt requested when PF = 1. 6 T8 5 TXDIR Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt requests. Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests. Note: 99. Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle. 4.16.2.7 SCI Data Register (SCID) This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. Table 148. SCI Data Register (SCID) Offset(100) 0x47 7 R W Reset R7 T7 0 6 R6 T6 0 5 R5 T5 0 4 R4 T4 0 3 R3 T3 0 2 R2 T2 0 Access: User read/write 1 R1 T1 0 0 R0 T0 0 Note: 100. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 111 Serial Communication Interface (S08SCIV4) 4.16.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI. 4.16.3.1 Baud Rate Generation As shown in Figure 31, the clock source for the SCI baud rate generator is the D2D clock. MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY 16 Tx BAUD RATE D2D SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 Rx SAMPLING CLOCK (16 ´ BAUD RATE) BUSCLK BAUD RATE = [SBR12:SBR0] ´ 16 Figure 31. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ±4.0 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 4.16.3.2 Transmitter Functional Description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters. The transmitter block diagram is shown in Figure 29. The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIC2. This queues a preamble character that is one full character frame of the idle state. The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the SCI data register (SCID). The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0, selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCID. If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 4.16.3.2.1 Send Break and Queued Idle The SBK control bit in SCIC2 is used to send break characters which were originally used to gain the attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 112 Serial Communication Interface (S08SCIV4) (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data bits and a framing error (FE = 1) occurs. When idle-line wake-up is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE. The length of the break character is affected by the BRK13 and M bits as shown below. Table 149. Break Character Length BRK13 0 0 1 1 M 0 1 0 1 Break Character Length 10 bit times 11 bit times 13 bit times 14 bit times 4.16.3.3 Receiver Functional Description In this section, the receiver block diagram (Figure 30) is used as a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wake-up function are explained. The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to Section •, “8 and 9-bit data modes.” For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (RDRF) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section 4.16.3.4, “Interrupts and Status Flags” for more details about flag clearing. 4.16.3.3.1 Data Sampling Technique The SCI receiver uses a 16 baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16 baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer. The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 113 Serial Communication Interface (S08SCIV4) In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 4.16.3.3.2 Receiver Wake-up Operation Receiver wake-up is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU bit is set, the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 4.16.3.3.2.1 Idle-line Wake-up When WAKE = 0, the receiver is configured for idle-line wake-up. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE flag. The receiver wakes up and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether RWU is zero or one. The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 4.16.3.3.2.2 Address-Mark Wake-up When WAKE = 1, the receiver is configured for address-mark wake-up. In this mode, RWU is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode). Address-mark wake-up allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is received and sets the RDRF flag. In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time. 4.16.3.4 Interrupts and Status Flags The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events, and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCID. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCID. The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then reading SCID. When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains idle for an extended period of time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading SCID. After IDLE has been cleared, it cannot become set again until the receiver has received at least one new character and has set RDRF. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 114 Serial Communication Interface (S08SCIV4) If the associated error was detected in the received character that caused RDRF to be set, the error flags — noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF. These flags are not set in overrun cases. If RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE, or PF condition is lost. At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled (RE = 1). 4.16.3.5 Additional SCI Functions The following sections describe additional SCI functions. 4.16.3.5.1 8- and 9-Bit Data Modes The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored in T8 in SCIC3. For the receiver, the ninth bit is held in R8 in SCIC3. For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID. If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used with address-mark wake-up so the ninth data bit can serve as the wake-up bit. In custom protocols, the ninth bit can also serve as a software-controlled marker. 4.16.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. An active edge on the receive input brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1). Note that because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module. 4.16.3.5.3 Loop Mode When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI, so it reverts to a general purpose port I/O pin. 4.16.3.5.4 Single-wire Operation When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter output and to the TxD pin. The RxD pin is not used and reverts to a general purpose port I/O pin. In single-wire mode, the TXDIR bit in SCIC3 controls the direction of serial data on the TxD pin. When TXDIR = 0, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 115 High Voltage Inputs - Lx 4.17 High Voltage Inputs - Lx MCU ANALOG Six High Voltage capable inputs are implemented with the following features: • Digital Input Capable • Analog Input Capable with selectable voltage divider. • Wake-up Capable during Low Power mode. See Section 4.9, “Wake-up / Cyclic Sense. When used as analog inputs to sense voltages outside the module a series resistor must be used on the used input. When a Lx input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. When a Lx input is selected in the analog multiplexer, it will be disconnected in low power mode if configured as Wake-up input. Unused Lx pins are recommended to be connected to GND to improve EMC behavior. 4.17.1 4.17.1.1 Register Definition Lx Status Register (LXR) Table 150. Lx Status Register (LXR) Offset (101) 0x08 7 6 0 5 L5 4 L4 3 L3 2 L2 1 L1 Access: User read 0 L0 R W 0 Note: 101. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 151. LXR - Register Field Descriptions Field L[5-0] Description Lx Status Register - Current Digital State of the Lx Input 4.17.1.2 Lx Control Register (LXCR) Table 152. Lx Control Register (LXCR) Offset(102) 0x09 7 6 0 5 L5DS 0 4 L4DS 0 3 L3DS 0 2 L2DS 0 Access: User read/write 1 L1DS 0 0 L0DS 0 R W Reset 0 0 0 Note: 102. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 153. LXCR - Register Field Descriptions Field 5-0 L[5-0]DS Analog Input Divider Ratio Selection - Lx 0 - 2 (typ.) 1 - 7.2 (typ) Description MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 116 General Purpose I/O - PTB[0…2] 4.18 General Purpose I/O - PTB[0…2] MCU ANALOG The three multipurpose I/O pins can be configured to operate as documented in the table below. Table 154. General purpose I/O - Operating modes Priority 1 (H) 2 3 4 (L) 2.5 V Analog Input Timer Input Capture / Output Compare LIN / SCI - Rx / Tx (PTB0…1) or PWM (PTB2) 5.0 V Input Output Function PTB2 AD2 TIMCH2 PWM PTB2 PTB1 AD1 TIMCH1 Tx PTB1 PTB0 AD0 TIMCH0 Rx PTB0 Chp/Pg 4.20/133 4.19/120 4.15/100 current The alternate function of PTB2, PTB1 and PTB0 can be configured by selecting the function in the corresponding module (e.g. TIMER). The selection with the highest priority will take effect when more than one function is selected. 4.18.1 Digital I/O Functionality All three pins act as standard digital Inputs / Outputs with selectable pull-up resistor. 4.18.2 Alternative SCI / LIN Functionality For alternative serial configuration and for debug and certification purpose, PTB0 and PTB1 can be configured to connect to the internal LIN and / or SCI signals (RxD and TxD). Figure 32 shows the 4 available configurations. PTB0/AD0/TIM0CH0/Rx 4 Channel Timer Module TIM0CH3 PTB0/AD0/TIM0CH0/Rx 4 Channel Timer Module TIM0CH3 PTB1/AD1/TIM0CH1/Tx PTB2/AD2/TIM0CH2/PWM PTB1/AD1/TIM0CH1/Tx PTB2/AD2/TIM0CH2/PWM Rx Serial Communication Interface (SCI) Tx Rx Tx LIN Physical Layer Interface LIN Rx Serial Communication Interface (SCI) Tx Rx Tx LIN Physical Layer Interface LIN Mode 0 (default) Mode 2 (external LIN) PTB0/AD0/TIM0CH0/Rx 4 Channel Timer Module TIM0CH3 PTB0/AD0/TIM0CH0/Rx 4 Channel Timer Module TIM0CH3 PTB1/AD1/TIM0CH1/Tx PTB2/AD2/TIM0CH2/PWM PTB1/AD1/TIM0CH1/Tx PTB2/AD2/TIM0CH2/PWM Rx Serial Communication Interface (SCI) Tx Rx Tx LIN Physical Layer Interface LIN Rx Serial Communication Interface (SCI) Tx Rx Tx LIN Physical Layer Interface LIN Mode 1 (external SCI) Mode 3 (observe) Figure 32. Alternative SCI / LIN Functionality 4.18.3 Alternative PWM Functionality As an alternative routing for the PWM channel (0 or 1) output, the PortB 2 (PTB2) can be configured to output one of the two PWM channels defined in the Section 4.14, “PWM Control Module (PWM8B2C). The selection and output enable can be configured in the Port B Configuration Register 2 (PTBC2). MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 117 General Purpose I/O - PTB[0…2] 4.18.4 4.18.4.1 Register definition Port B Configuration Register 1 (PTBC1) Table 155. Port B Configuration Register 1 (PTBC1) Offset(103) 0x20 7 6 PUEB2 0 5 PUEB1 0 4 PUEB0 0 3 0 2 DDRB2 0 Access: User read/write 1 DDRB1 0 0 DDRB0 0 R W Reset 0 0 0 Note: 103. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 156. PTBC1 - Register Field Descriptions Field 6-4 PUEB[2-0] 2-0 DDRB[2-0] Pull-up Enable Port B[2…0] 0 - Pull-up disabled on PTBx pin. 1- Pull-up enabled on PTBx pin. Data Direction Port B[2…0] 0 - PTBx configured as input. 1 - PTBx configured as output. Description NOTE The pull-up resistor is not active once the port is configured as an output. 4.18.4.2 Port B Configuration Register 2 (PTBC2) Table 157. Port B Configuration Register 2 (PTBC2) Offset (104) 0x21 7 6 0 5 0 4 0 3 PWMCS 0 2 PWMEN 0 Access: User read/write 1 SERMOD 0 0 0 R W Reset 0 0 0 0 0 Note: 104. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 118 General Purpose I/O - PTB[0…2] Table 158. PTBC2 - Register Field Descriptions Field 3 PWMCS 2 PWMEN Description PWM Channel Select PTB2. See Section 4.14, “PWM Control Module (PWM8B2C). 0 - PWM Channel 0 selected as PWM Channel for PTB2 1 - PWM Channel 1 selected as PWM Channel for PTB2 PWM Enable for PTB2. See Section 4.14, “PWM Control Module (PWM8B2C). 0 - PWM disabled on PTB2 1 - PWM enabled on PTB2 (Channel as selected with PWMCS) Serial Mode Select for PTB0 and PTB1. See Figure 32 for details. 00 - Mode 0, SCI internally connected the LIN Physical Layer Interface. PTB0 and PTB1 are Digital I/Os 1-0 SERMOD 01 - Mode 1, SCI connected to PTB0 and PTB1 (external SCI mode) 10 - Mode 2, LIN Physical Layer Interface connected to PTB0 and PTB1 (external LIN mode) 11 - Mode 3, SCI internally connected the LIN Physical Layer Interface and PTB0 and PTB1 are connected both as outputs (Observe mode) 4.18.4.3 Port B Data Register (PTB) Table 159. Port B Data Register (PTB) Offset(105) 0x22 7 R W Reset 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 PTB2 0 Access: User read/write 1 PTB1 0 0 PTB0 0 Note: 105. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 160. PTB - Register Field Descriptions Field 2-0 PTB[2-0] Description Port B general purpose input/output data — Data Register If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and synchronized pin input state is read. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 119 Basic Timer Module - TIM (TIM16B4C) 4.19 4.19.1 4.19.1.1 Basic Timer Module - TIM (TIM16B4C) Introduction Overview MCU ANALOG The basic timer consists of a 16-bit, software-programmable counter driven by a seven-stage programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer contains 4 complete input capture/output compare channels [IOC 3:2]. The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays. A full access for the counter registers or the input capture/output compare registers should take place in 16bit word access. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 4.19.1.2 Features The TIM16B4C includes these distinctive features: • Four input capture/output compare channels. • Clock prescaler • 16-bit counter 4.19.1.3 Modes of Operation The TIM16B4C is only active during Normal mode. 4.19.1.4 Block Diagram D2D Clock Prescaler Channel 0 Input capture Output compare Channel 1 Input capture Output compare Channel 2 Input capture Output compare IOC0 Timer overflow interrupt 16-bit Counter IOC1 Timer channel 0 interrupt Registers Timer channel 3 interrupt IOC2 Channel 3 Input capture Output compare IOC3 Figure 33. Timer Block Diagram For more information see the respective functional descriptions see Section 4.19.4, “Functional Description of this chapter. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 120 Basic Timer Module - TIM (TIM16B4C) 4.19.2 4.19.2.1 Signal Description Overview The TIM16B4C module is internally connected to the PTB (IOC0, IOC1, IOC2) and to the Rx signal as specified in Section 4.18, “General Purpose I/O - PTB[0…2] (IOC3). 4.19.2.2 4.19.2.2.1 Detailed Signal Descriptions IOC3 – Input Capture and Output Compare Channel 3 This pin serves as input capture or output compare for channel 3 and is internally connected to the Rx signal as specified in Section 4.18.2, “Alternative SCI / LIN Functionality. NOTE Since the Rx signal is only available as an input, using the output compare feature for this channel would have no effect. 4.19.2.2.2 IOC2 – Input Capture and Output Compare Channel 2 This pin serves as an input capture or output compare for channel 2 and can be routed to the PTB2 general purpose I/O. 4.19.2.2.3 IOC1 – Input Capture and Output Compare Channel 1 This pin serves as an input capture or output compare for channel 1 and can be routed to the PTB1 general purpose I/O. 4.19.2.2.4 IOC0 – Input Capture and Output Compare Channel 0 NOTE For the description of interrupts see Section 4.19.6, “Interrupts. This pin serves as an input capture or output compare for channel 0 and can be routed to the PTB0 general purpose I/O. 4.19.3 4.19.3.1 Memory Map and Registers Overview This section provides a detailed description of all memory and registers. 4.19.3.2 Module Memory Map Table 161. Module Memory Map The memory map for the TIM16B4C module is given below in Table 161. Offset(106) 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC Use Timer Input Capture/Output Compare Select (TIOS) Timer Compare Force Register (CFORC) Output Compare 3 Mask Register (OC3M) Output Compare 3 Data Register (OC3D) Timer Count Register (TCNT(hi)) Timer Count Register (TCNT(lo)) Timer System Control Register 1 (TSCR1) Timer Toggle Overflow Register (TTOV) Timer Control Register 1 (TCTL1) Timer Control Register 2 (TCTL2) Timer Interrupt Enable Register (TIE) Timer System Control Register 2 (TSCR2) Main Timer Interrupt Flag 1 (TFLG1) Access Read/Write Read/Write(107) Read/Write Read/Write Read/Write(108) Read/Write(107) Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 121 Basic Timer Module - TIM (TIM16B4C) Table 161. Module Memory Map Offset (106) Use Main Timer Interrupt Flag 2 (TFLG2) Timer Input Capture/Output Compare Register 0 (TC0(hi)) Timer Input Capture/Output Compare Register 0 (TC0(lo)) Timer Input Capture/Output Compare Register 1 (TC1(hi)) Timer Input Capture/Output Compare Register 1 (TC1(lo)) Timer Input Capture/Output Compare Register 2 (TC2(hi)) Timer Input Capture/Output Compare Register 2 (TC2(lo)) Timer Input Capture/Output Compare Register 3 (TC3(hi)) Access Read/Write Read/Write(109) Read/Write(108) Read/Write(108) Read/Write(108) Read/Write(108) Read/Write(108) Read/Write(108) 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 Note: 106. 107. 108. 109. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Always read $00. Only writable in special modes. (Refer to SOC Guide for different modes). Write to these registers have no meaning or effect during input capture. 4.19.3.3 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. 4.19.3.3.1 Timer Input Capture/Output Compare Select (TIOS) Table 162. Timer Input Capture/Output Compare Select (TIOS) Offset (110) 0xC0 7 6 0 5 0 4 0 3 IOS3 0 2 IOS2 0 Access: User read/write 1 IOS1 0 0 IOS0 0 R W Reset 0 0 0 0 0 Note: 110. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 163. TIOS - Register Field Descriptions Field 3-0 IOS[3-0] Description Input Capture or Output Compare Channel Configuration 0 - The corresponding channel acts as an input capture. 1 - The corresponding channel acts as an output compare. 4.19.3.3.2 Timer Compare Force Register (CFORC) Table 164. Timer Compare Force Register (CFORC) Offset (111) 0xC1 7 6 0 5 0 4 0 3 0 FOC3 0 0 0 0 0 2 0 FOC2 0 Access: User read/write 1 0 FOC1 0 0 0 FOC0 0 R W Reset 0 Note: 111. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 122 Basic Timer Module - TIM (TIM16B4C) Table 165. CFORC - Register Field Descriptions Field 3-0 FOC[3-0] Force Output Compare Action for Channel 3-0 0 - Force Output Compare Action disabled. Input Capture or Output Compare Channel Configuration 1 - Force Output Compare Action enabled Description A write to this register with the corresponding (FOC 3:0) data bit(s) set causes the action programmed for output compare on channel “n” to occur immediately.The action taken is the same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not get set. NOTE A successful channel 3 output compare overrides any channel 2:0 compares. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag will not get set. 4.19.3.3.3 Output Compare 3 Mask Register (OC3M) Table 166. Output Compare 3 Mask Register (OC3M) Offset(112) 0xC2 7 R W Reset 0 0 0 0 0 6 0 5 0 4 0 3 OC3M3 0 2 OC3M2 0 Access: User read/write 1 OC3M1 0 0 OC3M0 0 Note: 112. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 167. OC3M - Register Field Descriptions Field 3-0 OC3M[3-0] Output Compare 3 Mask "n" Channel bit 0 - Does not set the corresponding port to be an output port 1 - Sets the corresponding port to be an output port when this corresponding TIOS bit is set to be an output compare Description Setting the OC3Mn (n ranges from 0 to 2) will set the corresponding port to be an output port when the corresponding TIOSn (n ranges from 0 to 2) bit is set to be an output compare. NOTE A successful channel 3 output compare overrides any channel 2:0 compares. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit. 4.19.3.3.4 Output Compare 3 Data Register (OC3D) Table 168. Output Compare 3 Data Register (OC3D) Offset (113) 0xC3 7 6 0 5 0 4 0 3 OC3D3 2 OC3D2 Access: User read/write 1 OC3D1 0 OC3D0 R W Reset 0 0 0 0 0 0 0 0 0 Note: 113. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 123 Basic Timer Module - TIM (TIM16B4C) Table 169. OC3D - Register Field Descriptions Field 3-0 OC3D[3-0] Output Compare 3 Data for Channel "n" Description NOTE A channel 3 output compare will cause bits in the output compare 3 data register to transfer to the timer port data register if the corresponding output compare 3 mask register bits are set. 4.19.3.3.5 Timer Count Register (TCNT) Table 170. Timer Count Register (TCNT) Offset(114) 0xC4, 0xC5 15 R W Reset tcnt15 0 7 R W Reset tcnt7 0 14 tcnt14 0 6 tcnt6 0 13 tcnt13 0 5 tcnt5 0 12 tcnt12 0 4 tcnt4 0 11 tcnt11 0 3 tcnt3 0 Access: User read(anytime)/write (special mode) 10 tcnt10 0 2 tcnt2 0 9 tcnt9 0 1 tcnt1 0 8 tcnt8 0 0 tcnt0 0 Note: 114. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 171. TCNT - Register Field Descriptions Field 15-0 tcnt[15-0] 16 Bit Timer Count Register Description NOTE The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. The period of the first count after a write to the TCNT registers may be a different length because the write is not synchronized with the prescaler clock. 4.19.3.3.6 Timer System Control Register 1 (TSCR1) Table 172. Timer System Control Register 1 (TSCR1) Offset(115) 0xC6 7 R W Reset TEN 0 6 0 5 0 4 TFFCA 0 3 0 2 0 Access: User read/write 1 0 0 0 0 0 0 0 0 0 Note: 115. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 124 Basic Timer Module - TIM (TIM16B4C) Table 173. TSCR1 - Register Field Descriptions Field 7 TEN Timer Enable 1 = Enables the timer. 0 = Disables the timer. (Used for reducing power consumption). Timer Fast Flag Clear All 4 TFFCA 1 = For TFLG1 register, a read from an input capture or a write to the output compare channel [TC 3:0] causes the corresponding channel flag, CnF, to be cleared.For TFLG2 register, any access to the TCNT register clears the TOF flag. Any access to the PACNT registers clears the PAOVF and PAIF bits in the PAFLG register. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. 0 = Allows the timer flag clearing. Description 4.19.3.3.7 Timer Toggle On Overflow Register 1 (TTOV) Table 174. Timer Toggle On Overflow Register 1 (TTOV) Offset(116) 0xC7 7 R W Reset 0 0 0 0 0 6 0 5 0 4 0 3 TOV3 0 2 TOV2 0 Access: User read/write 1 TOV1 0 0 TOV0 0 Note: 116. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 175. TTOV - Register Field Descriptions Field 3-0 TOV[3-0] Toggle On Overflow Bits 1 = Toggle output compare pin on overflow feature enabled. 0 = Toggle output compare pin on overflow feature disabled. Description NOTE TOVn toggles output compare pin on overflow. This feature only takes effect when the corresponding channel is configured for an output compare mode. When set, an overflow toggle on the output compare pin takes precedence over forced output compare events. 4.19.3.3.8 Timer Control Register 1 (TCTL1) Table 176. Timer Control Register 1 (TCTL1) Offset(117) 0xC8 7 R W Reset OM3 0 6 OL3 0 5 OM2 0 4 OL2 0 3 OM1 0 2 OL1 0 Access: User read/write 1 OM0 0 0 OL0 0 Note: 117. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 125 Basic Timer Module - TIM (TIM16B4C) Table 177. TCTL1 - Register Field Descriptions Field 7,5,3,1 OMn 6,4,2,0 OLn Output Level bit Output Mode bit Description NOTE These four pairs of control bits are encoded to specify the output action to be taken as a result of a successful Output Compare on "n" channel. When either OMn or OLn, the pin associated with the corresponding channel becomes an output tied to its IOC. To enable output action by the OMn and OLn bits on a timer port, the corresponding bit in OC3M should be cleared. Table 178. Compare Result Output Action OMn 0 0 1 1 OLn 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line to zero Set OCn output line to one 4.19.3.3.9 Timer Control Register 2 (TCTL2) Table 179. Timer Control Register 2 (TCTL2) Offset(118) 0xC9 7 6 EDG3A 0 5 EDG2B 0 4 EDG2A 0 3 EDG1B 0 2 EDG1A 0 Access: User read/write 1 EDG0B 0 0 EDG0A 0 R W Reset EDG3B 0 Note: 118. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 180. TCTL2 - Register Field Descriptions Field EDGnB,EDGnA Input Capture Edge Control Description These four pairs of control bits configure the input capture edge detector circuits. Table 181. Edge Detector Circuit Configuration EDGnB 0 0 1 1 EDGnA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 126 Basic Timer Module - TIM (TIM16B4C) 4.19.3.3.10 Timer Interrupt Enable Register (TIE) Table 182. Timer Interrupt Enable Register (TIE) Offset(119) 0xCA 7 R W Reset 0 0 0 0 0 6 0 5 0 4 0 3 C3I 0 2 C2I 0 Access: User read/write 1 C1I 0 0 C0I 0 Note: 119. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 183. TIE - Register Field Descriptions Field 3-0 C[3-0]I Input Capture/Output Compare Interrupt Enable. 1 = Enables corresponding Interrupt flag (CnF of TFLG1 register) to cause a hardware interrupt 0 = Disables corresponding Interrupt flag (CnF of TFLG1 register) from causing a hardware interrupt Description 4.19.3.3.11 Timer System Control Register 2 (TSCR2) Table 184. Timer System Control Register 2 (TSCR2) Offset(120) 0xCB 7 6 0 5 0 4 0 3 TCRE 0 2 PR2 0 Access: User read/write 1 PR1 0 0 PR0 0 R W Reset TOI 0 0 0 0 Note: 120. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 185. TIE - Register Field Descriptions Field 7 TOI 3 TCRE 3-0 PR[2:0] Timer Overflow Interrupt Enable 1 = Hardware interrupt requested when TOF flag set in TFLG2 register. 0 = Hardware Interrupt request inhibited. TCRE — Timer Counter Reset Enable 1 = Enables Timer Counter reset by a successful output compare on channel 3 0 = Inhibits Timer Counter reset and counter continues to run. Timer Prescaler Select These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 186. Description NOTE This mode of operation is similar to an up-counting modulus counter. If register TC3 = $0000 and TCRE = 1, the timer counter register (TCNT) will stay at $0000 continuously. If register TC3 = $FFFF and TCRE = 1, TOF will not be set when the timer counter register (TCNT) is reset from $FFFF to $0000. The newly selected prescale factor will not take effect until the next synchronized edge, where all prescale counter stages equal zero. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 127 Basic Timer Module - TIM (TIM16B4C) Table 186. Timer Clock Selection PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Timer Clock D2D Clock / 1 D2D Clock / 2 D2D Clock / 4 D2D Clock / 8 D2D Clock / 16 D2D Clock / 32 D2D Clock / 64 D2D Clock / 128 4.19.3.3.12 Main Timer Interrupt Flag 1 (TFLG1) Table 187. Main Timer Interrupt Flag 1 (TFLG1) Offset(121) 0xCC 7 R W Reset 0 0 0 0 0 6 0 5 0 4 0 3 C3F 0 2 C2F 0 Access: User read/write 1 C1F 0 0 C0F 0 Note: 121. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 188. TFLG1 - Register Field Descriptions Field 3-0 C[3:0]F Input Capture/Output Compare Channel Flag. 1 = Input Capture or Output Compare event occurred 0 = No event (Input Capture or Output Compare event) occurred. Description NOTE These flags are set when an input capture or output compare event occurs. Flag set on a particular channel is cleared by writing a one to that corresponding CnF bit. Writing a zero to CnF bit has no effect on its status. When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel will cause the corresponding channel flag CnF to be cleared. 4.19.3.3.13 Main Timer Interrupt Flag 2 (TFLG2) Table 189. Main Timer Interrupt Flag 2 (TFLG2) Offset (112) 0xCD 7 6 0 5 0 4 0 3 0 2 0 Access: User read/write 1 0 0 0 R W Reset TOF 0 0 0 0 0 0 0 0 Note: 122. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 128 Basic Timer Module - TIM (TIM16B4C) Table 190. TFLG2 - Register Field Descriptions Field Timer Overflow Flag 7 TOF 1 = Indicates that an Interrupt has occurred (Set when 16-bit free-running timer counter overflows from $FFFF to $0000) 0 = Flag indicates an Interrupt has not occurred. Description NOTE The TFLG2 register indicates when an interrupt has occurred. Writing a one to the TOF bit will clear it. Any access to TCNT will clear TOF bit of TFLG2 register if the TFFCA bit in TSCR register is set. 4.19.3.3.14 Timer Input Capture/Output Compare Registers (TC3 - TC0) Table 191. Timer Input Capture/Output Compare Register 0 (TC0) Offset(123) 0xCE, 0xCF 15 R W Reset tc0_15 0 7 R W Reset tc0_7 0 14 tc0_14 0 6 tc0_6 0 13 tc0_13 0 5 tc0_5 0 12 tc0_12 0 4 tc0_4 0 11 tc0_11 0 3 tc0_3 0 Access: User read(anytime)/write (special mode) 10 tc0_10 0 2 tc0_2 0 9 tc0_9 0 1 tc0_1 0 8 tc0_8 0 0 tc0_0 0 Note: 123. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 192. Timer Input Capture/Output Compare Register 1(TC1) Offset (124) 0xD0, 0xD1 15 14 tc1_14 0 6 tc1_6 0 13 tc1_13 0 5 tc1_5 0 12 tc1_12 0 4 tc1_4 0 11 tc1_11 0 3 tc1_3 0 Access: User read(anytime)/write (special mode) 10 tc1_10 0 2 tc1_2 0 9 tc1_9 0 1 tc1_1 0 8 tc1_8 0 0 tc1_0 0 R W Reset tc1_15 0 7 R W Reset tc1_7 0 Note: 124. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 129 Basic Timer Module - TIM (TIM16B4C) Table 193. Timer Input Capture/Output Compare Register 2(TC2) Offset(125) 0xD2, 0xD3 15 R W Reset tc2_15 0 7 R W Reset tc2_7 0 14 tc2_14 0 6 tc2_6 0 13 tc2_13 0 5 tc2_5 0 12 tc2_12 0 4 tc2_4 0 11 tc2_11 0 3 tc2_3 0 Access: User read(anytime)/write (special mode) 10 tc2_10 0 2 tc2_2 0 9 tc2_9 0 1 tc2_1 0 8 tc2_8 0 0 tc2_0 0 Note: 125. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 194. Timer Input Capture/Output Compare Register 3(TC3) Offset(126) 0xD4, 0xD5 15 R W Reset tc3_15 0 7 R W Reset tc3_7 0 14 tc3_14 0 6 tc3_6 0 13 tc3_13 0 5 tc3_5 0 12 tc3_12 0 4 tc3_4 0 11 tc3_11 0 3 tc3_3 0 Access: User read(anytime)/write (special mode) 10 tc3_10 0 2 tc3_2 0 9 tc3_9 0 1 tc3_1 0 8 tc3_8 0 0 tc3_0 0 Note: 126. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 195. TCn - Register Field Descriptions Field 15-0 tcn[15-0] 16 Timer Input Capture/Output Compare Registers Description NOTE TRead anytime. Write anytime for output compare function. Writes to these registers have no effect during input capture. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 4.19.4 4.19.4.1 Functional Description General This section provides a complete functional description of the timer TIM16B4C block. Refer to the detailed timer block diagram in Figure 34 as necessary. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 130 Basic Timer Module - TIM (TIM16B4C) D2D Clock PR[2:1:0] channel 3 output compare TCRE CxI CxF CLEAR COUNTER TOF TE CHANNEL 0 TOI PRESCALER TCNT(hi):TCNT(lo) 16-BIT COUNTER INTERRUPT LOGIC TOF 16-BIT COMPARATOR TC0 EDG0A EDG0B C0F OM:OL0 EDGE DETECT TOV0 C0F CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0 COMPARE IOC0 PIN IOC0 CHANNEL3 16-BIT COMPARATOR TC3 EDG3A EDG3B EDGE DETECT C3F OM:OL3 TOV3 C3F CH.3 CAPTURE IOC3 PIN PA INPUT LOGIC CH.3 COMPARE IOC3 PIN IOC3 Figure 34. Detailed Timer Block Diagram 4.19.4.2 Prescaler The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64, or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in the timer system control register 2 (TSCR2). 4.19.4.3 Input Capture Clearing the I/O (input/output) select bit, IOSn, configures channel n as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCn. The minimum pulse width for the input capture input is greater than two bus clocks. An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests. 4.19.4.4 Output Compare Setting the I/O select bit, IOSn, configures channel n as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt requests. The output mode and level bits, OMn and OLn, select set, clear, toggle on output compare. Clearing both OMn and OLn disconnects the pin from the output logic. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 131 Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output compare does not set the channel flag. A successful output compare on channel 3 overrides output compares on all other output compare channels. The output compare 3 mask register masks the bits in the output compare 3 data register. The timer counter reset enable bit, TCRE, enables channel 3 output compares to reset the timer counter. A channel 3 output compare can reset the timer counter even if the IOC3 pin is being used as the pulse accumulator input. Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. 4.19.5 4.19.5.1 Resets General The reset state of each individual bit is listed within the Register Description section 4.19.3, “Memory Map and Registers“, which details the registers and their bit-fields. 4.19.6 4.19.6.1 Interrupts General This section describes interrupts originated by the TIM16B4C block. Table 196 lists the interrupts generated by the TIM16B4C to communicate with the MCU. Table 196. TIM16B4C Interrupts Interrupt C[3:0]F TOF Offset Vector Priority Source Timer Channel 3-0 Timer Overflow Description Active high timer channel interrupts 3-0 Timer Overflow interrupt 4.19.6.2 Description of Interrupt Operation The TIM16B4C uses a total of 5 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent. More information on interrupt vector offsets and interrupt numbers can be found in the Section 4.7, “Interrupts 4.19.6.2.1 Channel [3:0] Interrupt These active high outputs are asserted by the module to request a timer channel 3–0 interrupt, following an input capture or output compare event on these channels [3-0]. For the interrupt to be asserted on a specific channel, the enable, CnI bit of TIE register should be set. These interrupts are serviced by the system controller. 4.19.6.2.2 Timer Overflow Interrupt (TOF) This active high output will be asserted by the module to request a timer overflow interrupt, following the timer counter overflow when the overflow enable bit (TOI) bit of TFLG2 register is set. This interrupt is serviced by the system controller. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 132 Analog Digital Converter - ADC 4.20 4.20.1 4.20.1.1 Analog Digital Converter - ADC Introduction Overview MCU ANALOG In order to sample the MM912_634 analog die analog sources, a 10-bit resolution successive approximation Analog to Digital Converter has been implemented. Controlled by the A/D Control Logic (ADC Wrapper), the Analog Digital Converter allows fast and high precision conversions. D2DCLK A/D Control Logic (ADC Wrapper) STARTCONV, CLKA2D, SAMPLEA2D_N Figure 35. Analog Digital Converter Block Diagram 4.20.1.2 • • • • • • • • Features 10-bit resolution 13 µs (typ.), 10-bit Single Sample + Conversion Time External ADC2p5 pin with over-current protection to filter the analog reference voltage Total Error (TE) of ± 5 LSB without offset calibration active Integrated selectable offset compensation 14 + 1 analog channels (AD0…8; ISENSE, TSENSE and VSENSE, VS1SENSE, BANDGAP, plus calibration channel) Sequence- and Continuous Conversion Mode with IRQ for Sequence Complete indication Dedicated Result register for each channel 4.20.2 Modes of Operation The Analog Digital Converter Module is active only in normal mode; it is disabled in Sleep and Stop mode. 4.20.3 External Signal Description This section lists and describes the signals that do connect off-chip. Table 197 shows all the pins and their functions that are controlled by the Analog Digital Converter Module. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor AD_REF (ADC2p5, AGND) Analog Multiplexer A DATAA2D Data Registers D 133 Analog Digital Converter - ADC Table 197. ADC - Pin Functions and Priorities Pin Name AGND ADC2p5 Pin Function & Priority Analog Ground Analog Regulator I/O Analog Ground Connection Analog Digital Converter Regulator Filter Terminal. A capacitor CADC2p5 is required for operation. Description Pin Function after Reset - 4.20.4 4.20.4.1 Memory Map and Register Definition Module Memory Map Table 198 shows the register map of the Analog Digital Converter Module. All Register addresses given are referenced to the D2D interface offset. Table 198. Analog Digital Converter Module - Memory Map Register / Offset(127) 0x80 ACR 0x81 ASR 0x82 ACCR (hi) 0x83 ACCR (lo) 0x84 R W R W R W R W R CH15 CH14 0 CH12 CH11 CH10 CH9 CH8 Bit 7 6 5 4 3 0 2 1 Bit 0 SCIE SCF CCE 2p5CLF OCE 0 ADCRST 0 PS2 CCNT2 PS1 CCNT1 PS0 CCNT0 CCNT3 CH7 CC15 CH6 CC14 CH5 0 CH4 CC12 CH3 CC11 CH2 CC10 CH1 CC9 CH0 CC8 ACCSR (hi) W 0x85 R CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 ACCSR (lo) W 0x86 ADR0 (hi) 0x87 ADR0 (lo) 0x88 ADR1 (hi) 0x89 ADR1 (lo) 0x8A ADR2 (hi) 0x8B ADR2 (lo) 0x8C ADR3 (hi) 0x8D ADR3 (lo) 0x8E ADR4 (hi) R W R W R W R W R W R W R W R W R W ADR4[9:2] ADR3[1:0] ADR3[9:2] ADR2[1:0] ADR2[9:2] ADR1[1:0] ADR1[9:2] ADR0[1:0] ADR0[9:2] MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 134 Table 198. Analog Digital Converter Module - Memory Map Register / Offset(127) 0x8F ADR4 (lo) 0x90 ADR5 (hi) 0x91 ADR5 (lo) 0x92 ADR6 (hi) 0x93 ADR6 (lo) 0x94 ADR7 (hi) 0x95 ADR7 (lo) 0x96 ADR8 (hi) 0x97 ADR8 (lo) 0x98 ADR9 (hi) 0x99 ADR9 (lo) 0x9A R W R W R W R W R W R W R W R W R W R W R W R ADR10[9:2] ADR9[1:0] ADR9[9:2] ADR8[1:0] ADR8[9:2] ADR7[1:0] ADR7[9:2] ADR6[1:0] ADR6[9:2] ADR5[1:0] ADR5[9:2] Bit 7 ADR4[1:0] 6 5 4 3 2 1 Bit 0 ADR10 (hi) W 0x9B R ADR10[1:0] ADR10 (lo) W 0x9C R ADR11[9:2] ADR11 (hi) W 0x9D R ADR11[1:0] ADR11 (lo) W 0x9E R ADR12[9:2] ADR12 (hi) W 0x9F R ADR12[1:0] ADR12 (lo) W 0xA0 Reserved 0xA1 Reserved 0xA2 R W R W R ADR14[9:2] ADR14 (hi) W 0xA3 R ADR14[1:0] ADR14 (lo) W MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 135 Table 198. Analog Digital Converter Module - Memory Map Register / Offset(127) 0xA4 R Bit 7 6 5 4 ADR15[9:2] 3 2 1 Bit 0 ADR15 (hi) W 0xA5 R ADR15[1:0] ADR15 (lo) W Note: 127. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. 4.20.4.2 4.20.4.2.1 Register Definition ADC Config Register (ACR) Table 199. ADC Config Register (ACR) Offset(128) 0x80 7 6 CCE 0 5 OCE 0 4 ADCRST 0 3 0 2 PS2 0 Access: User read/write 1 PS1 0 0 PS0 0 R W Reset SCIE 0 0 Note: 128. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 200. ACR - Register Field Descriptions Field Sequence Complete Interrupt Enable 7 - SCIE 0 - Sequence Complete Interrupt Disabled 1 - Sequence Complete Interrupt Enabled Continuous Conversion Enable 6 - CCE 0 - Continuous Conversion Disabled 1 - Continuous Conversion Enabled Offset Compensation Enable 5 - OCE 0 - Offset Compensation Disabled 1 - Offset Compensation Enabled. This feature requires the CH15 bit in the ADC Conversion Control Register (ACCR) to be set for all conversions Analog Digital Converter RESET 4 - ADCRST 0 - Analog Digital Converter in Normal Operation 1 - Analog Digital Converter in Reset Mode. All ADC registers will reset to initial values. The bit has to be cleared to allow ADC operation ADC Clock Prescaler Select (D2DCLK to ADCCLK divider) 000 - 10 001 - 8 2-0 PS2…0 010 - 6 011 - 4 100 - 2 101 - 1 110 - 1 111 - 1 Description MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 136 NOTE ADCRST is strongly recommended to be set during D2D clock frequency changes. 4.20.4.2.2 ADC Status Register (ASR) Table 201. ADC Status Register (ASR) Offset(129) 0x81 7 R W Reset 0 0 0 0 1 1 1 1 SCF 6 2p5CLF 5 0 4 0 3 CCNT3 2 CCNT2 Access: User read/write 1 CCNT1 0 CCNT0 Note: 129. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 202. ACR - Register Field Descriptions Field 7 - SCF 6 - 2p5CLF 3-0 CCNT3…0 Description Sequence Complete Flag. Reading the ADC Status Register (ASR) will clear the Flag. ADC Reference Voltage Current Limitation Flag Conversion Counter Status. The content of CCNT reflects the current channel in conversion and the conversion of CCNT-1 being complete. The conversion order is CH15, CH0, CH1,..., CH14. 4.20.4.2.3 ADC Conversion Control Register (ACCR) Table 203. ADC Conversion Control Register (ACCR) Offset(130) 0x82 (0x82 and 0x83 for 8-Bit access) 15 14 CH14 0 13 0 12 CH12 0 11 CH11 0 10 CH10 0 9 CH9 0 8 CH8 0 7 CH7 0 6 CH6 0 5 CH5 0 4 CH4 0 3 CH3 0 Access: User read/write 2 CH2 0 1 CH1 0 0 CH0 0 R W Reset CH15 0 0 Note: 130. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 204. ACCR - Register Field Descriptions Field Description Channel Select - If 1, the selected channel is included into the sequence. Writing ACCR will stop the current sequence and restart. Writing ACCR=0 will stop the conversion, All CCx flags will be cleared when ACCR is written.Conversion will start after write. 16-Bit write operation recommended, writing 8-bit: Only writing the High Byte will start the conversion with Channel 15, if selected. Write to the Low Byte will not start a conversion. Measure individual Channels by writing a sequence of one channel. Channel 15 needs to be selected in order to have the offset compensation functional. 15-0 CHx MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 137 4.20.4.2.4 ADC Conversion Complete Status Register (ACCSR) Table 205. ADC Conversion Complete Status Register (ACCSR) Offset(131) 0x84 (0x84 and 0x85 for 8-Bit access) 15 14 CC14 13 0 12 CC12 11 CC11 10 CC10 9 CC9 8 CC8 7 CC7 6 CC6 5 CC5 4 CC4 3 CC3 2 Access: User read 1 CC1 0 CC0 R W Reset CC15 CC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: 131. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 206. ACCSR - Register Field Descriptions Field 15-0 CCx Description Conversion Complete Flag - Indicates the conversion being complete for channel x. Read operation only.16-bit read recommended. 8-Bit read will return the current status, no latching will be performed. 4.20.4.2.5 ADC Data Result Register x (ADRx) Table 207. ADC Data Result Register x (ADRx) Offset(132) 0x86+x (0x86 and 0x87 for 8-Bit access) 15 14 13 12 11 10 9 8 7 6 5 0 4 0 3 0 2 0 Access: User read 1 0 0 0 R W Reset 0 0 0 0 0 ADRx 0 0 0 0 0 0 0 0 0 0 0 Note: 132. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 208. ADRx - Register Field Descriptions Field 15-6 ADRx Description ADC - Channel X left adjusted Result Register. Reading the register will clear the corresponding CCx register in the ACCSR register. 16-bit read recommended. 8-Bit read: Reading the low byte will latch the high byte for the next read, reading the high byte will clear the cc flag. 4.20.5 4.20.5.1 Functional Description Analog Channel Definitions Table 209. Analog Channels Channel 0 1 2 3 4 5 6 AD0 - PTB0 Analog Input AD1 - PTB1 Analog Input AD2 - PTB2 Analog Input AD3 - L0 Analog Input AD4 - L1 Analog Input AD5 - L2 Analog Input AD6 - L3 Analog Input Description AD0 AD1 AD2 AD3 AD4 AD5 AD6 The following analog Channels are routed to the analog multiplexer: MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 138 Table 209. Analog Channels Channel 7 8 9 10 11 12 13 14 15 AD7 - L4 Analog Input AD8 - L5 Analog Input Current Sense Voltage Sense Temperature Sense VS1 Sense not implemented Bandgap(133) Calibration Reference Description AD7 AD8 ISENSE VSENSE TSENSE VS1SENSE n.i. BANDGAP CAL Note: 133. Internal “bg1p25sleep” reference. 4.20.5.2 Automatic Offset Compensation To eliminate the Analog Digital Converter Offset, an automatic compensation is implemented. The compensation is based on a calibrated voltage reference connected to ADC Channel 15. The reference trim is accomplished by the correct CTRx Register content. See Section 4.26, “MM912_634 - Analog Die Trimming. The reference is factory trimmed to 8 LSB. To activate the Offset compensation feature, the OCE bit in the ADC Config Register (ACR) has to be set, and the CH15 has to be enabled when starting a new conversion, by writing to the ADC Conversion Control Register (ACCR). The compensation will work with single and sequence conversion. MCU – IFR (4C..4F) => CTR0..3 OCE – Offset Compensation Enable = 1 ACCR – ADC Conversion Control Register CH15=1 + CHx = 1 internal CH15 is a trimmed reference of 8 LSB (requires CTRx) Sample CH15 Offset is calculated as difference between result and 8 LSB Sample CHx all x Adjust CHx Result by calculated offset Read ADRx after SCF is set Figure 36. Automatic Offset Compensation 4.20.5.3 Conversion Timing The conversion timing is based on the ADCCLK generated by the ADC prescaler (PS) out of the D2DCLK signal. The prescaler needs to be configured to have the ADCCLK match the specified fADC clock limits. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 139 A conversion is divided into the following 27+ clock cycles: • 9 cycle sampling time • 18 cycle remaining conversion time • A worst case (only channel 14) of 15 clock cycles to count up to the selected channel (15, 0, 1,....14) • 4 cycles between two channels Example 1. Single Conversion Channel 10 (VSENSE) 12c (count up to Ch10) + 9c (sample) + 18c (conversion) = 39 cycles from start to end of conversion. Example 2. Sequence of Channel 10 (VSENSE) + Channel 15 (Offset Compensation) 1c (count) + 9c (sample Ch15) + 18c (conversion Ch15) + 4c (in between) + 0c (count further to Ch10 is performed while converting ch15) + 9c (sample) + 18c (conversion) = 59 cycles from start to end of both conversions. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 140 Current Sense Module - ISENSE 4.21 Current Sense Module - ISENSE MCU ANALOG The Current Sense Module is implemented to amplify the voltage drop across an external shunt resistor to measure the actual application current using the internal Analog Digital Converter Channel 9. Typical application is the motor current in a window lift control module . Imot ISENSEH C G C 2 R filt C filt P1 Qin Vin ISENSEL P2 Rshunt Vout Qin ADC Vin R filt P1 G C 2 Figure 37. Current Sense Module with External Filter Option The implementation is based on a switched capacitor solution to eliminate unwanted offset.To fit several application scenarios, eight different GAIN setting are implemented. 4.21.1 4.21.1.1 Register Definition Current Sense Register (CSR) Table 210. Current Sense Register (CSR) Offset(134) 0x3C 7 6 0 5 0 4 0 3 CCD 0 0 2 Access: User read/write 1 CSGS 0 0 0 R W Reset CSE 0 0 0 0 Note: 134. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 141 Current Sense Module - ISENSE Table 211. CSR - Register Field Descriptions Field 7 CSE 3 CCD Current Sense Enable Bit 0 - Current Sense Module Disabled 1 - Current Sense Module Enabled Input Filter Charge Compensation Disable Bit(135) 0 - Enabled 1 - Disabled Current Sense Gain Select - Selects the amplification GAIN for the current sense module 000 - 7 (typ.) 001 - 9 (typ.) 2-0 CSGS 010 - 10 (typ.) 011 - 12 (typ.) 100 - 14 (typ.) 101 - 18 (typ.) 110 - 24 (typ.) 111 - 36 (typ.) Note: 135. This feature should be used when implementing an external filter to the current sense ISENSEx inputs. In principal an internal charge compensation is activated in synch with the conversion to avoid the sample capacitors to be discharged by the external filter. Description MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 142 Temperature Sensor - TSENSE 4.22 Temperature Sensor - TSENSE MCU ANALOG To be able to measure the current MM912_634 analog die chip temperature, the TSENSE feature is implemented. A constant temperature related gain of TSG can be routed to the internal Analog Digital Converter (Channel 11). V 2.5 2.0 1.5 1.0 0.5 0,15V -50°C Typ. 1,984V 150°C Typ. T -50°C 0°C 50°C 100°C 150°C Figure 38. TSENSE - Graph Refer to the Section 4.20, “Analog Digital Converter - ADC for details on the channel selection and analog measurement. NOTE Due to internal capacitor charging, temperature measurements are valid 200 ms (max) after system power up and wake-up. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 143 Supply Voltage Sense - VSENSE 4.23 Supply Voltage Sense - VSENSE MCU ANALOG The reverse battery protected VSENSE pin has been implemented to allow a direct measurement of the Battery level voltage. Bypassing the device VSUP capacitor and external reverse battery diode will detect under-voltage conditions without delay. A series resistor is required to protect the MM912_634 analog die from fast transients. LBI RVSENSE VSENSE VS1 VS2 Prescaler RATIOVSENSE CH11 MUX ADC Figure 39. VSENSE Module The voltage present on the VSENSE pin can be routed via an internal divider to the internal Analog Digital Converter or issue an interrupt (LBI) to alert the MCU. For the interrupt based alert, see Section 4.5, “Power Supply. For VSENSE measurement using the internal ADC see Section 4.20, “Analog Digital Converter - ADC. 4.24 I Internal Supply Voltage Sense - VS1SENSE MCU ANALOG In addition to the VSENSE module, the internal VS1 supply can be routed to the analog digital converter as well. See Section 4.20, “Analog Digital Converter - ADC for details on the acquisition. LVI RVSENSE VSENSE MUX Prescaler RATIOVS1 CH12 ADC VS1 VS2 Figure 40. VS1Sense Module 4.25 Internal Bandgap Reference Voltage Sense - BANDGAP The internal reference bandgap voltage “bg1p25sleep” is generated fully independent from the Analog Digital Converter reference voltages. Measuring(136) the “bg1p25sleep” reference through the ADC-CH14 allows should return a conversion result within ADCH14 under normal conditions. Any result outside the range would indicate faulty behavior of either the ADC chain or the 2p5sleep Bandgap circuity. MCU ANALOG Note: 136. The maximum allowed sample frequency for Channel 14 is limited to fCH14. Increasing the sample frequency above can result in unwanted turn off of the LS drivers due to a false VREG over-voltage. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 144 MM912_634 - Analog Die Trimming 4.26 MM912_634 - Analog Die Trimming MCU ANALOG A trimming option is implemented to increase some device parameter accuracy. As the MM912_634 analog die is exclusively combined with a FLASH- MCU, the required trimming values can be calculated during the final test of the device, and stored to a fixed position in the FLASH memory. During start-up of the system, the trimming values have to be copied into the MM912_634 analog die trimming registers. The trimming registers will maintain their content during Low Power mode, Reset will set the default value. 4.26.1 4.26.1.1 Memory Map and Register Definition Module Memory Map There are four trimming registers implemented (CTR0…CTR3), with CTR2 being reserved for future use. The following table shows the registers used. Table 212. MM912_634 Analog Die Trimming Registers Offset 0xF0 0xF1 0xF2 0xF3 Name CTR0 Trimming Reg 0 CTR1 Trimming Reg 1 CTR2 Trimming Reg 2 CTR3 Trimming Reg 3 R W R W R W R W 7 LINTRE BGTRE 0 OFFCTR E 6 LINTR CTR1_6 0 OFFCTR 2 5 WDCTRE BGTRIMU P 0 OFFCTR1 4 CTR0_4 BGTRIMD N SLPBGTR E OFFCTR0 3 CTR0_3 IREFTRE SLPBG_LOC K CTR3_E 2 WDCTR2 IREFTR2 SLPBGTR 2 CTR3_2 1 WDCTR1 IREFTR1 SLPBGTR 1 CTR3_1 0 WDCTR0 IREFTR0 SLPBGTR 0 CTR3_0 Note: 137. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. At system startup, the trimming information have to be copied from the MCU IFR Flash location to the corresponding MM912_634 analog die trimming registers. The following table shows the register correlation. Table 213. MM912_634 - MCU vs. Analog Die Trimming Register Correlation Name CTR0 CTR1 CTR2 CTR3 MCU IFR Address 0x4C 0x4D 0x4E 0x4F Analog Offset(138) 0xF0 0xF1 0xF2 0xF3 Note: 138. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. NOTE Two word (16-Bit) transfers including CTR2 are recommended at system startup. The IFR register has to be enabled for reading (Section 4.29.3.2.3, “MMC Control Register (MMCCTL1)) NOTE To trim the bg1p25sleep there is two steps: Step 1: First choose the right trim step by adjusting SLPBGTR[2:0] with SLPBGTRE=1, SLPBG_LOCK bit has to stay at 0. Step 2: Once the trim value is known, correct SLPBGTR[2:0], SLPBGTRE and SLPBG_LOCK bits have to be set at the same time to apply and lock the trim. Once the trim is locked, no other trim on the parameter is possible. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 145 MM912_634 - Analog Die Trimming 4.26.1.2 4.26.1.2.1 Register Descriptions Trimming Register 0 (CTR0) Table 214. Trimming Register 0 (CTR0) Offset(139) 0xF0 7 R W Reset LINTRE 0 6 LINTR 0 5 WDCTRE 0 4 CTR0_4 0 3 CTR0_3 0 2 WDCTR2 0 Access: User read/write 1 WDCTR1 0 0 WDCTR0 0 Note: 139. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 215. CTR0 - Register Field Descriptions Field 7 LINTRE 6 LINTR 5 WDCTRE 4 CTR0_4 3 CTR0_3 Watchdog clock trim (Trim effect to the 100 kHz Watch dog base clock) 000: 0% 001: +5% 2-0 WDCTR2…0 010: +10% 011: +15% 100: -20% 101: -15% 110: -10% 111: -5% Spare Trim bit 3 LIN trim enable 0 - no trim can be done 1- trim can be done by setting LINTR bit LIN trim bit 0 - default slope 1 - adjust the slope Watchdog trim enable 0 - no trim can be done 1 - trim can be done by setting WDCTR[2:0] bits Spare Trim bit 4 Description 4.26.1.2.2 Trimming Register 1 (CTR1) Table 216. Trimming Register 1 (CTR1) Offset (140) 0xF1 7 6 CTR1_6 0 5 BGTRIMUP 0 4 BGTRIMDN 0 3 IREFTRE 0 2 IREFTR2 0 Access: User read/write 1 IREFTR1 0 0 IREFTR0 0 R W Reset BGTRE 0 Note: 140. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 146 MM912_634 - Analog Die Trimming Table 217. CTR1 - Register Field Descriptions Field 7 BGTRE 6 CTR1_6 5 BGTRIMUP 4 BGTRIMDN 3 IREFTRE Bandgap trim up bit 0 - default slope 1 - increase bandgap slope Bandgap trim down bit 0 - default slope 1 - decrease bandgap slope Iref trim enable bit 0 - no trim can be done 1 - trim can be done by setting IREFTR[2:0] bits Iref trim - This trim is used to adjust the internal zero TC current reference 000: 0% 001: +7.6% 2-0 IREFTR2…0 010: +16.43% 011: +26.83% 100: -8.54% 101: -15.75% 110: -21.79% 111: 0% Bandgap trim enable 0 - no trim can be done 1 - trim can be done by setting BGTRIMUP and BGTRIMDN bits Spare Trim Bit Description 4.26.1.2.3 Trimming Register 2 (CTR2) Table 218. Trimming Register 2 (CTR2) Offset(141) 0xF2 7 6 0 5 0 4 SLPBGTRE 0 3 SLPBG_LOCK 0 2 SLPBGTR2 0 Access: User read/write 1 SLPBGTR1 0 0 SLPBGTR0 0 R W Reset 0 0 0 0 Note: 141. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 147 MM912_634 - Analog Die Trimming Table 219. CTR2 - Register Field Descriptions Field 4 SLPBGTRE 3 SLPBG_LOCK bg1p25sleep trim - This trim is used to adjust the internal sleep mode 1.25 V bandgap used as a reference for the VDD and VDDx over-voltage detection. 000: -12.2% (default) 001: -8.2% 2-0 SLPBGTR2…0 010: -4.2% 011: 0% 100: +4.2% 101: +8.3% 110: +12.5% 111: -12.2% (default) Sleep Bandgap trim enable 0 no trim can be done 1 trim lock can be done by setting SLPBGTR[2:0] bits and SLPBG_LOCK bit bg1p25sleep trim lock bit Description 4.26.1.2.4 Trimming Register 3 (CTR3) Table 220. Trimming Register 3 (CTR3) Offset(142) 0xF3 7 R W Reset OFFCTRE 0 6 OFFCTR2 0 5 OFFCTR1 0 4 OFFCTR0 0 3 CTR3_E 0 2 CTR3_2 0 Access: User read/write 1 CTR3_1 0 0 CTR3_0 0 Note: 142. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 221. CTR3 - Register Field Descriptions Field 7 OFFCTRE ADC offset compensation voltage trim enable bit 0 - no trim can be done 1 - trim can be done by setting OFFCTR[2:0] bits ADCOFFC trim - This trim is used to adjust the internal ADC offset compensation voltage 000: 0% 001: +7.98% 6-4 OFFCTR2…0 010: +15.97% 011: +23.95% 100: -23.95% 101: -15.97% 110: -7.98% 111: 0% 3 CTR3_E 2 CTR3_2 Spare Trim bit 2 Spare Trim enable bit Description MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 148 Table 221. CTR3 - Register Field Descriptions Field 1 CTR3_1 0 CTR3_0 Spare Trim bit 0 Spare Trim bit 1 Description MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 149 MM912_634 - MCU Die Overview 4.27 4.27.1 MM912_634 - MCU Die Overview Introduction MCU ANALOG The MC9S12I64 micro controller implemented in the MM912_634 is designed as counter part to an analog die, and is not being offered as a standalone MCU. The MC9S12I64 device contains a S12 Central Processing Unit (CPU), offers 64kB of Flash memory and 6.0 kB of system SRAM, up to eight general purpose I/Os, an on-chip oscillator and clock multiplier, one Serial Peripheral Interface (SPI), an interrupt module and debug capabilities via the on-chip debug module (DBG) in combination with the Background Debug Mode (BDM) interface. Additionally there is a die-to-die initiator (D2DI) which represents the communication interface to the companion (analog) die. 4.27.2 Features This section describes the key features of the MC9S12I64 micro controller unit. 4.27.2.1 Chip-Level Features On-chip modules available within the family include the following features: • S12 CPU core (CPU12_V1) • Kbyte on-chip flash with ECC • 4.0 kbyte on-chip data flash with ECC • 6.0 kbyte on-chip SRAM • Phase locked loop (IPLL) frequency multiplier with internal filter • 4–16 MHz amplitude controlled Pierce oscillator • 1.0 MHz internal RC oscillator • One serial peripheral interface (SPI) module • On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages • Die to Die Initiator (D2DI) 4.27.3 Module Features The following sections provide more details of the modules implemented on the MC9S12I64. 4.27.3.1 S12 16-Bit Central Processor Unit (CPU) S12 CPU is a high-speed 16-bit processing unit: • Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution • Includes many single-byte instructions. This allows much more efficient use of ROM space. • Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode — Accumulator offsets using A, B, or D accumulators — Automatic index pre-decrement, pre-increment, post-decrement, and post-increment (by –8 to +8) 4.27.3.2 On-Chip Flash with ECC On-chip flash memory on the MC9S12I64 features the following: • kbyte of program flash memory — 32 data bits plus 7 syndrome ECC (Error Correction Code) bits allow single bit error correction and double fault detection — Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 150 MM912_634 - MCU Die Overview • 4.0 kbyte data flash memory — 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit error correction and double-bit error detection — Erase sector size 256 bytes — Automated program and erase algorithm — User margin level setting for reads 4.27.3.3 On-Chip SRAM 6.0 kBytes of general-purpose RAM 4.27.3.4 Main External Oscillator (XOSC) Loop controlled Pierce oscillator using a 4.0 MHz to 16 MHz crystal or resonator — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals 4.27.3.5 Internal RC Oscillator (IRC) Trimmable internal reference clock. 4.27.3.6 Internal Phase-locked Loop (IPLL) Phase-locked loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – External 4.0 to 16 MHz resonator/crystal (XOSC) – Internal 1.0 MHz RC oscillator (IRC) 4.27.3.7 • • • • • • System Integrity Support • Power-on reset (POR) System reset generation Illegal address detection with reset Low-voltage detection with interrupt or reset Real time interrupt (RTI) Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection — Initialized out of reset using option bits located in flash memory Clock monitor supervising the correct function of the oscillator 4.27.3.8 • • • • • • Serial Peripheral Interface Module (SPI) Configurable 8 or 16-bit data size Full-duplex or single-wire bidirectional Double-buffered transmit and receive Master or slave mode MSB-first or LSB-first shifting Serial clock phase and polarity options MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 151 MM912_634 - MCU Die Overview 4.27.3.9 • • • • On-Chip Voltage Regulator (VREG) Linear voltage regulator with bandgap reference Low-voltage detect (LVD) with low-voltage interrupt (LVI) Power-on reset (POR) circuit Low-voltage reset (LVR) 4.27.3.10 • • Background Debug (BDM) Non-intrusive memory access commands Supports in-circuit programming of on-chip nonvolatile memory 4.27.3.11 • • Debugger (DBG) • • • Trace buffer with depth of 64 entries Three comparators (A, B and C) — Comparator A compares the full address bus and full 16-bit data bus — Exact address or address range comparisons Two types of comparator matches — Tagged: This matches just before a specific instruction begins execution — Force: This is valid on the first instruction boundary after a match occurs Four trace modes Four stage state sequencer 4.27.3.12 • • Die to Die Initiator (D2DI) Up to 2.0 Mbyte/s data rate Configurable 4-bit or 8-bit wide data path Figure 4.27.4 shows MC9S12I64 CPU and BDM local address translation to the global memory map. It indicates also the location of the internal resources in the memory map. The whole 256 k global memory space is visible through the P-Flash window located in the 64 k local memory map located at 0x8000 - 0xBFFF using the PPAGE register. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 152 MM912_634 - MCU Die Overview CPU and BDM Local Memory Map 0x0000 Registers 0x0400 D-Flash 4K Bytes 0x1400 Unpaged P-Flash Page 0x0C 0x2800 RAM 6K Bytes 0x4000 Global Memory Map 0x0_0000 Registers Unimplemented (PPAGE 0x00) 0x0_2800 RAM 6K 0x0_4000 0x0_4400 0x0_5400 NVM Resources 0x0_8000 Unimplemented Unpaged P-Flash Page 0x0D 0x2_0000 NVM Resources D-Flash (PPAGE 0x01) (PPAGES 0x02-0x07) (PPAGES 0x08-0x0B) P-Flash 4* 16K Pages 0x8000 0x3_0000 0 0 0 0 P3 P1 P2 P0 PPAGE 0x3_4000 0xC000 Unpaged P-Flash Unpaged P-Flash (PPAGE 0x0C) (PPAGE 0x0D) (PPAGE 0x0E) (PPAGE 0x0F) P-Flash window 0x3_8000 Unpaged P-Flash Page 0x0F 0xFFFF 0x3_C000 Unpaged P-Flash 0x3_FFFF Figure 41. MC9S12I128 Global Memory Map MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 153 MM912_634 - MCU Die Overview 4.27.4 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 222 shows the assigned part ID number and Mask Set number. The Version ID in Table 222 is a word located in a flash information row. The version ID number indicates a specific version of internal NVM controller. Table 222. Assigned Part ID Numbers Device MC9S12I64 Mask Set Number 0N53A Part ID(143) 0x38C0 Version ID 0x0000 Note: 143. The coding is as follows: Bit 15-12: Major family identifier Bit 11-6: Minor family identifier Bit 5-4: Major mask set revision number including FAB transfers Bit 3-0: Minor — non full — mask set revision 4.27.5 System Clock Description For the system clock description please refer to 4.38, “S12 Clock, Reset and Power Management Unit (S12CPMU)”. 4.27.6 Modes of Operation The MCU can operate in different modes. These are described in Section 4.27.6.1, “Chip Configuration Summary”. The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These are described in Section 4.27.6.2, “Low Power Operation”. Some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging. 4.27.6.1 Chip Configuration Summary The different modes and the security state of the MCU affect the debug features (enabled or disabled). The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 223). The MODC bit in the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET. Table 223. Chip Modes Chip Modes Normal single chip Special single chip MODC 1 0 4.27.6.1.1 Normal Single-Chip Mode This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). The processor program is executed from internal memory. 4.27.6.1.2 Special Single-Chip Mode This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin. 4.27.6.2 Low Power Operation The MM912_634 has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description refer to S12CPMU section. 4.27.7 Security The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to 4.33, “Security (S12X9SECV2)”, Section 4.31.4.1, “Security”, and Section 4.40.5, “Security”. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 154 MM912_634 - MCU Die Overview 4.27.8 Resets and Interrupts Consult the S12 CPU manual and the S12SINT section for information on exception processing. 4.27.8.1 Resets Table 224 lists all Reset sources and the vector locations. Resets are explained in detail in the 4.38, “S12 Clock, Reset and Power Management Unit (S12CPMU)”. Table 224. Reset Sources and Vector Locations Vector Address $FFFE $FFFE $FFFE $FFFE $FFFC $FFFA Reset Source Power-On Reset (POR) Low Voltage Reset (LVR) External pin RESET Illegal Address Reset Clock monitor reset COP watchdog reset CCR Mask None None None None None None Local Enable None None None None OSCE Bit in CPMUOSC register CR[2:0] in CPMUCOP register 4.27.8.2 Interrupt Vectors Table 225 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see 4.30, “Interrupt Module (S12SINTV1)”) provides an interrupt vector base register (IVBR) to relocate the vectors. Table 225. Interrupt Vector Locations (Sheet 1 of 2) Vector Address(144) Vector base + $F8 Vector base+ $F6 Vector base+ $F4 Vector base+ $F2 Vector base+ $F0 Vector base + $EE to Vector base + $DA Vector base + $D8 Vector base + $D6 to Vector base + $CA Vector base + $C8 Vector base + $C6 Vector base + $C4 to Vector base + $BC Vector base + $BA Vector base + $B8 Vector base + $B6 to Vector base + $8C Vector base + $8A Vector base + $88 to Vector base + $82 Low-voltage interrupt (LVI) FLASH error FLASH command Oscillator status interrupt PLL lock interrupt SPI Interrupt Source Unimplemented instruction trap SWI D2DI Error Interrupt D2DI External Error Interrupt RTI timeout interrupt CCR Mask None None X Bit I bit I bit Reserved I bit Reserved I bit I bit Reserved I bit I bit Reserved I bit Reserved CPMUCTRL (LVIE) No FERCNFG (SFDIE, DFDIE) FCNFG (CCIE) No No CPMUINT (OSCIE) CPMUINT (LOCKIE) No No SPICR1 (SPIE, SPTIE) No Local Enable None None None D2DCTL (D2DIE) CPMUINT (RTIE) Wake-up from STOP Yes Yes MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 155 MM912_634 - MCU Die Overview Table 225. Interrupt Vector Locations (Sheet 2 of 2) Vector Address(144) Vector base + $80 Note: 144. 16 bits vector address based Interrupt Source Spurious interrupt CCR Mask — Local Enable None Wake-up from STOP - 4.27.8.3 Effects of Reset When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On each reset, the Flash module executes a reset sequence to load Flash configuration registers. 4.27.8.3.1 Flash Configuration Reset Sequence Phase On each reset, the Flash module will hold CPU activity while loading Flash module registers from the Flash memory. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the Flash module Section 4.40.6, “Initialization”. 4.27.8.3.2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. 4.27.8.3.3 I/O Pins Refer to the PIM section for reset configurations of all peripheral module ports. 4.27.8.3.4 Memory The RAM arrays are not initialized out of reset. 4.27.9 COP Configuration The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are loaded from the Flash register FOPT. See Table 226 and Table 227 for coding. The FOPT register is loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence. Table 226. Initial COP Rate Configuration NV[2:0] in FOPT Register 000 001 010 011 100 101 110 111 CR[2:0] in COPCTL Register 111 110 101 100 011 010 001 000 Table 227. Initial WCOP Configuration NV[3] in FOPT Register 1 0 WCOP in COPCTL Register 0 1 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 156 Port Integration Module (S12IPIMV1) 4.28 4.28.1 Port Integration Module (S12IPIMV1) Introduction MCU ANALOG The Port Integration Module (PIM) establishes the interface between the MC9S12I64 peripheral modules SPI and Die-To-Die Interface module (D2DI) to the I/O pins of the MCU. All port A and port E pins support general purpose I/O functionality if not in use with other functions. The PIM controls the signal prioritization and multiplexing on shared pins. SPI Synchronous Serial IF CPMU OSC EXTAL XTAL PORTE DDRE PORTA DDRA MISO MOSI SCK SS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Port Integration Module Elements PE0 PE1 D2DI D2DCLK D2DINT D2DDAT0 D2DDAT1 D2DDAT2 D2DDAT3 D2DDAT4 D2DDAT5 D2DDAT6 D2DDAT7 PC0 PC1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Die-to-Die IF Figure 42. Block Diagram 4.28.1.1 • • • • • • • Features 8-pin port A associated with the SPI module 2-pin port C used as D2DI clock output and D2DI interrupt input 8-pin port D used as 8 or 4 bit data I/O for the D2DI module 2-pin port E associated with the CPMU OSC module GPIO function shared on port A, E pins Pull-down devices on PC1 and PD7-0 if used as D2DI inputs Reduced drive capability on PC0 and PD7-0 on per pin basis The Port Integration Module includes these distinctive registers: • Data registers for ports A, E when used as general-purpose I/O • Data direction registers for ports A, E when used as general-purpose I/O • Port input register on ports A and E • Reduced drive register on port C and D 4.28.2 Memory Map and Register Definition This section provides a detailed description of all Port Integration Module registers. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 157 Port Integration Module (S12IPIMV1) 4.28.2.1 Register Name 0x0000 PORTA 0x0001 PORTB 0x0002 DDRA 0x0003 DDRB 0x00040x0009 Reserved 0x000C PUCR 0x000D RDRIV 0x0120 PTIA 0x0121 PTIB 0x01220x17F Reserved R W R W R W R W R W R W R W R W R W R W Memory Map Bit 7 6 5 4 3 2 1 Bit 0 PA7 0 PA6 0 PA5 0 PA4 0 PA3 0 PA2 0 PA1 PA0 PE1 PE0 DDRA7 0 DDRA6 0 DDRA5 0 DDRA4 0 DDRA3 0 DDRA2 0 DDRA1 DDRA0 DDRE1 0 DDRE0 0 0 0 0 0 0 0 0 BKPUE 0 0 0 0 0 PDPEE 0 0 0 0 0 RDPD PTIA3 RDPC PTIA2 0 PTIA7 PTIA6 PTIA5 PTIA4 PTIA1 PTIA0 0 0 0 0 0 0 PTIE1 PTIE0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 4.28.2.2 Port A Data Register (PORTA) Figure 43. Port A Data Register (PORTA) Address 0x0000 7 R W SPI Function Reset PA7 — 0 6 PA6 — 0 5 PA5 — 0 4 PA4 — 0 3 PA3 SS 0 2 PA2 SCK 0 Access: User read/write(145) 1 PA1 MOSI 0 0 PA0 MISO 0 Note: 145. Read: Anytime. Write: Anytime. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 158 Port Integration Module (S12IPIMV1) Table 228. PORTA Register Field Descriptions Field 7–4 PA Description Port A general purpose input/output data—Data RegisterIn output mode the register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered and synchronized pin input state is read. Port A general purpose input/output data—Data Register, SPI SS input/output When not used with the alternative function, this pin can be used as general purpose I/O. In general purpose output mode the register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. • The SPI function takes precedence over the general purpose I/O function if enabled. Port A general purpose input/output data—Data Register, SPI SCK input/output When not used with the alternative function, this pin can be used as general purpose I/O. In general purpose output mode the register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. • The SPI function takes precedence over the general purpose I/O function if enabled. Port A general purpose input/output data—Data Register, SPI MOSI input/output When not used with the alternative function, this pin can be used as general purpose I/O. In general purpose output mode the register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. • The SPI function takes precedence over the general purpose I/O function if enabled. Port A general purpose input/output data—Data Register, SPI MISO input/output When not used with the alternative function, this pin can be used as general purpose I/O. In general purpose output mode the register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. • The SPI function takes precedence over the general purpose I/O function if enabled. 3 PA 2 PA 1 PA 0 PA 4.28.2.3 pim Port E Data Register (PORTE) Table 229. Port E Data Register (PORTE) Address 0x0001 7 R W CPMU OSC Function Reset — 0 — 0 — 0 — 0 — 0 — 0 0 6 0 5 0 4 0 3 0 2 0 Access: User read/write(146) 1 PE1 0 PE0 XTAL 0 EXTAL 0 Note: 146. Read: Anytime. Write: Anytime. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 159 Port Integration Module (S12IPIMV1) Table 230. PORTE Register Field Descriptions Field Description Port E general purpose input/output data—Data Register, CPMU OSC XTAL signal When not used with the alternative function, this pin can be used as general purpose I/O. In general purpose output mode the register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. • The CPMU OSC function takes precedence over the general purpose I/O function if enabled. Port E general purpose input/output data—Data Register, CPMU OSC EXTAL signal When not used with the alternative function, this pin can be used as general purpose I/O. In general purpose output mode the register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. • The CPMU OSC function takes precedence over the general purpose I/O function if enabled. 1 PE 0 PE 4.28.2.4 Port A Data Direction Register (DDRA) Figure 44. Port A Data Direction Register (DDRA) Address 0x0002 7 R W Reset DDRA7 0 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 Access: User read/write(147) 1 DDRA1 0 0 DDRA0 0 Note: 147. Read: Anytime. Write: Anytime. Table 231. DDRA Register Field Descriptions Field 7–4 DDRA Description Port A Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port A Data Direction— This bit determines whether the associated pin is an input or output. Depending on the configuration of the enabled SPI the I/O state will be forced to input or output. In this case the data direction bits will not change. 1 Associated pin is configured as output. 0 Associated pin is configured as input. 3–0 DDRA 4.28.2.5 Port E Data Direction Register (DDRE) Figure 45. Port E Data Direction Register (DDRE) Address 0x0003 7 R W Reset 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 Access: User read/write(148) 1 DDRE1 0 0 DDRE0 0 Note: 148. Read: Anytime. Write: Anytime. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 160 Port Integration Module (S12IPIMV1) Table 232. DDRE Register Field Descriptions Field Description Port E Data Direction— This bit determines whether the associated pin is an input or output. The enabled CPMU OSC function connects the associated pins directly to the oscillator module. In this case the data direction bits will not change. 1 Associated pin is configured as output. 0 Associated pin is configured as input. 1–0 DDRE 4.28.2.6 PIM Reserved Registers Table 233. PIM Reserved Registers These registers are reserved for factory testing of the PIM module. Writing to these addresses can alter the module functionality. Address 0x0004-0x0009 7 R W Reset 0 0 0 = Unimplemented or Reserved Note: 149. Read: Always reads 0x00 Write: Not allowed 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Access: User read(149) 0 0 0 4.28.2.7 Pull Control Register (PUCR) Table 234. Pull Control Register (PUCR) Address 0x0124 7 R W Reset 0 0 6 BKPUE 1 5 0 4 0 3 0 2 0 Access: User read/write(150) 1 PDPEE 1 0 0 0 0 0 0 0 Note: 150. Read: Anytime. Write: Anytime. Table 235. PUCR Register Field Descriptions Field Description BKGD pin pull-up Enable—Enable pull-up devices on BKGD pin. This bit configures whether a pull-up device is activated, if the pin is used as input. This bit has no effect if the pin is used as output. Out of reset the pull-up device is enabled. 1 Pull-up device enabled. 0 Pull-up device disabled. Pull-down Port E Enable—Enable pull-down devices on all Port E input pins. This bit configures whether pull-down devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-down devices are enabled. If the CPMU OSC function is active the pull-down devices are disabled. In this case the register bit will not change. 1 Pull-down devices enabled. 0 Pull-down devices disabled. 6 BKPUE 1 PDPEE MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 161 Port Integration Module (S12IPIMV1) 4.28.2.8 Reduced Drive Register (RDRIV) Table 236. Reduced Drive Register (RDRIV) Address 0x000D 7 R W Reset 0 0 0 0 0 6 0 5 0 4 0 3 RDPD 0 2 RDPC 0 Access: User read/write(151) 1 0 0 0 0 0 Note: 151. Read: Anytime. Write: Anytime. Table 237. RDRIV Register Field Descriptions Field Description Port D reduced drive—Select reduced drive for output pins. This bit configures the drive strength of output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/5 of the full drive strength) 0 Full drive strength enabled 2 RDPC Port C reduced drive—Select reduced drive for D2DCLK output pin. This bit configures the drive strength of D2DCLK output pin as either full or reduced. 1 Reduced drive selected (1/5 of the full drive strength) 0 Full drive strength enabled 3 RDPD 4.28.2.9 Port A Input Register (PTIA) Table 238. Port A Input Register (PTIA) Address 0x0120 7 R W Reset(153) u u u u u u u PTIA7 6 PTIA6 5 PTIA5 4 PTIA4 3 PTIA3 2 PTIA2 1 Access: User read(152) 0 PTIA0 PTIA1 u Note: 152. Read: Anytime. Write: Unimplemented. Writing to this register has no effect. 153. u = Unaffected by reset Table 239. PTIA Register Field Descriptions Field 7–0 PTIA Description Port A input data— A read always returns the buffered input state of the associated pin.It can be used to detect overload or short circuit conditions on output pins. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 162 Port Integration Module (S12IPIMV1) 4.28.2.10 Port E Input Register (PTIE) Table 240. Port E Input Register (PTIE) Address 0x0121 7 R W Reset(155) u u u u u u u 0 6 0 5 0 4 0 3 0 2 0 1 Access: User read(154) 0 PTIE0 PTIE1 u Note: 154. Read: Anytime. Write: Unimplemented. Writing to this register has no effect. 155. u = Unaffected by reset Table 241. PTIE Register Field Descriptions Field 1–0 PTIE Description Port E input data— A read always returns the buffered input state of the associated pin.It can be used to detect overload or short circuit conditions on output pins. 4.28.2.11 i PIM Reserved Registers Table 242. PIM Reserved Register Address 0x0122-0x017F 7 R W Reset 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Access: User read(156) 0 0 0 Note: 156. Read: Anytime. Write: Unimplemented. Writing to this register has no effect. 4.28.3 4.28.3.1 4.28.3.1.1 Functional Description Registers Data register (PORTx) This register holds the value driven out to the pin if the pin is used as a general purpose I/O. Writing to this register has only an effect on the pin if the pin is used as general purpose output. When reading this address, the buffered and synchronized state of the pin is returned if the associated data direction register bit is set to “0”. If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This is independent of any other configuration (Figure 46). 4.28.3.1.2 Data direction register (DDRx) This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 46). 4.28.3.1.3 Input register (PTIx) This is a read-only register and always returns the buffered and synchronized state of the pin (Figure 46). MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 163 Port Integration Module (S12IPIMV1) PTIx 0 1 synch. PORTx 0 1 PIN DDRx data out output enable port enable data in 0 1 Periph. Module Figure 46. Illustration of I/O Pin Functionality 4.28.3.1.4 Reduced Drive Register (RDRIV) If the pin is used as an output this register allows the configuration of the drive strength. 4.28.3.1.5 Pull Device Enable Register (PUCR) This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input. 4.28.3.2 4.28.3.2.1 Ports Port A This port is associated with the SPI. Port A pins PA7-0 can be used for general-purpose I/O and PA3-0 also with the SPI subsystem. 4.28.3.2.2 Port C This port is associated with the D2DI interface. Port C pins PC1-0 can be used as the D2DI interrupt input and D2DI clock output, respectively. A pull-down device is enabled on pin PC1 if used as D2DI input.A reduced drive strength can be selected on PC0 if used as D2DI output. The D2DI interrupt input is synchronized and has an asynchronous bypass in STOP mode to allow the generation of a wake-up interrupt. 4.28.3.2.3 Port D This port is associated with the D2DI interface. Port D pins PD7-0 can be used with the D2DI data I/O. Pull-down devices are enabled on all pins if used as D2DI inputs.A reduced drive strength can be selected on all pins if used as D2DI outputs. 4.28.3.2.4 Port E This port is associated with the CPMU OSC. Port E pins PE1-0 can be used for general-purpose or with the CPMU OSC module. 4.28.4 4.28.4.1 Initialization Information Port Data and Data Direction Register writes It is not recommended to write PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 164 4.29 4.29.1 Memory Map Control (S12PMMCV1) Introduction The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip resources. Figure 47 shows a block diagram of the S12PMMC module. 4.29.1.1 Glossary Table 243. Glossary Of Terms Term Definition Address within the CPU12’s Local Address Map (Figure 52) Address within the Global Address Map (Figure 52) Bus access to an even address. Bus access to an odd address. Normal Single-chip Mode Special Single-chip Mode Address ranges which are not mapped to any on-chip resource. Program Flash Data Flash Non-volatile Memory; P-Flash or D-Flash NVM Information Row. Refer to FTMRC Block Guide Local Addresses Global Address Aligned Bus Access Misaligned Bus Access NS SS Unimplemented Address Ranges P-Flash D-Plash NVM IFR 4.29.1.2 Overview The S12PMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources (memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12PMMC is responsible for constraining memory accesses on secured devices and for selecting the MCU’s functional mode. 4.29.1.3 Features The main features of this block are: • Paging capability to support a global 256 kByte memory address space • Bus arbitration between the masters CPU12, S12SBDM to different resources. • MCU operation mode control • MCU security control • Separate memory map schemes for each master CPU12, S12SBDM • Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 4.29.1.4 Modes of Operation The S12PMMC selects the MCU’s functional mode. It also determines the devices behavior in secured and unsecured state. 4.29.1.4.1 Functional Modes Two functional modes are implements on devices of the S12I product family: • Normal Single Chip (NS) The mode used for running applications. • Special Single Chip Mode (SS) A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals may also provide special debug features in this mode. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 165 4.29.1.4.2 Security S12I derives can be secured to prohibit external access to the on-chip P-Flash. The S12PMMC module determines the access permissions to the on-chip memories in secured and unsecured state. 4.29.1.5 Block Diagram Figure 47 shows a block diagram of the S12PMMC. BDM CPU MMC Address Decoder & Priority DBG Target Bus Controller D-Flash P-Flash RAM Peripherals Figure 47. S12PMMC Block Diagram 4.29.2 External Signal Description The S12PMMC uses two external pins to determine the devices operating mode: RESET and MODC (Table 244) See Device User Guide (DUG) for the mapping of these signals to device pins. Table 244. External System Pins Associated With S12PMMC Pin Name RESET (See DUG) MODC (See DUG) Pin Functions RESET MODC Description The RESET pin is used the select the MCU’s operating mode. The MODC pin is captured at the rising edge of the RESET pin. The captured value determines the MCU’s operating mode. 4.29.3 4.29.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the S12PMMC block is shown in Table 245. Detailed descriptions of the registers and bits are given in the subsections that follow. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 166 Table 245. MMC Register Summary Address 0x000A Register Name Reserved R W R W R W R W R W R W R W R W R W R W = Unimplemented or Reserved 0 0 0 0 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 0 0 RAMON 0 ROMON 0 0 0 0 0 0 0 0 IFRON 0 0 0 0 0 0 0 0 DP15 0 DP14 0 DP13 0 DP12 0 DP11 0 DP10 0 DP9 0 DP8 0 MODC 0 0 0 0 0 0 0 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0x000B MODE 0x0010 Reserved 0 0 0 0 0 0 0 0x0011 DIRECT 0x0012 Reserved 0x0013 Reserved 0x0013 MMCCTL1 0x0013 MMCCTL1 IFRON 0 0x0014 Reserved 0x0015 PPAGE 4.29.3.2 Register Descriptions This section consists of the S12PMMC control register descriptions in address order. 4.29.3.2.1 Mode Register (MODE) Table 246. Mode Register (MODE) Address: 0x000B 7 R W Reset MODC MODC(157) 6 0 5 0 4 0 3 0 2 0 1 0 0 0 0 0 = Unimplemented or Reserved 0 0 0 0 0 Note: 157. External signal (see Table 244). Read: Anytime. Write: Only if a transition is allowed (see Figure 48). The MODC bit of the MODE register is used to select the MCU’s operating mode. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 167 Table 247. MODE Field Descriptions Field Description Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external mode pin MODC determines the operating mode during RESET low (active). The state of the pin is registered into the respective register bit after the RESET signal goes inactive (see Figure 48). Write restrictions exist to disallow transitions between certain modes. Figure 48 illustrates all allowed mode changes. Attempting non authorized transitions will not change the MODE bit, but it will block further writes to the register bit except in special modes. Write accesses to the MODE register are blocked when the device is secured. 7 MODC RESET 1 0 Normal Single-Chip (NS) 1 1 Special Single-Chip (SS) 0 Figure 48. Mode Transition Diagram When MCU is Unsecured 4.29.3.2.2 Direct Page Register (DIRECT) Table 248. Direct Register (DIRECT) Address: 0x0011 7 R W Reset DP15 0 6 DP14 0 5 DP13 0 4 DP12 0 3 DP11 0 2 DP10 0 1 DP9 0 0 DP8 0 Read: Anytime Write: anytime in special SS, write-one in NS. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. Table 249. DIRECT Field Descriptions Field 7–0 DP[15:8] Description Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. These register bits form bits [15:8] of the local address (see Figure 49). Bit15 DP [15:8] Bit8 Bit7 Bit0 CPU Address [15:0] Figure 49. DIRECT Address Mapping MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 168 Example 1. This example demonstrates usage of the Direct Addressing Mode MOVB #$80,DIRECT ;Set DIRECT register to 0x80. Write once only. ;Global data accesses to the range 0xXX_80XX can be direct. ;Logical data accesses to the range 0x80XX are direct. ;Load the Y index register from 0x8000 (direct access). ;< operator forces direct access on some assemblers but in ;many cases assemblers are “direct page aware” and can ;automatically select direct mode. LDY GO 18 none Opcode (hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 0C 10 Data 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in none none none Description Increment X index register by 2 (X = X + 2), then read word X points to. Read program counter. Read D accumulator. Read X index register. Read Y index register. Read stack pointer. Increment X index register by 2 (X = X + 2), then write word to location pointed to by X. Write program counter. Write D accumulator. Write X index register. Write Y index register. Write stack pointer. Go to user program. If enabled, ACK will occur when leaving active background mode. Go to user program. If enabled, ACK will occur upon returning to active background mode. Execute one user instruction then return to active BDM. If enabled, ACK will occur upon returning to active background mode. (Previous enable tagging and go to user program.) This command will be deprecated and should not be used anymore. Opcode will be executed as a GO command. Note: 169. If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 170. When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources are accessed rather than user code. Writing BDM firmware is not possible. 171. System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop mode). The GO_UNTIL command will not get an Acknowledge if CPU executes the stop instruction before the “UNTIL” condition (BDM active again) is reached (see Section 4.31.4.7, “Serial Interface Hardware Handshake Protocol” last note). 4.31.4.5 BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word, depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name.{Satatement} 8-bit reads return 16-bits of data, only one byte of which contains valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 188 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM ignores the least significant bit of the address and assumes an even address from the remaining bits. For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For BDM firmware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. For BDM firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait for at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing, it is recommended that the ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 57 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8  16 target clock cycles.(172) Note: 172. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 4.31.4.6, “BDM Serial Interface” and Section 4.31.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected. 8 Bits AT ~16 TC/Bit Hardware Read Command 16 Bits AT ~16 TC/Bit Address 150-BC Delay 16 Bits AT ~16 TC/Bit Data 150-BC Delay Next Command Hardware Write Command 48-BC DELAY Address Data Next Command Firmware Read Command Data 36-BC DELAY Next Command Firmware Write Command 76-BC Delay Data Next Command GO, TRACE Command Next Command Figure 57. BDM Command Structure BC = Bus Clock Cycles TC = Target Clock Cycles MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 189 4.31.4.6 BDM Serial Interface The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 58 and that of target-to-host in Figure 59 and Figure 60. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 58 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. BDM Clock (Target MCU) Host Transmit 1 Host Transmit 0 Perceived Start of Bit Time 10 Cycles Synchronization Uncertainty Figure 58. BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 59 shows the host receiving a logic 1 from the target system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. Target Senses Bit Earliest Start of Next Bit MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 190 BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse Perceived Start of Bit Time R-C Rise BKGD Pin High-Impedance High-Impedance High-Impedance 10 Cycles 10 Cycles Host Samples BKGD Pin Figure 59. BDM Target-to-Host Serial Bit Timing (Logic 1) Earliest Start of Next Bit Figure 60 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Drive and Speedup Pulse Perceived Start of Bit Time BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Figure 60. BDM Target-to-Host Serial Bit Timing (Logic 0) Earliest Start of Next Bit High-Impedance Speedup Pulse 4.31.4.7 Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be modified , it is very helpful to provide a handshake protocol in which the host could determine when an issued command is MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 191 executed by the CPU. . The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 61). This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL(171) or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends upon the CPU bus, which in some cases could be very slow due to long accesses taking place.This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. BDM Clock (Target MCU) 16 Cycles Target Transmits ACK Pulse High-Impedance 32 Cycles Speedup Pulse Minimum Delay From the BDM Command BKGD Pin Earliest Start of Next Bit Figure 61. Target Acknowledge Pulse (ACK) NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters stop prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering stop mode, the BDM command is no longer pending. Figure 62 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even. Target BKGD Pin READ_BYTE Host Byte Address Target Host New BDM Command Host BDM Issues the ACK Pulse (out of scale) BDM Executes the BDM Decodes READ_BYTE Command the Command Figure 62. Handshake Protocol at the Command Level MM912_634 Advance Information, Rev. 4.0 High-Impedance 16th Tick of the Last Command Bit (2) Bytes are Retrieved Target Freescale Semiconductor 192 Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge on the BKGD pin. The hardware handshake protocol in Figure 61 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict on the BKGD pin. NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). Other “highs” are pulled rather than driven. However, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters stop while the host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the stop being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host (not aware of stop) should decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. NOTE The ACK pulse does not provide a timeout. This means for the GO_UNTIL(171) command that it can not be distinguished if a stop has been executed (command discarded and ACK not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command. See the handshake abort procedure described in Section 4.31.4.8, “Hardware Handshake Abort Procedure”. 4.31.4.8 Hardware Handshake Abort Procedure The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse.By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 4.31.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. For BDM firmware READ or WRITE commands it can not be guaranteed that the pending command is aborted when issuing a SYNC before the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware READ or WRITE command that is issued and on the selected bus clock rate. When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL(171) command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative edge to be detected by the target.In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 193 Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 4.31.4.9, “SYNC — Request Timed Reference Pulse”. Figure 63 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer. READ_BYTE CMD is Aborted by the SYNC Request (Out of Scale) BKGD Pin READ_BYTE Host Memory Address Target SYNC Response From the Target (Out of Scale) READ_STATUS Host Target New BDM Command Host Target BDM Decode New BDM Command and Starts to Execute the READ_BYTE Command Figure 63. ACK Abort Procedure at the Command Level NOTE Figure 63 does not represent the signals in a true timing scale Figure 64 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conflict from happening. At Least 128 Cycles BDM Clock (Target MCU) ACK Pulse Target MCU Drives to BKGD Pin Host Drives SYNC To BKGD Pin Host and Target Drive to BKGD Pin Host SYNC Request Pulse BKGD Pin 16 Cycles Figure 64. ACK Pulse and SYNC Request Conflict NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. The commands are described as follows: High-Impedance Electrical Conflict Speedup Pulse MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 194 • • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 4.31.4.3, “BDM Hardware Commands” and Section 4.31.4.4, “Standard BDM Firmware Commands” for more information on the BDM commands. The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command. The BACKGROUND command issues an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command issues an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL(171) command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. 4.31.4.9 SYNC — Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic one. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 195 4.31.4.10 Instruction Tracing When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. Be aware when tracing through the user code that the execution of the user code is done step by step but peripherals are free running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist. Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address pointing to BDM firmware address space. When tracing through user code which contains stop instructions the following will happen when the stop instruction is traced: The CPU enters stop mode and the TRACE1 command can not be finished before leaving the low power mode. This is the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM hardware commands except the BACKGROUND command are operational after tracing a stop instruction and still being in stop mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational. As soon as stop mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the corresponding interrupt service routine. In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a stop instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command after CPU exited from stop mode. All valid commands sent during CPU being in stop mode or after CPU exited from stop mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command. 4.31.4.11 Serial Communication Timeout The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any timeout limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the timeout has occurred. This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the timeout feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the timeout period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the timeout in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 196 4.32 4.32.1 S12S Debug Module (S12SDBGV2) Introduction The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU debugging. Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user configures the S12SDBG module for a debugging session over the BDM interface. Once configured the S12SDBG module is armed and the device leaves BDM returning control to the user program, which is then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a serial interface using SWI routines. 4.32.1.1 Glossary Of Terms COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt. BDM: Background Debug Mode S12SBDM: Background Debug Module DUG: Device User Guide, describing the features of the device into which the DBG is integrated. WORD: 16 bit data entity Data Line: 20 bit data entity CPU: S12SCPU module DBG: S12SDBG module POR: Power On Reset Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. 4.32.1.2 Overview The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated. Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered immediately by writing to the TRIG control bit. The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured. 4.32.1.3 • Features • • • • Three comparators (A, B and C) — Comparators A compares the full address bus and full 16-bit data bus — Comparator A features a data bus mask register — Comparators B and C compare the full address bus only — Each comparator features selection of read or write access cycles — Comparator B allows selection of byte or word access cycles — Comparator matches can initiate state sequencer transitions Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin  Address Addmax — Outside address range match mode, Address Addminor Address  Addmax Two types of matches — Tagged — This matches just before a specific instruction begins execution — Force — This is valid on the first instruction boundary after a match occurs Two types of breakpoints — CPU breakpoint entering BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) Trigger mode independent of comparators — TRIG Immediate software trigger MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 197 • • Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 4.32.4.5.2.1, “Normal Mode) for change of flow definition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Compressed Pure PC: all program counter addresses are stored 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin and End alignment of tracing to trigger 4.32.1.4 Modes of Operation The DBG module can be used in all MCU functional modes. During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already armed, remains armed. The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated Table 268. Mode Dependent Restriction Summary BDM Enable x 0 0 1 1 BDM Active x 0 1 0 1 MCU Secure 1 0 0 0 0 Yes No Comparator Matches Enabled Yes Yes Breakpoints Possible Yes Only SWI Tagging Possible Yes Yes Tracing Possible No Yes Active BDM not possible when not enabled Yes No Yes No Yes No 4.32.1.5 TAGHITS Block Diagram TAGS BREAKPOINT REQUESTS SECURE MATCH0 TRANSITION TO CPU COMPARATOR MATCH CONTROL CPU BUS BUS INTERFACE COMPARATOR A COMPARATOR B MATCH1 TAG & MATCH CONTROL LOGIC STATE STATE SEQUENCER STATE COMPARATOR C MATCH2 TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 65. Debug Module Block Diagram MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 198 4.32.2 External Signal Description There are no external signals associated with this module. 4.32.3 4.32.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the DBG sub-block is shown in Figure 269. Detailed descriptions of the registers and bits are given in the subsections that follow. Table 269. Quick Reference to DBG Registers Address 0x0020 Name DBGC1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 0 0 SZE SZ TAG BRK RW RWE NDB 0 COMPE 0 0 0 0 0 0 0 0 SC3 0 SC2 MC2 SC1 MC1 SC0 MC0 TBF 0 CNT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0 0 TSOURCE 0 0 0 TRCMOD 0 0 0 TALIGN Bit 7 ARM TBF(173) 6 0 TRIG 0 0 5 0 4 BDM 0 3 DBGBRK 0 2 0 1 COMRV SSF1 SSF0 Bit 0 0x0021 DBGSR SSF2 0x0022 DBGTCR 0x0023 DBGC2 0 0 ABCM Bit 8 0x0024 DBGTBH 0x0025 DBGTBL 0x0026 DBGCNT 0x0027 DBGSCRX 0x0027 DBGMFR 0x0028 DBGACTL 0x0028 DBGBCTL SZE 0 SZ 0 TAG BRK RW RWE COMPE 0x0028 DBGCCTL TAG 0 BRK 0 RW 0 RWE 0 0 COMPE 0x0029 DBGXAH Bit 17 Bit 16 0x002A DBGXAM 9 Bit 8 0x002B DBGXAL Bit 7 6 5 4 3 2 1 Bit 0 0x002C DBGADH Bit 15 14 13 12 11 10 9 Bit 8 0x002D DBGADL Bit 7 6 5 4 3 2 1 Bit 0 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 199 Table 269. Quick Reference to DBG Registers Address 0x002E Name DBGADHM R W R W Bit 7 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 0x002F Note: 173. 174. 175. 176. DBGADLM Bit 7 6 5 4 3 2 1 Bit 0 This bit is visible at DBGCNT[7] and DBGSR[7] This represents the contents if the Comparator A control register is blended into this address. This represents the contents if the Comparator B control register is blended into this address. This represents the contents if the Comparator C control register is blended into this address. 4.32.3.2 Register Descriptions This section consists of the DBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, TRIG, and COMRV[1:0] 4.32.3.2.1 Debug Control Register 1 (DBGC1) Table 270. Debug Control Register (DBGC1) Address: 0x0020 7 R W Reset ARM 0 6 0 TRIG 0 0 = Unimplemented or Reserved 5 0 4 BDM 0 3 DBGBRK 0 2 0 1 COMRV 0 0 0 0 Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 4:3 anytime DBG is not armed. NOTE When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 200 Table 271. DBGC1 Field Descriptions Field Description Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. 0 1 Debugger disarmed Debugger armed 7 ARM 6 TRIG Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state sequencer status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session. The session is ended by setting TRIG and ARM simultaneously. 0 1 Do not trigger until the state sequencer enters the Final State. Trigger immediately 4 BDM Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI. 0 1 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI 3 DBGBRK S12SDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. 0 1 No Breakpoint generated Breakpoint generated 1–0 COMRV Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register is visible at the address 0x0027. See Table 272. Table 272. COMRV Encoding COMRV 00 01 10 11 Visible Comparator Comparator A Comparator B Comparator C None Visible Register at 0x0027 DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR 4.32.3.2.2 Debug Status Register (DBGSR) Table 273. Debug Status Register (DBGSR) Address: 0x0021 7 R W Reset POR — 0 0 0 0 0 = Unimplemented or Reserved 0 0 0 0 0 0 0 0 0 0 TBF 6 0 5 0 4 0 3 0 2 SSF2 1 SSF1 0 SSF0 Read: Anytime Write: Never MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 201 Table 274. DBGSR Field Descriptions Field Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit This bit is also visible at DBGCNT[7] State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 275. 7 TBF 2–0 SSF[2:0] Table 275. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] 000 001 010 011 100 101,110,111 Current State State0 (disarmed) State1 State2 State3 Final State Reserved 4.32.3.2.3 Debug Trace Control Register (DBGTCR) Table 276. Debug Trace Control Register (DBGTCR) Address: 0x0022 7 R W Reset 0 0 6 TSOURCE 0 5 0 4 0 3 TRCMOD 0 0 2 1 0 0 TALIGN 0 0 0 0 Read: Anytime Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed. Table 277. DBGTCR Field Descriptions Field Description Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is secured, this bit cannot be set and tracing is inhibited. This bit must be set to read the trace buffer. 0 1 3–2 TRCMOD Debug session without tracing requested Debug session with tracing requested 6 TSOURCE Trace Mode Bits — See Section 4.32.4.5.2, “Trace Modes for detailed Trace Mode descriptions. In Normal Mode, change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. In Compressed Pure PC mode the program counter value for each instruction executed is stored. See Table 278. Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session. 0 1 Trigger at end of stored data Trigger before storing data 0 TALIGN MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 202 Table 278. TRCMOD Trace Mode Bit Encoding TRCMOD 00 01 10 11 Description Normal Loop1 Detail Compressed Pure PC 4.32.3.2.4 Debug Control Register2 (DBGC2) Table 279. Debug Control Register2 (DBGC2) Address: 0x0023 7 R W Reset 0 0 0 = Unimplemented or Reserved 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 ABCM 0 0 Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching. Table 280. DBGC2 Field Descriptions Field 1–0 ABCM[1:0] Description A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 281. Table 281. ABCM Encoding ABCM 00 01 10 11 Description Match0 mapped to comparator A match: Match1 mapped to comparator B match. Match 0 mapped to comparator A/B inside range: Match1 disabled. Match 0 mapped to comparator A/B outside range: Match1 disabled. Reserved(177) Note: 177. Currently defaults to Comparator A, Comparator B disabled 4.32.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL) Table 282. Debug Trace Buffer Register (DBGTB) Address: 0x0024, 0x0025 15 14 Bit 14 X — 13 Bit 13 X — 12 Bit 12 X — 11 Bit 11 X — 10 Bit 10 X — 9 Bit 9 X — 8 Bit 8 X — 7 Bit 7 X — 6 Bit 6 X — 5 Bit 5 X — 4 Bit 4 X — 3 Bit 3 X — 2 Bit 2 X — 1 Bit 1 X — 0 Bit 0 X — R W POR Other Resets Bit 15 X — Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 203 Table 283. DBGTB Field Descriptions Field Description Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is set the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned access of these registers return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect the trace buffer pointer. The POR state is undefined. Other resets do not affect the trace buffer contents. 15–0 Bit[15:0] 4.32.3.2.6 Debug Count Register (DBGCNT) Table 284. Debug Count Register (DBGCNT) Address: 0x0026 7 R W Reset POR — 0 — 0 — 0 = Unimplemented or Reserved — 0 — 0 — 0 — 0 — 0 TBF 6 0 5 4 3 CNT 2 1 0 Read: Anytime Write: Never Table 285. DBGCNT Field Descriptions Field Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit This bit is also visible at DBGSR[7] Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer. Table 286 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer. 7 TBF 5–0 CNT[5:0] Table 286. CNT Decoding Table TBF 0 CNT[5:0] 000000 000001 000010 0 000100 000110 … 111111 Description No data valid 1 line valid 2 lines valid 4 lines valid 6 lines valid … 63 lines valid MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 204 Table 286. CNT Decoding Table TBF 1 CNT[5:0] 000000 000001 1 … … 111110 64 lines valid, oldest data has been overwritten by most recent data Description 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 4.32.3.2.7 Debug State Control Registers There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 287. State Control Register Access Encoding COMRV 00 01 10 11 Visible State Control Register DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR 4.32.3.2.7.1 Debug State Control Register 1 (DBGSCR1) Table 288. Debug State Control Register 1 (DBGSCR1) Address: 0x0027 7 R W Reset 0 0 0 = Unimplemented or Reserved 0 0 6 0 5 0 4 0 3 SC3 0 2 SC2 0 1 SC1 0 0 SC0 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the match channels of the comparator match control logic as depicted in Figure 65 and described in 4.32.3.2.8.1. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 289. DBGSCR1 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State1, based upon the match event. Table 290. State1 Sequencer Next State Selection SC[3:0] 0000 0001 0010 Description (Unspecified matches have no effect) Any match to Final State Match1 to State3 Match2 to State2 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 205 Table 290. State1 Sequencer Next State Selection SC[3:0] 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description (Unspecified matches have no effect) Match1 to State2 Match0 to State2....... Match1 to State3 Match1 to State3.........Match0 to Final State Match0 to State2....... Match2 to State3 Either Match0 or Match1 to State2 Reserved Match0 to State3 Reserved Reserved Reserved Either Match0 or Match2 to Final State........Match1 to State2 Reserved Reserved The priorities described in Table 323 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions to final state. 4.32.3.2.7.2 Debug State Control Register 2 (DBGSCR2) Table 291. Debug State Control Register 2 (DBGSCR2) Address: 0x0027 7 R W Reset 0 0 0 = Unimplemented or Reserved 0 0 6 0 5 0 4 0 3 SC3 0 2 SC2 0 1 SC1 0 0 SC0 0 Read: If COMRV[1:0] = 01 Write: If COMRV[1:0] = 01 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2. The matches refer to the match channels of the comparator match control logic as depicted in Figure 65 and described in Section 4.32.3.2.8.1, “Debug Comparator Control Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 292. DBGSCR2 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State2, based upon the match event. Table 293. State2 —Sequencer Next State Selection SC[3:0] 0000 0001 0010 Description (Unspecified matches have no effect) Match0 to State1....... Match2 to State3. Match1 to State3 Match2 to State3 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 206 Table 293. State2 —Sequencer Next State Selection SC[3:0] 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description (Unspecified matches have no effect) Match1 to State3....... Match0 Final State Match1 to State1....... Match2 to State3. Match2 to Final State Match2 to State1..... Match0 to Final State Either Match0 or Match1 to Final State Reserved Reserved Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State3 Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State1 The priorities described in Table 323 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2) 4.32.3.2.7.3 Debug State Control Register 3 (DBGSCR3) Table 294. Debug State Control Register 3 (DBGSCR3) Address: 0x0027 7 R W Reset 0 0 0 = Unimplemented or Reserved 0 0 6 0 5 0 4 0 3 SC3 0 2 SC2 0 1 SC1 0 0 SC0 0 Read: If COMRV[1:0] = 10 Write: If COMRV[1:0] = 10 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3. The matches refer to the match channels of the comparator match control logic as depicted in Figure 65 and described in Section 4.32.3.2.8.1, “Debug Comparator Control Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 295. DBGSCR3 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State3, based upon the match event. Table 296. State3 — Sequencer Next State Selection SC[3:0] 0000 0001 0010 0011 Description (Unspecified matches have no effect) Match0 to State1 Match2 to State2........ Match1 to Final State Match0 to Final State....... Match1 to State1 Match1 to Final State....... Match2 to State1 MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 207 Table 296. State3 — Sequencer Next State Selection SC[3:0] 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description (Unspecified matches have no effect) Match1 to State2 Match1 to Final State Match2 to State2........ Match0 to Final State Match0 to Final State Reserved Reserved Either Match1 or Match2 to State1....... Match0 to Final State Reserved Reserved Either Match1 or Match2 to Final State....... Match0 to State1 Match0 to State2....... Match2 to Final State Reserved The priorities described in Table 323 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2). 4.32.3.2.7.4 Debug Match Flag Register (DBGMFR) Table 297. Debug Match Flag Register (DBGMFR) Address: 0x0027 7 R W Reset 0 0 0 = Unimplemented or Reserved 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 MC2 1 MC1 0 MC0 Read: If COMRV[1:0] = 11 Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly to a channel. Should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag is set, further comparator matches on the same channel in the same session have no affect on that flag. 4.32.3.2.8 Comparator Register Descriptions Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparator B consists of four register bytes (three address bus compare registers and a control register). Comparator C consists of four register bytes (three address bus compare registers and a control register). Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs from those of comparators A and C. Table 298. Comparator Register Layout 0x0028 0x0029 0x002A CONTROL ADDRESS HIGH ADDRESS MEDIUM Read/Write Read/Write Read/Write Comparators A,B and C Comparators A,B and C Comparators A,B and C MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 208 Table 298. Comparator Register Layout 0x002B 0x002C 0x002D 0x002E 0x002F ADDRESS LOW DATA HIGH COMPARATOR DATA LOW COMPARATOR DATA HIGH MASK DATA LOW MASK Read/Write Read/Write Read/Write Read/Write Read/Write Comparators A,B and C Comparator A only Comparator A only Comparator A only Comparator A only 4.32.3.2.8.1 Debug Comparator Control Register (DBGXCTL) The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. Table 299. Debug Comparator Control Register DBGACTL (Comparator A) Address: 0x0028 7 R W Reset SZE 0 6 SZ 0 5 TAG 0 = Unimplemented or Reserved 4 BRK 0 3 RW 0 2 RWE 0 1 NDB 0 0 COMPE 0 Table 300. Debug Comparator Control Register DBGBCTL (Comparator B) Address: 0x0028 7 R W Reset SZE 0 6 SZ 0 5 TAG 0 = Unimplemented or Reserved 4 BRK 0 3 RW 0 2 RWE 0 1 0 0 COMPE 0 0 Table 301. Debug Comparator Control Register DBGCCTL (Comparator C) Address: 0x0028 7 R W Reset 0 0 0 6 0 5 TAG 0 = Unimplemented or Reserved 4 BRK 0 3 RW 0 2 RWE 0 1 0 0 COMPE 0 0 Read: DBGACTL if COMRV[1:0] = 00 DBGBCTL if COMRV[1:0] = 01 DBGCCTL if COMRV[1:0] = 10 Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed DBGBCTL if COMRV[1:0] = 01 and DBG not armed DBGCCTL if COMRV[1:0] = 10 and DBG not armed MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 209 Table 302. DBGXCTL Field Descriptions Field 7 SZE (Comparators A and B) 6 SZ (Comparators A and B) Description Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator. This bit is ignored if the TAG bit in the same register is set. 0 1 Word/Byte access size is not used in comparison Word/Byte access size is used in comparison Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. 0 1 Word access size is compared Byte access size is compared 5 TAG Tag Select — This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 1 Allow state sequencer transition immediately on match On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition 4 BRK Break — This bit controls whether a comparator match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit DBGBRK. 0 The debug session termination is dependent upon the state sequencer and trigger conditions. 1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. 3 RW Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set. 0 Write cycle is matched1 Read cycle is matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator.This bit is ignored if the TAG bit in the same register is set 0 1 Read/Write is not used in comparison Read/Write is used in comparison 2 RWE 1 NDB (Comparator A) Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same register is set. This bit is only available for comparator A. 0 1 Match on data bus equivalence to comparator register contents Match on data bus difference to comparator register contents The comparator is not enabled The comparator is enabled 0 COMPE Determines if comparator is enabled 0 1 Table 303 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue. Table 303. Read or Write Comparison Logic Table RWE Bit 0 0 1 1 1 1 RW Bit x x 0 0 1 1 RW Signal 0 1 0 1 0 1 Comment RW not used in comparison RW not used in comparison Write data bus No match No match Read data bus MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 210 4.32.3.2.8.2 Debug Comparator Address High Register (DBGXAH) Table 304. Debug Comparator Address High Register (DBGXAH) Address: 0x0029 7 R W Reset 0 0 0 = Unimplemented or Reserved 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 Bit 17 0 0 Bit 16 0 The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section , “ Table 305. Comparator Address Register Visibility COMRV 00 01 10 11 Visible Comparator DBGAAH, DBGAAM, DBGAAL DBGBAH, DBGBAM, DBGBAL DBGCAH, DBGCAM, DBGCAL None Read: Anytime. See Table for visible register encoding. Write: If DBG not armed. See Table for visible register encoding. Table 306. DBGXAH Field Descriptions Field Description Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator compares the address bus bits [17:16] to a logic one or logic zero. 0 1 Compare corresponding address bit to a logic zero Compare corresponding address bit to a logic one 1–0 Bit[17:16] 4.32.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM) Table 307. Debug Comparator Address Mid Register (DBGXAM) Address: 0x002A 7 R W Reset Bit 15 0 6 Bit 14 0 5 Bit 13 0 4 Bit 12 0 3 Bit 11 0 2 Bit 10 0 1 Bit 9 0 0 Bit 8 0 Read: Anytime. See Table for visible register encoding. Write: If DBG not armed. See Table for visible register encoding. Table 308. DBGXAM Field Descriptions Field Description Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the selected comparator compares the address bus bits [15:8] to a logic one or logic zero. 0 1 Compare corresponding address bit to a logic zero Compare corresponding address bit to a logic one 7–0 Bit[15:8] MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 211 4.32.3.2.8.4 Debug Comparator Address Low Register (DBGXAL) Table 309. Debug Comparator Address Low Register (DBGXAL) Address: 0x002B 7 R W Reset Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 0 Bit 0 0 Read: Anytime. See Table for visible register encoding. Write: If DBG not armed. See Table for visible register encoding. Table 310. DBGXAL Field Descriptions Field Description Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator compares the address bus bits [7:0] to a logic one or logic zero. 0 1 Compare corresponding address bit to a logic zero Compare corresponding address bit to a logic one 7–0 Bits[7:0] 4.32.3.2.8.5 Debug Comparator Data High Register (DBGADH) Table 311. Debug Comparator Data High Register (DBGADH) Address: 0x002C 7 R W Reset Bit 15 0 6 Bit 14 0 5 Bit 13 0 4 Bit 12 0 3 Bit 11 0 2 Bit 10 0 1 Bit 9 0 0 Bit 8 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 312. DBGADH Field Descriptions Field Description Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear. 0 1 Compare corresponding data bit to a logic zero Compare corresponding data bit to a logic one 7–0 Bits[15:8] 4.32.3.2.8.6 Debug Comparator Data Low Register (DBGADL) Table 313. Debug Comparator Data Low Register (DBGADL) Address: 0x002D 7 R W Reset Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 0 Bit 0 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 212 Table 314. DBGADL Field Descriptions Field Description Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 1 Compare corresponding data bit to a logic zero Compare corresponding data bit to a logic one 7–0 Bits[7:0] 4.32.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM) Table 315. Debug Comparator Data High Mask Register (DBGADHM) Address: 0x002E 7 R W Reset Bit 15 0 6 Bit 14 0 5 Bit 13 0 4 Bit 12 0 3 Bit 11 0 2 Bit 10 0 1 Bit 9 0 0 Bit 8 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 316. DBGADHM Field Descriptions Field Description Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 1 Do not compare corresponding data bit Any value of corresponding data bit allows match. Compare corresponding data bit 7–0 Bits[15:8] 4.32.3.2.8.8 Debug Comparator Data Low Mask Register (DBGADLM) Table 317. Debug Comparator Data Low Mask Register (DBGADLM) Address: 0x002F 7 R W Reset Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 0 Bit 0 0 Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 318. DBGADLM Field Descriptions Field Description Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 1 Do not compare corresponding data bit. Any value of corresponding data bit allows match Compare corresponding data bit 7–0 Bits[7:0] MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 213 4.32.4 Functional Description This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can generate breakpoints but tracing is not possible. 4.32.4.1 S12SDBG Operation Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity. Comparator A can also be configured to monitor data bus activity and mask out individual data bus bits during a compare. Comparators can be configured to use R/W and word/byte access qualification in the comparison. A match with a comparator register value can initiate a state sequencer transition to another state (see Figure 67). Either forced or tagged matches are possible. Using a forced match, a state sequencer transition can occur immediately on a successful match of system busses and comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue can a state sequencer transition occur. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated. A state sequencer transition to final state (with associated breakpoint, if enabled) can be initiated by writing to the TRIG bit in the DBGC1 control register. The trace buffer is visible through a 2-byte window in the register address map and must be read out using standard 16-bit word reads. TAGHITS TAGS BREAKPOINT REQUESTS SECURE MATCH0 TRANSITION STATE STATE SEQUENCER STATE MATCH2 TRACE CONTROL TRIGGER TO CPU COMPARATOR MATCH CONTROL CPU BUS BUS INTERFACE COMPARATOR A COMPARATOR B MATCH1 TAG & MATCH CONTROL LOGIC COMPARATOR C TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 66. DBG Overview 4.32.4.2 Comparator Modes The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH, DBGADL and allows masking of individual data bus bits. All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (see Figure 66) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 214 A match can initiate a transition to another state sequencer state (see Section 4.32.4.4, “State Sequence Control”). The comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allow the size of access (word or byte) to be considered in the compare. Only comparators A and B feature SZE and SZ. The TAG bit in each comparator control register is used to determine the match condition. By setting TAG, the comparator qualifies a match with the output of opcode tracking logic and a state sequencer transition occurs when the tagged instruction reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE, and SZ bits and the comparator data registers are ignored; the comparator address register must be loaded with the exact opcode address. If the TAG bit is clear (forced type match) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory, which precedes the instruction execution by an indefinite number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data value when a subsequent match occurs. Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see Section 4.32.3.2.4, “Debug Control Register2 (DBGC2)). Comparator channel priority rules are described in the priority section (Section 4.32.4.3.4, “Channel Priorities). 4.32.4.2.1 Single Address Comparator Match With range comparisons disabled, the match condition is an exact equivalence of address bus with the value stored in the comparator address registers. Further qualification of the type of access (R/W, word/byte) and data bus contents is possible, depending on comparator channel. 4.32.4.2.1.1 Comparator C Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus with the comparator address register loaded with address (n) a word access of address (n–1) also accesses (n) but does not cause a match. Table 319. Comparator C Access Considerations Condition For Valid Match Read and write accesses of ADDR[n] Write accesses of ADDR[n] Read accesses of ADDR[n] Comp C Address ADDR[n](178) ADDR[n] ADDR[n] RWE 0 1 1 RW X 0 1 Examples LDAA ADDR[n] STAA #$BYTE ADDR[n] STAA #$BYTE ADDR[n] LDAA #$BYTE ADDR[n] Note: 178. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code. 4.32.4.2.1.2 Comparator B Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified size of access causes a match. Thus if configured for a byte access of a particular address, a word access covering the same address does not lead to match. Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are shown in Table 320. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 215 Table 320. Comparator B Access Size Considerations Condition For Valid Match Word and byte accesses of ADDR[n] Word accesses of ADDR[n] only Comp B Address ADDR[n](179) ADDR[n] RWE 0 0 SZE 0 1 SZ8 X 0 Examples MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] MOVW #$WORD ADDR[n] LDD ADDR[n] Note: 179. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code. Access direction can also be used to qualify a match for Comparator B in the same way as described for Comparator C in Table 319. 4.32.4.2.1.3 Comparator A Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison. Table lists access considerations with data bus comparison. On word accesses the data byte of the lower address is mapped to DBGADH. Access direction can also be used to qualify a match for Comparator A in the same way as described for Comparator C in Table 319. Table 321. Comparator A Matches When Accessing ADDR[n] SZE 0 0 0 0 0 0 1 1 1 1 1 1 SZ X X X X X X 0 0 0 0 1 1 DBGADHM, DBGADLM $0000 $FF00 $00FF $00FF $FFFF $FFFF $0000 $00FF $FF00 $FFFF $0000 $FF00 Byte Word Byte, data(ADDR[n])=DH Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL Word Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Byte Byte, data(ADDR[n])=DH Access DH=DBGADH, DL=DBGADL Comment No data bus comparison Match data(ADDR[n]) Match data(ADDR[n+1]) Possible unintended match Match data(ADDR[n], ADDR[n+1]) Possible unintended match No data bus comparison Match only data at ADDR[n+1] Match only data at ADDR[n] Match data at ADDR[n] & ADDR[n+1] No data bus comparison Match data at ADDR[n] 4.32.4.2.1.4 Comparator A Data Bus Comparison NDB Dependency Comparator A features an NDB control bit, which allows data bus comparators to be configured to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the contents of an address location from an expected value. When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 216 Table 322. NDB and MASK Bit Dependency NDB 0 0 1 1 DBGADHM[n] / DBGADLM[n] 0 1 0 1 Comment Do not compare data bus bit. Compare data bus bit. Match on equivalence. Do not compare data bus bit. Compare data bus bit. Match on difference. 4.32.4.2.2 Range Comparisons Using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A TAG bit is used to tag range comparisons. The comparator B TAG bit is ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is ignored in range mode. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 4.32.4.2.2.1 Inside Range (CompA_Addr  Address  CompB_Addr) In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons. This configuration depends upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary is valid only if the aligned address is inside the range. 4.32.4.2.2.2 Outside Range (address < CompA_Addr or Address > CompB_Addr) In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid only if the aligned address is outside the range. Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an unexpected range. In forced match mode the outside range match would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or lower range limit to $00000 respectively. 4.32.4.3 Match Modes (Forced or Tagged) Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register TAG bits select the match mode. The modes are described in the following sections. 4.32.4.3.1 Forced Match When configured for forced matching, a comparator channel match can immediately initiate a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state. Forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent of comparator RWE/RW settings. Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an opcode address typically precedes a tagged match at the same address. 4.32.4.3.2 Tagged Match If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition. 4.32.4.3.3 Immediate Trigger Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the session and issues a forced breakpoint request to the CPU. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 217 It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of ARM. 4.32.4.3.4 Channel Priorities In case of simultaneous matches the priority is resolved according to Table 323. The lower priority is suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described in Table 323 dictate that in the case of simultaneous matches, the match pointing to final state has highest priority followed by the lower channel number (0,1,2). Table 323. Channel Priorities Priority Highest Source TRIG Channel pointing to Final State Match0 (force or tag hit) Match1 (force or tag hit) Lowest Match2 (force or tag hit) Action Enter Final State Transition to next state as defined by state control registers Transition to next state as defined by state control registers Transition to next state as defined by state control registers Transition to next state as defined by state control registers 4.32.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 ARM = 0 Session Complete (Disarm) Final State ARM = 0 State3 State2 Figure 67. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and channel matches. From Final State the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of comparator matches. Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. 4.32.4.4.1 Final State On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control as defined by the TALIGN bit (see Section 4.32.3.2.3, “Debug Trace Control Register (DBGTCR)”). If the TSOURCE bit in DBGTCR is clear then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 218 the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed. 4.32.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next read receives fresh information. Data is stored in the format shown in Table 324 and Table . After each store the counter register DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented. 4.32.4.5.1 Trace Trigger Alignment Using the TALIGN bit (see Section 4.32.3.2.3, “Debug Trace Control Register (DBGTCR)) it is possible to align the trigger with the end or the beginning of a tracing session. If end alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State signals the end of the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. Using end alignment or when the tracing is initiated by writing to the TRIG bit whilst configured for begin alignment, tracing starts in the second cycle after the DBGC1 write cycle. 4.32.4.5.1.1 Storing with Begin Trigger Alignment Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger is stored in the Trace Buffer. Using begin alignment together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 4.32.4.5.1.2 Storing with End Trigger Alignment Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction, the trigger event is not stored in the Trace Buffer. If all trace buffer lines have been used before a trigger event occurs then the trace continues at the first line, overwriting the oldest entries. 4.32.4.5.2 Trace Modes Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections. 4.32.4.5.2.1 Normal Mode In Normal Mode, change of flow (COF) program counter (PC) addresses are stored. COF addresses are defined as follows: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR, and CALL instruction • Destination address of RTI, RTS, and RTC instructions • Vector address of interrupts, except for BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. NOTE When a COF instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets executed after the interrupt service routine. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 219 In the following example an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place. MARK1 MARK2 SUB_1 LDX JMP NOP BRN NOP DBNE LDAB STAB RTI LDX JMP LDAB STAB RTI BRN NOP DBNE #SUB_1 0,X ; IRQ interrupt occurs during execution of this ; ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ; ; Source address TRACE BUFFER ENTRY 4 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 * ADDR1 IRQ_ISR A,PART5 #$F0 VAR_C1 ; The execution flow taking into account the IRQ is as follows #SUB_1 0,X #$F0 VAR_C1 * A,PART5 Loop1 Mode ; ; ; ; ; MARK1 IRQ_ISR SUB_1 ADDR1 4.32.4.5.2.2 Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches. Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. 4.32.4.5.2.3 Detail Mode In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information bit storage to the trace buffer, for each address byte storage. The information bits indicate the size of access (word or byte) and the type of access (read or write). When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle. 4.32.4.5.2.4 Compressed Pure PC Mode In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are stored. A compressed storage format is used to increase the effective depth of the trace buffer. This is achieved by storing the lower order bits each time and using 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full PC is stored. Each Trace Buffer row consists of 2 information bits and 18 PC address bits MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 220 NOTE: When tracing is terminated using forced breakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoint can be stored to the trace buffer. The number of opcodes is dependent on program flow. This can be avoided by using tagged breakpoints. 4.32.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes) ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32. In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and CSZ respectively). Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte1 and the byte at the higher address is stored to byte0. Table 324. Trace Buffer Organization (Normal,Loop1,Detail modes) Mode Entry Number Entry 1 Detail Mode Entry 2 Normal/Loop1 Modes Entry 1 Entry 2 4-bits Field 2 CINF1,ADRH1 0 CINF2,ADRH2 0 PCH1 PCH2 8-bits Field 1 ADRM1 DATAH1 ADRM2 DATAH2 PCM1 PCM2 8-bits Field 0 ADRL1 DATAL1 ADRL2 DATAL2 PCL1 PCL2 4.32.4.5.3.1 Information Bit Organization The format of the bits is dependent upon the active trace mode as described below. Field2 Bits in Detail Mode Table 325. Field2 Bits in Detail Mode Bit 3 CSZ Bit 2 CRW Bit 1 ADDR[17] Bit 0 ADDR[16] In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU. Table 326. Field Descriptions Bit 3 CSZ Description Access Type Indicator — This bit indicates if the access was a byte or word size when tracing in Detail Mode 0 1 Word Access Byte Access 2 CRW 1 ADDR[17] 0 ADDR[16] Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access when tracing in Detail Mode. 0 1 Write Access Read Access Address Bus bit 17 — Corresponds to system address bus bit 17. Address Bus bit 16 — Corresponds to system address bus bit 16. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 221 Field2 Bits in Normal and Loop1 Modes Figure 68. Information Bits PCH Bit 3 CSD Bit 2 CVA Bit 1 PC17 Bit 0 PC16 Table 327. PCH Field Descriptions Bit Description Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source or destination address. This bit has no meaning in Compressed Pure PC mode. 0 1 Source Address Destination Address 3 CSD 2 CVA Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no meaning in Compressed Pure PC mode. 0 1 Non-Vector Destination Address Vector Destination Address 1 PC17 0 PC16 Program Counter bit 17 — In Normal and Loop1 mode this bit corresponds to program counter bit 17. Program Counter bit 16 — In Normal and Loop1 mode this bit corresponds to program counter bit 16. 4.32.4.5.4 Trace Buffer Organization (Compressed Pure PC mode) Table 328. Trace Buffer Organization Example (Compressed PurePC mode) Mode Line Number Line 1 Line 2 2-bits Field 3 00 11 01 00 10 00 0 PC4 0 6-bits Field 2 6-bits Field 1 PC1 (Initial 18-bit PC Base Address) PC3 0 PC6 (New 18-bit PC Base Address) PC8 PC9 (New 18-bit PC Base Address) PC7 PC2 PC5 6-bits Field 0 Compressed Pure PC Mode Line 3 Line 4 Line 5 Line 6 NOTE Configured for end aligned triggering in compressed PurePC mode, then after rollover it is possible that the oldest base address is overwritten. In this case all entries between the pointer and the next base address have lost their base address following rollover. For example in Table 329 if one line of rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the entries on Lines 2 and 3 have lost their base address. For reconstruction of program flow the first base address following the pointer must be used, in the example, Line 4. The pointer points to the oldest entry, Line 2. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 222 Field3 Bits in Compressed Pure PC Modes Table 329. Compressed Pure PC Mode Field 3 Information Bit Encoding INF1 0 0 1 1 INF0 0 1 0 1 TRACE BUFFER ROW CONTENT Base PC address TB[17:0] contains a full PC[17:0] value Trace Buffer[5:0] contain incremental PC relative to base address zero value Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value Each time that PC[17:6] differs from the previous base PC[17:6], then a new base address is stored. The base address zero value is the lowest address in the 64 address range The first line of the trace buffer always gets a base PC address, this applies also on rollover. 4.32.4.5.5 Reading Data from Trace Buffer The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid lines can be determined. DBGCNT does not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no rollover has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with the oldest data entry may also contain newer data entries in fields 0 and 1. Thus if rollover is indicated by the TBF bit, the line status must be decoded using the INF bits in field3 of that line. If both INF bits are clear then the line contains only entries from before the last rollover. If INF0=1 then field 0 contains post rollover data but fields 1 and 2 contain pre rollover data. If INF1=1 then fields 0 and 1 contain post rollover data but field 2 contains pre rollover data. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least significant word of line is read out first. This corresponds to the fields 1 and 0 of Table 324. The next word read returns field 2 in the least significant bits [3:0] and “0” for bits [15:4]. Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM pointer occurs. 4.32.4.5.6 Trace Buffer Reset State The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out and the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data even if a reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set, otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best handled using end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. The Trace Buffer contents and DBGCNT bits are undefined following a POR. NOTE An external pin RESET that occurs simultaneous to a trace buffer entry can, in very seldom cases, lead to either that entry being corrupted or the first entry of the session being corrupted. In such cases the other contents of the trace buffer still contain valid tracing information. The case occurs when the reset assertion coincides with the trace buffer entry clock edge. 4.32.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 223 Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address. Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access. Thus these bits are ignored if tagging is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. Tagging is disabled when the BDM becomes active. 4.32.4.7 Breakpoints It is possible to generate breakpoints from channel transitions to final state or using software to write to the TRIG bit in the DBGC1 register. 4.32.4.7.1 Breakpoints From Comparator Channels Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 330). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment. Table 330. Breakpoint Setup For CPU Breakpoints BRK 0 0 0 0 1 1 TALIGN 0 0 1 1 x x DBGBRK 0 1 0 1 1 0 Breakpoint Alignment Fill Trace Buffer until trigger then disarm (no breakpoints) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints) Start Trace Buffer at trigger. A breakpoint request occurs when Trace Buffer is full Terminate tracing and generate breakpoint immediately on trigger Terminate tracing immediately on trigger 4.32.4.7.2 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 330). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and TRIG simultaneously. 4.32.4.7.3 Breakpoint Priorities If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator channel match, it has no effect, since tracing has already started. If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is activated by the BGND and the breakpoint to SWI is suppressed. 4.32.4.7.3.1 DBG Breakpoint Priorities And BDM Interfacing Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint gives priority to BDM requests over SWI requests MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 224 if the breakpoint happens to coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed. Table 331. Breakpoint Mapping Summary DBGBRK 0 1 X 1 1 BDM Bit (DBGC1[4]) X 0 X 1 1 BDM Enabled X X 1 0 1 BDM Active X 0 1 X 0 Breakpoint Mapping No Breakpoint Breakpoint to SWI No Breakpoint Breakpoint to SWI Breakpoint to BDM BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated breakpoint at the same address. Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes. NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it returns to the instruction whose tag generated the breakpoint. To avoid a repeated breakpoint at the same location reconfigure the DBG module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program flow past the tagged instruction. 4.32.5 4.32.5.1 Application Information State Machine scenarios Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2 respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR register. Thus the existing encoding for SCRx[2:0] is not changed. 4.32.5.2 Scenario 1 A trigger is generated if a given sequence of 3 code events is executed. SCR1=0011 State1 M1 SCR2=0010 State2 M2 SCR3=0111 State3 M0 Final State Figure 69. Scenario 1 Scenario 1 is possible with S12SDBGV1 SCR encoding 4.32.5.3 Scenario 2 A trigger is generated if a given sequence of 2 code events is executed. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 225 SCR1=0011 State1 M1 SCR2=0101 State2 M2 Final State Figure 70. Scenario 2a A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes. SCR1=0111 State1 M01 SCR2=0101 State2 M2 Final State Figure 71. Scenario 2b A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry into a range (COMPA,COMPB configured for range mode) SCR1=0010 State1 M2 SCR2=0011 State2 M0 Final State Figure 72. Scenario 2c All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding 4.32.5.4 Scenario 3 A trigger is generated immediately when one of up to 3 given events occurs SCR1=0000 State1 M012 Final State Figure 73. Scenario 3 Scenario 3 is possible with S12SDBGV1 SCR encoding 4.32.5.5 Scenario 4 Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A cause a trigger. This is possible by using CompA and CompC to match on the same address as shown. SCR1=0100 State1 M1 M0 M2 M1 State2 M0 SCR2=0011 SCR3=0001 State 3 M1 Final State Figure 74. Scenario 4a MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 226 This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2 comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown. SCR1=0110 State1 M2 M0 M0 M2 State2 M01 SCR2=1100 M1 disabled in range mode Final State SCR3=1110 State 3 M2 Figure 75. Scenario 4b (with 2 comparators) The advantage of using only 2 channels is that now range comparisons can be included (channel0) This however violates the S12SDBGV1 specification, which states that a match leading to final state always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on simultaneous taghits, taghits pointing to final state have highest priority. If no taghit points to final state then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG would break on a simultaneous M0/M2. 4.32.5.6 Scenario 5 Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C. SCR1=0011 State1 M1 M2 SCR2=0110 State2 M0 Final State Figure 76. Scenario 5 Scenario 5 is possible with the S12SDBGV1 SCR encoding 4.32.5.7 Scenario 6 Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The change in SCR1 encoding also has the advantage that a State1->State3 transition using M0 is now possible. This is advantageous because range and data bus comparisons use channel0 only. SCR1=1001 State1 M0 M12 SCR3=1010 State3 M0 Final State Figure 77. Scenario 6 4.32.5.8 Scenario 7 Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding OR forks as shown in red this scenario is possible. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 227 M01 SCR1=1101 State1 M1 SCR2=1100 State2 M2 SCR3=1101 State3 M12 Final State M0 M02 Figure 78. Scenario 7 On simultaneous matches the lowest channel number has priority so with this configuration the forking from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a simultaneous match2/match1transitions to state2. 4.32.5.9 Scenario 8 Trigger when a routine/event at M2 follows either M1 or M0. SCR1=0111 State1 M01 SCR2=0101 State2 M2 Final State Figure 79. Scenario 8a Trigger when an event M2 is followed by either event M0 or event M1 SCR1=0010 State1 M2 SCR2=0111 State2 M01 Final State Figure 80. Scenario 8b Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding. 4.32.5.10 Scenario 9 Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing the SCR2 encoding as shown in red this scenario becomes possible. SCR1=0111 State1 M01 M2 SCR2=1111 State2 M01 Final State Figure 81. Scenario 9 4.32.5.11 Scenario 10 Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1. As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third consecutive occurrence of event M0 without a reset M1. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 228 M1 SCR1=0010 State1 M2 SCR2=0100 State2 M2 SCR3=0010 State3 M0 Final State M1 Figure 82. Scenario 10a M0 SCR1=0010 State1 M2 SCR2=0011 State2 M1 SCR3=0000 State3 Final State M0 Figure 83. Scenario 10b Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 229 4.33 4.33.1 Security (S12X9SECV2) Introduction NOTE No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH and/or EEPROM difficult for unauthorized users. This specification describes the function of the security mechanism in the S12I chip family (9SEC). 4.33.1.1 Features The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access to a programming routine that updates parameters stored in another section of the Flash memory. The security features of the S12I chip family (in secure mode) are: • Protect the content of non-volatile memories (Flash, EEPROM) • Execution of NVM commands is restricted • Disable access to internal memory via background debug module (BDM) 4.33.1.2 Modes of Operation Table 332 gives an overview over availability of security relevant features in unsecure and secure modes. Figure 84 shows all modules affected by security in an MCU. Table 332. Feature Availability in Unsecure and Secure Modes on S12I Unsecure Mode NS SS NX ES EX ST NS SS Secure Mode NX ES EX ST Note: 180. Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information. 181. BDM hardware commands restricted to peripheral registers only. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 230 xbdm unsecure xmmc secreq flash security control security status mmc_secure xdbg xgate eeprom Figure 84. Chip Security Block Diagram The security mechanism relies on non-volatile bits contained in the FLASH module. The state of these bits is passed to the S12XMMC. Several of the MCU modules are involved in blocking certain operations which would reveal the contents of the protected FLASH and EEPROM. 4.34 4.34.1 Impact on MCU modules MMC When the device is in secure mode, the following blocks are affected by security There is a signal called “secreq” from the FLASH or EEPROM which indicates if the security is enabled. There is also a signal from the xbdm, which is used in the process of unsecuring the chip. This signal is called “unsecure”. These two signals and the resulting state of “device security” are shown in Table 333. Table 333. : Security Bits - System Control secreq 0 0 1 1 bdm_unsecure 0 1 0 1 mmc_secure 0 (unsecured) 0 (unsecured) 1 (secured) 0 (unsecured) In expanded modes, if the “mmc_secure_t2” signal is asserted, the ROMON and EEON bits are forced to zero. This operation is independent of how the part got to expanded mode (straight out of reset or by writing the mode register). When security is enabled and the part is brought up in special single chip mode, the secure BDM firmware is brought into the map along with the standard BDM firmware. The secure firmware has higher priority, but does not fill the whole space. It occupies $7F_FF80 to $7F_FFFF. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 231 One cycle after bdm_unsecure is asserted the secure firmware is disabled from the map. In secure mode aBDM access to a non register address will be translated to a peripheral register address, and BDM registers are not accessible. No BDM global access is possible if the chip is secured. In secured expanded mode or emulation mode, FLASH and EEPROM are disabled by the MMC. 4.34.2 BDM When security is active and the blank check is performed and failed, only BDM hardware commands are available. If the blank check is succeeds, all BDM commands are available. The BDM status register contains a bit called UNSEC. This bit is only writable by the secure firmware in special single chip mode. Based on the state of this bit, the BDM generates a signal called “unsecure”. The bit and signal are always reset to 0 (= de-asserted = secure). If the user resets into special single chip mode with the part secured, an alternate BDM firmware (“SECURE firmware”), is placed in the map along with the standard BDM firmware. The secure firmware has higher priority than the standard firmware, but it is smaller (less bytes). The secure firmware covers the vector space, but does not reach the beginning of the BDM firmware space. When blank check is successfully performed, UNSEC is asserted. The BDM program jumps to the start of the standard BDM firmware program and the secure firmware is turned off. If the blank check fails, then the ENBDM bit in the BDMSTS register is set without asserting UNSEC, and the BDM firmware code enters a loop. This enables the BDM hardware commands. In secure mode the MMC restricts BDM accesses to the register space. With UNSEC asserted, security is off and the user can change the state of the secure bits in the FLASH. Note that if the user does not change the state of these bits to “unsecured”, the part will be secured again when it is next taken out of reset. 4.34.3 DBG S12X_DBG will disable the trace buffer, but breakpoints are still valid. 4.34.4 XGATE XGATE internal registers XGCCR, XGPC, and XGR1 - XGR7 can not be written and will read zero from IPBI. Single stepping in XGATE is not possible. XGATE code residing in the internal RAM cannot be protected: 1. start MCU in NSC, let it run for a while 2. reset into SSC, MASERS the NVM 3. reset into SSC, blank check of BDM secure firmware succeeds 4. MCU is temporarily unsecured 5. BDM can be used to read internal RAM (contents not affected by reset) 4.35 Secure firmware Code Overview The BDM contains a secure firmware code. This firmware code is invoked when the user comes out of reset in special single chip mode with security enabled. The function of the firmware code is straight forward: • Verify the FLASH is erased • Verify the EEPROM is erased • If both are erased, release security If either the FLASH or the EEPROM is not erased, then security is not released. The ENBDM bit is set and the code enters a loop. This allows BDM hardware commands, which may be used to erase the EEPROM and FLASH. Note that erasing the memories and erasing / reprogramming the security bits is NOT part of the firmware code. The user must perform these operations. The blank check of FLASH and EEPROM is done in the BDM firmware. As such it could be changed on future parts. The current scheme uses the NVM command state-machines (FTX, EETX) to perform the blank check. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 232 4.35.0.1 Securing the Microcontroller Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down. The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence. Table 334. Flash Options/Security Byte 7 0xFF0F KEYEN1 6 KEYEN0 5 NV5 4 NV4 3 NV3 2 NV2 1 SEC1 0 SEC0 The meaning of the bits KEYEN[1:0] is shown in Table 335. Please refer to Section 4.35.0.3.2, “Unsecuring the MCU Using the Backdoor Key Access” for more information. Table 335. Backdoor Key Access Enable Bits KEYEN[1:0] 00 01 10 11 Backdoor Key Access Enabled 0 (disabled) 0 (disabled) 1 (enabled) 0 (disabled) The meaning of the security bits SEC[1:0] is shown in Table 336. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. Table 336. Security Bits SEC[1:0] 00 01 10 11 Security State 1 (secured) 1 (secured) 0 (unsecured) 1 (secured) NOTE Please refer to the Flash block guide for actual security configuration (in section “Flash Module Security”). 4.35.0.2 Operation of the Secured Microcontroller By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. Secured operation has the following effects on the microcontroller: 4.35.0.2.1 • • • Normal Single Chip Mode (NS) Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 233 4.35.0.2.2 • • • • Special Single Chip Mode (SS) BDM firmware commands are disabled. BDM hardware commands are restricted to the register space. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. Special single chip mode means BDM is active after reset. The availability of BDM firmware commands depends on the security state of the device. The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked. 4.35.0.2.3 Executing from Internal Memory in Expanded Mode The user may choose to operate from internal memory while in expanded mode. To do this the user must start in single chip mode and write to the mode bits selecting expanded operation. In this mode internal visibility and IPIPE are blocked. If the users program tries to execute from outside the program memory space (internal space occupied by the FLASH), the FLASH and EEPROM will be disabled. BDM operations will be blocked. 4.35.0.3 If the user begins operation in single chip mode with security on, the user is constrained to operate out of internal memory - even if the user changes to expanded mode. To accomplish this the MMC needs to register that the part started in single chip mode and was secured. The CPU will provide the state of the two high-order bits of the Program Counter. All this information, plus the firmware size information is used to determine that the part is executing in the proper space. If the program strays, the selects for FLASH and EEPROM are disabled by the MMC until the part goes through reset. Unsecuring the Microcontroller 4.35.0.3.1 Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 4.35.0.3.2 Unsecuring the MCU Using the Backdoor Key Access In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that: • The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been programmed to a valid value. • The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. • In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF. 4.35.0.4 Reprogramming the Security Bits In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 234 normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that: • The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte. • The Flash sector containing the Flash options/security byte is not protected. 4.35.0.5 Complete Memory Erase (Special Modes) The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks. When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset. 4.36 Initialization of a Virgin Device “Virgin” cells in the Flash array will read all programmed and the MCU will be secured as the SEC[1:0] bits would be loaded with ‘00’ from the Flash security byte. At wafer probe NVM BIST mode is used to test and initialize the Flash IFR block. Wafer probe will leave the Flash block erased so the MCU will be secured. For blind-assembled products, the following sequence must be used to initialize the Flash array: • Reset the MCU into special mode. • Set FCLKDIV to provide a proper FCLK period. • Set FPROT register to the unprotected state. • Set the WRALL bit in the FTSTMOD register, if available. • Load the Flash Pulse Timer with the mass erase time by executing a LDPTMR command write sequence. • Execute MASERSI commands to mass erase the Flash main block and Flash IFR block. • Execute the LDPTMR and PGMI command write sequence to program all timing parameters into the Flash IFR block. • Reset the MCU into special single chip mode. After the reset the BDM secure firmware executes a blank check command. If the blank check succeeds the MCU will be temporarily unsecured. • Execute the PGM command write sequence to program the security byte to the unsecured state. Blocking access to memories which can be secured during SCAN testing is necessary. While it would take a fair amount of sophistication on the part of a “thief”, our DFT people still consider this a major risk to security. It is therefore highly recommended that accesses to the FLASH and EEPROM arrays be blocked at chip level during scan test. Blocking or not blocking security at the core level will not help this. 4.37 Impact of Security on Test When silicon comes out of processing, it is extremely unlikely that the security bits will be configured for unsecure. There will need to be “hooks” for running BIST (if present) or Burn-in by bypassing the security. If wafer level burn-in is to be used, security must have a bypass which can be connected to by the burn-in layer. In burn-in, security is bypassed, but when the burn-in layer is removed, the state of secreq determines whether the part is secured or not. This may require some sort of weak pull-up device. At some point during testing the internal FLASH and EEPROM will need to be unsecured. This test program should follow the same sequence as a user to unsecure the part: erase the memories, bring the part up in special mode, erase and program the security bits to the unsecured state. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 235 4.38 4.38.1 S12 Clock, Reset and Power Management Unit (S12CPMU) Introduction This specification describes the function of the Clock, Reset and Power Management Unit. • The Pierce oscillator (OSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for optimal start-up margin with typical crystal oscillators. • The Voltage regulator (IVREG) operates from the range 3.13 to 5.5 V. It provides all the required chip internal voltages and voltage monitors. • The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter. • The Internal Reference Clock (IRC1M) provides a 1.0 MHz clock. 4.38.1.1 Features The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. • Supports crystals or resonators from 4.0 to 16 MHz. • High noise immunity due to input hysteresis and spike filtering. • Low RF emissions with peak-to-peak swing limited dynamically • Transconductance (gm) sized for optimum start-up margin for typical crystals • Dynamic gain control eliminates the need for external current limiting resistor • Integrated resistor eliminates the need for external bias resistor. • Low power consumption: Operates from internal 1.8 V (nominal) supply, Amplitude control limits power The Voltage Regulator (IVREG) has the following features: • Input voltage range from 3.13 to 5.5 V • Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) • Low-voltage reset (LVR) • during scan pattern execution option to go to RPM to support IDDq test. • external voltage reference used for HV-stress test and MIM screen, the external voltage on VDDA, divided by series resistors, will be used as input to the regulating loop of the IVREG The Phase Locked Loop (PLL) has the following features: • highly accurate and phase locked frequency multiplier • Configurable internal filter for best stability and lock time. • Frequency modulation for defined jitter and reduced emission • Automatic frequency lock detector • Interrupt request on entry or exit from locked condition • Reference clock either external (crystal) or internal square wave (1.0 MHz IRC1M) based. • PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock The Internal Reference Clock (IRC1M) has the following features: • Trimmable in frequency • Factory trimmed value for 1.0 MHz in Flash Memory, can be overwritten by application if required Other features of the S12CPMU include • Clock monitor to detect loss of crystal • Autonomous periodical interrupt (API) • Bus Clock Generator — Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock — PLLCLK divider to adjust system speed • System Reset generation from the following possible sources: — Power-on reset (POR) — Low-voltage reset (LVR) — Illegal address access — COP timeout — Loss of oscillation (clock monitor fail) — External pin RESET MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 236 4.38.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12CPMU. 4.38.1.2.1 Run Mode The voltage regulator is in Full Performance Mode (FPM). The Phase-locked Loop (PLL) is on. The Internal Reference Clock (IRC1M) is on. The API is available. • PLL Engaged Internal (PEI) — This is the default mode after System Reset and Power-on Reset. — The Bus Clock is based on the PLLCLK. — After reset the PLL is configured for 64 MHz VCOCLK operation Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 16 MHz and Bus Clock is 8.0 MHz. The PLL can be reconfigured for other bus frequencies. — The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M • PLL Engaged External (PEE) — The Bus Clock is based on the PLLCLK. — This mode can be entered from default mode PEI by performing the following steps: – Configure the PLL for desired bus frequency. – Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary. – Enable the external oscillator (OSCE bit) • PLL Bypassed External (PBE) — The Bus Clock is based on the Oscillator Clock (OSCCLK). — This mode can be entered from default mode PEI by performing the following steps: – Enable the external oscillator (OSCE bit) – Wait for oscillator to start up (UPOSC=1) – Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0) — The PLLCLK is still on to filter possible spikes of the external oscillator clock 4.38.1.2.2 Stop Mode This mode is entered by executing the CPU STOP instruction. The voltage regulator is in Reduced Power mode (RPM) The API is available The Phase Locked Loop (PLL) is off The Internal Reference Clock (IRC1M) is off Core Clock, Bus Clock and BDM Clock are stopped Depending on the setting of the PSTP and the OSCE bit, Stop mode can be differentiated between Full Stop mode (PSTP = 0 or OSCE=0) and Pseudo Stop mode (PSTP = 1 and OSCE=1). • Full Stop mode (pstp = 0 or osce=0) The external oscillator (OSCLCP) is disabled After wake-up from Full Stop mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). After wake-up from Full Stop mode the COP and RTI are running on IRCCLK (COPOSCSEL=0, RTIOSCSEL=0) • Pseudo Stop Mode (PSTP = 1 and OSCE=1) The external oscillator (OSCLCP) continues to run. If the respective enable bits are set the COP and RTI will continue to run. The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged NOTE When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator tUPOSC before entering Pseudo Stop mode. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 237 4.38.1.3 S12CPMU Block Diagram MMC Illegal Address Access VDD, VDDF (core supplies) Low Voltage Detect VDDA Low Voltage Detect VDDX Voltage Regulator 3.13 to 5.5V Power-On Detect LVRF PORF Power-On Reset Clock Monitor monitor fail UPOSC Adaptive Oscillator Filter Reset Generator UPOSC=0 sets PLLSEL bit COP time out VDDR VSS VDDX VSSX VDDA VSSA RESET ILAF LVDS LVIE Low Voltage Interrupt S12CPMU System Reset Oscillator status Interrupt OSCIE Loop EXTAL Controlled Pierce Oscillator XTAL (OSCLCP) 4MHz-16MHz REFDIV[3:0] Reference Divider OSCCLK OSCFILT[4:0] & PLLSEL CAN_OSCCLK (to MSCAN) OSCBW IRCTRIM[9:0] Internal Reference Clock (IRC1M) POSTDIV[4:0] Post Divider 1,2,…,32 divide by 4 ECLK2X (Core Clock) PLLCLK divide ECLK by 2 (Bus Clock) IRCCLK (to LCD) divide by 8 BDM Clock PSTP OSCE VCOFRQ[1:0] VCOCLK Lock detect REFCLK FBCLK Phase locked Loop with internal Filter (PLL) REFFRQ[1:0] LOCK Divide by 2*(SYNDIV+1) SYNDIV[5:0] Bus Clock RC ACLK Osc. APICLK LOCKIE PLL Lock Interrupt Autonomous API_EXTCLK Periodic Interrupt (API) APIE RTIE API Interrupt RTI Interrupt UPOSC UPOSC=0 clears IRCCLK COPCLK COP OSCCLK COP time out to Reset Generator IRCCLK Watchdog RTICLK OSCCLK Real Time Interrupt (RTI) PRE CPMURTI COPOSCSEL PCE CPMUCOP RTIOSCSEL Figure 85. Block diagram of S12CPMU MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 238 Figure 86 shows a block diagram of the OSCLCP. OSCCLK Peak Detector Gain Control VDD = 1.8 V VSS Rf EXTAL XTAL Figure 86. OSCLCP Block Diagram 4.38.2 Signal Description This section lists and describes the signals that connect off chip. 4.38.2.1 RESET RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered. 4.38.2.2 EXTAL and XTAL These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal OSCCLK is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 k and the XTAL pin is pulled down by an internal resistor of approximately 700 k. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals. 4.38.2.3 VDDR — Regulator Power Input Pin Pin VDDR is the power input of IVREG. All currents sourced into the regulator loads flow through this pin. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSS can smooth ripple on VDDR. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 239 4.38.2.4 4.38.2.5 VSS — Ground Pin VSS must be grounded.VDDA, VSSA — Regulator Reference Supply Pins Pins VDDA and VSSA are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can improve the quality of this supply. 4.38.2.6 VDDX, VSSX— Pad Supply Pins This supply domain is monitored by the Low Voltage Reset circuit. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can improve the quality of this supply. NOTE Depending on the device package following device supply pins are maybe combined into one supply pin: VDDR, VDDX and VDDA. Depending on the device package following device supply pins are maybe combined into one supply pin: VSS, VSSX and VSSA. Please refer to the device Reference Manual for information if device supply pins are combined into one supply pin for certain packages and which supply pins are combined together. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between the combined supply pin pair can improve the quality of this supply. 4.38.2.7 VDD — Internal Regulator Output Supply (Core Logic) Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the core logic. This supply domain is monitored by the Low Voltage Reset circuit. 4.38.2.8 VDDF — Internal Regulator Output Supply (NVM Logic) Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This supply domain is monitored by the Low Voltage Reset circuit 4.38.2.9 API_EXTCLK — API external clock output pin This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification to which pin it connects. 4.38.2.10 vddf_test, vdd_test, vddpll_test — supply testmode pins These pins allow to measure internal VDDF, VDD, VDDPLL. 4.38.2.11 cpmu_test_clk This signal is connected to a device pin and allows measuring internal clocks if cpmu_test_clk_en bit is set. 4.38.2.12 cpmu_test_xfc This signal is connected to a device pin and allows measuring the internal PLL filter node if cpmu_test_xfc_en bit is set. 4.38.2.13 REGFT[2:0] and REGT[2:0] With the ipt_trim_ld_en signal of the PTI, the trim values for VDD and VDDF of the VREG are loaded into CPMUTEST3 register which directly trims the VREG. 4.38.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the S12CPMU. 4.38.3.1 Module Memory Map The S12CPMU registers are shown in Figure 337. MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 240 Table 337. CPMU Register Summary Address 0x0034 Name CPMU SYNR CPMU REFDIV CPMU POSTDIV CPMUFLG R W R W R W R W R W R W R W R W R W R W R W RTDEC RTR6 RTIF PORF 0 LVRF 0 LOCKIF LOCK Bit 7 6 5 4 3 2 1 Bit 0 VCOFRQ[1:0] 0 0 SYNDIV[5:0] 0x0035 REFFRQ[1:0] 0 0 REFDIV[3:0] 0x0036 0 POSTDIV[4:0] UPOSC 0x0037 ILAF 0 OSCIF 0x0038 CPMUINT RTIE LOCKIE 0 0 OSCIE RTI OSCSEL 0 0 0x0039 CPMUCLKS PLLSEL 0 PSTP 0 0 PRE 0 PCE 0 COP OSCSEL 0 0x003A CPMUPLL FM1 FM0 0x003B CPMURTI RTR5 0 WRTMASK RTR4 0 RTR3 0 RTR2 RTR1 RTR0 0x003C CPMUCOP WCOP RSBCK CR2 0 CR1 CR0 0x003D RESERVEDC PMUTEST0 fmcs_reg_ cpmu_tes cpmu_test sel0 t_gfe0 _xfc_en0 fc_force_ en0 vcofrq20 fm_test0 test_sqw_ osc0 0x003E RESERVEDC PMUTEST1 cpmu_test cpmu_tes osc_lcp_ osc_lcp_e pfd_force_ cpmu_tes pfd_force_ _clk_sel[1] t_clk_sel[ monitor_d xtsqw_en en0 t_clk_en0 up0 0]0 isable0 able0 0 pfd_force _down0 0x003E 0x003F RESERVED R CPMUFMCS W CPMU ARMCOP RESERVED CPMU LVCTL R W R W R W R W R W R W R W 0 0 0 0 Bit 7 0 0 Bit 6 0 0 Bit 5 0 fmcs_cs[7:0] 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0x02F0 0x02F1 0 0 LVDS LVIE LVIF 0x02F2 CPMU APICTL CPMUAPITR CPMUAPIR H CPMUAPIRL APICLK APITR5 APIR15 APIR7 0 0 APIES APITR2 APIR12 APIR4 APIEA APITR1 APIR11 APIR3 APIFE APITR0 APIR10 APIR2 APIE 0 APIF 0 0x02F3 APITR4 APIR14 APIR6 APITR3 APIR13 APIR5 0x02F4 APIR9 APIR1 APIR8 APIR0 0x02F5 = Unimplemented or Reserved MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 241 Table 337. CPMU Register Summary Address Name RESERVEDC PMUTEST3 R W R W R W R W R W 0x02FB CPMUPROT RESERVEDC PMUTEST2 R W R W = Unimplemented or Reserved 0 0 0 LVRS 0 LVRFS 0 LVRXS 0 0 0 0 0 0 0 0 0 PROT 0RCEXA OSCE OSCBW OSCPINS_ EN TCTRIM[4:0] 0 IRCTRIM[9:8] 0 0 0 0 0 0 0 0 Bit 7 0 LVRT 6 0vdd_ext 5 0 REGFT2 4 0 3 0 2 0 REGT2 1 0 REGT1 Bit 0 0 REGT0 0x02F6 ernal_en REGFT1 REGFT0 0x02F7 RESERVED CPMU IRCTRIMH CPMU IRCTRIML 0x02F8 0x02F9 IRCTRIM[7:0] 0x02FA CPMUOSC OSCFILT[4:0] 0x02FC 4.38.3.2 Register Descriptions This section describes all the S12CPMU registers and their individual bits. Address order is as listed in Figure 337. 4.38.3.2.1 { S12CPMU Synthesizer Register (CPMUSYNR) The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range. Table 338. S12CPMU Synthesizer Register (CPMUSYNR) 0x0034 7 R W Reset 0 VCOFRQ[1:0] 1 0 1 1 6 5 4 3 SYNDIV[5:0] 1 1 1 2 1 0 Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Writing to this register clears the LOCK and UPOSC status bits. If PLL has locked (LOCK=1) f VCO = 2  f REF   SYNDIV + 1  NOTE fVCO must be within the specified VCO frequency lock range. Bus frequency fBUS must not exceed the specified maximum. The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in Table 339. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufficient stability). MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 242 Table 339. VCO Clock Frequency Selection VCOCLK Frequency Ranges 32 MHz